qemu

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/*
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 * nRF51 System-on-Chip general purpose input/output register definition
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 *
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 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
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 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
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 *
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 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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 *
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 * This code is licensed under the GPL version 2 or later.  See
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 * the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/gpio/nrf51_gpio.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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/*
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 * Check if the output driver is connected to the direction switch
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 * given the current configuration and logic level.
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 * It is not differentiated between standard and "high"(-power) drive modes.
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 */
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static bool is_connected(uint32_t config, uint32_t level)
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{
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    bool state;
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    uint32_t drive_config = extract32(config, 8, 3);
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    switch (drive_config) {
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    case 0 ... 3:
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        state = true;
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        break;
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    case 4 ... 5:
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        state = level != 0;
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        break;
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    case 6 ... 7:
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        state = level == 0;
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        break;
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    default:
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        g_assert_not_reached();
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        break;
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    }
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    return state;
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}
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static int pull_value(uint32_t config)
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{
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    int pull = extract32(config, 2, 2);
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    if (pull == NRF51_GPIO_PULLDOWN) {
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        return 0;
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    } else if (pull == NRF51_GPIO_PULLUP) {
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        return 1;
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    }
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    return -1;
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}
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static void update_output_irq(NRF51GPIOState *s, size_t i,
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                              bool connected, bool level)
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{
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    int64_t irq_level = connected ? level : -1;
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    bool old_connected = extract32(s->old_out_connected, i, 1);
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    bool old_level = extract32(s->old_out, i, 1);
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    if ((old_connected != connected) || (old_level != level)) {
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        qemu_set_irq(s->output[i], irq_level);
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        trace_nrf51_gpio_update_output_irq(i, irq_level);
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    }
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    s->old_out = deposit32(s->old_out, i, 1, level);
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    s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected);
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}
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static void update_state(NRF51GPIOState *s)
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{
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    int pull;
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    size_t i;
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    bool connected_out, dir, connected_in, out, in, input;
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    bool assert_detect = false;
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    for (i = 0; i < NRF51_GPIO_PINS; i++) {
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        pull = pull_value(s->cnf[i]);
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        dir = extract32(s->cnf[i], 0, 1);
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        connected_in = extract32(s->in_mask, i, 1);
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        out = extract32(s->out, i, 1);
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        in = extract32(s->in, i, 1);
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        input = !extract32(s->cnf[i], 1, 1);
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        connected_out = is_connected(s->cnf[i], out) && dir;
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        if (!input) {
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            if (pull >= 0) {
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                /* Input buffer disconnected from external drives */
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                s->in = deposit32(s->in, i, 1, pull);
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            }
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        } else {
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            if (connected_out && connected_in && out != in) {
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                /* Pin both driven externally and internally */
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                qemu_log_mask(LOG_GUEST_ERROR,
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                              "GPIO pin %zu short circuited\n", i);
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            }
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            if (connected_in) {
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                uint32_t detect_config = extract32(s->cnf[i], 16, 2);
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                if ((detect_config == 2) && (in == 1)) {
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                    assert_detect = true;
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                }
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                if ((detect_config == 3) && (in == 0)) {
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                    assert_detect = true;
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                }
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            } else {
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                /*
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                 * Floating input: the output stimulates IN if connected,
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                 * otherwise pull-up/pull-down resistors put a value on both
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                 * IN and OUT.
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                 */
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                if (pull >= 0 && !connected_out) {
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                    connected_out = true;
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                    out = pull;
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                }
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                if (connected_out) {
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                    s->in = deposit32(s->in, i, 1, out);
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                }
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            }
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        }
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        update_output_irq(s, i, connected_out, out);
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    }
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    qemu_set_irq(s->detect, assert_detect);
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}
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/*
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 * Direction is exposed in both the DIR register and the DIR bit
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 * of each PINs CNF configuration register. Reflect bits for pins in DIR
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 * to individual pin configuration registers.
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 */
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static void reflect_dir_bit_in_cnf(NRF51GPIOState *s)
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{
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    size_t i;
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    uint32_t value = s->dir;
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    for (i = 0; i < NRF51_GPIO_PINS; i++) {
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        s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01);
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    }
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}
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static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size)
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{
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    NRF51GPIOState *s = NRF51_GPIO(opaque);
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    uint64_t r = 0;
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    size_t idx;
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    switch (offset) {
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    case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR:
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        r = s->out;
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        break;
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    case NRF51_GPIO_REG_IN:
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        r = s->in;
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        break;
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    case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR:
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        r = s->dir;
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        break;
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    case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END:
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        idx = (offset - NRF51_GPIO_REG_CNF_START) / 4;
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        r = s->cnf[idx];
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                "%s: bad read offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    trace_nrf51_gpio_read(offset, r);
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    return r;
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}
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static void nrf51_gpio_write(void *opaque, hwaddr offset,
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                       uint64_t value, unsigned int size)
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{
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    NRF51GPIOState *s = NRF51_GPIO(opaque);
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    size_t idx;
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    trace_nrf51_gpio_write(offset, value);
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    switch (offset) {
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    case NRF51_GPIO_REG_OUT:
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        s->out = value;
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        break;
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    case NRF51_GPIO_REG_OUTSET:
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        s->out |= value;
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        break;
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    case NRF51_GPIO_REG_OUTCLR:
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        s->out &= ~value;
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        break;
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    case NRF51_GPIO_REG_DIR:
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        s->dir = value;
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        reflect_dir_bit_in_cnf(s);
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        break;
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    case NRF51_GPIO_REG_DIRSET:
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        s->dir |= value;
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        reflect_dir_bit_in_cnf(s);
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        break;
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    case NRF51_GPIO_REG_DIRCLR:
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        s->dir &= ~value;
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        reflect_dir_bit_in_cnf(s);
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        break;
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    case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END:
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        idx = (offset - NRF51_GPIO_REG_CNF_START) / 4;
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        s->cnf[idx] = value;
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        /*
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         * direction is exposed in both the DIR register and the DIR bit
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         * of each PINs CNF configuration register.
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         */
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        s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx);
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    update_state(s);
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}
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static const MemoryRegionOps gpio_ops = {
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    .read =  nrf51_gpio_read,
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    .write = nrf51_gpio_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl.min_access_size = 4,
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    .impl.max_access_size = 4,
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};
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static void nrf51_gpio_set(void *opaque, int line, int value)
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{
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    NRF51GPIOState *s = NRF51_GPIO(opaque);
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    trace_nrf51_gpio_set(line, value);
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    assert(line >= 0 && line < NRF51_GPIO_PINS);
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    s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);
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    if (value >= 0) {
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        s->in = deposit32(s->in, line, 1, value != 0);
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    }
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    update_state(s);
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}
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static void nrf51_gpio_reset(DeviceState *dev)
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{
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    NRF51GPIOState *s = NRF51_GPIO(dev);
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    size_t i;
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    s->out = 0;
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    s->old_out = 0;
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    s->old_out_connected = 0;
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    s->in = 0;
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    s->in_mask = 0;
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    s->dir = 0;
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    for (i = 0; i < NRF51_GPIO_PINS; i++) {
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        s->cnf[i] = 0x00000002;
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    }
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}
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static const VMStateDescription vmstate_nrf51_gpio = {
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    .name = TYPE_NRF51_GPIO,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(out, NRF51GPIOState),
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        VMSTATE_UINT32(in, NRF51GPIOState),
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        VMSTATE_UINT32(in_mask, NRF51GPIOState),
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        VMSTATE_UINT32(dir, NRF51GPIOState),
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        VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS),
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        VMSTATE_UINT32(old_out, NRF51GPIOState),
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        VMSTATE_UINT32(old_out_connected, NRF51GPIOState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void nrf51_gpio_init(Object *obj)
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{
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    NRF51GPIOState *s = NRF51_GPIO(obj);
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    memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
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            TYPE_NRF51_GPIO, NRF51_GPIO_SIZE);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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    qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS);
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    qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS);
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    qdev_init_gpio_out_named(DEVICE(s), &s->detect, "detect", 1);
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}
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static void nrf51_gpio_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->vmsd = &vmstate_nrf51_gpio;
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    dc->reset = nrf51_gpio_reset;
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    dc->desc = "nRF51 GPIO";
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}
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static const TypeInfo nrf51_gpio_info = {
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    .name = TYPE_NRF51_GPIO,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(NRF51GPIOState),
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    .instance_init = nrf51_gpio_init,
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    .class_init = nrf51_gpio_class_init
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};
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static void nrf51_gpio_register_types(void)
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{
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    type_register_static(&nrf51_gpio_info);
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}
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type_init(nrf51_gpio_register_types)
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