qemu

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/*
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 * QEMU Sparc32 DMA controller emulation
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * Modifications:
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 *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sparc/sparc32_dma.h"
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#include "hw/sparc/sun4m_iommu.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "sysemu/dma.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "trace.h"
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/*
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 * This is the DMA controller part of chip STP2000 (Master I/O), also
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 * produced as NCR89C100. See
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 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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 * and
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 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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 */
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#define DMA_SIZE (4 * sizeof(uint32_t))
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/* We need the mask, because one instance of the device is not page
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   aligned (ledma, start address 0x0010) */
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#define DMA_MASK (DMA_SIZE - 1)
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/* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
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#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
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#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
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#define DMA_VER 0xa0000000
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#define DMA_INTR 1
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#define DMA_INTREN 0x10
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#define DMA_WRITE_MEM 0x100
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#define DMA_EN 0x200
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#define DMA_LOADED 0x04000000
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#define DMA_DRAIN_FIFO 0x40
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#define DMA_RESET 0x80
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/* XXX SCSI and ethernet should have different read-only bit masks */
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#define DMA_CSR_RO_MASK 0xfe000007
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enum {
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    GPIO_RESET = 0,
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    GPIO_DMA,
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};
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/* Note: on sparc, the lance 16 bit bus is swapped */
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void ledma_memory_read(void *opaque, hwaddr addr,
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                       uint8_t *buf, int len, int do_bswap)
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{
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    DMADeviceState *s = opaque;
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    IOMMUState *is = (IOMMUState *)s->iommu;
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    int i;
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    addr |= s->dmaregs[3];
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    trace_ledma_memory_read(addr, len);
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    if (do_bswap) {
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        dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);
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    } else {
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        addr &= ~1;
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        len &= ~1;
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        dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);
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        for(i = 0; i < len; i += 2) {
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            bswap16s((uint16_t *)(buf + i));
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        }
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    }
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}
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void ledma_memory_write(void *opaque, hwaddr addr,
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                        uint8_t *buf, int len, int do_bswap)
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{
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    DMADeviceState *s = opaque;
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    IOMMUState *is = (IOMMUState *)s->iommu;
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    int l, i;
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    uint16_t tmp_buf[32];
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    addr |= s->dmaregs[3];
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    trace_ledma_memory_write(addr, len);
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    if (do_bswap) {
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        dma_memory_write(&is->iommu_as, addr, buf, len,
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                         MEMTXATTRS_UNSPECIFIED);
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    } else {
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        addr &= ~1;
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        len &= ~1;
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        while (len > 0) {
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            l = len;
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            if (l > sizeof(tmp_buf))
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                l = sizeof(tmp_buf);
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            for(i = 0; i < l; i += 2) {
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                tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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            }
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            dma_memory_write(&is->iommu_as, addr, tmp_buf, l,
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                             MEMTXATTRS_UNSPECIFIED);
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            len -= l;
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            buf += l;
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            addr += l;
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        }
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    }
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}
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static void dma_set_irq(void *opaque, int irq, int level)
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{
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    DMADeviceState *s = opaque;
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    if (level) {
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        s->dmaregs[0] |= DMA_INTR;
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        if (s->dmaregs[0] & DMA_INTREN) {
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            trace_sparc32_dma_set_irq_raise();
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            qemu_irq_raise(s->irq);
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        }
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    } else {
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        if (s->dmaregs[0] & DMA_INTR) {
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            s->dmaregs[0] &= ~DMA_INTR;
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            if (s->dmaregs[0] & DMA_INTREN) {
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                trace_sparc32_dma_set_irq_lower();
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                qemu_irq_lower(s->irq);
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            }
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        }
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    }
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}
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void espdma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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    DMADeviceState *s = opaque;
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    IOMMUState *is = (IOMMUState *)s->iommu;
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    trace_espdma_memory_read(s->dmaregs[1], len);
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    dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len,
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                    MEMTXATTRS_UNSPECIFIED);
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    s->dmaregs[1] += len;
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}
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void espdma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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    DMADeviceState *s = opaque;
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    IOMMUState *is = (IOMMUState *)s->iommu;
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    trace_espdma_memory_write(s->dmaregs[1], len);
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    dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len,
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                     MEMTXATTRS_UNSPECIFIED);
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    s->dmaregs[1] += len;
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}
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static uint64_t dma_mem_read(void *opaque, hwaddr addr,
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                             unsigned size)
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{
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    DMADeviceState *s = opaque;
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    uint32_t saddr;
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    saddr = (addr & DMA_MASK) >> 2;
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    trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
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    return s->dmaregs[saddr];
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}
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static void dma_mem_write(void *opaque, hwaddr addr,
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                          uint64_t val, unsigned size)
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{
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    DMADeviceState *s = opaque;
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    uint32_t saddr;
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    saddr = (addr & DMA_MASK) >> 2;
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    trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
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    switch (saddr) {
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    case 0:
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        if (val & DMA_INTREN) {
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            if (s->dmaregs[0] & DMA_INTR) {
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                trace_sparc32_dma_set_irq_raise();
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                qemu_irq_raise(s->irq);
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            }
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        } else {
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            if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
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                trace_sparc32_dma_set_irq_lower();
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                qemu_irq_lower(s->irq);
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            }
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        }
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        if (val & DMA_RESET) {
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            qemu_irq_raise(s->gpio[GPIO_RESET]);
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            qemu_irq_lower(s->gpio[GPIO_RESET]);
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        } else if (val & DMA_DRAIN_FIFO) {
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            val &= ~DMA_DRAIN_FIFO;
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        } else if (val == 0)
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            val = DMA_DRAIN_FIFO;
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        if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
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            trace_sparc32_dma_enable_raise();
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            qemu_irq_raise(s->gpio[GPIO_DMA]);
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        } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
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            trace_sparc32_dma_enable_lower();
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            qemu_irq_lower(s->gpio[GPIO_DMA]);
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        }
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        val &= ~DMA_CSR_RO_MASK;
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        val |= DMA_VER;
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        s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
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        break;
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    case 1:
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        s->dmaregs[0] |= DMA_LOADED;
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        /* fall through */
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    default:
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        s->dmaregs[saddr] = val;
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        break;
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    }
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}
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static const MemoryRegionOps dma_mem_ops = {
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    .read = dma_mem_read,
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    .write = dma_mem_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static void sparc32_dma_device_reset(DeviceState *d)
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{
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    DMADeviceState *s = SPARC32_DMA_DEVICE(d);
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    memset(s->dmaregs, 0, DMA_SIZE);
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    s->dmaregs[0] = DMA_VER;
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}
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static const VMStateDescription vmstate_sparc32_dma_device = {
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    .name ="sparc32_dma",
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    .version_id = 2,
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    .minimum_version_id = 2,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void sparc32_dma_device_init(Object *obj)
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{
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    DeviceState *dev = DEVICE(obj);
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    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    sysbus_init_irq(sbd, &s->irq);
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    sysbus_init_mmio(sbd, &s->iomem);
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    object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
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                             (Object **) &s->iommu,
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                             qdev_prop_allow_set_link_before_realize,
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                             0);
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    qdev_init_gpio_in(dev, dma_set_irq, 1);
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    qdev_init_gpio_out(dev, s->gpio, 2);
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}
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static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = sparc32_dma_device_reset;
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    dc->vmsd = &vmstate_sparc32_dma_device;
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}
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static const TypeInfo sparc32_dma_device_info = {
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    .name          = TYPE_SPARC32_DMA_DEVICE,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .abstract      = true,
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    .instance_size = sizeof(DMADeviceState),
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    .instance_init = sparc32_dma_device_init,
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    .class_init    = sparc32_dma_device_class_init,
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};
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static void sparc32_espdma_device_init(Object *obj)
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{
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    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
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    ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
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    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
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                          "espdma-mmio", DMA_SIZE);
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    object_initialize_child(obj, "esp", &es->esp, TYPE_SYSBUS_ESP);
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}
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static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
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{
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    ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
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    SysBusESPState *sysbus = SYSBUS_ESP(&es->esp);
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    ESPState *esp = &sysbus->esp;
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    esp->dma_memory_read = espdma_memory_read;
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    esp->dma_memory_write = espdma_memory_write;
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    esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
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    sysbus->it_shift = 2;
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    esp->dma_enabled = 1;
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    sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
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}
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static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = sparc32_espdma_device_realize;
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}
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static const TypeInfo sparc32_espdma_device_info = {
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    .name          = TYPE_SPARC32_ESPDMA_DEVICE,
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    .parent        = TYPE_SPARC32_DMA_DEVICE,
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    .instance_size = sizeof(ESPDMADeviceState),
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    .instance_init = sparc32_espdma_device_init,
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    .class_init    = sparc32_espdma_device_class_init,
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};
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static void sparc32_ledma_device_init(Object *obj)
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{
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    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
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    LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
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    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
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                          "ledma-mmio", DMA_SIZE);
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    object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
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}
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static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
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{
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    LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
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    SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
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    object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
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    sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
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}
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static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = sparc32_ledma_device_realize;
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}
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static const TypeInfo sparc32_ledma_device_info = {
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    .name          = TYPE_SPARC32_LEDMA_DEVICE,
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    .parent        = TYPE_SPARC32_DMA_DEVICE,
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    .instance_size = sizeof(LEDMADeviceState),
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    .instance_init = sparc32_ledma_device_init,
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    .class_init    = sparc32_ledma_device_class_init,
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};
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static void sparc32_dma_realize(DeviceState *dev, Error **errp)
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{
371
    SPARC32DMAState *s = SPARC32_DMA(dev);
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    DeviceState *espdma, *esp, *ledma, *lance;
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    SysBusDevice *sbd;
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    Object *iommu;
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    iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
377
    if (!iommu) {
378
        error_setg(errp, "unable to locate sun4m IOMMU device");
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        return;
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    }
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    espdma = DEVICE(&s->espdma);
383
    object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
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    sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
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    esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
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    sbd = SYS_BUS_DEVICE(esp);
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    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
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    qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
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    qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
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    sbd = SYS_BUS_DEVICE(espdma);
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    memory_region_add_subregion(&s->dmamem, 0x0,
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                                sysbus_mmio_get_region(sbd, 0));
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    ledma = DEVICE(&s->ledma);
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    object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
398
    sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
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400
    lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
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    sbd = SYS_BUS_DEVICE(lance);
402
    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
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    qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
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    sbd = SYS_BUS_DEVICE(ledma);
406
    memory_region_add_subregion(&s->dmamem, 0x10,
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                                sysbus_mmio_get_region(sbd, 0));
408

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    /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */
410
    memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
411
                             sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
412
    memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
413
}
414

415
static void sparc32_dma_init(Object *obj)
416
{
417
    SPARC32DMAState *s = SPARC32_DMA(obj);
418
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
419

420
    memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
421
    sysbus_init_mmio(sbd, &s->dmamem);
422

423
    object_initialize_child(obj, "espdma", &s->espdma,
424
                            TYPE_SPARC32_ESPDMA_DEVICE);
425
    object_initialize_child(obj, "ledma", &s->ledma,
426
                            TYPE_SPARC32_LEDMA_DEVICE);
427
}
428

429
static void sparc32_dma_class_init(ObjectClass *klass, void *data)
430
{
431
    DeviceClass *dc = DEVICE_CLASS(klass);
432

433
    dc->realize = sparc32_dma_realize;
434
}
435

436
static const TypeInfo sparc32_dma_info = {
437
    .name          = TYPE_SPARC32_DMA,
438
    .parent        = TYPE_SYS_BUS_DEVICE,
439
    .instance_size = sizeof(SPARC32DMAState),
440
    .instance_init = sparc32_dma_init,
441
    .class_init    = sparc32_dma_class_init,
442
};
443

444

445
static void sparc32_dma_register_types(void)
446
{
447
    type_register_static(&sparc32_dma_device_info);
448
    type_register_static(&sparc32_espdma_device_info);
449
    type_register_static(&sparc32_ledma_device_info);
450
    type_register_static(&sparc32_dma_info);
451
}
452

453
type_init(sparc32_dma_register_types)
454