qemu

1
/*
2
 * Arm PrimeCell PL080/PL081 DMA controller
3
 *
4
 * Copyright (c) 2006 CodeSourcery.
5
 * Written by Paul Brook
6
 *
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 * This code is licensed under the GPL.
8
 */
9

10
#include "qemu/osdep.h"
11
#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/dma/pl080.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
20

21
#define PL080_CONF_E    0x1
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#define PL080_CONF_M1   0x2
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#define PL080_CONF_M2   0x4
24

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#define PL080_CCONF_H   0x40000
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#define PL080_CCONF_A   0x20000
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#define PL080_CCONF_L   0x10000
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#define PL080_CCONF_ITC 0x08000
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#define PL080_CCONF_IE  0x04000
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#define PL080_CCONF_E   0x00001
31

32
#define PL080_CCTRL_I   0x80000000
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#define PL080_CCTRL_DI  0x08000000
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#define PL080_CCTRL_SI  0x04000000
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#define PL080_CCTRL_D   0x02000000
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#define PL080_CCTRL_S   0x01000000
37

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static const VMStateDescription vmstate_pl080_channel = {
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    .name = "pl080_channel",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(src, pl080_channel),
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        VMSTATE_UINT32(dest, pl080_channel),
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        VMSTATE_UINT32(lli, pl080_channel),
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        VMSTATE_UINT32(ctrl, pl080_channel),
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        VMSTATE_UINT32(conf, pl080_channel),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static const VMStateDescription vmstate_pl080 = {
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    .name = "pl080",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8(tc_int, PL080State),
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        VMSTATE_UINT8(tc_mask, PL080State),
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        VMSTATE_UINT8(err_int, PL080State),
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        VMSTATE_UINT8(err_mask, PL080State),
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        VMSTATE_UINT32(conf, PL080State),
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        VMSTATE_UINT32(sync, PL080State),
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        VMSTATE_UINT32(req_single, PL080State),
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        VMSTATE_UINT32(req_burst, PL080State),
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        VMSTATE_UINT8(tc_int, PL080State),
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        VMSTATE_UINT8(tc_int, PL080State),
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        VMSTATE_UINT8(tc_int, PL080State),
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        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
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                             1, vmstate_pl080_channel, pl080_channel),
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        VMSTATE_INT32(running, PL080State),
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        VMSTATE_END_OF_LIST()
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    }
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};
74

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static const unsigned char pl080_id[] =
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{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
77

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static const unsigned char pl081_id[] =
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{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
80

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static void pl080_update(PL080State *s)
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{
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    bool tclevel = (s->tc_int & s->tc_mask);
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    bool errlevel = (s->err_int & s->err_mask);
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    qemu_set_irq(s->interr, errlevel);
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    qemu_set_irq(s->inttc, tclevel);
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    qemu_set_irq(s->irq, errlevel || tclevel);
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}
90

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static void pl080_run(PL080State *s)
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{
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    int c;
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    int flow;
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    pl080_channel *ch;
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    int swidth;
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    int dwidth;
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    int xsize;
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    int n;
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    int src_id;
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    int dest_id;
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    int size;
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    uint8_t buff[4];
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    uint32_t req;
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106
    s->tc_mask = 0;
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    for (c = 0; c < s->nchannels; c++) {
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        if (s->chan[c].conf & PL080_CCONF_ITC)
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            s->tc_mask |= 1 << c;
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        if (s->chan[c].conf & PL080_CCONF_IE)
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            s->err_mask |= 1 << c;
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    }
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    if ((s->conf & PL080_CONF_E) == 0)
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        return;
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    /* If we are already in the middle of a DMA operation then indicate that
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       there may be new DMA requests and return immediately.  */
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    if (s->running) {
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        s->running++;
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        return;
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    }
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    s->running = 1;
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    while (s->running) {
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        for (c = 0; c < s->nchannels; c++) {
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            ch = &s->chan[c];
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again:
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            /* Test if thiws channel has any pending DMA requests.  */
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            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
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                    != PL080_CCONF_E)
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                continue;
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            flow = (ch->conf >> 11) & 7;
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            if (flow >= 4) {
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                hw_error(
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                    "pl080_run: Peripheral flow control not implemented\n");
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            }
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            src_id = (ch->conf >> 1) & 0x1f;
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            dest_id = (ch->conf >> 6) & 0x1f;
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            size = ch->ctrl & 0xfff;
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            req = s->req_single | s->req_burst;
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            switch (flow) {
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            case 0:
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                break;
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            case 1:
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                if ((req & (1u << dest_id)) == 0)
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                    size = 0;
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                break;
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            case 2:
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                if ((req & (1u << src_id)) == 0)
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                    size = 0;
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                break;
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            case 3:
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                if ((req & (1u << src_id)) == 0
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                        || (req & (1u << dest_id)) == 0)
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                    size = 0;
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                break;
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            }
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            if (!size)
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                continue;
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            /* Transfer one element.  */
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            /* ??? Should transfer multiple elements for a burst request.  */
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            /* ??? Unclear what the proper behavior is when source and
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               destination widths are different.  */
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            swidth = 1 << ((ch->ctrl >> 18) & 7);
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            dwidth = 1 << ((ch->ctrl >> 21) & 7);
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            for (n = 0; n < dwidth; n+= swidth) {
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                address_space_read(&s->downstream_as, ch->src,
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                                   MEMTXATTRS_UNSPECIFIED, buff + n, swidth);
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                if (ch->ctrl & PL080_CCTRL_SI)
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                    ch->src += swidth;
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            }
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            xsize = (dwidth < swidth) ? swidth : dwidth;
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            /* ??? This may pad the value incorrectly for dwidth < 32.  */
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            for (n = 0; n < xsize; n += dwidth) {
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                address_space_write(&s->downstream_as, ch->dest + n,
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                                    MEMTXATTRS_UNSPECIFIED, buff + n, dwidth);
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                if (ch->ctrl & PL080_CCTRL_DI)
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                    ch->dest += swidth;
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            }
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            size--;
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            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
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            if (size == 0) {
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                /* Transfer complete.  */
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                if (ch->lli) {
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                    ch->src = address_space_ldl_le(&s->downstream_as,
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                                                   ch->lli,
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                                                   MEMTXATTRS_UNSPECIFIED,
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                                                   NULL);
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                    ch->dest = address_space_ldl_le(&s->downstream_as,
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                                                    ch->lli + 4,
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                                                    MEMTXATTRS_UNSPECIFIED,
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                                                    NULL);
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                    ch->ctrl = address_space_ldl_le(&s->downstream_as,
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                                                    ch->lli + 12,
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                                                    MEMTXATTRS_UNSPECIFIED,
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                                                    NULL);
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                    ch->lli = address_space_ldl_le(&s->downstream_as,
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                                                   ch->lli + 8,
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                                                   MEMTXATTRS_UNSPECIFIED,
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                                                   NULL);
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                } else {
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                    ch->conf &= ~PL080_CCONF_E;
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                }
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                if (ch->ctrl & PL080_CCTRL_I) {
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                    s->tc_int |= 1 << c;
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                }
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            }
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            goto again;
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        }
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        if (--s->running)
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            s->running = 1;
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    }
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}
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static uint64_t pl080_read(void *opaque, hwaddr offset,
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                           unsigned size)
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{
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    PL080State *s = (PL080State *)opaque;
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    uint32_t i;
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    uint32_t mask;
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    if (offset >= 0xfe0 && offset < 0x1000) {
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        if (s->nchannels == 8) {
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            return pl080_id[(offset - 0xfe0) >> 2];
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        } else {
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            return pl081_id[(offset - 0xfe0) >> 2];
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        }
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    }
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    if (offset >= 0x100 && offset < 0x200) {
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        i = (offset & 0xe0) >> 5;
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        if (i >= s->nchannels)
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            goto bad_offset;
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        switch ((offset >> 2) & 7) {
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        case 0: /* SrcAddr */
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            return s->chan[i].src;
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        case 1: /* DestAddr */
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            return s->chan[i].dest;
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        case 2: /* LLI */
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            return s->chan[i].lli;
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        case 3: /* Control */
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            return s->chan[i].ctrl;
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        case 4: /* Configuration */
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            return s->chan[i].conf;
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        default:
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            goto bad_offset;
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        }
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    }
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    switch (offset >> 2) {
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    case 0: /* IntStatus */
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        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
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    case 1: /* IntTCStatus */
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        return (s->tc_int & s->tc_mask);
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    case 3: /* IntErrorStatus */
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        return (s->err_int & s->err_mask);
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    case 5: /* RawIntTCStatus */
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        return s->tc_int;
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    case 6: /* RawIntErrorStatus */
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        return s->err_int;
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    case 7: /* EnbldChns */
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        mask = 0;
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        for (i = 0; i < s->nchannels; i++) {
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            if (s->chan[i].conf & PL080_CCONF_E)
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                mask |= 1 << i;
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        }
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        return mask;
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    case 8: /* SoftBReq */
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    case 9: /* SoftSReq */
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    case 10: /* SoftLBReq */
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    case 11: /* SoftLSReq */
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        /* ??? Implement these. */
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        return 0;
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    case 12: /* Configuration */
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        return s->conf;
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    case 13: /* Sync */
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        return s->sync;
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    default:
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    bad_offset:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "pl080_read: Bad offset %x\n", (int)offset);
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        return 0;
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    }
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}
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static void pl080_write(void *opaque, hwaddr offset,
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                        uint64_t value, unsigned size)
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{
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    PL080State *s = (PL080State *)opaque;
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    int i;
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    if (offset >= 0x100 && offset < 0x200) {
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        i = (offset & 0xe0) >> 5;
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        if (i >= s->nchannels)
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            goto bad_offset;
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        switch ((offset >> 2) & 7) {
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        case 0: /* SrcAddr */
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            s->chan[i].src = value;
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            break;
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        case 1: /* DestAddr */
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            s->chan[i].dest = value;
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            break;
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        case 2: /* LLI */
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            s->chan[i].lli = value;
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            break;
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        case 3: /* Control */
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            s->chan[i].ctrl = value;
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            break;
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        case 4: /* Configuration */
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            s->chan[i].conf = value;
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            pl080_run(s);
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            break;
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        }
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        return;
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    }
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    switch (offset >> 2) {
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    case 2: /* IntTCClear */
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        s->tc_int &= ~value;
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        break;
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    case 4: /* IntErrorClear */
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        s->err_int &= ~value;
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        break;
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    case 8: /* SoftBReq */
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    case 9: /* SoftSReq */
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    case 10: /* SoftLBReq */
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    case 11: /* SoftLSReq */
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        /* ??? Implement these.  */
328
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
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        break;
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    case 12: /* Configuration */
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        s->conf = value;
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        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
333
            qemu_log_mask(LOG_UNIMP,
334
                          "pl080_write: Big-endian DMA not implemented\n");
335
        }
336
        pl080_run(s);
337
        break;
338
    case 13: /* Sync */
339
        s->sync = value;
340
        break;
341
    default:
342
    bad_offset:
343
        qemu_log_mask(LOG_GUEST_ERROR,
344
                      "pl080_write: Bad offset %x\n", (int)offset);
345
    }
346
    pl080_update(s);
347
}
348

349
static const MemoryRegionOps pl080_ops = {
350
    .read = pl080_read,
351
    .write = pl080_write,
352
    .endianness = DEVICE_NATIVE_ENDIAN,
353
};
354

355
static void pl080_reset(DeviceState *dev)
356
{
357
    PL080State *s = PL080(dev);
358
    int i;
359

360
    s->tc_int = 0;
361
    s->tc_mask = 0;
362
    s->err_int = 0;
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    s->err_mask = 0;
364
    s->conf = 0;
365
    s->sync = 0;
366
    s->req_single = 0;
367
    s->req_burst = 0;
368
    s->running = 0;
369

370
    for (i = 0; i < s->nchannels; i++) {
371
        s->chan[i].src = 0;
372
        s->chan[i].dest = 0;
373
        s->chan[i].lli = 0;
374
        s->chan[i].ctrl = 0;
375
        s->chan[i].conf = 0;
376
    }
377
}
378

379
static void pl080_init(Object *obj)
380
{
381
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
382
    PL080State *s = PL080(obj);
383

384
    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
385
    sysbus_init_mmio(sbd, &s->iomem);
386
    sysbus_init_irq(sbd, &s->irq);
387
    sysbus_init_irq(sbd, &s->interr);
388
    sysbus_init_irq(sbd, &s->inttc);
389
    s->nchannels = 8;
390
}
391

392
static void pl080_realize(DeviceState *dev, Error **errp)
393
{
394
    PL080State *s = PL080(dev);
395

396
    if (!s->downstream) {
397
        error_setg(errp, "PL080 'downstream' link not set");
398
        return;
399
    }
400

401
    address_space_init(&s->downstream_as, s->downstream, "pl080-downstream");
402
}
403

404
static void pl081_init(Object *obj)
405
{
406
    PL080State *s = PL080(obj);
407

408
    s->nchannels = 2;
409
}
410

411
static Property pl080_properties[] = {
412
    DEFINE_PROP_LINK("downstream", PL080State, downstream,
413
                     TYPE_MEMORY_REGION, MemoryRegion *),
414
    DEFINE_PROP_END_OF_LIST(),
415
};
416

417
static void pl080_class_init(ObjectClass *oc, void *data)
418
{
419
    DeviceClass *dc = DEVICE_CLASS(oc);
420

421
    dc->vmsd = &vmstate_pl080;
422
    dc->realize = pl080_realize;
423
    device_class_set_props(dc, pl080_properties);
424
    dc->reset = pl080_reset;
425
}
426

427
static const TypeInfo pl080_info = {
428
    .name          = TYPE_PL080,
429
    .parent        = TYPE_SYS_BUS_DEVICE,
430
    .instance_size = sizeof(PL080State),
431
    .instance_init = pl080_init,
432
    .class_init    = pl080_class_init,
433
};
434

435
static const TypeInfo pl081_info = {
436
    .name          = TYPE_PL081,
437
    .parent        = TYPE_PL080,
438
    .instance_init = pl081_init,
439
};
440

441
/* The PL080 and PL081 are the same except for the number of channels
442
   they implement (8 and 2 respectively).  */
443
static void pl080_register_types(void)
444
{
445
    type_register_static(&pl080_info);
446
    type_register_static(&pl081_info);
447
}
448

449
type_init(pl080_register_types)
450