qemu

1
/*
2
 * RealView ARM11MPCore internal peripheral emulation
3
 *
4
 * Copyright (c) 2006-2007 CodeSourcery.
5
 * Copyright (c) 2013 SUSE LINUX Products GmbH
6
 * Written by Paul Brook and Andreas Färber
7
 *
8
 * This code is licensed under the GPL.
9
 */
10

11
#include "qemu/osdep.h"
12
#include "qapi/error.h"
13
#include "qemu/module.h"
14
#include "hw/cpu/arm11mpcore.h"
15
#include "hw/intc/realview_gic.h"
16
#include "hw/irq.h"
17
#include "hw/qdev-properties.h"
18
#include "qom/object.h"
19

20
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
21
OBJECT_DECLARE_SIMPLE_TYPE(mpcore_rirq_state, REALVIEW_MPCORE_RIRQ)
22

23
/* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
24
   controllers.  The output of these, plus some of the raw input lines
25
   are fed into a single SMP-aware interrupt controller on the CPU.  */
26
struct mpcore_rirq_state {
27
    SysBusDevice parent_obj;
28

29
    qemu_irq cpuic[32];
30
    qemu_irq rvic[4][64];
31
    uint32_t num_cpu;
32

33
    ARM11MPCorePriveState priv;
34
    RealViewGICState gic[4];
35
};
36

37
/* Map baseboard IRQs onto CPU IRQ lines.  */
38
static const int mpcore_irq_map[32] = {
39
    -1, -1, -1, -1,  1,  2, -1, -1,
40
    -1, -1,  6, -1,  4,  5, -1, -1,
41
    -1, 14, 15,  0,  7,  8, -1, -1,
42
    -1, -1, -1, -1,  9,  3, -1, -1,
43
};
44

45
static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
46
{
47
    mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
48
    int i;
49

50
    for (i = 0; i < 4; i++) {
51
        qemu_set_irq(s->rvic[i][irq], level);
52
    }
53
    if (irq < 32) {
54
        irq = mpcore_irq_map[irq];
55
        if (irq >= 0) {
56
            qemu_set_irq(s->cpuic[irq], level);
57
        }
58
    }
59
}
60

61
static void realview_mpcore_realize(DeviceState *dev, Error **errp)
62
{
63
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
64
    mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
65
    DeviceState *priv = DEVICE(&s->priv);
66
    DeviceState *gic;
67
    SysBusDevice *gicbusdev;
68
    int n;
69
    int i;
70

71
    qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
72
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) {
73
        return;
74
    }
75
    sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
76
    for (i = 0; i < 32; i++) {
77
        s->cpuic[i] = qdev_get_gpio_in(priv, i);
78
    }
79
    /* ??? IRQ routing is hardcoded to "normal" mode.  */
80
    for (n = 0; n < 4; n++) {
81
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), errp)) {
82
            return;
83
        }
84
        gic = DEVICE(&s->gic[n]);
85
        gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
86
        sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
87
        sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
88
        for (i = 0; i < 64; i++) {
89
            s->rvic[n][i] = qdev_get_gpio_in(gic, i);
90
        }
91
    }
92
    qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
93
}
94

95
static void mpcore_rirq_init(Object *obj)
96
{
97
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
98
    mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
99
    SysBusDevice *privbusdev;
100
    int i;
101

102
    object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
103
    privbusdev = SYS_BUS_DEVICE(&s->priv);
104
    sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
105

106
    for (i = 0; i < 4; i++) {
107
        object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC);
108
    }
109
}
110

111
static Property mpcore_rirq_properties[] = {
112
    DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
113
    DEFINE_PROP_END_OF_LIST(),
114
};
115

116
static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
117
{
118
    DeviceClass *dc = DEVICE_CLASS(klass);
119

120
    dc->realize = realview_mpcore_realize;
121
    device_class_set_props(dc, mpcore_rirq_properties);
122
}
123

124
static const TypeInfo mpcore_rirq_info = {
125
    .name          = TYPE_REALVIEW_MPCORE_RIRQ,
126
    .parent        = TYPE_SYS_BUS_DEVICE,
127
    .instance_size = sizeof(mpcore_rirq_state),
128
    .instance_init = mpcore_rirq_init,
129
    .class_init    = mpcore_rirq_class_init,
130
};
131

132
static void realview_mpcore_register_types(void)
133
{
134
    type_register_static(&mpcore_rirq_info);
135
}
136

137
type_init(realview_mpcore_register_types)
138