qemu

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/*
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 * Cortex-A9MPCore internal peripheral emulation.
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 *
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 * Copyright (c) 2009 CodeSourcery.
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 * Copyright (c) 2011 Linaro Limited.
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 * Written by Paul Brook, Peter Maydell.
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 *
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 * This code is licensed under the GPL.
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 */
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/core/cpu.h"
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#include "target/arm/cpu-qom.h"
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#define A9_GIC_NUM_PRIORITY_BITS    5
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static void a9mp_priv_set_irq(void *opaque, int irq, int level)
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{
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    A9MPPrivState *s = (A9MPPrivState *)opaque;
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    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
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}
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static void a9mp_priv_initfn(Object *obj)
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{
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    A9MPPrivState *s = A9MPCORE_PRIV(obj);
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    memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
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    object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU);
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    object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
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    object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER);
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    object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
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    object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER);
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}
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static void a9mp_priv_realize(DeviceState *dev, Error **errp)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    A9MPPrivState *s = A9MPCORE_PRIV(dev);
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    DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
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    SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
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                 *wdtbusdev;
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    int i;
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    bool has_el3;
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    CPUState *cpu0;
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    Object *cpuobj;
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    cpu0 = qemu_get_cpu(0);
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    cpuobj = OBJECT(cpu0);
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    if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
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        /* We might allow Cortex-A5 once we model it */
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        error_setg(errp,
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                   "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU");
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        return;
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    }
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    scudev = DEVICE(&s->scu);
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    qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
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    if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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        return;
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    }
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    scubusdev = SYS_BUS_DEVICE(&s->scu);
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    gicdev = DEVICE(&s->gic);
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    qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
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    qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
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    qdev_prop_set_uint32(gicdev, "num-priority-bits",
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                         A9_GIC_NUM_PRIORITY_BITS);
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    /* Make the GIC's TZ support match the CPUs. We assume that
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     * either all the CPUs have TZ, or none do.
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     */
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    has_el3 = object_property_find(cpuobj, "has_el3") &&
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        object_property_get_bool(cpuobj, "has_el3", &error_abort);
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    qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
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    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
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        return;
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    }
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    gicbusdev = SYS_BUS_DEVICE(&s->gic);
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    /* Pass through outbound IRQ lines from the GIC */
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    sysbus_pass_irq(sbd, gicbusdev);
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    /* Pass through inbound GPIO lines to the GIC */
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    qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
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    gtimerdev = DEVICE(&s->gtimer);
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    qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
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    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) {
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        return;
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    }
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    gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
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    mptimerdev = DEVICE(&s->mptimer);
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    qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
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    if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) {
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        return;
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    }
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    mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
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    wdtdev = DEVICE(&s->wdt);
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    qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
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    if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) {
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        return;
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    }
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    wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
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    /* Memory map (addresses are offsets from PERIPHBASE):
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     *  0x0000-0x00ff -- Snoop Control Unit
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     *  0x0100-0x01ff -- GIC CPU interface
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     *  0x0200-0x02ff -- Global Timer
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     *  0x0300-0x05ff -- nothing
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     *  0x0600-0x06ff -- private timers and watchdogs
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     *  0x0700-0x0fff -- nothing
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     *  0x1000-0x1fff -- GIC Distributor
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     */
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    memory_region_add_subregion(&s->container, 0,
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                                sysbus_mmio_get_region(scubusdev, 0));
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    /* GIC CPU interface */
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    memory_region_add_subregion(&s->container, 0x100,
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                                sysbus_mmio_get_region(gicbusdev, 1));
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    memory_region_add_subregion(&s->container, 0x200,
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                                sysbus_mmio_get_region(gtimerbusdev, 0));
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    /* Note that the A9 exposes only the "timer/watchdog for this core"
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     * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
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     */
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    memory_region_add_subregion(&s->container, 0x600,
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                                sysbus_mmio_get_region(mptimerbusdev, 0));
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    memory_region_add_subregion(&s->container, 0x620,
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                                sysbus_mmio_get_region(wdtbusdev, 0));
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    memory_region_add_subregion(&s->container, 0x1000,
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                                sysbus_mmio_get_region(gicbusdev, 0));
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    /* Wire up the interrupt from each watchdog and timer.
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     * For each core the global timer is PPI 27, the private
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     * timer is PPI 29 and the watchdog PPI 30.
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     */
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    for (i = 0; i < s->num_cpu; i++) {
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        int ppibase = (s->num_irq - 32) + i * 32;
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        sysbus_connect_irq(gtimerbusdev, i,
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                           qdev_get_gpio_in(gicdev, ppibase + 27));
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        sysbus_connect_irq(mptimerbusdev, i,
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                           qdev_get_gpio_in(gicdev, ppibase + 29));
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        sysbus_connect_irq(wdtbusdev, i,
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                           qdev_get_gpio_in(gicdev, ppibase + 30));
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    }
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}
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static Property a9mp_priv_properties[] = {
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    DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
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    /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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     * IRQ lines (with another 32 internal). We default to 64+32, which
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     * is the number provided by the Cortex-A9MP test chip in the
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     * Realview PBX-A9 and Versatile Express A9 development boards.
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     * Other boards may differ and should set this property appropriately.
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     */
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    DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void a9mp_priv_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = a9mp_priv_realize;
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    device_class_set_props(dc, a9mp_priv_properties);
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}
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static const TypeInfo a9mp_priv_info = {
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    .name          = TYPE_A9MPCORE_PRIV,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(A9MPPrivState),
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    .instance_init = a9mp_priv_initfn,
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    .class_init    = a9mp_priv_class_init,
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};
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static void a9mp_register_types(void)
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{
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    type_register_static(&a9mp_priv_info);
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}
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type_init(a9mp_register_types)
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