qemu

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/*
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 * QEMU model of the UART on the SiFive E300 and U500 series SOCs.
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 *
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 * Copyright (c) 2016 Stefan O'Rear
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2 or later, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "chardev/char.h"
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#include "chardev/char-fe.h"
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#include "hw/irq.h"
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#include "hw/char/sifive_uart.h"
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#include "hw/qdev-properties-system.h"
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/*
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 * Not yet implemented:
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 *
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 * Transmit FIFO using "qemu/fifo8.h"
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 */
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/* Returns the state of the IP (interrupt pending) register */
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static uint64_t sifive_uart_ip(SiFiveUARTState *s)
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{
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    uint64_t ret = 0;
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    uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl);
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    uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl);
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    if (txcnt != 0) {
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        ret |= SIFIVE_UART_IP_TXWM;
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    }
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    if (s->rx_fifo_len > rxcnt) {
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        ret |= SIFIVE_UART_IP_RXWM;
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    }
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    return ret;
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}
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static void sifive_uart_update_irq(SiFiveUARTState *s)
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{
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    int cond = 0;
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    if ((s->ie & SIFIVE_UART_IE_TXWM) ||
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        ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) {
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        cond = 1;
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    }
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    if (cond) {
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        qemu_irq_raise(s->irq);
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    } else {
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        qemu_irq_lower(s->irq);
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    }
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}
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static uint64_t
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sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    SiFiveUARTState *s = opaque;
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    unsigned char r;
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    switch (addr) {
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    case SIFIVE_UART_RXFIFO:
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        if (s->rx_fifo_len) {
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            r = s->rx_fifo[0];
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            memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
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            s->rx_fifo_len--;
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            qemu_chr_fe_accept_input(&s->chr);
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            sifive_uart_update_irq(s);
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            return r;
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        }
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        return 0x80000000;
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    case SIFIVE_UART_TXFIFO:
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        return 0; /* Should check tx fifo */
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    case SIFIVE_UART_IE:
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        return s->ie;
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    case SIFIVE_UART_IP:
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        return sifive_uart_ip(s);
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    case SIFIVE_UART_TXCTRL:
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        return s->txctrl;
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    case SIFIVE_UART_RXCTRL:
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        return s->rxctrl;
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    case SIFIVE_UART_DIV:
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        return s->div;
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    }
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    qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
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                  __func__, (int)addr);
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    return 0;
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}
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static void
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sifive_uart_write(void *opaque, hwaddr addr,
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                  uint64_t val64, unsigned int size)
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{
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    SiFiveUARTState *s = opaque;
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    uint32_t value = val64;
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    unsigned char ch = value;
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    switch (addr) {
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    case SIFIVE_UART_TXFIFO:
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        qemu_chr_fe_write(&s->chr, &ch, 1);
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        sifive_uart_update_irq(s);
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        return;
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    case SIFIVE_UART_IE:
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        s->ie = val64;
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        sifive_uart_update_irq(s);
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        return;
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    case SIFIVE_UART_TXCTRL:
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        s->txctrl = val64;
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        return;
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    case SIFIVE_UART_RXCTRL:
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        s->rxctrl = val64;
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        return;
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    case SIFIVE_UART_DIV:
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        s->div = val64;
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        return;
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    }
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    qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
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                  __func__, (int)addr, (int)value);
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}
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static const MemoryRegionOps sifive_uart_ops = {
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    .read = sifive_uart_read,
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    .write = sifive_uart_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4
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    }
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};
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static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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    SiFiveUARTState *s = opaque;
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    /* Got a byte.  */
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    if (s->rx_fifo_len >= sizeof(s->rx_fifo)) {
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        printf("WARNING: UART dropped char.\n");
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        return;
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    }
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    s->rx_fifo[s->rx_fifo_len++] = *buf;
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    sifive_uart_update_irq(s);
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}
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static int sifive_uart_can_rx(void *opaque)
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{
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    SiFiveUARTState *s = opaque;
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    return s->rx_fifo_len < sizeof(s->rx_fifo);
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}
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static void sifive_uart_event(void *opaque, QEMUChrEvent event)
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{
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}
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static int sifive_uart_be_change(void *opaque)
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{
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    SiFiveUARTState *s = opaque;
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    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
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                             sifive_uart_event, sifive_uart_be_change, s,
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                             NULL, true);
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    return 0;
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}
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static Property sifive_uart_properties[] = {
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    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void sifive_uart_init(Object *obj)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    SiFiveUARTState *s = SIFIVE_UART(obj);
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    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
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                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
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    sysbus_init_mmio(sbd, &s->mmio);
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    sysbus_init_irq(sbd, &s->irq);
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}
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static void sifive_uart_realize(DeviceState *dev, Error **errp)
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{
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    SiFiveUARTState *s = SIFIVE_UART(dev);
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    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
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                             sifive_uart_event, sifive_uart_be_change, s,
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                             NULL, true);
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}
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static void sifive_uart_reset_enter(Object *obj, ResetType type)
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{
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    SiFiveUARTState *s = SIFIVE_UART(obj);
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    s->ie = 0;
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    s->ip = 0;
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    s->txctrl = 0;
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    s->rxctrl = 0;
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    s->div = 0;
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    s->rx_fifo_len = 0;
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}
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static void sifive_uart_reset_hold(Object *obj, ResetType type)
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{
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    SiFiveUARTState *s = SIFIVE_UART(obj);
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    qemu_irq_lower(s->irq);
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}
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static const VMStateDescription vmstate_sifive_uart = {
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    .name = TYPE_SIFIVE_UART,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
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                            SIFIVE_UART_RX_FIFO_SIZE),
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        VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
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        VMSTATE_UINT32(ie, SiFiveUARTState),
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        VMSTATE_UINT32(ip, SiFiveUARTState),
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        VMSTATE_UINT32(txctrl, SiFiveUARTState),
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        VMSTATE_UINT32(rxctrl, SiFiveUARTState),
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        VMSTATE_UINT32(div, SiFiveUARTState),
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        VMSTATE_END_OF_LIST()
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    },
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};
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static void sifive_uart_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(oc);
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    ResettableClass *rc = RESETTABLE_CLASS(oc);
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    dc->realize = sifive_uart_realize;
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    dc->vmsd = &vmstate_sifive_uart;
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    rc->phases.enter = sifive_uart_reset_enter;
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    rc->phases.hold  = sifive_uart_reset_hold;
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    device_class_set_props(dc, sifive_uart_properties);
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    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static const TypeInfo sifive_uart_info = {
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    .name          = TYPE_SIFIVE_UART,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(SiFiveUARTState),
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    .instance_init = sifive_uart_init,
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    .class_init    = sifive_uart_class_init,
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};
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static void sifive_uart_register_types(void)
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{
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    type_register_static(&sifive_uart_info);
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}
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type_init(sifive_uart_register_types)
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/*
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 * Create UART device.
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 */
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SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
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    Chardev *chr, qemu_irq irq)
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{
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    DeviceState *dev;
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    SysBusDevice *s;
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    dev = qdev_new("riscv.sifive.uart");
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    s = SYS_BUS_DEVICE(dev);
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    qdev_prop_set_chr(dev, "chardev", chr);
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    sysbus_realize_and_unref(s, &error_fatal);
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    memory_region_add_subregion(address_space, base,
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                                sysbus_mmio_get_region(s, 0));
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    sysbus_connect_irq(s, 0, irq);
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    return SIFIVE_UART(dev);
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}
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