qemu

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/*
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 * SHAKTI UART
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 *
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 * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/char/shakti_uart.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "qemu/log.h"
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static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
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{
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    ShaktiUartState *s = opaque;
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    switch (addr) {
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    case SHAKTI_UART_BAUD:
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        return s->uart_baud;
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    case SHAKTI_UART_RX:
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        qemu_chr_fe_accept_input(&s->chr);
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        s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
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        return s->uart_rx;
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    case SHAKTI_UART_STATUS:
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        return s->uart_status;
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    case SHAKTI_UART_DELAY:
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        return s->uart_delay;
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    case SHAKTI_UART_CONTROL:
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        return s->uart_control;
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    case SHAKTI_UART_INT_EN:
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        return s->uart_interrupt;
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    case SHAKTI_UART_IQ_CYCLES:
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        return s->uart_iq_cycles;
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    case SHAKTI_UART_RX_THRES:
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        return s->uart_rx_threshold;
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    default:
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        /* Also handles TX REG which is write only */
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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    }
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    return 0;
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}
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static void shakti_uart_write(void *opaque, hwaddr addr,
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                              uint64_t data, unsigned size)
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{
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    ShaktiUartState *s = opaque;
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    uint32_t value = data;
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    uint8_t ch;
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    switch (addr) {
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    case SHAKTI_UART_BAUD:
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        s->uart_baud = value;
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        break;
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    case SHAKTI_UART_TX:
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        ch = value;
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        qemu_chr_fe_write_all(&s->chr, &ch, 1);
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        s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
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        break;
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    case SHAKTI_UART_STATUS:
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        s->uart_status = value;
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        break;
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    case SHAKTI_UART_DELAY:
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        s->uart_delay = value;
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        break;
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    case SHAKTI_UART_CONTROL:
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        s->uart_control = value;
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        break;
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    case SHAKTI_UART_INT_EN:
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        s->uart_interrupt = value;
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        break;
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    case SHAKTI_UART_IQ_CYCLES:
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        s->uart_iq_cycles = value;
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        break;
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    case SHAKTI_UART_RX_THRES:
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        s->uart_rx_threshold = value;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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    }
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}
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static const MemoryRegionOps shakti_uart_ops = {
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    .read = shakti_uart_read,
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    .write = shakti_uart_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .impl = {.min_access_size = 1, .max_access_size = 4},
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    .valid = {.min_access_size = 1, .max_access_size = 4},
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};
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static void shakti_uart_reset(DeviceState *dev)
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{
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    ShaktiUartState *s = SHAKTI_UART(dev);
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    s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
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    s->uart_tx = 0x0;
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    s->uart_rx = 0x0;
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    s->uart_status = 0x0000;
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    s->uart_delay = 0x0000;
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    s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
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    s->uart_interrupt = 0x0000;
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    s->uart_iq_cycles = 0x00;
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    s->uart_rx_threshold = 0x00;
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}
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static int shakti_uart_can_receive(void *opaque)
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{
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    ShaktiUartState *s = opaque;
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    return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
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}
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static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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    ShaktiUartState *s = opaque;
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    s->uart_rx = *buf;
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    s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
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}
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static void shakti_uart_realize(DeviceState *dev, Error **errp)
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{
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    ShaktiUartState *sus = SHAKTI_UART(dev);
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    qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
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                             shakti_uart_receive, NULL, NULL, sus, NULL, true);
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}
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static void shakti_uart_instance_init(Object *obj)
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{
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    ShaktiUartState *sus = SHAKTI_UART(obj);
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    memory_region_init_io(&sus->mmio,
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                          obj,
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                          &shakti_uart_ops,
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                          sus,
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                          TYPE_SHAKTI_UART,
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                          0x1000);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
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}
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static Property shakti_uart_properties[] = {
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    DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void shakti_uart_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = shakti_uart_reset;
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    dc->realize = shakti_uart_realize;
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    device_class_set_props(dc, shakti_uart_properties);
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    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static const TypeInfo shakti_uart_info = {
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    .name = TYPE_SHAKTI_UART,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(ShaktiUartState),
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    .class_init = shakti_uart_class_init,
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    .instance_init = shakti_uart_instance_init,
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};
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static void shakti_uart_register_types(void)
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{
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    type_register_static(&shakti_uart_info);
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}
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type_init(shakti_uart_register_types)
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