qemu

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/*
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 * QEMU SCI/SCIF serial port emulation
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 *
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 * Copyright (c) 2007 Magnus Damm
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 *
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 * Based on serial.c - QEMU 16450 UART emulation
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sh4/sh.h"
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#include "chardev/char-fe.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "trace.h"
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#define SH_SERIAL_FLAG_TEND (1 << 0)
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#define SH_SERIAL_FLAG_TDE  (1 << 1)
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#define SH_SERIAL_FLAG_RDF  (1 << 2)
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#define SH_SERIAL_FLAG_BRK  (1 << 3)
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#define SH_SERIAL_FLAG_DR   (1 << 4)
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#define SH_RX_FIFO_LENGTH (16)
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OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL)
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struct SHSerialState {
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    SysBusDevice parent;
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    uint8_t smr;
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    uint8_t brr;
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    uint8_t scr;
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    uint8_t dr; /* ftdr / tdr */
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    uint8_t sr; /* fsr / ssr */
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    uint16_t fcr;
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    uint8_t sptr;
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    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
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    uint8_t rx_cnt;
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    uint8_t rx_tail;
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    uint8_t rx_head;
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    uint8_t feat;
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    int flags;
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    int rtrg;
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    CharBackend chr;
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    QEMUTimer fifo_timeout_timer;
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    uint64_t etu; /* Elementary Time Unit (ns) */
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    qemu_irq eri;
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    qemu_irq rxi;
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    qemu_irq txi;
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    qemu_irq tei;
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    qemu_irq bri;
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};
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typedef struct {} SHSerialStateClass;
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OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE)
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static void sh_serial_clear_fifo(SHSerialState *s)
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{
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    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
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    s->rx_cnt = 0;
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    s->rx_head = 0;
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    s->rx_tail = 0;
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}
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static void sh_serial_write(void *opaque, hwaddr offs,
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                            uint64_t val, unsigned size)
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{
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    SHSerialState *s = opaque;
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    DeviceState *d = DEVICE(s);
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    unsigned char ch;
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    trace_sh_serial_write(d->id, size, offs, val);
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    switch (offs) {
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    case 0x00: /* SMR */
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        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
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        return;
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    case 0x04: /* BRR */
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        s->brr = val;
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        return;
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    case 0x08: /* SCR */
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        /* TODO : For SH7751, SCIF mask should be 0xfb. */
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        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
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        if (!(val & (1 << 5))) {
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            s->flags |= SH_SERIAL_FLAG_TEND;
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        }
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        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
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            qemu_set_irq(s->txi, val & (1 << 7));
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        }
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        if (!(val & (1 << 6))) {
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            qemu_set_irq(s->rxi, 0);
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        }
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        return;
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    case 0x0c: /* FTDR / TDR */
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        if (qemu_chr_fe_backend_connected(&s->chr)) {
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            ch = val;
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            /*
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             * XXX this blocks entire thread. Rewrite to use
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             * qemu_chr_fe_write and background I/O callbacks
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             */
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            qemu_chr_fe_write_all(&s->chr, &ch, 1);
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        }
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        s->dr = val;
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        s->flags &= ~SH_SERIAL_FLAG_TDE;
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        return;
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#if 0
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    case 0x14: /* FRDR / RDR */
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        ret = 0;
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        break;
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#endif
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    }
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    if (s->feat & SH_SERIAL_FEAT_SCIF) {
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        switch (offs) {
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        case 0x10: /* FSR */
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            if (!(val & (1 << 6))) {
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                s->flags &= ~SH_SERIAL_FLAG_TEND;
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            }
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            if (!(val & (1 << 5))) {
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                s->flags &= ~SH_SERIAL_FLAG_TDE;
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            }
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            if (!(val & (1 << 4))) {
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                s->flags &= ~SH_SERIAL_FLAG_BRK;
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            }
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            if (!(val & (1 << 1))) {
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                s->flags &= ~SH_SERIAL_FLAG_RDF;
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            }
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            if (!(val & (1 << 0))) {
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                s->flags &= ~SH_SERIAL_FLAG_DR;
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            }
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            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
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                if (s->rxi) {
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                    qemu_set_irq(s->rxi, 0);
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                }
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            }
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            return;
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        case 0x18: /* FCR */
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            s->fcr = val;
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            switch ((val >> 6) & 3) {
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            case 0:
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                s->rtrg = 1;
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                break;
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            case 1:
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                s->rtrg = 4;
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                break;
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            case 2:
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                s->rtrg = 8;
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                break;
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            case 3:
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                s->rtrg = 14;
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                break;
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            }
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            if (val & (1 << 1)) {
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                sh_serial_clear_fifo(s);
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                s->sr &= ~(1 << 1);
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            }
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            return;
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        case 0x20: /* SPTR */
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            s->sptr = val & 0xf3;
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            return;
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        case 0x24: /* LSR */
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            return;
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        }
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    } else {
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        switch (offs) {
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#if 0
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        case 0x0c:
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            ret = s->dr;
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            break;
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        case 0x10:
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            ret = 0;
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            break;
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#endif
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        case 0x1c:
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            s->sptr = val & 0x8f;
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            return;
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        }
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    }
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    qemu_log_mask(LOG_GUEST_ERROR,
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                  "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
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                  __func__, offs);
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}
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static uint64_t sh_serial_read(void *opaque, hwaddr offs,
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                               unsigned size)
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{
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    SHSerialState *s = opaque;
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    DeviceState *d = DEVICE(s);
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    uint32_t ret = UINT32_MAX;
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#if 0
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    switch (offs) {
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    case 0x00:
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        ret = s->smr;
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        break;
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    case 0x04:
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        ret = s->brr;
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        break;
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    case 0x08:
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        ret = s->scr;
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        break;
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    case 0x14:
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        ret = 0;
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        break;
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    }
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#endif
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    if (s->feat & SH_SERIAL_FEAT_SCIF) {
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        switch (offs) {
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        case 0x00: /* SMR */
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            ret = s->smr;
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            break;
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        case 0x08: /* SCR */
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            ret = s->scr;
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            break;
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        case 0x10: /* FSR */
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            ret = 0;
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            if (s->flags & SH_SERIAL_FLAG_TEND) {
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                ret |= (1 << 6);
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            }
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            if (s->flags & SH_SERIAL_FLAG_TDE) {
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                ret |= (1 << 5);
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            }
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            if (s->flags & SH_SERIAL_FLAG_BRK) {
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                ret |= (1 << 4);
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            }
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            if (s->flags & SH_SERIAL_FLAG_RDF) {
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                ret |= (1 << 1);
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            }
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            if (s->flags & SH_SERIAL_FLAG_DR) {
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                ret |= (1 << 0);
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            }
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            if (s->scr & (1 << 5)) {
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                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
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            }
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            break;
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        case 0x14:
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            if (s->rx_cnt > 0) {
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                ret = s->rx_fifo[s->rx_tail++];
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                s->rx_cnt--;
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                if (s->rx_tail == SH_RX_FIFO_LENGTH) {
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                    s->rx_tail = 0;
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                }
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                if (s->rx_cnt < s->rtrg) {
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                    s->flags &= ~SH_SERIAL_FLAG_RDF;
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                }
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            }
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            break;
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        case 0x18:
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            ret = s->fcr;
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            break;
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        case 0x1c:
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            ret = s->rx_cnt;
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            break;
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        case 0x20:
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            ret = s->sptr;
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            break;
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        case 0x24:
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            ret = 0;
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            break;
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        }
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    } else {
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        switch (offs) {
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#if 0
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        case 0x0c:
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            ret = s->dr;
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            break;
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        case 0x10:
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            ret = 0;
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            break;
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        case 0x14:
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            ret = s->rx_fifo[0];
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            break;
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#endif
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        case 0x1c:
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            ret = s->sptr;
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            break;
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        }
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    }
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    trace_sh_serial_read(d->id, size, offs, ret);
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    if (ret > UINT16_MAX) {
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
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                      __func__, offs);
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        ret = 0;
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    }
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    return ret;
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}
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static int sh_serial_can_receive(SHSerialState *s)
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{
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    return s->scr & (1 << 4);
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}
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static void sh_serial_receive_break(SHSerialState *s)
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{
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    if (s->feat & SH_SERIAL_FEAT_SCIF) {
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        s->sr |= (1 << 4);
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    }
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}
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static int sh_serial_can_receive1(void *opaque)
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{
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    SHSerialState *s = opaque;
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    return sh_serial_can_receive(s);
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}
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static void sh_serial_timeout_int(void *opaque)
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{
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    SHSerialState *s = opaque;
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    s->flags |= SH_SERIAL_FLAG_RDF;
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    if (s->scr & (1 << 6) && s->rxi) {
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        qemu_set_irq(s->rxi, 1);
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    }
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}
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static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
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{
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    SHSerialState *s = opaque;
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    if (s->feat & SH_SERIAL_FEAT_SCIF) {
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        int i;
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        for (i = 0; i < size; i++) {
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            if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
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                s->rx_fifo[s->rx_head++] = buf[i];
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                if (s->rx_head == SH_RX_FIFO_LENGTH) {
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                    s->rx_head = 0;
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                }
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                s->rx_cnt++;
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                if (s->rx_cnt >= s->rtrg) {
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                    s->flags |= SH_SERIAL_FLAG_RDF;
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                    if (s->scr & (1 << 6) && s->rxi) {
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                        timer_del(&s->fifo_timeout_timer);
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                        qemu_set_irq(s->rxi, 1);
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                    }
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                } else {
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                    timer_mod(&s->fifo_timeout_timer,
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                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
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                }
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            }
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        }
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    } else {
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        s->rx_fifo[0] = buf[0];
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    }
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}
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static void sh_serial_event(void *opaque, QEMUChrEvent event)
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{
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    SHSerialState *s = opaque;
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    if (event == CHR_EVENT_BREAK) {
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        sh_serial_receive_break(s);
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    }
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}
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static const MemoryRegionOps sh_serial_ops = {
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    .read = sh_serial_read,
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    .write = sh_serial_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void sh_serial_reset(DeviceState *dev)
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{
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    SHSerialState *s = SH_SERIAL(dev);
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    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
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    s->rtrg = 1;
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    s->smr = 0;
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    s->brr = 0xff;
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    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
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    s->sptr = 0;
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    if (s->feat & SH_SERIAL_FEAT_SCIF) {
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        s->fcr = 0;
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    } else {
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        s->dr = 0xff;
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    }
410

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    sh_serial_clear_fifo(s);
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}
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static void sh_serial_realize(DeviceState *d, Error **errp)
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{
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    SHSerialState *s = SH_SERIAL(d);
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    MemoryRegion *iomem = g_malloc(sizeof(*iomem));
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    assert(d->id);
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    memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28);
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    sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem);
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    qdev_init_gpio_out_named(d, &s->eri, "eri", 1);
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    qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1);
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    qdev_init_gpio_out_named(d, &s->txi, "txi", 1);
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    qdev_init_gpio_out_named(d, &s->tei, "tei", 1);
426
    qdev_init_gpio_out_named(d, &s->bri, "bri", 1);
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428
    if (qemu_chr_fe_backend_connected(&s->chr)) {
429
        qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
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                                 sh_serial_receive1,
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                                 sh_serial_event, NULL, s, NULL, true);
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    }
433

434
    timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL,
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                  sh_serial_timeout_int, s);
436
    s->etu = NANOSECONDS_PER_SECOND / 9600;
437
}
438

439
static void sh_serial_finalize(Object *obj)
440
{
441
    SHSerialState *s = SH_SERIAL(obj);
442

443
    timer_del(&s->fifo_timeout_timer);
444
}
445

446
static void sh_serial_init(Object *obj)
447
{
448
}
449

450
static Property sh_serial_properties[] = {
451
    DEFINE_PROP_CHR("chardev", SHSerialState, chr),
452
    DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),
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    DEFINE_PROP_END_OF_LIST()
454
};
455

456
static void sh_serial_class_init(ObjectClass *oc, void *data)
457
{
458
    DeviceClass *dc = DEVICE_CLASS(oc);
459

460
    device_class_set_props(dc, sh_serial_properties);
461
    dc->realize = sh_serial_realize;
462
    dc->reset = sh_serial_reset;
463
    /* Reason: part of SuperH CPU/SoC, needs to be wired up */
464
    dc->user_creatable = false;
465
}
466