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#include "qemu/osdep.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/char/renesas_sci.h"
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#include "migration/vmstate.h"
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FIELD(SMR, STOP, 3, 1)
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FIELD(SCR, TEIE, 2, 1)
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FIELD(SCR, MPIE, 3, 1)
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FIELD(SSR, MPBT, 0, 1)
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FIELD(SSR, TEND, 2, 1)
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FIELD(SSR, ORER, 5, 1)
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FIELD(SSR, RDRF, 6, 1)
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FIELD(SSR, TDRE, 7, 1)
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FIELD(SCMR, SMIF, 0, 1)
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FIELD(SCMR, SINV, 2, 1)
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FIELD(SCMR, SDIR, 3, 1)
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FIELD(SCMR, BCP2, 7, 1)
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FIELD(SEMR, ACS0, 0, 1)
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FIELD(SEMR, ABCS, 4, 1)
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static int can_receive(void *opaque)
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RSCIState *sci = RSCI(opaque);
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if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
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return FIELD_EX8(sci->scr, SCR, RE);
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static void receive(void *opaque, const uint8_t *buf, int size)
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RSCIState *sci = RSCI(opaque);
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sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
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if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, ORER, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 1);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_irq_pulse(sci->irq[RXI]);
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static void send_byte(RSCIState *sci)
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if (qemu_chr_fe_backend_connected(&sci->chr)) {
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qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
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timer_mod(&sci->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 0);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
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qemu_set_irq(sci->irq[TEI], 0);
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if (FIELD_EX8(sci->scr, SCR, TIE)) {
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qemu_irq_pulse(sci->irq[TXI]);
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static void txend(void *opaque)
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RSCIState *sci = RSCI(opaque);
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if (!FIELD_EX8(sci->ssr, SSR, TDRE)) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
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if (FIELD_EX8(sci->scr, SCR, TEIE)) {
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qemu_set_irq(sci->irq[TEI], 1);
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static void update_trtime(RSCIState *sci)
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sci->trtime = 8 - FIELD_EX8(sci->smr, SMR, CHR);
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sci->trtime += FIELD_EX8(sci->smr, SMR, PE);
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sci->trtime += FIELD_EX8(sci->smr, SMR, STOP) + 1;
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sci->trtime *= 32 * sci->brr;
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sci->trtime *= 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS));
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sci->trtime *= NANOSECONDS_PER_SECOND;
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sci->trtime /= sci->input_freq;
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static bool sci_is_tr_enabled(RSCIState *sci)
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return FIELD_EX8(sci->scr, SCR, TE) || FIELD_EX8(sci->scr, SCR, RE);
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static void sci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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RSCIState *sci = RSCI(opaque);
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if (!sci_is_tr_enabled(sci)) {
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if (!sci_is_tr_enabled(sci)) {
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if (FIELD_EX8(sci->scr, SCR, TE)) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
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if (FIELD_EX8(sci->scr, SCR, TIE)) {
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qemu_irq_pulse(sci->irq[TXI]);
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if (!FIELD_EX8(sci->scr, SCR, TEIE)) {
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qemu_set_irq(sci->irq[TEI], 0);
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if (!FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 0);
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if (FIELD_EX8(sci->ssr, SSR, TEND)) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 0);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, MPBT,
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FIELD_EX8(val, SSR, MPBT));
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sci->ssr = FIELD_DP8(sci->ssr, SSR, ERR,
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FIELD_EX8(val, SSR, ERR) & 0x07);
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if (FIELD_EX8(sci->read_ssr, SSR, ERR) &&
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FIELD_EX8(sci->ssr, SSR, ERR) == 0) {
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qemu_set_irq(sci->irq[ERI], 0);
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qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
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sci->scmr = val; break;
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sci->semr = val; break;
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qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX " "
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static uint64_t sci_read(void *opaque, hwaddr offset, unsigned size)
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RSCIState *sci = RSCI(opaque);
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sci->read_ssr = sci->ssr;
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sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 0);
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qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
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" not implemented.\n", offset);
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static const MemoryRegionOps sci_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.max_access_size = 1,
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.valid.max_access_size = 1,
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static void rsci_reset(DeviceState *dev)
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RSCIState *sci = RSCI(dev);
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sci->smr = sci->scr = 0x00;
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sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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static void sci_event(void *opaque, QEMUChrEvent event)
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RSCIState *sci = RSCI(opaque);
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if (event == CHR_EVENT_BREAK) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, FER, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 1);
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static void rsci_realize(DeviceState *dev, Error **errp)
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RSCIState *sci = RSCI(dev);
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if (sci->input_freq == 0) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"renesas_sci: input-freq property must be set.");
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qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive,
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sci_event, NULL, sci, NULL, true);
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static void rsci_init(Object *obj)
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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RSCIState *sci = RSCI(obj);
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memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
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sci, "renesas-sci", 0x8);
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sysbus_init_mmio(d, &sci->memory);
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for (i = 0; i < SCI_NR_IRQ; i++) {
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sysbus_init_irq(d, &sci->irq[i]);
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timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci);
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static const VMStateDescription vmstate_rsci = {
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.name = "renesas-sci",
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_INT64(trtime, RSCIState),
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VMSTATE_INT64(rx_next, RSCIState),
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VMSTATE_UINT8(smr, RSCIState),
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VMSTATE_UINT8(brr, RSCIState),
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VMSTATE_UINT8(scr, RSCIState),
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VMSTATE_UINT8(tdr, RSCIState),
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VMSTATE_UINT8(ssr, RSCIState),
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VMSTATE_UINT8(rdr, RSCIState),
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VMSTATE_UINT8(scmr, RSCIState),
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VMSTATE_UINT8(semr, RSCIState),
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VMSTATE_UINT8(read_ssr, RSCIState),
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VMSTATE_TIMER(timer, RSCIState),
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VMSTATE_END_OF_LIST()
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static Property rsci_properties[] = {
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DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
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DEFINE_PROP_CHR("chardev", RSCIState, chr),
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DEFINE_PROP_END_OF_LIST(),
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static void rsci_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rsci_realize;
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dc->vmsd = &vmstate_rsci;
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dc->reset = rsci_reset;
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device_class_set_props(dc, rsci_properties);
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static const TypeInfo rsci_info = {
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.name = TYPE_RENESAS_SCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RSCIState),
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.instance_init = rsci_init,
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.class_init = rsci_class_init,
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static void rsci_register_types(void)
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type_register_static(&rsci_info);
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type_init(rsci_register_types)