qemu

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/*
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 * TI OMAP processors UART emulation.
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 *
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 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
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 * Copyright (C) 2007-2009 Nokia Corporation
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "chardev/char.h"
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#include "hw/arm/omap.h"
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#include "hw/char/serial.h"
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#include "exec/address-spaces.h"
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/* UARTs */
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struct omap_uart_s {
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    MemoryRegion iomem;
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    hwaddr base;
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    SerialMM *serial; /* TODO */
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    struct omap_target_agent_s *ta;
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    omap_clk fclk;
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    qemu_irq irq;
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    uint8_t eblr;
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    uint8_t syscontrol;
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    uint8_t wkup;
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    uint8_t cfps;
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    uint8_t mdr[2];
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    uint8_t scr;
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    uint8_t clksel;
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};
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void omap_uart_reset(struct omap_uart_s *s)
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{
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    s->eblr = 0x00;
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    s->syscontrol = 0;
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    s->wkup = 0x3f;
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    s->cfps = 0x69;
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    s->clksel = 0;
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}
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struct omap_uart_s *omap_uart_init(hwaddr base,
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                qemu_irq irq, omap_clk fclk, omap_clk iclk,
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                qemu_irq txdma, qemu_irq rxdma,
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                const char *label, Chardev *chr)
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{
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    struct omap_uart_s *s = g_new0(struct omap_uart_s, 1);
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    s->base = base;
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    s->fclk = fclk;
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    s->irq = irq;
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    s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
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                               omap_clk_getrate(fclk) / 16,
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                               chr ?: qemu_chr_new(label, "null", NULL),
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                               DEVICE_NATIVE_ENDIAN);
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    return s;
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}
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static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
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{
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    struct omap_uart_s *s = opaque;
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    if (size == 4) {
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        return omap_badwidth_read8(opaque, addr);
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    }
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    switch (addr) {
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    case 0x20:  /* MDR1 */
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        return s->mdr[0];
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    case 0x24:  /* MDR2 */
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        return s->mdr[1];
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    case 0x40:  /* SCR */
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        return s->scr;
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    case 0x44:  /* SSR */
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        return 0x0;
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    case 0x48:  /* EBLR (OMAP2) */
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        return s->eblr;
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    case 0x4C:  /* OSC_12M_SEL (OMAP1) */
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        return s->clksel;
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    case 0x50:  /* MVR */
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        return 0x30;
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    case 0x54:  /* SYSC (OMAP2) */
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        return s->syscontrol;
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    case 0x58:  /* SYSS (OMAP2) */
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        return 1;
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    case 0x5c:  /* WER (OMAP2) */
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        return s->wkup;
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    case 0x60:  /* CFPS (OMAP2) */
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        return s->cfps;
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    }
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    OMAP_BAD_REG(addr);
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    return 0;
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}
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static void omap_uart_write(void *opaque, hwaddr addr,
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                            uint64_t value, unsigned size)
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{
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    struct omap_uart_s *s = opaque;
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    if (size == 4) {
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        omap_badwidth_write8(opaque, addr, value);
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        return;
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    }
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    switch (addr) {
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    case 0x20:  /* MDR1 */
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        s->mdr[0] = value & 0x7f;
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        break;
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    case 0x24:  /* MDR2 */
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        s->mdr[1] = value & 0xff;
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        break;
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    case 0x40:  /* SCR */
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        s->scr = value & 0xff;
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        break;
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    case 0x48:  /* EBLR (OMAP2) */
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        s->eblr = value & 0xff;
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        break;
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    case 0x4C:  /* OSC_12M_SEL (OMAP1) */
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        s->clksel = value & 1;
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        break;
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    case 0x44:  /* SSR */
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    case 0x50:  /* MVR */
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    case 0x58:  /* SYSS (OMAP2) */
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        OMAP_RO_REG(addr);
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        break;
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    case 0x54:  /* SYSC (OMAP2) */
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        s->syscontrol = value & 0x1d;
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        if (value & 2) {
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            omap_uart_reset(s);
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        }
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        break;
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    case 0x5c:  /* WER (OMAP2) */
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        s->wkup = value & 0x7f;
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        break;
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    case 0x60:  /* CFPS (OMAP2) */
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        s->cfps = value & 0xff;
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        break;
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    default:
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        OMAP_BAD_REG(addr);
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    }
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}
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static const MemoryRegionOps omap_uart_ops = {
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    .read = omap_uart_read,
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    .write = omap_uart_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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                struct omap_target_agent_s *ta,
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                qemu_irq irq, omap_clk fclk, omap_clk iclk,
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                qemu_irq txdma, qemu_irq rxdma,
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                const char *label, Chardev *chr)
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{
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    hwaddr base = omap_l4_attach(ta, 0, NULL);
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    struct omap_uart_s *s = omap_uart_init(base, irq,
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                    fclk, iclk, txdma, rxdma, label, chr);
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    memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100);
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    s->ta = ta;
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    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
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    return s;
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}
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