qemu

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/*
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 * nRF51 SoC UART emulation
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 *
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 * See nRF51 Series Reference Manual, "29 Universal Asynchronous
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 * Receiver/Transmitter" for hardware specifications:
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 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
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 *
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 * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 or
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 * (at your option) any later version.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/char/nrf51_uart.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static void nrf51_uart_update_irq(NRF51UARTState *s)
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{
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    bool irq = false;
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    irq |= (s->reg[R_UART_RXDRDY] &&
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            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
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    irq |= (s->reg[R_UART_TXDRDY] &&
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            (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
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    irq |= (s->reg[R_UART_ERROR]  &&
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            (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
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    irq |= (s->reg[R_UART_RXTO]   &&
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            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
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    qemu_set_irq(s->irq, irq);
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}
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static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    uint64_t r;
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    if (!s->enabled) {
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        return 0;
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    }
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    switch (addr) {
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    case A_UART_RXD:
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        r = s->rx_fifo[s->rx_fifo_pos];
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        if (s->rx_started && s->rx_fifo_len) {
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            s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
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            s->rx_fifo_len--;
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            if (s->rx_fifo_len) {
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                s->reg[R_UART_RXDRDY] = 1;
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                nrf51_uart_update_irq(s);
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            }
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            qemu_chr_fe_accept_input(&s->chr);
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        }
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        break;
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    case A_UART_INTENSET:
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    case A_UART_INTENCLR:
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    case A_UART_INTEN:
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        r = s->reg[R_UART_INTEN];
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        break;
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    default:
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        r = s->reg[addr / 4];
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        break;
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    }
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    trace_nrf51_uart_read(addr, r, size);
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    return r;
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}
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static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    int r;
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    uint8_t c = s->reg[R_UART_TXD];
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    s->watch_tag = 0;
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    r = qemu_chr_fe_write(&s->chr, &c, 1);
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    if (r <= 0) {
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        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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                                             uart_transmit, s);
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        if (!s->watch_tag) {
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            /* The hardware has no transmit error reporting,
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             * so silently drop the byte
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             */
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            goto buffer_drained;
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        }
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        return G_SOURCE_REMOVE;
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    }
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buffer_drained:
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    s->reg[R_UART_TXDRDY] = 1;
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    s->pending_tx_byte = false;
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    return G_SOURCE_REMOVE;
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}
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static void uart_cancel_transmit(NRF51UARTState *s)
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{
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    if (s->watch_tag) {
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        g_source_remove(s->watch_tag);
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        s->watch_tag = 0;
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    }
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}
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static void uart_write(void *opaque, hwaddr addr,
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                       uint64_t value, unsigned int size)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    trace_nrf51_uart_write(addr, value, size);
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    if (!s->enabled && (addr != A_UART_ENABLE)) {
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        return;
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    }
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    switch (addr) {
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    case A_UART_TXD:
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        if (!s->pending_tx_byte && s->tx_started) {
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            s->reg[R_UART_TXD] = value;
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            s->pending_tx_byte = true;
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            uart_transmit(NULL, G_IO_OUT, s);
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        }
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        break;
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    case A_UART_INTEN:
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        s->reg[R_UART_INTEN] = value;
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        break;
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    case A_UART_INTENSET:
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        s->reg[R_UART_INTEN] |= value;
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        break;
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    case A_UART_INTENCLR:
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        s->reg[R_UART_INTEN] &= ~value;
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        break;
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    case A_UART_TXDRDY ... A_UART_RXTO:
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        s->reg[addr / 4] = value;
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        break;
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    case A_UART_ERRORSRC:
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        s->reg[addr / 4] &= ~value;
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        break;
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    case A_UART_RXD:
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        break;
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    case A_UART_RXDRDY:
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        if (value == 0) {
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            s->reg[R_UART_RXDRDY] = 0;
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        }
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        break;
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    case A_UART_STARTTX:
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        if (value == 1) {
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            s->tx_started = true;
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        }
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        break;
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    case A_UART_STARTRX:
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        if (value == 1) {
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            s->rx_started = true;
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        }
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        break;
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    case A_UART_ENABLE:
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        if (value) {
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            if (value == 4) {
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                s->enabled = true;
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            }
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            break;
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        }
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        s->enabled = false;
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        value = 1;
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        /* fall through */
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    case A_UART_SUSPEND:
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    case A_UART_STOPTX:
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        if (value == 1) {
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            s->tx_started = false;
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        }
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        /* fall through */
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    case A_UART_STOPRX:
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        if (addr != A_UART_STOPTX && value == 1) {
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            s->rx_started = false;
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            s->reg[R_UART_RXTO] = 1;
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        }
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        break;
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    default:
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        s->reg[addr / 4] = value;
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        break;
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    }
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    nrf51_uart_update_irq(s);
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}
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static const MemoryRegionOps uart_ops = {
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    .read =  uart_read,
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    .write = uart_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void nrf51_uart_reset(DeviceState *dev)
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{
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    NRF51UARTState *s = NRF51_UART(dev);
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    s->pending_tx_byte = 0;
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    uart_cancel_transmit(s);
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    memset(s->reg, 0, sizeof(s->reg));
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    s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
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    s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
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    s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
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    s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
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    s->reg[R_UART_BAUDRATE] = 0x4000000;
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    s->rx_fifo_len = 0;
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    s->rx_fifo_pos = 0;
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    s->rx_started = false;
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    s->tx_started = false;
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    s->enabled = false;
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}
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static void uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    int i;
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    if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
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        return;
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    }
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    for (i = 0; i < size; i++) {
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        uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
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        s->rx_fifo[pos] = buf[i];
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        s->rx_fifo_len++;
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    }
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    s->reg[R_UART_RXDRDY] = 1;
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    nrf51_uart_update_irq(s);
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}
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static int uart_can_receive(void *opaque)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
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}
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static void uart_event(void *opaque, QEMUChrEvent event)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    if (event == CHR_EVENT_BREAK) {
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        s->reg[R_UART_ERRORSRC] |= 3;
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        s->reg[R_UART_ERROR] = 1;
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        nrf51_uart_update_irq(s);
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    }
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}
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static void nrf51_uart_realize(DeviceState *dev, Error **errp)
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{
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    NRF51UARTState *s = NRF51_UART(dev);
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    qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
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                             uart_event, NULL, s, NULL, true);
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}
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static void nrf51_uart_init(Object *obj)
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{
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    NRF51UARTState *s = NRF51_UART(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    memory_region_init_io(&s->iomem, obj, &uart_ops, s,
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                          "nrf51_soc.uart", UART_SIZE);
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    sysbus_init_mmio(sbd, &s->iomem);
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    sysbus_init_irq(sbd, &s->irq);
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}
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static int nrf51_uart_post_load(void *opaque, int version_id)
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{
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    NRF51UARTState *s = NRF51_UART(opaque);
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    if (s->pending_tx_byte) {
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        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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                                             uart_transmit, s);
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    }
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    return 0;
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}
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static const VMStateDescription nrf51_uart_vmstate = {
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    .name = "nrf51_soc.uart",
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    .post_load = nrf51_uart_post_load,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
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        VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
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        VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
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        VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
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        VMSTATE_BOOL(rx_started, NRF51UARTState),
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        VMSTATE_BOOL(tx_started, NRF51UARTState),
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        VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
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        VMSTATE_BOOL(enabled, NRF51UARTState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static Property nrf51_uart_properties[] = {
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    DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void nrf51_uart_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = nrf51_uart_reset;
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    dc->realize = nrf51_uart_realize;
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    device_class_set_props(dc, nrf51_uart_properties);
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    dc->vmsd = &nrf51_uart_vmstate;
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}
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static const TypeInfo nrf51_uart_info = {
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    .name = TYPE_NRF51_UART,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(NRF51UARTState),
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    .instance_init = nrf51_uart_init,
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    .class_init = nrf51_uart_class_init
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};
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static void nrf51_uart_register_types(void)
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{
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    type_register_static(&nrf51_uart_info);
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}
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type_init(nrf51_uart_register_types)
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