qemu

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/*
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 *
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 * Goldfish TTY
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 *
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 * (c) 2020 Laurent Vivier <laurent@vivier.eu>
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 *
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "chardev/char-fe.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "exec/address-spaces.h"
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#include "sysemu/dma.h"
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#include "hw/char/goldfish_tty.h"
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#define GOLDFISH_TTY_VERSION 1
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/* registers */
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enum {
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    REG_PUT_CHAR      = 0x00,
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    REG_BYTES_READY   = 0x04,
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    REG_CMD           = 0x08,
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    REG_DATA_PTR      = 0x10,
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    REG_DATA_LEN      = 0x14,
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    REG_DATA_PTR_HIGH = 0x18,
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    REG_VERSION       = 0x20,
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};
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/* commands */
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enum {
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    CMD_INT_DISABLE   = 0x00,
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    CMD_INT_ENABLE    = 0x01,
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    CMD_WRITE_BUFFER  = 0x02,
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    CMD_READ_BUFFER   = 0x03,
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};
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static uint64_t goldfish_tty_read(void *opaque, hwaddr addr,
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                                  unsigned size)
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{
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    GoldfishTTYState *s = opaque;
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    uint64_t value = 0;
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    switch (addr) {
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    case REG_BYTES_READY:
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        value = fifo8_num_used(&s->rx_fifo);
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        break;
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    case REG_VERSION:
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        value = GOLDFISH_TTY_VERSION;
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: unimplemented register read 0x%02"HWADDR_PRIx"\n",
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                      __func__, addr);
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        break;
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    }
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    trace_goldfish_tty_read(s, addr, size, value);
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    return value;
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}
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static void goldfish_tty_cmd(GoldfishTTYState *s, uint32_t cmd)
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{
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    uint32_t to_copy;
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    uint8_t data_out[GOLFISH_TTY_BUFFER_SIZE];
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    int len;
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    uint64_t ptr;
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    switch (cmd) {
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    case CMD_INT_DISABLE:
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        if (s->int_enabled) {
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            if (!fifo8_is_empty(&s->rx_fifo)) {
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                qemu_set_irq(s->irq, 0);
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            }
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            s->int_enabled = false;
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        }
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        break;
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    case CMD_INT_ENABLE:
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        if (!s->int_enabled) {
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            if (!fifo8_is_empty(&s->rx_fifo)) {
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                qemu_set_irq(s->irq, 1);
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            }
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            s->int_enabled = true;
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        }
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        break;
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    case CMD_WRITE_BUFFER:
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        len = s->data_len;
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        ptr = s->data_ptr;
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        while (len) {
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            to_copy = MIN(GOLFISH_TTY_BUFFER_SIZE, len);
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            dma_memory_read_relaxed(&address_space_memory, ptr,
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                                    data_out, to_copy);
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            qemu_chr_fe_write_all(&s->chr, data_out, to_copy);
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            len -= to_copy;
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            ptr += to_copy;
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        }
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        break;
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    case CMD_READ_BUFFER:
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        len = s->data_len;
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        ptr = s->data_ptr;
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        while (len && !fifo8_is_empty(&s->rx_fifo)) {
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            const uint8_t *buf = fifo8_pop_bufptr(&s->rx_fifo, len, &to_copy);
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            dma_memory_write_relaxed(&address_space_memory, ptr, buf, to_copy);
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            len -= to_copy;
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            ptr += to_copy;
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        }
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        if (s->int_enabled && fifo8_is_empty(&s->rx_fifo)) {
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            qemu_set_irq(s->irq, 0);
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        }
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        break;
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    }
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}
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static void goldfish_tty_write(void *opaque, hwaddr addr,
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                               uint64_t value, unsigned size)
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{
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    GoldfishTTYState *s = opaque;
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    unsigned char c;
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    trace_goldfish_tty_write(s, addr, size, value);
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    switch (addr) {
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    case REG_PUT_CHAR:
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        c = value;
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        qemu_chr_fe_write_all(&s->chr, &c, sizeof(c));
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        break;
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    case REG_CMD:
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        goldfish_tty_cmd(s, value);
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        break;
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    case REG_DATA_PTR:
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        s->data_ptr = value;
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        break;
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    case REG_DATA_PTR_HIGH:
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        s->data_ptr = deposit64(s->data_ptr, 32, 32, value);
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        break;
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    case REG_DATA_LEN:
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        s->data_len = value;
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: unimplemented register write 0x%02"HWADDR_PRIx"\n",
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                      __func__, addr);
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        break;
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    }
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}
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static const MemoryRegionOps goldfish_tty_ops = {
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    .read = goldfish_tty_read,
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    .write = goldfish_tty_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid.max_access_size = 4,
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    .impl.max_access_size = 4,
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    .impl.min_access_size = 4,
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};
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static int goldfish_tty_can_receive(void *opaque)
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{
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    GoldfishTTYState *s = opaque;
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    int available = fifo8_num_free(&s->rx_fifo);
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    trace_goldfish_tty_can_receive(s, available);
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    return available;
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}
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static void goldfish_tty_receive(void *opaque, const uint8_t *buffer, int size)
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{
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    GoldfishTTYState *s = opaque;
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    trace_goldfish_tty_receive(s, size);
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    g_assert(size <= fifo8_num_free(&s->rx_fifo));
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    fifo8_push_all(&s->rx_fifo, buffer, size);
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    if (s->int_enabled && !fifo8_is_empty(&s->rx_fifo)) {
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        qemu_set_irq(s->irq, 1);
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    }
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}
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static void goldfish_tty_reset(DeviceState *dev)
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{
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    GoldfishTTYState *s = GOLDFISH_TTY(dev);
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    trace_goldfish_tty_reset(s);
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    fifo8_reset(&s->rx_fifo);
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    s->int_enabled = false;
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    s->data_ptr = 0;
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    s->data_len = 0;
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}
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static void goldfish_tty_realize(DeviceState *dev, Error **errp)
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{
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    GoldfishTTYState *s = GOLDFISH_TTY(dev);
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    trace_goldfish_tty_realize(s);
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    fifo8_create(&s->rx_fifo, GOLFISH_TTY_BUFFER_SIZE);
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    memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_tty_ops, s,
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                          "goldfish_tty", 0x24);
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    if (qemu_chr_fe_backend_connected(&s->chr)) {
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        qemu_chr_fe_set_handlers(&s->chr, goldfish_tty_can_receive,
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                                 goldfish_tty_receive, NULL, NULL,
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                                 s, NULL, true);
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    }
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}
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static void goldfish_tty_unrealize(DeviceState *dev)
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{
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    GoldfishTTYState *s = GOLDFISH_TTY(dev);
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    trace_goldfish_tty_unrealize(s);
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    fifo8_destroy(&s->rx_fifo);
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}
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static const VMStateDescription vmstate_goldfish_tty = {
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    .name = "goldfish_tty",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(data_len, GoldfishTTYState),
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        VMSTATE_UINT64(data_ptr, GoldfishTTYState),
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        VMSTATE_BOOL(int_enabled, GoldfishTTYState),
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        VMSTATE_FIFO8(rx_fifo, GoldfishTTYState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static Property goldfish_tty_properties[] = {
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    DEFINE_PROP_CHR("chardev", GoldfishTTYState, chr),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void goldfish_tty_instance_init(Object *obj)
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{
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    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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    GoldfishTTYState *s = GOLDFISH_TTY(obj);
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    trace_goldfish_tty_instance_init(s);
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    sysbus_init_mmio(dev, &s->iomem);
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    sysbus_init_irq(dev, &s->irq);
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}
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static void goldfish_tty_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(oc);
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    device_class_set_props(dc, goldfish_tty_properties);
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    dc->reset = goldfish_tty_reset;
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    dc->realize = goldfish_tty_realize;
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    dc->unrealize = goldfish_tty_unrealize;
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    dc->vmsd = &vmstate_goldfish_tty;
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    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static const TypeInfo goldfish_tty_info = {
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    .name = TYPE_GOLDFISH_TTY,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .class_init = goldfish_tty_class_init,
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    .instance_init = goldfish_tty_instance_init,
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    .instance_size = sizeof(GoldfishTTYState),
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};
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static void goldfish_tty_register_types(void)
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{
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    type_register_static(&goldfish_tty_info);
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}
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type_init(goldfish_tty_register_types)
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