qemu

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/*
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 * QEMU ETRAX System Emulator
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 *
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 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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#define D(x)
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#define RW_TR_CTRL     (0x00 / 4)
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#define RW_TR_DMA_EN   (0x04 / 4)
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#define RW_REC_CTRL    (0x08 / 4)
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#define RW_DOUT        (0x1c / 4)
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#define RS_STAT_DIN    (0x20 / 4)
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#define R_STAT_DIN     (0x24 / 4)
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#define RW_INTR_MASK   (0x2c / 4)
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#define RW_ACK_INTR    (0x30 / 4)
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#define R_INTR         (0x34 / 4)
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#define R_MASKED_INTR  (0x38 / 4)
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#define R_MAX          (0x3c / 4)
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#define STAT_DAV     16
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#define STAT_TR_IDLE 22
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#define STAT_TR_RDY  24
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#define TYPE_ETRAX_FS_SERIAL "etraxfs-serial"
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typedef struct ETRAXSerial ETRAXSerial;
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DECLARE_INSTANCE_CHECKER(ETRAXSerial, ETRAX_SERIAL,
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                         TYPE_ETRAX_FS_SERIAL)
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struct ETRAXSerial {
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    SysBusDevice parent_obj;
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    MemoryRegion mmio;
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    CharBackend chr;
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    qemu_irq irq;
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    int pending_tx;
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    uint8_t rx_fifo[16];
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    unsigned int rx_fifo_pos;
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    unsigned int rx_fifo_len;
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    /* Control registers.  */
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    uint32_t regs[R_MAX];
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};
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static void ser_update_irq(ETRAXSerial *s)
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{
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    if (s->rx_fifo_len) {
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        s->regs[R_INTR] |= 8;
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    } else {
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        s->regs[R_INTR] &= ~8;
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    }
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    s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
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    qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
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}
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static uint64_t
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ser_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    ETRAXSerial *s = opaque;
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    uint32_t r = 0;
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    addr >>= 2;
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    switch (addr)
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    {
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        case R_STAT_DIN:
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            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
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            if (s->rx_fifo_len) {
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                r |= 1 << STAT_DAV;
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            }
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            r |= 1 << STAT_TR_RDY;
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            r |= 1 << STAT_TR_IDLE;
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            break;
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        case RS_STAT_DIN:
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            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
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            if (s->rx_fifo_len) {
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                r |= 1 << STAT_DAV;
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                s->rx_fifo_len--;
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            }
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            r |= 1 << STAT_TR_RDY;
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            r |= 1 << STAT_TR_IDLE;
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            break;
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        default:
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            r = s->regs[addr];
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            D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, r));
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            break;
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    }
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    return r;
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}
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static void
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ser_write(void *opaque, hwaddr addr,
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          uint64_t val64, unsigned int size)
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{
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    ETRAXSerial *s = opaque;
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    uint32_t value = val64;
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    unsigned char ch = val64;
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    D(qemu_log("%s " HWADDR_FMT_plx "=%x\n",  __func__, addr, value));
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    addr >>= 2;
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    switch (addr)
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    {
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        case RW_DOUT:
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            /* XXX this blocks entire thread. Rewrite to use
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             * qemu_chr_fe_write and background I/O callbacks */
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            qemu_chr_fe_write_all(&s->chr, &ch, 1);
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            s->regs[R_INTR] |= 3;
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            s->pending_tx = 1;
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            s->regs[addr] = value;
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            break;
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        case RW_ACK_INTR:
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            if (s->pending_tx) {
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                value &= ~1;
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                s->pending_tx = 0;
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                D(qemu_log("fixedup value=%x r_intr=%x\n",
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                           value, s->regs[R_INTR]));
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            }
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            s->regs[addr] = value;
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            s->regs[R_INTR] &= ~value;
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            D(printf("r_intr=%x\n", s->regs[R_INTR]));
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            break;
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        default:
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            s->regs[addr] = value;
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            break;
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    }
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    ser_update_irq(s);
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}
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static const MemoryRegionOps ser_ops = {
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    .read = ser_read,
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    .write = ser_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4
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    }
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};
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static Property etraxfs_ser_properties[] = {
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    DEFINE_PROP_CHR("chardev", ETRAXSerial, chr),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void serial_receive(void *opaque, const uint8_t *buf, int size)
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{
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    ETRAXSerial *s = opaque;
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    int i;
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    /* Got a byte.  */
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    if (s->rx_fifo_len >= 16) {
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        D(qemu_log("WARNING: UART dropped char.\n"));
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        return;
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    }
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    for (i = 0; i < size; i++) { 
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        s->rx_fifo[s->rx_fifo_pos] = buf[i];
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        s->rx_fifo_pos++;
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        s->rx_fifo_pos &= 15;
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        s->rx_fifo_len++;
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    }
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    ser_update_irq(s);
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}
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static int serial_can_receive(void *opaque)
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{
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    ETRAXSerial *s = opaque;
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    /* Is the receiver enabled?  */
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    if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
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        return 0;
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    }
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    return sizeof(s->rx_fifo) - s->rx_fifo_len;
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}
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static void serial_event(void *opaque, QEMUChrEvent event)
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{
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}
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static void etraxfs_ser_reset(DeviceState *d)
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{
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    ETRAXSerial *s = ETRAX_SERIAL(d);
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    /* transmitter begins ready and idle.  */
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    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
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    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
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    s->regs[RW_REC_CTRL] = 0x10000;
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}
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static void etraxfs_ser_init(Object *obj)
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{
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    ETRAXSerial *s = ETRAX_SERIAL(obj);
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    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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    sysbus_init_irq(dev, &s->irq);
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    memory_region_init_io(&s->mmio, obj, &ser_ops, s,
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                          "etraxfs-serial", R_MAX * 4);
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    sysbus_init_mmio(dev, &s->mmio);
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}
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static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
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{
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    ETRAXSerial *s = ETRAX_SERIAL(dev);
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    qemu_chr_fe_set_handlers(&s->chr,
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                             serial_can_receive, serial_receive,
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                             serial_event, NULL, s, NULL, true);
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}
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static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = etraxfs_ser_reset;
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    device_class_set_props(dc, etraxfs_ser_properties);
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    dc->realize = etraxfs_ser_realize;
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}
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static const TypeInfo etraxfs_ser_info = {
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    .name          = TYPE_ETRAX_FS_SERIAL,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(ETRAXSerial),
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    .instance_init = etraxfs_ser_init,
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    .class_init    = etraxfs_ser_class_init,
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};
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static void etraxfs_serial_register_types(void)
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{
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    type_register_static(&etraxfs_ser_info);
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}
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type_init(etraxfs_serial_register_types)
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