qemu

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/*
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 * ARM CMSDK APB UART emulation
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 *
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 * Copyright (c) 2017 Linaro Limited
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 * Written by Peter Maydell
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 *
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 *  This program is free software; you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License version 2 or
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 *  (at your option) any later version.
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 */
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/* This is a model of the "APB UART" which is part of the Cortex-M
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 * System Design Kit (CMSDK) and documented in the Cortex-M System
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 * Design Kit Technical Reference Manual (ARM DDI0479C):
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 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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#include "hw/char/cmsdk-apb-uart.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties-system.h"
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REG32(DATA, 0)
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REG32(STATE, 4)
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    FIELD(STATE, TXFULL, 0, 1)
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    FIELD(STATE, RXFULL, 1, 1)
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    FIELD(STATE, TXOVERRUN, 2, 1)
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    FIELD(STATE, RXOVERRUN, 3, 1)
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REG32(CTRL, 8)
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    FIELD(CTRL, TX_EN, 0, 1)
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    FIELD(CTRL, RX_EN, 1, 1)
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    FIELD(CTRL, TX_INTEN, 2, 1)
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    FIELD(CTRL, RX_INTEN, 3, 1)
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    FIELD(CTRL, TXO_INTEN, 4, 1)
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    FIELD(CTRL, RXO_INTEN, 5, 1)
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    FIELD(CTRL, HSTEST, 6, 1)
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REG32(INTSTATUS, 0xc)
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    FIELD(INTSTATUS, TX, 0, 1)
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    FIELD(INTSTATUS, RX, 1, 1)
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    FIELD(INTSTATUS, TXO, 2, 1)
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    FIELD(INTSTATUS, RXO, 3, 1)
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REG32(BAUDDIV, 0x10)
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REG32(PID4, 0xFD0)
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REG32(PID5, 0xFD4)
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REG32(PID6, 0xFD8)
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REG32(PID7, 0xFDC)
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REG32(PID0, 0xFE0)
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REG32(PID1, 0xFE4)
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REG32(PID2, 0xFE8)
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REG32(PID3, 0xFEC)
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REG32(CID0, 0xFF0)
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REG32(CID1, 0xFF4)
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REG32(CID2, 0xFF8)
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REG32(CID3, 0xFFC)
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/* PID/CID values */
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static const int uart_id[] = {
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    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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    0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
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    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static bool uart_baudrate_ok(CMSDKAPBUART *s)
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{
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    /* The minimum permitted bauddiv setting is 16, so we just ignore
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     * settings below that (usually this means the device has just
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     * been reset and not yet programmed).
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     */
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    return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq;
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}
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static void uart_update_parameters(CMSDKAPBUART *s)
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{
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    QEMUSerialSetParams ssp;
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    /* This UART is always 8N1 but the baud rate is programmable. */
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    if (!uart_baudrate_ok(s)) {
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        return;
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    }
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    ssp.data_bits = 8;
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    ssp.parity = 'N';
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    ssp.stop_bits = 1;
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    ssp.speed = s->pclk_frq / s->bauddiv;
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    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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    trace_cmsdk_apb_uart_set_params(ssp.speed);
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}
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static void cmsdk_apb_uart_update(CMSDKAPBUART *s)
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{
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    /* update outbound irqs, including handling the way the rxo and txo
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     * interrupt status bits are just logical AND of the overrun bit in
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     * STATE and the overrun interrupt enable bit in CTRL.
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     */
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    uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK);
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    s->intstatus &= ~omask;
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    s->intstatus |= (s->state & (s->ctrl >> 2) & omask);
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    qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK));
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    qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK));
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    qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK));
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    qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK));
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    qemu_set_irq(s->uartint, !!(s->intstatus));
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}
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static int uart_can_receive(void *opaque)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    /* We can take a char if RX is enabled and the buffer is empty */
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    if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) {
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        return 1;
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    }
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    return 0;
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}
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static void uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    trace_cmsdk_apb_uart_receive(*buf);
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    /* In fact uart_can_receive() ensures that we can't be
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     * called unless RX is enabled and the buffer is empty,
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     * but we include this logic as documentation of what the
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     * hardware does if a character arrives in these circumstances.
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     */
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    if (!(s->ctrl & R_CTRL_RX_EN_MASK)) {
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        /* Just drop the character on the floor */
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        return;
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    }
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    if (s->state & R_STATE_RXFULL_MASK) {
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        s->state |= R_STATE_RXOVERRUN_MASK;
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    }
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    s->rxbuf = *buf;
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    s->state |= R_STATE_RXFULL_MASK;
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    if (s->ctrl & R_CTRL_RX_INTEN_MASK) {
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        s->intstatus |= R_INTSTATUS_RX_MASK;
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    }
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    cmsdk_apb_uart_update(s);
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}
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static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    uint64_t r;
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    switch (offset) {
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    case A_DATA:
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        r = s->rxbuf;
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        s->state &= ~R_STATE_RXFULL_MASK;
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        cmsdk_apb_uart_update(s);
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        qemu_chr_fe_accept_input(&s->chr);
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        break;
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    case A_STATE:
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        r = s->state;
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        break;
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    case A_CTRL:
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        r = s->ctrl;
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        break;
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    case A_INTSTATUS:
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        r = s->intstatus;
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        break;
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    case A_BAUDDIV:
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        r = s->bauddiv;
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        break;
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    case A_PID4 ... A_CID3:
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        r = uart_id[(offset - A_PID4) / 4];
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "CMSDK APB UART read: bad offset %x\n", (int) offset);
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        r = 0;
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        break;
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    }
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    trace_cmsdk_apb_uart_read(offset, r, size);
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    return r;
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}
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/* Try to send tx data, and arrange to be called back later if
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 * we can't (ie the char backend is busy/blocking).
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 */
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static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    int ret;
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    s->watch_tag = 0;
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    if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) {
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        return G_SOURCE_REMOVE;
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    }
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    ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1);
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    if (ret <= 0) {
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        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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                                             uart_transmit, s);
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        if (!s->watch_tag) {
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            /* Most common reason to be here is "no chardev backend":
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             * just insta-drain the buffer, so the serial output
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             * goes into a void, rather than blocking the guest.
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             */
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            goto buffer_drained;
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        }
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        /* Transmit pending */
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        trace_cmsdk_apb_uart_tx_pending();
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        return G_SOURCE_REMOVE;
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    }
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buffer_drained:
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    /* Character successfully sent */
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    trace_cmsdk_apb_uart_tx(s->txbuf);
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    s->state &= ~R_STATE_TXFULL_MASK;
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    /* Going from TXFULL set to clear triggers the tx interrupt */
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    if (s->ctrl & R_CTRL_TX_INTEN_MASK) {
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        s->intstatus |= R_INTSTATUS_TX_MASK;
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    }
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    cmsdk_apb_uart_update(s);
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    return G_SOURCE_REMOVE;
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}
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static void uart_cancel_transmit(CMSDKAPBUART *s)
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{
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    if (s->watch_tag) {
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        g_source_remove(s->watch_tag);
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        s->watch_tag = 0;
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    }
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}
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static void uart_write(void *opaque, hwaddr offset, uint64_t value,
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                       unsigned size)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    trace_cmsdk_apb_uart_write(offset, value, size);
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    switch (offset) {
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    case A_DATA:
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        s->txbuf = value;
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        if (s->state & R_STATE_TXFULL_MASK) {
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            /* Buffer already full -- note the overrun and let the
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             * existing pending transmit callback handle the new char.
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             */
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            s->state |= R_STATE_TXOVERRUN_MASK;
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            cmsdk_apb_uart_update(s);
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        } else {
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            s->state |= R_STATE_TXFULL_MASK;
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            uart_transmit(NULL, G_IO_OUT, s);
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        }
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        break;
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    case A_STATE:
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        /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */
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        s->state &= ~(value &
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                      (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK));
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        cmsdk_apb_uart_update(s);
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        break;
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    case A_CTRL:
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        s->ctrl = value & 0x7f;
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        if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) {
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            qemu_log_mask(LOG_GUEST_ERROR,
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                          "CMSDK APB UART: Tx enabled with invalid baudrate\n");
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        }
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        cmsdk_apb_uart_update(s);
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        break;
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    case A_INTSTATUS:
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        /* All bits are W1C. Clearing the overrun interrupt bits really
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         * clears the overrun status bits in the STATE register (which
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         * is then reflected into the intstatus value by the update function).
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         */
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        s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK));
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        s->intstatus &= ~value;
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        cmsdk_apb_uart_update(s);
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        break;
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    case A_BAUDDIV:
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        s->bauddiv = value & 0xFFFFF;
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        uart_update_parameters(s);
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        break;
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    case A_PID4 ... A_CID3:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "CMSDK APB UART write: write to RO offset 0x%x\n",
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                      (int)offset);
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "CMSDK APB UART write: bad offset 0x%x\n", (int) offset);
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        break;
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    }
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}
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static const MemoryRegionOps uart_ops = {
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    .read = uart_read,
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    .write = uart_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void cmsdk_apb_uart_reset(DeviceState *dev)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(dev);
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    trace_cmsdk_apb_uart_reset();
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    uart_cancel_transmit(s);
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    s->state = 0;
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    s->ctrl = 0;
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    s->intstatus = 0;
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    s->bauddiv = 0;
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    s->txbuf = 0;
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    s->rxbuf = 0;
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}
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static void cmsdk_apb_uart_init(Object *obj)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    CMSDKAPBUART *s = CMSDK_APB_UART(obj);
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    memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
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    sysbus_init_mmio(sbd, &s->iomem);
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    sysbus_init_irq(sbd, &s->txint);
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    sysbus_init_irq(sbd, &s->rxint);
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    sysbus_init_irq(sbd, &s->txovrint);
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    sysbus_init_irq(sbd, &s->rxovrint);
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    sysbus_init_irq(sbd, &s->uartint);
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}
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static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(dev);
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    if (s->pclk_frq == 0) {
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        error_setg(errp, "CMSDK APB UART: pclk-frq property must be set");
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        return;
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    }
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    /* This UART has no flow control, so we do not need to register
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     * an event handler to deal with CHR_EVENT_BREAK.
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     */
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    qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
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                             NULL, NULL, s, NULL, true);
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}
350

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static int cmsdk_apb_uart_post_load(void *opaque, int version_id)
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{
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    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
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    /* If we have a pending character, arrange to resend it. */
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    if (s->state & R_STATE_TXFULL_MASK) {
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        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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                                             uart_transmit, s);
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    }
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    uart_update_parameters(s);
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    return 0;
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}
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static const VMStateDescription cmsdk_apb_uart_vmstate = {
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    .name = "cmsdk-apb-uart",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .post_load = cmsdk_apb_uart_post_load,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(state, CMSDKAPBUART),
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        VMSTATE_UINT32(ctrl, CMSDKAPBUART),
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        VMSTATE_UINT32(intstatus, CMSDKAPBUART),
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        VMSTATE_UINT32(bauddiv, CMSDKAPBUART),
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        VMSTATE_UINT8(txbuf, CMSDKAPBUART),
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        VMSTATE_UINT8(rxbuf, CMSDKAPBUART),
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        VMSTATE_END_OF_LIST()
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    }
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};
379

380
static Property cmsdk_apb_uart_properties[] = {
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    DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr),
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    DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0),
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    DEFINE_PROP_END_OF_LIST(),
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};
385

386
static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data)
387
{
388
    DeviceClass *dc = DEVICE_CLASS(klass);
389

390
    dc->realize = cmsdk_apb_uart_realize;
391
    dc->vmsd = &cmsdk_apb_uart_vmstate;
392
    dc->reset = cmsdk_apb_uart_reset;
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    device_class_set_props(dc, cmsdk_apb_uart_properties);
394
}
395

396
static const TypeInfo cmsdk_apb_uart_info = {
397
    .name = TYPE_CMSDK_APB_UART,
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    .parent = TYPE_SYS_BUS_DEVICE,
399
    .instance_size = sizeof(CMSDKAPBUART),
400
    .instance_init = cmsdk_apb_uart_init,
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    .class_init = cmsdk_apb_uart_class_init,
402
};
403

404
static void cmsdk_apb_uart_register_types(void)
405
{
406
    type_register_static(&cmsdk_apb_uart_info);
407
}
408

409
type_init(cmsdk_apb_uart_register_types);
410