opencv

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/* x86_features.c - x86 feature check
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 *
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 * Copyright (C) 2013 Intel Corporation. All rights reserved.
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 * Author:
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 *  Jim Kukunas
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 *
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 * For conditions of distribution and use, see copyright notice in zlib.h
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 */
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#include "../../zbuild.h"
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#include "x86_features.h"
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#ifdef _MSC_VER
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#  include <intrin.h>
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#else
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// Newer versions of GCC and clang come with cpuid.h
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#  include <cpuid.h>
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#endif
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#include <string.h>
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static inline void cpuid(int info, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#ifdef _MSC_VER
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    unsigned int registers[4];
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    __cpuid((int *)registers, info);
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    *eax = registers[0];
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    *ebx = registers[1];
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    *ecx = registers[2];
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    *edx = registers[3];
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#else
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    __cpuid(info, *eax, *ebx, *ecx, *edx);
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#endif
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}
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static inline void cpuidex(int info, int subinfo, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#ifdef _MSC_VER
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    unsigned int registers[4];
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    __cpuidex((int *)registers, info, subinfo);
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    *eax = registers[0];
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    *ebx = registers[1];
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    *ecx = registers[2];
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    *edx = registers[3];
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#else
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    __cpuid_count(info, subinfo, *eax, *ebx, *ecx, *edx);
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#endif
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}
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static inline uint64_t xgetbv(unsigned int xcr) {
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#ifdef _MSC_VER
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    return _xgetbv(xcr);
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#else
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    uint32_t eax, edx;
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    __asm__ ( ".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
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    return (uint64_t)(edx) << 32 | eax;
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#endif
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}
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void Z_INTERNAL x86_check_features(struct x86_cpu_features *features) {
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    unsigned eax, ebx, ecx, edx;
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    unsigned maxbasic;
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    cpuid(0, &maxbasic, &ebx, &ecx, &edx);
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    cpuid(1 /*CPU_PROCINFO_AND_FEATUREBITS*/, &eax, &ebx, &ecx, &edx);
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    features->has_sse2 = edx & 0x4000000;
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    features->has_ssse3 = ecx & 0x200;
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    features->has_sse42 = ecx & 0x100000;
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    features->has_pclmulqdq = ecx & 0x2;
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    if (ecx & 0x08000000) {
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        uint64_t xfeature = xgetbv(0);
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        features->has_os_save_ymm = ((xfeature & 0x06) == 0x06);
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        features->has_os_save_zmm = ((xfeature & 0xe6) == 0xe6);
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    }
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    if (maxbasic >= 7) {
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        cpuidex(7, 0, &eax, &ebx, &ecx, &edx);
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        // check BMI1 bit
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        // Reference: https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf
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        features->has_vpclmulqdq = ecx & 0x400;
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        // check AVX2 bit if the OS supports saving YMM registers
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        if (features->has_os_save_ymm) {
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            features->has_avx2 = ebx & 0x20;
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        }
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        // check AVX512 bits if the OS supports saving ZMM registers
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        if (features->has_os_save_zmm) {
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            features->has_avx512 = ebx & 0x00010000;
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            features->has_avx512vnni = ecx & 0x800;
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        }
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    }
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}
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