opencv

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/* adler32_avx2.c -- compute the Adler-32 checksum of a data stream
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 * Copyright (C) 1995-2011 Mark Adler
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 * Copyright (C) 2022 Adam Stylinski
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 * Authors:
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 *   Brian Bockelman <bockelman@gmail.com>
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 *   Adam Stylinski <kungfujesus06@gmail.com>
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 * For conditions of distribution and use, see copyright notice in zlib.h
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 */
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#ifdef X86_AVX2
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#include "../../zbuild.h"
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#include <immintrin.h>
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#include "../../adler32_fold.h"
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#include "../../adler32_p.h"
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#include "adler32_avx2_p.h"
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#include "x86_intrins.h"
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#ifdef X86_SSE42
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extern uint32_t adler32_fold_copy_sse42(uint32_t adler, uint8_t *dst, const uint8_t *src, size_t len);
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extern uint32_t adler32_ssse3(uint32_t adler, const uint8_t *src, size_t len);
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#define copy_sub32(a, b, c, d) adler32_fold_copy_sse42(a, b, c, d)
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#define sub32(a, b, c) adler32_ssse3(a, b, c)
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#else
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#define copy_sub32(a, b, c, d) adler32_copy_len_16(adler0, c, b, d, adler1)
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#define sub32(a, b, c) adler32_len_16(adler0, b, c, adler1)
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#endif
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static inline uint32_t adler32_fold_copy_impl(uint32_t adler, uint8_t *dst, const uint8_t *src, size_t len, const int COPY) {
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    if (src == NULL) return 1L;
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    if (len == 0) return adler;
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    uint32_t adler0, adler1;
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    adler1 = (adler >> 16) & 0xffff;
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    adler0 = adler & 0xffff;
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rem_peel:
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    if (len < 16) {
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        if (COPY) {
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            return adler32_copy_len_16(adler0, src, dst, len, adler1);
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        } else {
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            return adler32_len_16(adler0, src, len, adler1);
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        }
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    } else if (len < 32) {
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        if (COPY) {
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            return copy_sub32(adler, dst, src, len);
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        } else {
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            return sub32(adler, src, len);
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        }
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    }
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    __m256i vs1, vs2;
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    const __m256i dot2v = _mm256_setr_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15,
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                                           14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
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    const __m256i dot3v = _mm256_set1_epi16(1);
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    const __m256i zero = _mm256_setzero_si256();
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    while (len >= 32) {
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        vs1 = _mm256_zextsi128_si256(_mm_cvtsi32_si128(adler0));
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        vs2 = _mm256_zextsi128_si256(_mm_cvtsi32_si128(adler1));
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        __m256i vs1_0 = vs1;
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        __m256i vs3 = _mm256_setzero_si256();
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        size_t k = MIN(len, NMAX);
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        k -= k % 32;
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        len -= k;
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        while (k >= 32) {
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            /*
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               vs1 = adler + sum(c[i])
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               vs2 = sum2 + 32 vs1 + sum( (32-i+1) c[i] )
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            */
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            __m256i vbuf = _mm256_loadu_si256((__m256i*)src);
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            src += 32;
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            k -= 32;
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            __m256i vs1_sad = _mm256_sad_epu8(vbuf, zero); // Sum of abs diff, resulting in 2 x int32's
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            if (COPY) {
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                _mm256_storeu_si256((__m256i*)dst, vbuf);
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                dst += 32;
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            }
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            vs1 = _mm256_add_epi32(vs1, vs1_sad);
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            vs3 = _mm256_add_epi32(vs3, vs1_0);
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            __m256i v_short_sum2 = _mm256_maddubs_epi16(vbuf, dot2v); // sum 32 uint8s to 16 shorts
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            __m256i vsum2 = _mm256_madd_epi16(v_short_sum2, dot3v); // sum 16 shorts to 8 uint32s
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            vs2 = _mm256_add_epi32(vsum2, vs2);
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            vs1_0 = vs1;
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        }
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        /* Defer the multiplication with 32 to outside of the loop */
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        vs3 = _mm256_slli_epi32(vs3, 5);
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        vs2 = _mm256_add_epi32(vs2, vs3);
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        /* The compiler is generating the following sequence for this integer modulus
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         * when done the scalar way, in GPRs:
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         adler = (s1_unpack[0] % BASE) + (s1_unpack[1] % BASE) + (s1_unpack[2] % BASE) + (s1_unpack[3] % BASE) +
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                 (s1_unpack[4] % BASE) + (s1_unpack[5] % BASE) + (s1_unpack[6] % BASE) + (s1_unpack[7] % BASE);
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         mov    $0x80078071,%edi // move magic constant into 32 bit register %edi
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         ...
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         vmovd  %xmm1,%esi // move vector lane 0 to 32 bit register %esi
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         mov    %rsi,%rax  // zero-extend this value to 64 bit precision in %rax
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         imul   %rdi,%rsi // do a signed multiplication with magic constant and vector element
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         shr    $0x2f,%rsi // shift right by 47
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         imul   $0xfff1,%esi,%esi // do a signed multiplication with value truncated to 32 bits with 0xfff1
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         sub    %esi,%eax // subtract lower 32 bits of original vector value from modified one above
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         ...
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         // repeats for each element with vpextract instructions
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         This is tricky with AVX2 for a number of reasons:
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             1.) There's no 64 bit multiplication instruction, but there is a sequence to get there
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             2.) There's ways to extend vectors to 64 bit precision, but no simple way to truncate
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                 back down to 32 bit precision later (there is in AVX512)
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             3.) Full width integer multiplications aren't cheap
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         We can, however, do a relatively cheap sequence for horizontal sums.
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         Then, we simply do the integer modulus on the resulting 64 bit GPR, on a scalar value. It was
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         previously thought that casting to 64 bit precision was needed prior to the horizontal sum, but
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         that is simply not the case, as NMAX is defined as the maximum number of scalar sums that can be
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         performed on the maximum possible inputs before overflow
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         */
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         /* In AVX2-land, this trip through GPRs will probably be unavoidable, as there's no cheap and easy
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          * conversion from 64 bit integer to 32 bit (needed for the inexpensive modulus with a constant).
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          * This casting to 32 bit is cheap through GPRs (just register aliasing). See above for exactly
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          * what the compiler is doing to avoid integer divisions. */
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         adler0 = partial_hsum256(vs1) % BASE;
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         adler1 = hsum256(vs2) % BASE;
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    }
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    adler = adler0 | (adler1 << 16);
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    if (len) {
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        goto rem_peel;
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    }
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    return adler;
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}
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Z_INTERNAL uint32_t adler32_avx2(uint32_t adler, const uint8_t *src, size_t len) {
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    return adler32_fold_copy_impl(adler, NULL, src, len, 0);
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}
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Z_INTERNAL uint32_t adler32_fold_copy_avx2(uint32_t adler, uint8_t *dst, const uint8_t *src, size_t len) {
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    return adler32_fold_copy_impl(adler, dst, src, len, 1);
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}
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#endif
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