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thermosensor
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thermosensor
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Debug/termosensor.list
18 522 строки
696 KB
Andrianooo
Исправлена логика парсера, расчет CRC
28 апр 2026, 09:43
28 апр 2026, 09:43
a632529
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О чём код?
termosensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007278 0800010c 0800010c 0001010c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000007a8 08007384 08007384 00017384 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007b2c 08007b2c 000200c8 2**0 CONTENTS 4 .ARM 00000000 08007b2c 08007b2c 000200c8 2**0 CONTENTS 5 .preinit_array 00000000 08007b2c 08007b2c 000200c8 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007b2c 08007b2c 00017b2c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08007b30 08007b30 00017b30 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000000c8 20000000 08007b34 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000009a4 200000c8 08007bfc 000200c8 2**2 ALLOC 10 ._user_heap_stack 00000604 20000a6c 08007bfc 00020a6c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000200c8 2**0 CONTENTS, READONLY 12 .debug_info 000111f8 00000000 00000000 000200f1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002e2f 00000000 00000000 000312e9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001168 00000000 00000000 00034118 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00001040 00000000 00000000 00035280 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001a20e 00000000 00000000 000362c0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000143aa 00000000 00000000 000504ce 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00091f43 00000000 00000000 00064878 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000f67bb 2**0 CONTENTS, READONLY 20 .debug_frame 00004e30 00000000 00000000 000f680c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 200000c8 .word 0x200000c8 8000128: 00000000 .word 0x00000000 800012c: 0800736c .word 0x0800736c 08000130 <frame_dummy>: 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>) 8000134: b11b cbz r3, 800013e <frame_dummy+0xe> 8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>) 8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 200000cc .word 0x200000cc 8000148: 0800736c .word 0x0800736c 0800014c <strlen>: 800014c: 4603 mov r3, r0 800014e: f813 2b01 ldrb.w r2, [r3], #1 8000152: 2a00 cmp r2, #0 8000154: d1fb bne.n 800014e <strlen+0x2> 8000156: 1a18 subs r0, r3, r0 8000158: 3801 subs r0, #1 800015a: 4770 bx lr 0800015c <__aeabi_dmul>: 800015c: b570 push {r4, r5, r6, lr} 800015e: f04f 0cff mov.w ip, #255 ; 0xff 8000162: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20 800016a: bf1d ittte ne 800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000170: ea94 0f0c teqne r4, ip 8000174: ea95 0f0c teqne r5, ip 8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc> 800017c: 442c add r4, r5 800017e: ea81 0603 eor.w r6, r1, r3 8000182: ea21 514c bic.w r1, r1, ip, lsl #21 8000186: ea23 534c bic.w r3, r3, ip, lsl #21 800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12 800018e: bf18 it ne 8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000194: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000198: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4> 800019e: fba0 ce02 umull ip, lr, r0, r2 80001a2: f04f 0500 mov.w r5, #0 80001a6: fbe1 e502 umlal lr, r5, r1, r2 80001aa: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80001ae: fbe0 e503 umlal lr, r5, r0, r3 80001b2: f04f 0600 mov.w r6, #0 80001b6: fbe1 5603 umlal r5, r6, r1, r3 80001ba: f09c 0f00 teq ip, #0 80001be: bf18 it ne 80001c0: f04e 0e01 orrne.w lr, lr, #1 80001c4: f1a4 04ff sub.w r4, r4, #255 ; 0xff 80001c8: f5b6 7f00 cmp.w r6, #512 ; 0x200 80001cc: f564 7440 sbc.w r4, r4, #768 ; 0x300 80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80> 80001d2: ea5f 0e4e movs.w lr, lr, lsl #1 80001d6: 416d adcs r5, r5 80001d8: eb46 0606 adc.w r6, r6, r6 80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11 80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21 80001e4: ea4f 20c5 mov.w r0, r5, lsl #11 80001e8: ea40 505e orr.w r0, r0, lr, lsr #21 80001ec: ea4f 2ece mov.w lr, lr, lsl #11 80001f0: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 80001f4: bf88 it hi 80001f6: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde> 80001fc: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 8000200: bf08 it eq 8000202: ea5f 0e50 movseq.w lr, r0, lsr #1 8000206: f150 0000 adcs.w r0, r0, #0 800020a: eb41 5104 adc.w r1, r1, r4, lsl #20 800020e: bd70 pop {r4, r5, r6, pc} 8000210: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000214: ea46 0101 orr.w r1, r6, r1 8000218: ea40 0002 orr.w r0, r0, r2 800021c: ea81 0103 eor.w r1, r1, r3 8000220: ebb4 045c subs.w r4, r4, ip, lsr #1 8000224: bfc2 ittt gt 8000226: ebd4 050c rsbsgt r5, r4, ip 800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800022e: bd70 popgt {r4, r5, r6, pc} 8000230: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000234: f04f 0e00 mov.w lr, #0 8000238: 3c01 subs r4, #1 800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238> 800023e: f114 0f36 cmn.w r4, #54 ; 0x36 8000242: bfde ittt le 8000244: 2000 movle r0, #0 8000246: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 800024a: bd70 pople {r4, r5, r6, pc} 800024c: f1c4 0400 rsb r4, r4, #0 8000250: 3c20 subs r4, #32 8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164> 8000254: 340c adds r4, #12 8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134> 8000258: f104 0414 add.w r4, r4, #20 800025c: f1c4 0520 rsb r5, r4, #32 8000260: fa00 f305 lsl.w r3, r0, r5 8000264: fa20 f004 lsr.w r0, r0, r4 8000268: fa01 f205 lsl.w r2, r1, r5 800026c: ea40 0002 orr.w r0, r0, r2 8000270: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 8000274: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31 800027c: fa21 f604 lsr.w r6, r1, r4 8000280: eb42 0106 adc.w r1, r2, r6 8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000288: bf08 it eq 800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800028e: bd70 pop {r4, r5, r6, pc} 8000290: f1c4 040c rsb r4, r4, #12 8000294: f1c4 0520 rsb r5, r4, #32 8000298: fa00 f304 lsl.w r3, r0, r4 800029c: fa20 f005 lsr.w r0, r0, r5 80002a0: fa01 f204 lsl.w r2, r1, r4 80002a4: ea40 0002 orr.w r0, r0, r2 80002a8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31 80002b0: f141 0100 adc.w r1, r1, #0 80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80002b8: bf08 it eq 80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80002be: bd70 pop {r4, r5, r6, pc} 80002c0: f1c4 0520 rsb r5, r4, #32 80002c4: fa00 f205 lsl.w r2, r0, r5 80002c8: ea4e 0e02 orr.w lr, lr, r2 80002cc: fa20 f304 lsr.w r3, r0, r4 80002d0: fa01 f205 lsl.w r2, r1, r5 80002d4: ea43 0302 orr.w r3, r3, r2 80002d8: fa21 f004 lsr.w r0, r1, r4 80002dc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80002e0: fa21 f204 lsr.w r2, r1, r4 80002e4: ea20 0002 bic.w r0, r0, r2 80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31 80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80002f0: bf08 it eq 80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80002f6: bd70 pop {r4, r5, r6, pc} 80002f8: f094 0f00 teq r4, #0 80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2> 80002fe: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 8000302: 0040 lsls r0, r0, #1 8000304: eb41 0101 adc.w r1, r1, r1 8000308: f411 1f80 tst.w r1, #1048576 ; 0x100000 800030c: bf08 it eq 800030e: 3c01 subeq r4, #1 8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6> 8000312: ea41 0106 orr.w r1, r1, r6 8000316: f095 0f00 teq r5, #0 800031a: bf18 it ne 800031c: 4770 bxne lr 800031e: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 8000322: 0052 lsls r2, r2, #1 8000324: eb43 0303 adc.w r3, r3, r3 8000328: f413 1f80 tst.w r3, #1048576 ; 0x100000 800032c: bf08 it eq 800032e: 3d01 subeq r5, #1 8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6> 8000332: ea43 0306 orr.w r3, r3, r6 8000336: 4770 bx lr 8000338: ea94 0f0c teq r4, ip 800033c: ea0c 5513 and.w r5, ip, r3, lsr #20 8000340: bf18 it ne 8000342: ea95 0f0c teqne r5, ip 8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206> 8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1 800034c: bf18 it ne 800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c> 8000354: ea81 0103 eor.w r1, r1, r3 8000358: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800035c: f04f 0000 mov.w r0, #0 8000360: bd70 pop {r4, r5, r6, pc} 8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000366: bf06 itte eq 8000368: 4610 moveq r0, r2 800036a: 4619 moveq r1, r3 800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a> 8000372: ea94 0f0c teq r4, ip 8000376: d102 bne.n 800037e <__aeabi_dmul+0x222> 8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12 800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a> 800037e: ea95 0f0c teq r5, ip 8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234> 8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12 8000388: bf1c itt ne 800038a: 4610 movne r0, r2 800038c: 4619 movne r1, r3 800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a> 8000390: ea81 0103 eor.w r1, r1, r3 8000394: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000398: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 800039c: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80003a0: f04f 0000 mov.w r0, #0 80003a4: bd70 pop {r4, r5, r6, pc} 80003a6: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80003aa: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80003ae: bd70 pop {r4, r5, r6, pc} 080003b0 <__aeabi_drsub>: 80003b0: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 80003b4: e002 b.n 80003bc <__adddf3> 80003b6: bf00 nop 080003b8 <__aeabi_dsub>: 80003b8: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 080003bc <__adddf3>: 80003bc: b530 push {r4, r5, lr} 80003be: ea4f 0441 mov.w r4, r1, lsl #1 80003c2: ea4f 0543 mov.w r5, r3, lsl #1 80003c6: ea94 0f05 teq r4, r5 80003ca: bf08 it eq 80003cc: ea90 0f02 teqeq r0, r2 80003d0: bf1f itttt ne 80003d2: ea54 0c00 orrsne.w ip, r4, r0 80003d6: ea55 0c02 orrsne.w ip, r5, r2 80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21 80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21 80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee> 80003e6: ea4f 5454 mov.w r4, r4, lsr #21 80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21 80003ee: bfb8 it lt 80003f0: 426d neglt r5, r5 80003f2: dd0c ble.n 800040e <__adddf3+0x52> 80003f4: 442c add r4, r5 80003f6: ea80 0202 eor.w r2, r0, r2 80003fa: ea81 0303 eor.w r3, r1, r3 80003fe: ea82 0000 eor.w r0, r2, r0 8000402: ea83 0101 eor.w r1, r3, r1 8000406: ea80 0202 eor.w r2, r0, r2 800040a: ea81 0303 eor.w r3, r1, r3 800040e: 2d36 cmp r5, #54 ; 0x36 8000410: bf88 it hi 8000412: bd30 pophi {r4, r5, pc} 8000414: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000418: ea4f 3101 mov.w r1, r1, lsl #12 800041c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000424: d002 beq.n 800042c <__adddf3+0x70> 8000426: 4240 negs r0, r0 8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1 800042c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 8000430: ea4f 3303 mov.w r3, r3, lsl #12 8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12 8000438: d002 beq.n 8000440 <__adddf3+0x84> 800043a: 4252 negs r2, r2 800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000440: ea94 0f05 teq r4, r5 8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da> 8000448: f1a4 0401 sub.w r4, r4, #1 800044c: f1d5 0e20 rsbs lr, r5, #32 8000450: db0d blt.n 800046e <__adddf3+0xb2> 8000452: fa02 fc0e lsl.w ip, r2, lr 8000456: fa22 f205 lsr.w r2, r2, r5 800045a: 1880 adds r0, r0, r2 800045c: f141 0100 adc.w r1, r1, #0 8000460: fa03 f20e lsl.w r2, r3, lr 8000464: 1880 adds r0, r0, r2 8000466: fa43 f305 asr.w r3, r3, r5 800046a: 4159 adcs r1, r3 800046c: e00e b.n 800048c <__adddf3+0xd0> 800046e: f1a5 0520 sub.w r5, r5, #32 8000472: f10e 0e20 add.w lr, lr, #32 8000476: 2a01 cmp r2, #1 8000478: fa03 fc0e lsl.w ip, r3, lr 800047c: bf28 it cs 800047e: f04c 0c02 orrcs.w ip, ip, #2 8000482: fa43 f305 asr.w r3, r3, r5 8000486: 18c0 adds r0, r0, r3 8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31 800048c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000490: d507 bpl.n 80004a2 <__adddf3+0xe6> 8000492: f04f 0e00 mov.w lr, #0 8000496: f1dc 0c00 rsbs ip, ip, #0 800049a: eb7e 0000 sbcs.w r0, lr, r0 800049e: eb6e 0101 sbc.w r1, lr, r1 80004a2: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 80004a6: d31b bcc.n 80004e0 <__adddf3+0x124> 80004a8: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c> 80004ae: 0849 lsrs r1, r1, #1 80004b0: ea5f 0030 movs.w r0, r0, rrx 80004b4: ea4f 0c3c mov.w ip, ip, rrx 80004b8: f104 0401 add.w r4, r4, #1 80004bc: ea4f 5244 mov.w r2, r4, lsl #21 80004c0: f512 0f80 cmn.w r2, #4194304 ; 0x400000 80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240> 80004c8: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 80004cc: bf08 it eq 80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1 80004d2: f150 0000 adcs.w r0, r0, #0 80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20 80004da: ea41 0105 orr.w r1, r1, r5 80004de: bd30 pop {r4, r5, pc} 80004e0: ea5f 0c4c movs.w ip, ip, lsl #1 80004e4: 4140 adcs r0, r0 80004e6: eb41 0101 adc.w r1, r1, r1 80004ea: 3c01 subs r4, #1 80004ec: bf28 it cs 80004ee: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c> 80004f4: f091 0f00 teq r1, #0 80004f8: bf04 itt eq 80004fa: 4601 moveq r1, r0 80004fc: 2000 moveq r0, #0 80004fe: fab1 f381 clz r3, r1 8000502: bf08 it eq 8000504: 3320 addeq r3, #32 8000506: f1a3 030b sub.w r3, r3, #11 800050a: f1b3 0220 subs.w r2, r3, #32 800050e: da0c bge.n 800052a <__adddf3+0x16e> 8000510: 320c adds r2, #12 8000512: dd08 ble.n 8000526 <__adddf3+0x16a> 8000514: f102 0c14 add.w ip, r2, #20 8000518: f1c2 020c rsb r2, r2, #12 800051c: fa01 f00c lsl.w r0, r1, ip 8000520: fa21 f102 lsr.w r1, r1, r2 8000524: e00c b.n 8000540 <__adddf3+0x184> 8000526: f102 0214 add.w r2, r2, #20 800052a: bfd8 it le 800052c: f1c2 0c20 rsble ip, r2, #32 8000530: fa01 f102 lsl.w r1, r1, r2 8000534: fa20 fc0c lsr.w ip, r0, ip 8000538: bfdc itt le 800053a: ea41 010c orrle.w r1, r1, ip 800053e: 4090 lslle r0, r2 8000540: 1ae4 subs r4, r4, r3 8000542: bfa2 ittt ge 8000544: eb01 5104 addge.w r1, r1, r4, lsl #20 8000548: 4329 orrge r1, r5 800054a: bd30 popge {r4, r5, pc} 800054c: ea6f 0404 mvn.w r4, r4 8000550: 3c1f subs r4, #31 8000552: da1c bge.n 800058e <__adddf3+0x1d2> 8000554: 340c adds r4, #12 8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba> 8000558: f104 0414 add.w r4, r4, #20 800055c: f1c4 0220 rsb r2, r4, #32 8000560: fa20 f004 lsr.w r0, r0, r4 8000564: fa01 f302 lsl.w r3, r1, r2 8000568: ea40 0003 orr.w r0, r0, r3 800056c: fa21 f304 lsr.w r3, r1, r4 8000570: ea45 0103 orr.w r1, r5, r3 8000574: bd30 pop {r4, r5, pc} 8000576: f1c4 040c rsb r4, r4, #12 800057a: f1c4 0220 rsb r2, r4, #32 800057e: fa20 f002 lsr.w r0, r0, r2 8000582: fa01 f304 lsl.w r3, r1, r4 8000586: ea40 0003 orr.w r0, r0, r3 800058a: 4629 mov r1, r5 800058c: bd30 pop {r4, r5, pc} 800058e: fa21 f004 lsr.w r0, r1, r4 8000592: 4629 mov r1, r5 8000594: bd30 pop {r4, r5, pc} 8000596: f094 0f00 teq r4, #0 800059a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800059e: bf06 itte eq 80005a0: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 80005a4: 3401 addeq r4, #1 80005a6: 3d01 subne r5, #1 80005a8: e74e b.n 8000448 <__adddf3+0x8c> 80005aa: ea7f 5c64 mvns.w ip, r4, asr #21 80005ae: bf18 it ne 80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21 80005b4: d029 beq.n 800060a <__adddf3+0x24e> 80005b6: ea94 0f05 teq r4, r5 80005ba: bf08 it eq 80005bc: ea90 0f02 teqeq r0, r2 80005c0: d005 beq.n 80005ce <__adddf3+0x212> 80005c2: ea54 0c00 orrs.w ip, r4, r0 80005c6: bf04 itt eq 80005c8: 4619 moveq r1, r3 80005ca: 4610 moveq r0, r2 80005cc: bd30 pop {r4, r5, pc} 80005ce: ea91 0f03 teq r1, r3 80005d2: bf1e ittt ne 80005d4: 2100 movne r1, #0 80005d6: 2000 movne r0, #0 80005d8: bd30 popne {r4, r5, pc} 80005da: ea5f 5c54 movs.w ip, r4, lsr #21 80005de: d105 bne.n 80005ec <__adddf3+0x230> 80005e0: 0040 lsls r0, r0, #1 80005e2: 4149 adcs r1, r1 80005e4: bf28 it cs 80005e6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 80005ea: bd30 pop {r4, r5, pc} 80005ec: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 80005f0: bf3c itt cc 80005f2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 80005f6: bd30 popcc {r4, r5, pc} 80005f8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80005fc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000600: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000604: f04f 0000 mov.w r0, #0 8000608: bd30 pop {r4, r5, pc} 800060a: ea7f 5c64 mvns.w ip, r4, asr #21 800060e: bf1a itte ne 8000610: 4619 movne r1, r3 8000612: 4610 movne r0, r2 8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000618: bf1c itt ne 800061a: 460b movne r3, r1 800061c: 4602 movne r2, r0 800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000622: bf06 itte eq 8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000628: ea91 0f03 teqeq r1, r3 800062c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 8000630: bd30 pop {r4, r5, pc} 8000632: bf00 nop 08000634 <__aeabi_ui2d>: 8000634: f090 0f00 teq r0, #0 8000638: bf04 itt eq 800063a: 2100 moveq r1, #0 800063c: 4770 bxeq lr 800063e: b530 push {r4, r5, lr} 8000640: f44f 6480 mov.w r4, #1024 ; 0x400 8000644: f104 0432 add.w r4, r4, #50 ; 0x32 8000648: f04f 0500 mov.w r5, #0 800064c: f04f 0100 mov.w r1, #0 8000650: e750 b.n 80004f4 <__adddf3+0x138> 8000652: bf00 nop 08000654 <__aeabi_i2d>: 8000654: f090 0f00 teq r0, #0 8000658: bf04 itt eq 800065a: 2100 moveq r1, #0 800065c: 4770 bxeq lr 800065e: b530 push {r4, r5, lr} 8000660: f44f 6480 mov.w r4, #1024 ; 0x400 8000664: f104 0432 add.w r4, r4, #50 ; 0x32 8000668: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 800066c: bf48 it mi 800066e: 4240 negmi r0, r0 8000670: f04f 0100 mov.w r1, #0 8000674: e73e b.n 80004f4 <__adddf3+0x138> 8000676: bf00 nop 08000678 <__aeabi_f2d>: 8000678: 0042 lsls r2, r0, #1 800067a: ea4f 01e2 mov.w r1, r2, asr #3 800067e: ea4f 0131 mov.w r1, r1, rrx 8000682: ea4f 7002 mov.w r0, r2, lsl #28 8000686: bf1f itttt ne 8000688: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 800068c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000690: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000694: 4770 bxne lr 8000696: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800069a: bf08 it eq 800069c: 4770 bxeq lr 800069e: f093 4f7f teq r3, #4278190080 ; 0xff000000 80006a2: bf04 itt eq 80006a4: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 80006a8: 4770 bxeq lr 80006aa: b530 push {r4, r5, lr} 80006ac: f44f 7460 mov.w r4, #896 ; 0x380 80006b0: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80006b4: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006b8: e71c b.n 80004f4 <__adddf3+0x138> 80006ba: bf00 nop 080006bc <__aeabi_ul2d>: 80006bc: ea50 0201 orrs.w r2, r0, r1 80006c0: bf08 it eq 80006c2: 4770 bxeq lr 80006c4: b530 push {r4, r5, lr} 80006c6: f04f 0500 mov.w r5, #0 80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16> 080006cc <__aeabi_l2d>: 80006cc: ea50 0201 orrs.w r2, r0, r1 80006d0: bf08 it eq 80006d2: 4770 bxeq lr 80006d4: b530 push {r4, r5, lr} 80006d6: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16> 80006dc: 4240 negs r0, r0 80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1 80006e2: f44f 6480 mov.w r4, #1024 ; 0x400 80006e6: f104 0432 add.w r4, r4, #50 ; 0x32 80006ea: ea5f 5c91 movs.w ip, r1, lsr #22 80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6> 80006f2: f04f 0203 mov.w r2, #3 80006f6: ea5f 0cdc movs.w ip, ip, lsr #3 80006fa: bf18 it ne 80006fc: 3203 addne r2, #3 80006fe: ea5f 0cdc movs.w ip, ip, lsr #3 8000702: bf18 it ne 8000704: 3203 addne r2, #3 8000706: eb02 02dc add.w r2, r2, ip, lsr #3 800070a: f1c2 0320 rsb r3, r2, #32 800070e: fa00 fc03 lsl.w ip, r0, r3 8000712: fa20 f002 lsr.w r0, r0, r2 8000716: fa01 fe03 lsl.w lr, r1, r3 800071a: ea40 000e orr.w r0, r0, lr 800071e: fa21 f102 lsr.w r1, r1, r2 8000722: 4414 add r4, r2 8000724: e6bd b.n 80004a2 <__adddf3+0xe6> 8000726: bf00 nop 08000728 <__aeabi_d2uiz>: 8000728: 004a lsls r2, r1, #1 800072a: d211 bcs.n 8000750 <__aeabi_d2uiz+0x28> 800072c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000730: d211 bcs.n 8000756 <__aeabi_d2uiz+0x2e> 8000732: d50d bpl.n 8000750 <__aeabi_d2uiz+0x28> 8000734: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000738: ebb3 5262 subs.w r2, r3, r2, asr #21 800073c: d40e bmi.n 800075c <__aeabi_d2uiz+0x34> 800073e: ea4f 23c1 mov.w r3, r1, lsl #11 8000742: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000746: ea43 5350 orr.w r3, r3, r0, lsr #21 800074a: fa23 f002 lsr.w r0, r3, r2 800074e: 4770 bx lr 8000750: f04f 0000 mov.w r0, #0 8000754: 4770 bx lr 8000756: ea50 3001 orrs.w r0, r0, r1, lsl #12 800075a: d102 bne.n 8000762 <__aeabi_d2uiz+0x3a> 800075c: f04f 30ff mov.w r0, #4294967295 8000760: 4770 bx lr 8000762: f04f 0000 mov.w r0, #0 8000766: 4770 bx lr 08000768 <__aeabi_frsub>: 8000768: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 800076c: e002 b.n 8000774 <__addsf3> 800076e: bf00 nop 08000770 <__aeabi_fsub>: 8000770: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 08000774 <__addsf3>: 8000774: 0042 lsls r2, r0, #1 8000776: bf1f itttt ne 8000778: ea5f 0341 movsne.w r3, r1, lsl #1 800077c: ea92 0f03 teqne r2, r3 8000780: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000784: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000788: d06a beq.n 8000860 <__addsf3+0xec> 800078a: ea4f 6212 mov.w r2, r2, lsr #24 800078e: ebd2 6313 rsbs r3, r2, r3, lsr #24 8000792: bfc1 itttt gt 8000794: 18d2 addgt r2, r2, r3 8000796: 4041 eorgt r1, r0 8000798: 4048 eorgt r0, r1 800079a: 4041 eorgt r1, r0 800079c: bfb8 it lt 800079e: 425b neglt r3, r3 80007a0: 2b19 cmp r3, #25 80007a2: bf88 it hi 80007a4: 4770 bxhi lr 80007a6: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 80007aa: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 80007ae: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 80007b2: bf18 it ne 80007b4: 4240 negne r0, r0 80007b6: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80007ba: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 80007be: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 80007c2: bf18 it ne 80007c4: 4249 negne r1, r1 80007c6: ea92 0f03 teq r2, r3 80007ca: d03f beq.n 800084c <__addsf3+0xd8> 80007cc: f1a2 0201 sub.w r2, r2, #1 80007d0: fa41 fc03 asr.w ip, r1, r3 80007d4: eb10 000c adds.w r0, r0, ip 80007d8: f1c3 0320 rsb r3, r3, #32 80007dc: fa01 f103 lsl.w r1, r1, r3 80007e0: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 80007e4: d502 bpl.n 80007ec <__addsf3+0x78> 80007e6: 4249 negs r1, r1 80007e8: eb60 0040 sbc.w r0, r0, r0, lsl #1 80007ec: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 80007f0: d313 bcc.n 800081a <__addsf3+0xa6> 80007f2: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 80007f6: d306 bcc.n 8000806 <__addsf3+0x92> 80007f8: 0840 lsrs r0, r0, #1 80007fa: ea4f 0131 mov.w r1, r1, rrx 80007fe: f102 0201 add.w r2, r2, #1 8000802: 2afe cmp r2, #254 ; 0xfe 8000804: d251 bcs.n 80008aa <__addsf3+0x136> 8000806: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 800080a: eb40 50c2 adc.w r0, r0, r2, lsl #23 800080e: bf08 it eq 8000810: f020 0001 biceq.w r0, r0, #1 8000814: ea40 0003 orr.w r0, r0, r3 8000818: 4770 bx lr 800081a: 0049 lsls r1, r1, #1 800081c: eb40 0000 adc.w r0, r0, r0 8000820: 3a01 subs r2, #1 8000822: bf28 it cs 8000824: f5b0 0f00 cmpcs.w r0, #8388608 ; 0x800000 8000828: d2ed bcs.n 8000806 <__addsf3+0x92> 800082a: fab0 fc80 clz ip, r0 800082e: f1ac 0c08 sub.w ip, ip, #8 8000832: ebb2 020c subs.w r2, r2, ip 8000836: fa00 f00c lsl.w r0, r0, ip 800083a: bfaa itet ge 800083c: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000840: 4252 neglt r2, r2 8000842: 4318 orrge r0, r3 8000844: bfbc itt lt 8000846: 40d0 lsrlt r0, r2 8000848: 4318 orrlt r0, r3 800084a: 4770 bx lr 800084c: f092 0f00 teq r2, #0 8000850: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 8000854: bf06 itte eq 8000856: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 800085a: 3201 addeq r2, #1 800085c: 3b01 subne r3, #1 800085e: e7b5 b.n 80007cc <__addsf3+0x58> 8000860: ea4f 0341 mov.w r3, r1, lsl #1 8000864: ea7f 6c22 mvns.w ip, r2, asr #24 8000868: bf18 it ne 800086a: ea7f 6c23 mvnsne.w ip, r3, asr #24 800086e: d021 beq.n 80008b4 <__addsf3+0x140> 8000870: ea92 0f03 teq r2, r3 8000874: d004 beq.n 8000880 <__addsf3+0x10c> 8000876: f092 0f00 teq r2, #0 800087a: bf08 it eq 800087c: 4608 moveq r0, r1 800087e: 4770 bx lr 8000880: ea90 0f01 teq r0, r1 8000884: bf1c itt ne 8000886: 2000 movne r0, #0 8000888: 4770 bxne lr 800088a: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 800088e: d104 bne.n 800089a <__addsf3+0x126> 8000890: 0040 lsls r0, r0, #1 8000892: bf28 it cs 8000894: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 8000898: 4770 bx lr 800089a: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 800089e: bf3c itt cc 80008a0: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 80008a4: 4770 bxcc lr 80008a6: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 80008aa: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 80008ae: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 80008b2: 4770 bx lr 80008b4: ea7f 6222 mvns.w r2, r2, asr #24 80008b8: bf16 itet ne 80008ba: 4608 movne r0, r1 80008bc: ea7f 6323 mvnseq.w r3, r3, asr #24 80008c0: 4601 movne r1, r0 80008c2: 0242 lsls r2, r0, #9 80008c4: bf06 itte eq 80008c6: ea5f 2341 movseq.w r3, r1, lsl #9 80008ca: ea90 0f01 teqeq r0, r1 80008ce: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 80008d2: 4770 bx lr 080008d4 <__aeabi_ui2f>: 80008d4: f04f 0300 mov.w r3, #0 80008d8: e004 b.n 80008e4 <__aeabi_i2f+0x8> 80008da: bf00 nop 080008dc <__aeabi_i2f>: 80008dc: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 80008e0: bf48 it mi 80008e2: 4240 negmi r0, r0 80008e4: ea5f 0c00 movs.w ip, r0 80008e8: bf08 it eq 80008ea: 4770 bxeq lr 80008ec: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 80008f0: 4601 mov r1, r0 80008f2: f04f 0000 mov.w r0, #0 80008f6: e01c b.n 8000932 <__aeabi_l2f+0x2a> 080008f8 <__aeabi_ul2f>: 80008f8: ea50 0201 orrs.w r2, r0, r1 80008fc: bf08 it eq 80008fe: 4770 bxeq lr 8000900: f04f 0300 mov.w r3, #0 8000904: e00a b.n 800091c <__aeabi_l2f+0x14> 8000906: bf00 nop 08000908 <__aeabi_l2f>: 8000908: ea50 0201 orrs.w r2, r0, r1 800090c: bf08 it eq 800090e: 4770 bxeq lr 8000910: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 8000914: d502 bpl.n 800091c <__aeabi_l2f+0x14> 8000916: 4240 negs r0, r0 8000918: eb61 0141 sbc.w r1, r1, r1, lsl #1 800091c: ea5f 0c01 movs.w ip, r1 8000920: bf02 ittt eq 8000922: 4684 moveq ip, r0 8000924: 4601 moveq r1, r0 8000926: 2000 moveq r0, #0 8000928: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 800092c: bf08 it eq 800092e: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 8000932: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 8000936: fabc f28c clz r2, ip 800093a: 3a08 subs r2, #8 800093c: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000940: db10 blt.n 8000964 <__aeabi_l2f+0x5c> 8000942: fa01 fc02 lsl.w ip, r1, r2 8000946: 4463 add r3, ip 8000948: fa00 fc02 lsl.w ip, r0, r2 800094c: f1c2 0220 rsb r2, r2, #32 8000950: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000954: fa20 f202 lsr.w r2, r0, r2 8000958: eb43 0002 adc.w r0, r3, r2 800095c: bf08 it eq 800095e: f020 0001 biceq.w r0, r0, #1 8000962: 4770 bx lr 8000964: f102 0220 add.w r2, r2, #32 8000968: fa01 fc02 lsl.w ip, r1, r2 800096c: f1c2 0220 rsb r2, r2, #32 8000970: ea50 004c orrs.w r0, r0, ip, lsl #1 8000974: fa21 f202 lsr.w r2, r1, r2 8000978: eb43 0002 adc.w r0, r3, r2 800097c: bf08 it eq 800097e: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000982: 4770 bx lr 08000984 <__aeabi_fmul>: 8000984: f04f 0cff mov.w ip, #255 ; 0xff 8000988: ea1c 52d0 ands.w r2, ip, r0, lsr #23 800098c: bf1e ittt ne 800098e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000992: ea92 0f0c teqne r2, ip 8000996: ea93 0f0c teqne r3, ip 800099a: d06f beq.n 8000a7c <__aeabi_fmul+0xf8> 800099c: 441a add r2, r3 800099e: ea80 0c01 eor.w ip, r0, r1 80009a2: 0240 lsls r0, r0, #9 80009a4: bf18 it ne 80009a6: ea5f 2141 movsne.w r1, r1, lsl #9 80009aa: d01e beq.n 80009ea <__aeabi_fmul+0x66> 80009ac: f04f 6300 mov.w r3, #134217728 ; 0x8000000 80009b0: ea43 1050 orr.w r0, r3, r0, lsr #5 80009b4: ea43 1151 orr.w r1, r3, r1, lsr #5 80009b8: fba0 3101 umull r3, r1, r0, r1 80009bc: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 80009c0: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 80009c4: bf3e ittt cc 80009c6: 0049 lslcc r1, r1, #1 80009c8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 80009cc: 005b lslcc r3, r3, #1 80009ce: ea40 0001 orr.w r0, r0, r1 80009d2: f162 027f sbc.w r2, r2, #127 ; 0x7f 80009d6: 2afd cmp r2, #253 ; 0xfd 80009d8: d81d bhi.n 8000a16 <__aeabi_fmul+0x92> 80009da: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80009de: eb40 50c2 adc.w r0, r0, r2, lsl #23 80009e2: bf08 it eq 80009e4: f020 0001 biceq.w r0, r0, #1 80009e8: 4770 bx lr 80009ea: f090 0f00 teq r0, #0 80009ee: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 80009f2: bf08 it eq 80009f4: 0249 lsleq r1, r1, #9 80009f6: ea4c 2050 orr.w r0, ip, r0, lsr #9 80009fa: ea40 2051 orr.w r0, r0, r1, lsr #9 80009fe: 3a7f subs r2, #127 ; 0x7f 8000a00: bfc2 ittt gt 8000a02: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000a06: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000a0a: 4770 bxgt lr 8000a0c: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000a10: f04f 0300 mov.w r3, #0 8000a14: 3a01 subs r2, #1 8000a16: dc5d bgt.n 8000ad4 <__aeabi_fmul+0x150> 8000a18: f112 0f19 cmn.w r2, #25 8000a1c: bfdc itt le 8000a1e: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 8000a22: 4770 bxle lr 8000a24: f1c2 0200 rsb r2, r2, #0 8000a28: 0041 lsls r1, r0, #1 8000a2a: fa21 f102 lsr.w r1, r1, r2 8000a2e: f1c2 0220 rsb r2, r2, #32 8000a32: fa00 fc02 lsl.w ip, r0, r2 8000a36: ea5f 0031 movs.w r0, r1, rrx 8000a3a: f140 0000 adc.w r0, r0, #0 8000a3e: ea53 034c orrs.w r3, r3, ip, lsl #1 8000a42: bf08 it eq 8000a44: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000a48: 4770 bx lr 8000a4a: f092 0f00 teq r2, #0 8000a4e: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000a52: bf02 ittt eq 8000a54: 0040 lsleq r0, r0, #1 8000a56: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000a5a: 3a01 subeq r2, #1 8000a5c: d0f9 beq.n 8000a52 <__aeabi_fmul+0xce> 8000a5e: ea40 000c orr.w r0, r0, ip 8000a62: f093 0f00 teq r3, #0 8000a66: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000a6a: bf02 ittt eq 8000a6c: 0049 lsleq r1, r1, #1 8000a6e: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000a72: 3b01 subeq r3, #1 8000a74: d0f9 beq.n 8000a6a <__aeabi_fmul+0xe6> 8000a76: ea41 010c orr.w r1, r1, ip 8000a7a: e78f b.n 800099c <__aeabi_fmul+0x18> 8000a7c: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000a80: ea92 0f0c teq r2, ip 8000a84: bf18 it ne 8000a86: ea93 0f0c teqne r3, ip 8000a8a: d00a beq.n 8000aa2 <__aeabi_fmul+0x11e> 8000a8c: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000a90: bf18 it ne 8000a92: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000a96: d1d8 bne.n 8000a4a <__aeabi_fmul+0xc6> 8000a98: ea80 0001 eor.w r0, r0, r1 8000a9c: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000aa0: 4770 bx lr 8000aa2: f090 0f00 teq r0, #0 8000aa6: bf17 itett ne 8000aa8: f090 4f00 teqne r0, #2147483648 ; 0x80000000 8000aac: 4608 moveq r0, r1 8000aae: f091 0f00 teqne r1, #0 8000ab2: f091 4f00 teqne r1, #2147483648 ; 0x80000000 8000ab6: d014 beq.n 8000ae2 <__aeabi_fmul+0x15e> 8000ab8: ea92 0f0c teq r2, ip 8000abc: d101 bne.n 8000ac2 <__aeabi_fmul+0x13e> 8000abe: 0242 lsls r2, r0, #9 8000ac0: d10f bne.n 8000ae2 <__aeabi_fmul+0x15e> 8000ac2: ea93 0f0c teq r3, ip 8000ac6: d103 bne.n 8000ad0 <__aeabi_fmul+0x14c> 8000ac8: 024b lsls r3, r1, #9 8000aca: bf18 it ne 8000acc: 4608 movne r0, r1 8000ace: d108 bne.n 8000ae2 <__aeabi_fmul+0x15e> 8000ad0: ea80 0001 eor.w r0, r0, r1 8000ad4: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000ad8: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000adc: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000ae0: 4770 bx lr 8000ae2: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000ae6: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 8000aea: 4770 bx lr 08000aec <__aeabi_fdiv>: 8000aec: f04f 0cff mov.w ip, #255 ; 0xff 8000af0: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000af4: bf1e ittt ne 8000af6: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000afa: ea92 0f0c teqne r2, ip 8000afe: ea93 0f0c teqne r3, ip 8000b02: d069 beq.n 8000bd8 <__aeabi_fdiv+0xec> 8000b04: eba2 0203 sub.w r2, r2, r3 8000b08: ea80 0c01 eor.w ip, r0, r1 8000b0c: 0249 lsls r1, r1, #9 8000b0e: ea4f 2040 mov.w r0, r0, lsl #9 8000b12: d037 beq.n 8000b84 <__aeabi_fdiv+0x98> 8000b14: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8000b18: ea43 1111 orr.w r1, r3, r1, lsr #4 8000b1c: ea43 1310 orr.w r3, r3, r0, lsr #4 8000b20: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000b24: 428b cmp r3, r1 8000b26: bf38 it cc 8000b28: 005b lslcc r3, r3, #1 8000b2a: f142 027d adc.w r2, r2, #125 ; 0x7d 8000b2e: f44f 0c00 mov.w ip, #8388608 ; 0x800000 8000b32: 428b cmp r3, r1 8000b34: bf24 itt cs 8000b36: 1a5b subcs r3, r3, r1 8000b38: ea40 000c orrcs.w r0, r0, ip 8000b3c: ebb3 0f51 cmp.w r3, r1, lsr #1 8000b40: bf24 itt cs 8000b42: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000b46: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000b4a: ebb3 0f91 cmp.w r3, r1, lsr #2 8000b4e: bf24 itt cs 8000b50: eba3 0391 subcs.w r3, r3, r1, lsr #2 8000b54: ea40 009c orrcs.w r0, r0, ip, lsr #2 8000b58: ebb3 0fd1 cmp.w r3, r1, lsr #3 8000b5c: bf24 itt cs 8000b5e: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8000b62: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000b66: 011b lsls r3, r3, #4 8000b68: bf18 it ne 8000b6a: ea5f 1c1c movsne.w ip, ip, lsr #4 8000b6e: d1e0 bne.n 8000b32 <__aeabi_fdiv+0x46> 8000b70: 2afd cmp r2, #253 ; 0xfd 8000b72: f63f af50 bhi.w 8000a16 <__aeabi_fmul+0x92> 8000b76: 428b cmp r3, r1 8000b78: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000b7c: bf08 it eq 8000b7e: f020 0001 biceq.w r0, r0, #1 8000b82: 4770 bx lr 8000b84: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000b88: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000b8c: 327f adds r2, #127 ; 0x7f 8000b8e: bfc2 ittt gt 8000b90: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000b94: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000b98: 4770 bxgt lr 8000b9a: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000b9e: f04f 0300 mov.w r3, #0 8000ba2: 3a01 subs r2, #1 8000ba4: e737 b.n 8000a16 <__aeabi_fmul+0x92> 8000ba6: f092 0f00 teq r2, #0 8000baa: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000bae: bf02 ittt eq 8000bb0: 0040 lsleq r0, r0, #1 8000bb2: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000bb6: 3a01 subeq r2, #1 8000bb8: d0f9 beq.n 8000bae <__aeabi_fdiv+0xc2> 8000bba: ea40 000c orr.w r0, r0, ip 8000bbe: f093 0f00 teq r3, #0 8000bc2: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000bc6: bf02 ittt eq 8000bc8: 0049 lsleq r1, r1, #1 8000bca: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000bce: 3b01 subeq r3, #1 8000bd0: d0f9 beq.n 8000bc6 <__aeabi_fdiv+0xda> 8000bd2: ea41 010c orr.w r1, r1, ip 8000bd6: e795 b.n 8000b04 <__aeabi_fdiv+0x18> 8000bd8: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000bdc: ea92 0f0c teq r2, ip 8000be0: d108 bne.n 8000bf4 <__aeabi_fdiv+0x108> 8000be2: 0242 lsls r2, r0, #9 8000be4: f47f af7d bne.w 8000ae2 <__aeabi_fmul+0x15e> 8000be8: ea93 0f0c teq r3, ip 8000bec: f47f af70 bne.w 8000ad0 <__aeabi_fmul+0x14c> 8000bf0: 4608 mov r0, r1 8000bf2: e776 b.n 8000ae2 <__aeabi_fmul+0x15e> 8000bf4: ea93 0f0c teq r3, ip 8000bf8: d104 bne.n 8000c04 <__aeabi_fdiv+0x118> 8000bfa: 024b lsls r3, r1, #9 8000bfc: f43f af4c beq.w 8000a98 <__aeabi_fmul+0x114> 8000c00: 4608 mov r0, r1 8000c02: e76e b.n 8000ae2 <__aeabi_fmul+0x15e> 8000c04: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000c08: bf18 it ne 8000c0a: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000c0e: d1ca bne.n 8000ba6 <__aeabi_fdiv+0xba> 8000c10: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 8000c14: f47f af5c bne.w 8000ad0 <__aeabi_fmul+0x14c> 8000c18: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 8000c1c: f47f af3c bne.w 8000a98 <__aeabi_fmul+0x114> 8000c20: e75f b.n 8000ae2 <__aeabi_fmul+0x15e> 8000c22: bf00 nop 08000c24 <__gesf2>: 8000c24: f04f 3cff mov.w ip, #4294967295 8000c28: e006 b.n 8000c38 <__cmpsf2+0x4> 8000c2a: bf00 nop 08000c2c <__lesf2>: 8000c2c: f04f 0c01 mov.w ip, #1 8000c30: e002 b.n 8000c38 <__cmpsf2+0x4> 8000c32: bf00 nop 08000c34 <__cmpsf2>: 8000c34: f04f 0c01 mov.w ip, #1 8000c38: f84d cd04 str.w ip, [sp, #-4]! 8000c3c: ea4f 0240 mov.w r2, r0, lsl #1 8000c40: ea4f 0341 mov.w r3, r1, lsl #1 8000c44: ea7f 6c22 mvns.w ip, r2, asr #24 8000c48: bf18 it ne 8000c4a: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000c4e: d011 beq.n 8000c74 <__cmpsf2+0x40> 8000c50: b001 add sp, #4 8000c52: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8000c56: bf18 it ne 8000c58: ea90 0f01 teqne r0, r1 8000c5c: bf58 it pl 8000c5e: ebb2 0003 subspl.w r0, r2, r3 8000c62: bf88 it hi 8000c64: 17c8 asrhi r0, r1, #31 8000c66: bf38 it cc 8000c68: ea6f 70e1 mvncc.w r0, r1, asr #31 8000c6c: bf18 it ne 8000c6e: f040 0001 orrne.w r0, r0, #1 8000c72: 4770 bx lr 8000c74: ea7f 6c22 mvns.w ip, r2, asr #24 8000c78: d102 bne.n 8000c80 <__cmpsf2+0x4c> 8000c7a: ea5f 2c40 movs.w ip, r0, lsl #9 8000c7e: d105 bne.n 8000c8c <__cmpsf2+0x58> 8000c80: ea7f 6c23 mvns.w ip, r3, asr #24 8000c84: d1e4 bne.n 8000c50 <__cmpsf2+0x1c> 8000c86: ea5f 2c41 movs.w ip, r1, lsl #9 8000c8a: d0e1 beq.n 8000c50 <__cmpsf2+0x1c> 8000c8c: f85d 0b04 ldr.w r0, [sp], #4 8000c90: 4770 bx lr 8000c92: bf00 nop 08000c94 <__aeabi_cfrcmple>: 8000c94: 4684 mov ip, r0 8000c96: 4608 mov r0, r1 8000c98: 4661 mov r1, ip 8000c9a: e7ff b.n 8000c9c <__aeabi_cfcmpeq> 08000c9c <__aeabi_cfcmpeq>: 8000c9c: b50f push {r0, r1, r2, r3, lr} 8000c9e: f7ff ffc9 bl 8000c34 <__cmpsf2> 8000ca2: 2800 cmp r0, #0 8000ca4: bf48 it mi 8000ca6: f110 0f00 cmnmi.w r0, #0 8000caa: bd0f pop {r0, r1, r2, r3, pc} 08000cac <__aeabi_fcmpeq>: 8000cac: f84d ed08 str.w lr, [sp, #-8]! 8000cb0: f7ff fff4 bl 8000c9c <__aeabi_cfcmpeq> 8000cb4: bf0c ite eq 8000cb6: 2001 moveq r0, #1 8000cb8: 2000 movne r0, #0 8000cba: f85d fb08 ldr.w pc, [sp], #8 8000cbe: bf00 nop 08000cc0 <__aeabi_fcmplt>: 8000cc0: f84d ed08 str.w lr, [sp, #-8]! 8000cc4: f7ff ffea bl 8000c9c <__aeabi_cfcmpeq> 8000cc8: bf34 ite cc 8000cca: 2001 movcc r0, #1 8000ccc: 2000 movcs r0, #0 8000cce: f85d fb08 ldr.w pc, [sp], #8 8000cd2: bf00 nop 08000cd4 <__aeabi_fcmple>: 8000cd4: f84d ed08 str.w lr, [sp, #-8]! 8000cd8: f7ff ffe0 bl 8000c9c <__aeabi_cfcmpeq> 8000cdc: bf94 ite ls 8000cde: 2001 movls r0, #1 8000ce0: 2000 movhi r0, #0 8000ce2: f85d fb08 ldr.w pc, [sp], #8 8000ce6: bf00 nop 08000ce8 <__aeabi_fcmpge>: 8000ce8: f84d ed08 str.w lr, [sp, #-8]! 8000cec: f7ff ffd2 bl 8000c94 <__aeabi_cfrcmple> 8000cf0: bf94 ite ls 8000cf2: 2001 movls r0, #1 8000cf4: 2000 movhi r0, #0 8000cf6: f85d fb08 ldr.w pc, [sp], #8 8000cfa: bf00 nop 08000cfc <__aeabi_fcmpgt>: 8000cfc: f84d ed08 str.w lr, [sp, #-8]! 8000d00: f7ff ffc8 bl 8000c94 <__aeabi_cfrcmple> 8000d04: bf34 ite cc 8000d06: 2001 movcc r0, #1 8000d08: 2000 movcs r0, #0 8000d0a: f85d fb08 ldr.w pc, [sp], #8 8000d0e: bf00 nop 08000d10 <HAL_GPIO_EXTI_Callback>: void switchBuffer(bool spi_state); void initResponseBuffer(); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8000d10: b580 push {r7, lr} 8000d12: b082 sub sp, #8 8000d14: af00 add r7, sp, #0 8000d16: 4603 mov r3, r0 8000d18: 80fb strh r3, [r7, #6] // Мастер опустил CS if (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == GPIO_PIN_RESET) { 8000d1a: f44f 5180 mov.w r1, #4096 ; 0x1000 8000d1e: 4815 ldr r0, [pc, #84] ; (8000d74 <HAL_GPIO_EXTI_Callback+0x64>) 8000d20: f002 fcc6 bl 80036b0 <HAL_GPIO_ReadPin> 8000d24: 4603 mov r3, r0 8000d26: 2b00 cmp r3, #0 8000d28: d11f bne.n 8000d6a <HAL_GPIO_EXTI_Callback+0x5a> // проверка на наличие готового ответа для отправки if(response_ready && spi_state == SPI_MODE_TX) { // если ответ готов и датчик в режиме передатчика 8000d2a: 4b13 ldr r3, [pc, #76] ; (8000d78 <HAL_GPIO_EXTI_Callback+0x68>) 8000d2c: 781b ldrb r3, [r3, #0] 8000d2e: 2b00 cmp r3, #0 8000d30: d00b beq.n 8000d4a <HAL_GPIO_EXTI_Callback+0x3a> 8000d32: 4b12 ldr r3, [pc, #72] ; (8000d7c <HAL_GPIO_EXTI_Callback+0x6c>) 8000d34: 781b ldrb r3, [r3, #0] 8000d36: 2b00 cmp r3, #0 8000d38: d007 beq.n 8000d4a <HAL_GPIO_EXTI_Callback+0x3a> spi_tx_ptr = new_response_frame; // использовать для передачи сформированный ответ 8000d3a: 4b11 ldr r3, [pc, #68] ; (8000d80 <HAL_GPIO_EXTI_Callback+0x70>) 8000d3c: 681b ldr r3, [r3, #0] 8000d3e: 4a11 ldr r2, [pc, #68] ; (8000d84 <HAL_GPIO_EXTI_Callback+0x74>) 8000d40: 6013 str r3, [r2, #0] response_ready = false; 8000d42: 4b0d ldr r3, [pc, #52] ; (8000d78 <HAL_GPIO_EXTI_Callback+0x68>) 8000d44: 2200 movs r2, #0 8000d46: 701a strb r2, [r3, #0] 8000d48: e006 b.n 8000d58 <HAL_GPIO_EXTI_Callback+0x48> } else if (spi_state == SPI_MODE_TX){ // ответ не готов и датчик в режиме передатчика 8000d4a: 4b0c ldr r3, [pc, #48] ; (8000d7c <HAL_GPIO_EXTI_Callback+0x6c>) 8000d4c: 781b ldrb r3, [r3, #0] 8000d4e: 2b00 cmp r3, #0 8000d50: d002 beq.n 8000d58 <HAL_GPIO_EXTI_Callback+0x48> spi_tx_ptr = wait_response_frame; // использовать для передачи кадр с состоянием STATE_WAIT 8000d52: 4b0c ldr r3, [pc, #48] ; (8000d84 <HAL_GPIO_EXTI_Callback+0x74>) 8000d54: 4a0c ldr r2, [pc, #48] ; (8000d88 <HAL_GPIO_EXTI_Callback+0x78>) 8000d56: 601a str r2, [r3, #0] } // Запускаем прием/передачу HAL_SPI_TransmitReceive_IT(&hspi2, spi_tx_ptr, spi_rx_ptr, FRAME_LEN); 8000d58: 4b0a ldr r3, [pc, #40] ; (8000d84 <HAL_GPIO_EXTI_Callback+0x74>) 8000d5a: 6819 ldr r1, [r3, #0] 8000d5c: 4b0b ldr r3, [pc, #44] ; (8000d8c <HAL_GPIO_EXTI_Callback+0x7c>) 8000d5e: 681a ldr r2, [r3, #0] 8000d60: f44f 7384 mov.w r3, #264 ; 0x108 8000d64: 480a ldr r0, [pc, #40] ; (8000d90 <HAL_GPIO_EXTI_Callback+0x80>) 8000d66: f003 ff07 bl 8004b78 <HAL_SPI_TransmitReceive_IT> } } 8000d6a: bf00 nop 8000d6c: 3708 adds r7, #8 8000d6e: 46bd mov sp, r7 8000d70: bd80 pop {r7, pc} 8000d72: bf00 nop 8000d74: 40010c00 .word 0x40010c00 8000d78: 200000e5 .word 0x200000e5 8000d7c: 200000e6 .word 0x200000e6 8000d80: 20000510 .word 0x20000510 8000d84: 20000508 .word 0x20000508 8000d88: 20000514 .word 0x20000514 8000d8c: 2000050c .word 0x2000050c 8000d90: 200006a4 .word 0x200006a4 08000d94 <fillBuffer>: void fillBuffer(uint8_t* buf, uint8_t fill_symbol) { 8000d94: b480 push {r7} 8000d96: b085 sub sp, #20 8000d98: af00 add r7, sp, #0 8000d9a: 6078 str r0, [r7, #4] 8000d9c: 460b mov r3, r1 8000d9e: 70fb strb r3, [r7, #3] for(int i = 0; i < FRAME_LEN; i++) { 8000da0: 2300 movs r3, #0 8000da2: 60fb str r3, [r7, #12] 8000da4: e007 b.n 8000db6 <fillBuffer+0x22> buf[i] = fill_symbol; 8000da6: 68fb ldr r3, [r7, #12] 8000da8: 687a ldr r2, [r7, #4] 8000daa: 4413 add r3, r2 8000dac: 78fa ldrb r2, [r7, #3] 8000dae: 701a strb r2, [r3, #0] for(int i = 0; i < FRAME_LEN; i++) { 8000db0: 68fb ldr r3, [r7, #12] 8000db2: 3301 adds r3, #1 8000db4: 60fb str r3, [r7, #12] 8000db6: 68fb ldr r3, [r7, #12] 8000db8: f5b3 7f84 cmp.w r3, #264 ; 0x108 8000dbc: dbf3 blt.n 8000da6 <fillBuffer+0x12> } } 8000dbe: bf00 nop 8000dc0: bf00 nop 8000dc2: 3714 adds r7, #20 8000dc4: 46bd mov sp, r7 8000dc6: bc80 pop {r7} 8000dc8: 4770 bx lr ... 08000dcc <initSPIConnection>: void initSPIConnection() { 8000dcc: b580 push {r7, lr} 8000dce: af00 add r7, sp, #0 spi_state = SPI_MODE_RX; 8000dd0: 4b07 ldr r3, [pc, #28] ; (8000df0 <initSPIConnection+0x24>) 8000dd2: 2200 movs r2, #0 8000dd4: 701a strb r2, [r3, #0] switchBuffer(spi_state); 8000dd6: 4b06 ldr r3, [pc, #24] ; (8000df0 <initSPIConnection+0x24>) 8000dd8: 781b ldrb r3, [r3, #0] 8000dda: 4618 mov r0, r3 8000ddc: f000 f844 bl 8000e68 <switchBuffer> fillBuffer(dummy_frame, 0xAA); 8000de0: 21aa movs r1, #170 ; 0xaa 8000de2: 4804 ldr r0, [pc, #16] ; (8000df4 <initSPIConnection+0x28>) 8000de4: f7ff ffd6 bl 8000d94 <fillBuffer> initResponseBuffer(); 8000de8: f000 f806 bl 8000df8 <initResponseBuffer> }; 8000dec: bf00 nop 8000dee: bd80 pop {r7, pc} 8000df0: 200000e6 .word 0x200000e6 8000df4: 200002f8 .word 0x200002f8 08000df8 <initResponseBuffer>: void resetSPIConnection() { initSPIConnection(); response_ready = 0; } void initResponseBuffer() { 8000df8: b580 push {r7, lr} 8000dfa: b082 sub sp, #8 8000dfc: af00 add r7, sp, #0 wait_response_frame[0] = 0xFA; 8000dfe: 4b19 ldr r3, [pc, #100] ; (8000e64 <initResponseBuffer+0x6c>) 8000e00: 22fa movs r2, #250 ; 0xfa 8000e02: 701a strb r2, [r3, #0] wait_response_frame[1] = 0xAF; 8000e04: 4b17 ldr r3, [pc, #92] ; (8000e64 <initResponseBuffer+0x6c>) 8000e06: 22af movs r2, #175 ; 0xaf 8000e08: 705a strb r2, [r3, #1] wait_response_frame[2] = STATE_WAIT; 8000e0a: 4b16 ldr r3, [pc, #88] ; (8000e64 <initResponseBuffer+0x6c>) 8000e0c: 2203 movs r2, #3 8000e0e: 709a strb r2, [r3, #2] wait_response_frame[258] = 0xFF; 8000e10: 4b14 ldr r3, [pc, #80] ; (8000e64 <initResponseBuffer+0x6c>) 8000e12: 22ff movs r2, #255 ; 0xff 8000e14: f883 2102 strb.w r2, [r3, #258] ; 0x102 wait_response_frame[259] = 0x0D; 8000e18: 4b12 ldr r3, [pc, #72] ; (8000e64 <initResponseBuffer+0x6c>) 8000e1a: 220d movs r2, #13 8000e1c: f883 2103 strb.w r2, [r3, #259] ; 0x103 // TODO: добавить расчет CRC uint32_t crc = calculateCRC32(wait_response_frame, FRAME_LEN-4); 8000e20: f44f 7182 mov.w r1, #260 ; 0x104 8000e24: 480f ldr r0, [pc, #60] ; (8000e64 <initResponseBuffer+0x6c>) 8000e26: f000 ffc3 bl 8001db0 <calculateCRC32> 8000e2a: 6078 str r0, [r7, #4] wait_response_frame[260] = (crc >> 24) & 0xFF; 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 0e1b lsrs r3, r3, #24 8000e30: b2da uxtb r2, r3 8000e32: 4b0c ldr r3, [pc, #48] ; (8000e64 <initResponseBuffer+0x6c>) 8000e34: f883 2104 strb.w r2, [r3, #260] ; 0x104 wait_response_frame[261] = (crc >> 16) & 0xFF; 8000e38: 687b ldr r3, [r7, #4] 8000e3a: 0c1b lsrs r3, r3, #16 8000e3c: b2da uxtb r2, r3 8000e3e: 4b09 ldr r3, [pc, #36] ; (8000e64 <initResponseBuffer+0x6c>) 8000e40: f883 2105 strb.w r2, [r3, #261] ; 0x105 wait_response_frame[262] = (crc >> 8) & 0xFF; 8000e44: 687b ldr r3, [r7, #4] 8000e46: 0a1b lsrs r3, r3, #8 8000e48: b2da uxtb r2, r3 8000e4a: 4b06 ldr r3, [pc, #24] ; (8000e64 <initResponseBuffer+0x6c>) 8000e4c: f883 2106 strb.w r2, [r3, #262] ; 0x106 wait_response_frame[263] = crc & 0xFF; 8000e50: 687b ldr r3, [r7, #4] 8000e52: b2da uxtb r2, r3 8000e54: 4b03 ldr r3, [pc, #12] ; (8000e64 <initResponseBuffer+0x6c>) 8000e56: f883 2107 strb.w r2, [r3, #263] ; 0x107 }; 8000e5a: bf00 nop 8000e5c: 3708 adds r7, #8 8000e5e: 46bd mov sp, r7 8000e60: bd80 pop {r7, pc} 8000e62: bf00 nop 8000e64: 20000514 .word 0x20000514 08000e68 <switchBuffer>: void switchBuffer(bool spi_state) { 8000e68: b480 push {r7} 8000e6a: b083 sub sp, #12 8000e6c: af00 add r7, sp, #0 8000e6e: 4603 mov r3, r0 8000e70: 71fb strb r3, [r7, #7] if(spi_state == SPI_MODE_TX) { 8000e72: 79fb ldrb r3, [r7, #7] 8000e74: 2b00 cmp r3, #0 8000e76: d003 beq.n 8000e80 <switchBuffer+0x18> //spi_tx_ptr = &response_frame[0]; spi_rx_ptr = &trash_frame[0]; 8000e78: 4b07 ldr r3, [pc, #28] ; (8000e98 <switchBuffer+0x30>) 8000e7a: 4a08 ldr r2, [pc, #32] ; (8000e9c <switchBuffer+0x34>) 8000e7c: 601a str r2, [r3, #0] } else { spi_tx_ptr = &dummy_frame[0]; spi_rx_ptr = &response_frame[0]; } }; 8000e7e: e005 b.n 8000e8c <switchBuffer+0x24> spi_tx_ptr = &dummy_frame[0]; 8000e80: 4b07 ldr r3, [pc, #28] ; (8000ea0 <switchBuffer+0x38>) 8000e82: 4a08 ldr r2, [pc, #32] ; (8000ea4 <switchBuffer+0x3c>) 8000e84: 601a str r2, [r3, #0] spi_rx_ptr = &response_frame[0]; 8000e86: 4b04 ldr r3, [pc, #16] ; (8000e98 <switchBuffer+0x30>) 8000e88: 4a07 ldr r2, [pc, #28] ; (8000ea8 <switchBuffer+0x40>) 8000e8a: 601a str r2, [r3, #0] }; 8000e8c: bf00 nop 8000e8e: 370c adds r7, #12 8000e90: 46bd mov sp, r7 8000e92: bc80 pop {r7} 8000e94: 4770 bx lr 8000e96: bf00 nop 8000e98: 2000050c .word 0x2000050c 8000e9c: 20000400 .word 0x20000400 8000ea0: 20000508 .word 0x20000508 8000ea4: 200002f8 .word 0x200002f8 8000ea8: 200000e8 .word 0x200000e8 08000eac <HAL_SPI_TxRxCpltCallback>: /* Обработчик прерывания по окончанию передачи/приема всего кадра */ void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { 8000eac: b580 push {r7, lr} 8000eae: b082 sub sp, #8 8000eb0: af00 add r7, sp, #0 8000eb2: 6078 str r0, [r7, #4] if (hspi->Instance == SPI2) 8000eb4: 687b ldr r3, [r7, #4] 8000eb6: 681b ldr r3, [r3, #0] 8000eb8: 4a11 ldr r2, [pc, #68] ; (8000f00 <HAL_SPI_TxRxCpltCallback+0x54>) 8000eba: 4293 cmp r3, r2 8000ebc: d11b bne.n 8000ef6 <HAL_SPI_TxRxCpltCallback+0x4a> { if (spi_state == SPI_MODE_TX) { 8000ebe: 4b11 ldr r3, [pc, #68] ; (8000f04 <HAL_SPI_TxRxCpltCallback+0x58>) 8000ec0: 781b ldrb r3, [r3, #0] 8000ec2: 2b00 cmp r3, #0 8000ec4: d003 beq.n 8000ece <HAL_SPI_TxRxCpltCallback+0x22> // сделать датчик приемником в следующем сеансе spi_state = SPI_MODE_RX; 8000ec6: 4b0f ldr r3, [pc, #60] ; (8000f04 <HAL_SPI_TxRxCpltCallback+0x58>) 8000ec8: 2200 movs r2, #0 8000eca: 701a strb r2, [r3, #0] 8000ecc: e00e b.n 8000eec <HAL_SPI_TxRxCpltCallback+0x40> } else { // сделать датчик передатчиком в следующем сеансе spi_state = SPI_MODE_TX; 8000ece: 4b0d ldr r3, [pc, #52] ; (8000f04 <HAL_SPI_TxRxCpltCallback+0x58>) 8000ed0: 2201 movs r2, #1 8000ed2: 701a strb r2, [r3, #0] // сохранить полученную команду от мастера в безопасный буфер memcpy(safe_command_frame,response_frame,FRAME_LEN); 8000ed4: 4a0c ldr r2, [pc, #48] ; (8000f08 <HAL_SPI_TxRxCpltCallback+0x5c>) 8000ed6: 4b0d ldr r3, [pc, #52] ; (8000f0c <HAL_SPI_TxRxCpltCallback+0x60>) 8000ed8: 4610 mov r0, r2 8000eda: 4619 mov r1, r3 8000edc: f44f 7384 mov.w r3, #264 ; 0x108 8000ee0: 461a mov r2, r3 8000ee2: f005 fdc1 bl 8006a68 <memcpy> spi_rx_complete = true; 8000ee6: 4b0a ldr r3, [pc, #40] ; (8000f10 <HAL_SPI_TxRxCpltCallback+0x64>) 8000ee8: 2201 movs r2, #1 8000eea: 701a strb r2, [r3, #0] } switchBuffer(spi_state); 8000eec: 4b05 ldr r3, [pc, #20] ; (8000f04 <HAL_SPI_TxRxCpltCallback+0x58>) 8000eee: 781b ldrb r3, [r3, #0] 8000ef0: 4618 mov r0, r3 8000ef2: f7ff ffb9 bl 8000e68 <switchBuffer> } } 8000ef6: bf00 nop 8000ef8: 3708 adds r7, #8 8000efa: 46bd mov sp, r7 8000efc: bd80 pop {r7, pc} 8000efe: bf00 nop 8000f00: 40003800 .word 0x40003800 8000f04: 200000e6 .word 0x200000e6 8000f08: 200001f0 .word 0x200001f0 8000f0c: 200000e8 .word 0x200000e8 8000f10: 200000e4 .word 0x200000e4 08000f14 <main>: /** * @brief The application entry point. * @retval int */ int main(void) { 8000f14: b590 push {r4, r7, lr} 8000f16: b087 sub sp, #28 8000f18: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000f1a: f001 fb29 bl 8002570 <HAL_Init> /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000f1e: f000 f945 bl 80011ac <SystemClock_Config> /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000f22: f000 fb3b bl 800159c <MX_GPIO_Init> MX_SPI2_Init(); 8000f26: f000 fa11 bl 800134c <MX_SPI2_Init> MX_USART1_UART_Init(); 8000f2a: f000 fb0d bl 8001548 <MX_USART1_UART_Init> MX_ADC1_Init(); 8000f2e: f000 f999 bl 8001264 <MX_ADC1_Init> MX_SPI1_Init(); 8000f32: f000 f9d5 bl 80012e0 <MX_SPI1_Init> MX_TIM3_Init(); 8000f36: f000 fab9 bl 80014ac <MX_TIM3_Init> MX_TIM2_Init(); 8000f3a: f000 fa39 bl 80013b0 <MX_TIM2_Init> /* USER CODE BEGIN 2 */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3 | GPIO_PIN_4, GPIO_PIN_SET); 8000f3e: 2201 movs r2, #1 8000f40: 2118 movs r1, #24 8000f42: 4888 ldr r0, [pc, #544] ; (8001164 <main+0x250>) 8000f44: f002 fbcb bl 80036de <HAL_GPIO_WritePin> // инициализация датчика sensorInit(); 8000f48: f000 ff5e bl 8001e08 <sensorInit> // задание значения счетчика для получения данных с АЦП сразу после включения __HAL_TIM_SET_COUNTER(&htim3, 29000); 8000f4c: 4b86 ldr r3, [pc, #536] ; (8001168 <main+0x254>) 8000f4e: 681b ldr r3, [r3, #0] 8000f50: f247 1248 movw r2, #29000 ; 0x7148 8000f54: 625a str r2, [r3, #36] ; 0x24 HAL_TIM_Base_Start(&htim3); //start timer for ADC 8000f56: 4884 ldr r0, [pc, #528] ; (8001168 <main+0x254>) 8000f58: f004 fa2c bl 80053b4 <HAL_TIM_Base_Start> HAL_ADC_Start_IT(&hadc1); 8000f5c: 4883 ldr r0, [pc, #524] ; (800116c <main+0x258>) 8000f5e: f001 fd6b bl 8002a38 <HAL_ADC_Start_IT> HAL_ADC_PollForConversion(&hadc1, 100); 8000f62: 2164 movs r1, #100 ; 0x64 8000f64: 4881 ldr r0, [pc, #516] ; (800116c <main+0x258>) 8000f66: f001 fc61 bl 800282c <HAL_ADC_PollForConversion> /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { if (spi_rx_complete) { // команда от мастера полностью получена 8000f6a: 4b81 ldr r3, [pc, #516] ; (8001170 <main+0x25c>) 8000f6c: 781b ldrb r3, [r3, #0] 8000f6e: 2b00 cmp r3, #0 8000f70: d004 beq.n 8000f7c <main+0x68> spi_rx_complete = false; 8000f72: 4b7f ldr r3, [pc, #508] ; (8001170 <main+0x25c>) 8000f74: 2200 movs r2, #0 8000f76: 701a strb r2, [r3, #0] // разбор команды parserFSM(); 8000f78: f000 fd58 bl 8001a2c <parserFSM> } /* KSS CODE BEGIN */ if(dt1[0] == '0') //erase mem 8000f7c: 4b7d ldr r3, [pc, #500] ; (8001174 <main+0x260>) 8000f7e: 781b ldrb r3, [r3, #0] 8000f80: 2b30 cmp r3, #48 ; 0x30 8000f82: d10c bne.n 8000f9e <main+0x8a> { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8000f84: 2201 movs r2, #1 8000f86: 2104 movs r1, #4 8000f88: 4876 ldr r0, [pc, #472] ; (8001164 <main+0x250>) 8000f8a: f002 fba8 bl 80036de <HAL_GPIO_WritePin> W25_Erase_Chip(); 8000f8e: f005 fa53 bl 8006438 <W25_Erase_Chip> page_pos_ptr = 0; 8000f92: 4b79 ldr r3, [pc, #484] ; (8001178 <main+0x264>) 8000f94: 2200 movs r2, #0 8000f96: 701a strb r2, [r3, #0] page_ptr = 0;/* 8000f98: 4b78 ldr r3, [pc, #480] ; (800117c <main+0x268>) 8000f9a: 2200 movs r2, #0 8000f9c: 801a strh r2, [r3, #0] uint8_t pData[5] = {"0!\r\n"}; HAL_UART_Transmit(&huart1, pData, 4, 100);*/ } if(dt1[0] == '1') //start measure 8000f9e: 4b75 ldr r3, [pc, #468] ; (8001174 <main+0x260>) 8000fa0: 781b ldrb r3, [r3, #0] 8000fa2: 2b31 cmp r3, #49 ; 0x31 8000fa4: d107 bne.n 8000fb6 <main+0xa2> { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8000fa6: 2201 movs r2, #1 8000fa8: 2104 movs r1, #4 8000faa: 486e ldr r0, [pc, #440] ; (8001164 <main+0x250>) 8000fac: f002 fb97 bl 80036de <HAL_GPIO_WritePin> need_save = 1;/* 8000fb0: 4b73 ldr r3, [pc, #460] ; (8001180 <main+0x26c>) 8000fb2: 2201 movs r2, #1 8000fb4: 701a strb r2, [r3, #0] uint8_t pData[5] = {"1!\r\n"}; HAL_UART_Transmit(&huart1, pData, 4, 100);*/ } if(dt1[0] == '2') //stop measure 8000fb6: 4b6f ldr r3, [pc, #444] ; (8001174 <main+0x260>) 8000fb8: 781b ldrb r3, [r3, #0] 8000fba: 2b32 cmp r3, #50 ; 0x32 8000fbc: d107 bne.n 8000fce <main+0xba> { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8000fbe: 2201 movs r2, #1 8000fc0: 2104 movs r1, #4 8000fc2: 4868 ldr r0, [pc, #416] ; (8001164 <main+0x250>) 8000fc4: f002 fb8b bl 80036de <HAL_GPIO_WritePin> need_save = 0;/* 8000fc8: 4b6d ldr r3, [pc, #436] ; (8001180 <main+0x26c>) 8000fca: 2200 movs r2, #0 8000fcc: 701a strb r2, [r3, #0] uint8_t pData[5] = {"2!\r\n"}; HAL_UART_Transmit(&huart1, pData, 4, 100);*/ } if(dt1[0] == '3') //read mem 8000fce: 4b69 ldr r3, [pc, #420] ; (8001174 <main+0x260>) 8000fd0: 781b ldrb r3, [r3, #0] 8000fd2: 2b33 cmp r3, #51 ; 0x33 8000fd4: d114 bne.n 8001000 <main+0xec> { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8000fd6: 2201 movs r2, #1 8000fd8: 2104 movs r1, #4 8000fda: 4862 ldr r0, [pc, #392] ; (8001164 <main+0x250>) 8000fdc: f002 fb7f bl 80036de <HAL_GPIO_WritePin> W25_Read_Page(data_buf, dt1[1], 0, w25_info.PageSize); 8000fe0: 4b64 ldr r3, [pc, #400] ; (8001174 <main+0x260>) 8000fe2: 785b ldrb r3, [r3, #1] 8000fe4: 4619 mov r1, r3 8000fe6: 4b67 ldr r3, [pc, #412] ; (8001184 <main+0x270>) 8000fe8: 881b ldrh r3, [r3, #0] 8000fea: 2200 movs r2, #0 8000fec: 4866 ldr r0, [pc, #408] ; (8001188 <main+0x274>) 8000fee: f005 fc95 bl 800691c <W25_Read_Page> HAL_UART_Transmit(&huart1, data_buf, w25_info.PageSize, 100);/* 8000ff2: 4b64 ldr r3, [pc, #400] ; (8001184 <main+0x270>) 8000ff4: 881a ldrh r2, [r3, #0] 8000ff6: 2364 movs r3, #100 ; 0x64 8000ff8: 4963 ldr r1, [pc, #396] ; (8001188 <main+0x274>) 8000ffa: 4864 ldr r0, [pc, #400] ; (800118c <main+0x278>) 8000ffc: f004 fffd bl 8005ffa <HAL_UART_Transmit> uint8_t pData[7] = {"\r\n3!\r\n"}; HAL_UART_Transmit(&huart1, pData, 6, 100);*/ } dt1[0] = 0; 8001000: 4b5c ldr r3, [pc, #368] ; (8001174 <main+0x260>) 8001002: 2200 movs r2, #0 8001004: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET); 8001006: 2200 movs r2, #0 8001008: 2104 movs r1, #4 800100a: 4856 ldr r0, [pc, #344] ; (8001164 <main+0x250>) 800100c: f002 fb67 bl 80036de <HAL_GPIO_WritePin> if ((need_save) && (new_conv == 1)) //measure ongoing and new conversion recieved from ADC 8001010: 4b5b ldr r3, [pc, #364] ; (8001180 <main+0x26c>) 8001012: 781b ldrb r3, [r3, #0] 8001014: 2b00 cmp r3, #0 8001016: d0a8 beq.n 8000f6a <main+0x56> 8001018: 4b5d ldr r3, [pc, #372] ; (8001190 <main+0x27c>) 800101a: 781b ldrb r3, [r3, #0] 800101c: b2db uxtb r3, r3 800101e: 2b01 cmp r3, #1 8001020: d1a3 bne.n 8000f6a <main+0x56> { uint16_t word; uint8_t bytes[2]; } result_data; new_conv = 0; //reset flag 8001022: 4b5b ldr r3, [pc, #364] ; (8001190 <main+0x27c>) 8001024: 2200 movs r2, #0 8001026: 701a strb r2, [r3, #0] uint16_t code = ADC_data; 8001028: 4b5a ldr r3, [pc, #360] ; (8001194 <main+0x280>) 800102a: 881b ldrh r3, [r3, #0] 800102c: 827b strh r3, [r7, #18] float RT_R25 = (float)(code)/(float)(4095-code); //R_t/R25 800102e: 8a7b ldrh r3, [r7, #18] 8001030: 4618 mov r0, r3 8001032: f7ff fc4f bl 80008d4 <__aeabi_ui2f> 8001036: 4604 mov r4, r0 8001038: 8a7b ldrh r3, [r7, #18] 800103a: f5c3 637f rsb r3, r3, #4080 ; 0xff0 800103e: 330f adds r3, #15 8001040: 4618 mov r0, r3 8001042: f7ff fc4b bl 80008dc <__aeabi_i2f> 8001046: 4603 mov r3, r0 8001048: 4619 mov r1, r3 800104a: 4620 mov r0, r4 800104c: f7ff fd4e bl 8000aec <__aeabi_fdiv> 8001050: 4603 mov r3, r0 8001052: 60fb str r3, [r7, #12] for ( int i = 9; i >= 0; i-- ) 8001054: 2309 movs r3, #9 8001056: 617b str r3, [r7, #20] 8001058: e047 b.n 80010ea <main+0x1d6> { if ( Krt_r25[i] >= RT_R25 ) //we are in true band 800105a: 4a4f ldr r2, [pc, #316] ; (8001198 <main+0x284>) 800105c: 697b ldr r3, [r7, #20] 800105e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001062: 4619 mov r1, r3 8001064: 68f8 ldr r0, [r7, #12] 8001066: f7ff fe35 bl 8000cd4 <__aeabi_fcmple> 800106a: 4603 mov r3, r0 800106c: 2b00 cmp r3, #0 800106e: d039 beq.n 80010e4 <main+0x1d0> { float tga = 5/(Krt_r25[i+1] - Krt_r25[i]); //k = calc td(a) 8001070: 697b ldr r3, [r7, #20] 8001072: 3301 adds r3, #1 8001074: 4a48 ldr r2, [pc, #288] ; (8001198 <main+0x284>) 8001076: f852 2023 ldr.w r2, [r2, r3, lsl #2] 800107a: 4947 ldr r1, [pc, #284] ; (8001198 <main+0x284>) 800107c: 697b ldr r3, [r7, #20] 800107e: f851 3023 ldr.w r3, [r1, r3, lsl #2] 8001082: 4619 mov r1, r3 8001084: 4610 mov r0, r2 8001086: f7ff fb73 bl 8000770 <__aeabi_fsub> 800108a: 4603 mov r3, r0 800108c: 4619 mov r1, r3 800108e: 4843 ldr r0, [pc, #268] ; (800119c <main+0x288>) 8001090: f7ff fd2c bl 8000aec <__aeabi_fdiv> 8001094: 4603 mov r3, r0 8001096: 60bb str r3, [r7, #8] float b = (i-1)*5 - tga*Krt_r25[i]; // calc b = offset 8001098: 697b ldr r3, [r7, #20] 800109a: 1e5a subs r2, r3, #1 800109c: 4613 mov r3, r2 800109e: 009b lsls r3, r3, #2 80010a0: 4413 add r3, r2 80010a2: 4618 mov r0, r3 80010a4: f7ff fc1a bl 80008dc <__aeabi_i2f> 80010a8: 4604 mov r4, r0 80010aa: 4a3b ldr r2, [pc, #236] ; (8001198 <main+0x284>) 80010ac: 697b ldr r3, [r7, #20] 80010ae: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80010b2: 68b9 ldr r1, [r7, #8] 80010b4: 4618 mov r0, r3 80010b6: f7ff fc65 bl 8000984 <__aeabi_fmul> 80010ba: 4603 mov r3, r0 80010bc: 4619 mov r1, r3 80010be: 4620 mov r0, r4 80010c0: f7ff fb56 bl 8000770 <__aeabi_fsub> 80010c4: 4603 mov r3, r0 80010c6: 607b str r3, [r7, #4] t = tga * RT_R25 + b; 80010c8: 68f9 ldr r1, [r7, #12] 80010ca: 68b8 ldr r0, [r7, #8] 80010cc: f7ff fc5a bl 8000984 <__aeabi_fmul> 80010d0: 4603 mov r3, r0 80010d2: 6879 ldr r1, [r7, #4] 80010d4: 4618 mov r0, r3 80010d6: f7ff fb4d bl 8000774 <__addsf3> 80010da: 4603 mov r3, r0 80010dc: 461a mov r2, r3 80010de: 4b30 ldr r3, [pc, #192] ; (80011a0 <main+0x28c>) 80010e0: 601a str r2, [r3, #0] break; 80010e2: e005 b.n 80010f0 <main+0x1dc> for ( int i = 9; i >= 0; i-- ) 80010e4: 697b ldr r3, [r7, #20] 80010e6: 3b01 subs r3, #1 80010e8: 617b str r3, [r7, #20] 80010ea: 697b ldr r3, [r7, #20] 80010ec: 2b00 cmp r3, #0 80010ee: dab4 bge.n 800105a <main+0x146> } } result_data.word = (uint16_t)(t*100.0); 80010f0: 4b2b ldr r3, [pc, #172] ; (80011a0 <main+0x28c>) 80010f2: 681b ldr r3, [r3, #0] 80010f4: 4618 mov r0, r3 80010f6: f7ff fabf bl 8000678 <__aeabi_f2d> 80010fa: f04f 0200 mov.w r2, #0 80010fe: 4b29 ldr r3, [pc, #164] ; (80011a4 <main+0x290>) 8001100: f7ff f82c bl 800015c <__aeabi_dmul> 8001104: 4602 mov r2, r0 8001106: 460b mov r3, r1 8001108: 4610 mov r0, r2 800110a: 4619 mov r1, r3 800110c: f7ff fb0c bl 8000728 <__aeabi_d2uiz> 8001110: 4603 mov r3, r0 8001112: b29a uxth r2, r3 8001114: 4b24 ldr r3, [pc, #144] ; (80011a8 <main+0x294>) 8001116: 801a strh r2, [r3, #0] W25_Write_Page(result_data.bytes, page_ptr, page_pos_ptr*2, 2); //save 2 bytes to flash 8001118: 4b18 ldr r3, [pc, #96] ; (800117c <main+0x268>) 800111a: 881b ldrh r3, [r3, #0] 800111c: b29b uxth r3, r3 800111e: 4619 mov r1, r3 8001120: 4b15 ldr r3, [pc, #84] ; (8001178 <main+0x264>) 8001122: 781b ldrb r3, [r3, #0] 8001124: 005b lsls r3, r3, #1 8001126: 461a mov r2, r3 8001128: 2302 movs r3, #2 800112a: 481f ldr r0, [pc, #124] ; (80011a8 <main+0x294>) 800112c: f005 f9a8 bl 8006480 <W25_Write_Page> page_pos_ptr++; 8001130: 4b11 ldr r3, [pc, #68] ; (8001178 <main+0x264>) 8001132: 781b ldrb r3, [r3, #0] 8001134: 3301 adds r3, #1 8001136: b2da uxtb r2, r3 8001138: 4b0f ldr r3, [pc, #60] ; (8001178 <main+0x264>) 800113a: 701a strb r2, [r3, #0] if (page_pos_ptr == 127) //page is full 800113c: 4b0e ldr r3, [pc, #56] ; (8001178 <main+0x264>) 800113e: 781b ldrb r3, [r3, #0] 8001140: 2b7f cmp r3, #127 ; 0x7f 8001142: d109 bne.n 8001158 <main+0x244> { page_ptr++; 8001144: 4b0d ldr r3, [pc, #52] ; (800117c <main+0x268>) 8001146: 881b ldrh r3, [r3, #0] 8001148: b29b uxth r3, r3 800114a: 3301 adds r3, #1 800114c: b29a uxth r2, r3 800114e: 4b0b ldr r3, [pc, #44] ; (800117c <main+0x268>) 8001150: 801a strh r2, [r3, #0] page_pos_ptr = 0; 8001152: 4b09 ldr r3, [pc, #36] ; (8001178 <main+0x264>) 8001154: 2200 movs r2, #0 8001156: 701a strb r2, [r3, #0] } HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_2); 8001158: 2104 movs r1, #4 800115a: 4802 ldr r0, [pc, #8] ; (8001164 <main+0x250>) 800115c: f002 fad7 bl 800370e <HAL_GPIO_TogglePin> if (spi_rx_complete) { // команда от мастера полностью получена 8001160: e703 b.n 8000f6a <main+0x56> 8001162: bf00 nop 8001164: 40010800 .word 0x40010800 8001168: 20000744 .word 0x20000744 800116c: 2000061c .word 0x2000061c 8001170: 200000e4 .word 0x200000e4 8001174: 200008d8 .word 0x200008d8 8001178: 200008d5 .word 0x200008d5 800117c: 200008d2 .word 0x200008d2 8001180: 200008d0 .word 0x200008d0 8001184: 20000a0c .word 0x20000a0c 8001188: 200007d0 .word 0x200007d0 800118c: 2000078c .word 0x2000078c 8001190: 200008d4 .word 0x200008d4 8001194: 20000a00 .word 0x20000a00 8001198: 20000000 .word 0x20000000 800119c: 40a00000 .word 0x40a00000 80011a0: 200008e4 .word 0x200008e4 80011a4: 40590000 .word 0x40590000 80011a8: 200008e8 .word 0x200008e8 080011ac <SystemClock_Config>: /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80011ac: b580 push {r7, lr} 80011ae: b094 sub sp, #80 ; 0x50 80011b0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80011b2: f107 0328 add.w r3, r7, #40 ; 0x28 80011b6: 2228 movs r2, #40 ; 0x28 80011b8: 2100 movs r1, #0 80011ba: 4618 mov r0, r3 80011bc: f005 fc62 bl 8006a84 <memset> RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80011c0: f107 0314 add.w r3, r7, #20 80011c4: 2200 movs r2, #0 80011c6: 601a str r2, [r3, #0] 80011c8: 605a str r2, [r3, #4] 80011ca: 609a str r2, [r3, #8] 80011cc: 60da str r2, [r3, #12] 80011ce: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80011d0: 1d3b adds r3, r7, #4 80011d2: 2200 movs r2, #0 80011d4: 601a str r2, [r3, #0] 80011d6: 605a str r2, [r3, #4] 80011d8: 609a str r2, [r3, #8] 80011da: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80011dc: 2301 movs r3, #1 80011de: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80011e0: f44f 3380 mov.w r3, #65536 ; 0x10000 80011e4: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 80011e6: 2300 movs r3, #0 80011e8: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80011ea: 2301 movs r3, #1 80011ec: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80011ee: 2302 movs r3, #2 80011f0: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80011f2: f44f 3380 mov.w r3, #65536 ; 0x10000 80011f6: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 80011f8: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 80011fc: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80011fe: f107 0328 add.w r3, r7, #40 ; 0x28 8001202: 4618 mov r0, r3 8001204: f002 fab4 bl 8003770 <HAL_RCC_OscConfig> 8001208: 4603 mov r3, r0 800120a: 2b00 cmp r3, #0 800120c: d001 beq.n 8001212 <SystemClock_Config+0x66> { Error_Handler(); 800120e: f000 fa27 bl 8001660 <Error_Handler> } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001212: 230f movs r3, #15 8001214: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001216: 2302 movs r3, #2 8001218: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800121a: 2300 movs r3, #0 800121c: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800121e: f44f 6380 mov.w r3, #1024 ; 0x400 8001222: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001224: 2300 movs r3, #0 8001226: 627b str r3, [r7, #36] ; 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001228: f107 0314 add.w r3, r7, #20 800122c: 2102 movs r1, #2 800122e: 4618 mov r0, r3 8001230: f002 fd20 bl 8003c74 <HAL_RCC_ClockConfig> 8001234: 4603 mov r3, r0 8001236: 2b00 cmp r3, #0 8001238: d001 beq.n 800123e <SystemClock_Config+0x92> { Error_Handler(); 800123a: f000 fa11 bl 8001660 <Error_Handler> } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 800123e: 2302 movs r3, #2 8001240: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 8001242: f44f 4300 mov.w r3, #32768 ; 0x8000 8001246: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001248: 1d3b adds r3, r7, #4 800124a: 4618 mov r0, r3 800124c: f002 feaa bl 8003fa4 <HAL_RCCEx_PeriphCLKConfig> 8001250: 4603 mov r3, r0 8001252: 2b00 cmp r3, #0 8001254: d001 beq.n 800125a <SystemClock_Config+0xae> { Error_Handler(); 8001256: f000 fa03 bl 8001660 <Error_Handler> } } 800125a: bf00 nop 800125c: 3750 adds r7, #80 ; 0x50 800125e: 46bd mov sp, r7 8001260: bd80 pop {r7, pc} ... 08001264 <MX_ADC1_Init>: * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8001264: b580 push {r7, lr} 8001266: b084 sub sp, #16 8001268: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800126a: 1d3b adds r3, r7, #4 800126c: 2200 movs r2, #0 800126e: 601a str r2, [r3, #0] 8001270: 605a str r2, [r3, #4] 8001272: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8001274: 4b18 ldr r3, [pc, #96] ; (80012d8 <MX_ADC1_Init+0x74>) 8001276: 4a19 ldr r2, [pc, #100] ; (80012dc <MX_ADC1_Init+0x78>) 8001278: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 800127a: 4b17 ldr r3, [pc, #92] ; (80012d8 <MX_ADC1_Init+0x74>) 800127c: 2200 movs r2, #0 800127e: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8001280: 4b15 ldr r3, [pc, #84] ; (80012d8 <MX_ADC1_Init+0x74>) 8001282: 2200 movs r2, #0 8001284: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8001286: 4b14 ldr r3, [pc, #80] ; (80012d8 <MX_ADC1_Init+0x74>) 8001288: 2200 movs r2, #0 800128a: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 800128c: 4b12 ldr r3, [pc, #72] ; (80012d8 <MX_ADC1_Init+0x74>) 800128e: f44f 2200 mov.w r2, #524288 ; 0x80000 8001292: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001294: 4b10 ldr r3, [pc, #64] ; (80012d8 <MX_ADC1_Init+0x74>) 8001296: 2200 movs r2, #0 8001298: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800129a: 4b0f ldr r3, [pc, #60] ; (80012d8 <MX_ADC1_Init+0x74>) 800129c: 2201 movs r2, #1 800129e: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80012a0: 480d ldr r0, [pc, #52] ; (80012d8 <MX_ADC1_Init+0x74>) 80012a2: f001 f9eb bl 800267c <HAL_ADC_Init> 80012a6: 4603 mov r3, r0 80012a8: 2b00 cmp r3, #0 80012aa: d001 beq.n 80012b0 <MX_ADC1_Init+0x4c> { Error_Handler(); 80012ac: f000 f9d8 bl 8001660 <Error_Handler> } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80012b0: 2301 movs r3, #1 80012b2: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80012b4: 2301 movs r3, #1 80012b6: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80012b8: 2300 movs r3, #0 80012ba: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80012bc: 1d3b adds r3, r7, #4 80012be: 4619 mov r1, r3 80012c0: 4805 ldr r0, [pc, #20] ; (80012d8 <MX_ADC1_Init+0x74>) 80012c2: f001 fd51 bl 8002d68 <HAL_ADC_ConfigChannel> 80012c6: 4603 mov r3, r0 80012c8: 2b00 cmp r3, #0 80012ca: d001 beq.n 80012d0 <MX_ADC1_Init+0x6c> { Error_Handler(); 80012cc: f000 f9c8 bl 8001660 <Error_Handler> } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80012d0: bf00 nop 80012d2: 3710 adds r7, #16 80012d4: 46bd mov sp, r7 80012d6: bd80 pop {r7, pc} 80012d8: 2000061c .word 0x2000061c 80012dc: 40012400 .word 0x40012400 080012e0 <MX_SPI1_Init>: * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 80012e0: b580 push {r7, lr} 80012e2: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 80012e4: 4b17 ldr r3, [pc, #92] ; (8001344 <MX_SPI1_Init+0x64>) 80012e6: 4a18 ldr r2, [pc, #96] ; (8001348 <MX_SPI1_Init+0x68>) 80012e8: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 80012ea: 4b16 ldr r3, [pc, #88] ; (8001344 <MX_SPI1_Init+0x64>) 80012ec: f44f 7282 mov.w r2, #260 ; 0x104 80012f0: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 80012f2: 4b14 ldr r3, [pc, #80] ; (8001344 <MX_SPI1_Init+0x64>) 80012f4: 2200 movs r2, #0 80012f6: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 80012f8: 4b12 ldr r3, [pc, #72] ; (8001344 <MX_SPI1_Init+0x64>) 80012fa: 2200 movs r2, #0 80012fc: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 80012fe: 4b11 ldr r3, [pc, #68] ; (8001344 <MX_SPI1_Init+0x64>) 8001300: 2200 movs r2, #0 8001302: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8001304: 4b0f ldr r3, [pc, #60] ; (8001344 <MX_SPI1_Init+0x64>) 8001306: 2200 movs r2, #0 8001308: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 800130a: 4b0e ldr r3, [pc, #56] ; (8001344 <MX_SPI1_Init+0x64>) 800130c: f44f 7200 mov.w r2, #512 ; 0x200 8001310: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; 8001312: 4b0c ldr r3, [pc, #48] ; (8001344 <MX_SPI1_Init+0x64>) 8001314: 2220 movs r2, #32 8001316: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8001318: 4b0a ldr r3, [pc, #40] ; (8001344 <MX_SPI1_Init+0x64>) 800131a: 2200 movs r2, #0 800131c: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 800131e: 4b09 ldr r3, [pc, #36] ; (8001344 <MX_SPI1_Init+0x64>) 8001320: 2200 movs r2, #0 8001322: 625a str r2, [r3, #36] ; 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001324: 4b07 ldr r3, [pc, #28] ; (8001344 <MX_SPI1_Init+0x64>) 8001326: 2200 movs r2, #0 8001328: 629a str r2, [r3, #40] ; 0x28 hspi1.Init.CRCPolynomial = 10; 800132a: 4b06 ldr r3, [pc, #24] ; (8001344 <MX_SPI1_Init+0x64>) 800132c: 220a movs r2, #10 800132e: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi1) != HAL_OK) 8001330: 4804 ldr r0, [pc, #16] ; (8001344 <MX_SPI1_Init+0x64>) 8001332: f002 ffad bl 8004290 <HAL_SPI_Init> 8001336: 4603 mov r3, r0 8001338: 2b00 cmp r3, #0 800133a: d001 beq.n 8001340 <MX_SPI1_Init+0x60> { Error_Handler(); 800133c: f000 f990 bl 8001660 <Error_Handler> } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8001340: bf00 nop 8001342: bd80 pop {r7, pc} 8001344: 2000064c .word 0x2000064c 8001348: 40013000 .word 0x40013000 0800134c <MX_SPI2_Init>: * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 800134c: b580 push {r7, lr} 800134e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 8001350: 4b15 ldr r3, [pc, #84] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001352: 4a16 ldr r2, [pc, #88] ; (80013ac <MX_SPI2_Init+0x60>) 8001354: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_SLAVE; 8001356: 4b14 ldr r3, [pc, #80] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001358: 2200 movs r2, #0 800135a: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 800135c: 4b12 ldr r3, [pc, #72] ; (80013a8 <MX_SPI2_Init+0x5c>) 800135e: 2200 movs r2, #0 8001360: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 8001362: 4b11 ldr r3, [pc, #68] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001364: 2200 movs r2, #0 8001366: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8001368: 4b0f ldr r3, [pc, #60] ; (80013a8 <MX_SPI2_Init+0x5c>) 800136a: 2200 movs r2, #0 800136c: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 800136e: 4b0e ldr r3, [pc, #56] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001370: 2200 movs r2, #0 8001372: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 8001374: 4b0c ldr r3, [pc, #48] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001376: f44f 7200 mov.w r2, #512 ; 0x200 800137a: 619a str r2, [r3, #24] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 800137c: 4b0a ldr r3, [pc, #40] ; (80013a8 <MX_SPI2_Init+0x5c>) 800137e: 2200 movs r2, #0 8001380: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 8001382: 4b09 ldr r3, [pc, #36] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001384: 2200 movs r2, #0 8001386: 625a str r2, [r3, #36] ; 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001388: 4b07 ldr r3, [pc, #28] ; (80013a8 <MX_SPI2_Init+0x5c>) 800138a: 2200 movs r2, #0 800138c: 629a str r2, [r3, #40] ; 0x28 hspi2.Init.CRCPolynomial = 10; 800138e: 4b06 ldr r3, [pc, #24] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001390: 220a movs r2, #10 8001392: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi2) != HAL_OK) 8001394: 4804 ldr r0, [pc, #16] ; (80013a8 <MX_SPI2_Init+0x5c>) 8001396: f002 ff7b bl 8004290 <HAL_SPI_Init> 800139a: 4603 mov r3, r0 800139c: 2b00 cmp r3, #0 800139e: d001 beq.n 80013a4 <MX_SPI2_Init+0x58> { Error_Handler(); 80013a0: f000 f95e bl 8001660 <Error_Handler> } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 80013a4: bf00 nop 80013a6: bd80 pop {r7, pc} 80013a8: 200006a4 .word 0x200006a4 80013ac: 40003800 .word 0x40003800 080013b0 <MX_TIM2_Init>: * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80013b0: b580 push {r7, lr} 80013b2: b08e sub sp, #56 ; 0x38 80013b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80013b6: f107 0328 add.w r3, r7, #40 ; 0x28 80013ba: 2200 movs r2, #0 80013bc: 601a str r2, [r3, #0] 80013be: 605a str r2, [r3, #4] 80013c0: 609a str r2, [r3, #8] 80013c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80013c4: f107 0320 add.w r3, r7, #32 80013c8: 2200 movs r2, #0 80013ca: 601a str r2, [r3, #0] 80013cc: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 80013ce: 1d3b adds r3, r7, #4 80013d0: 2200 movs r2, #0 80013d2: 601a str r2, [r3, #0] 80013d4: 605a str r2, [r3, #4] 80013d6: 609a str r2, [r3, #8] 80013d8: 60da str r2, [r3, #12] 80013da: 611a str r2, [r3, #16] 80013dc: 615a str r2, [r3, #20] 80013de: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80013e0: 4b31 ldr r3, [pc, #196] ; (80014a8 <MX_TIM2_Init+0xf8>) 80013e2: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 80013e6: 601a str r2, [r3, #0] htim2.Init.Prescaler = 72; 80013e8: 4b2f ldr r3, [pc, #188] ; (80014a8 <MX_TIM2_Init+0xf8>) 80013ea: 2248 movs r2, #72 ; 0x48 80013ec: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80013ee: 4b2e ldr r3, [pc, #184] ; (80014a8 <MX_TIM2_Init+0xf8>) 80013f0: 2200 movs r2, #0 80013f2: 609a str r2, [r3, #8] htim2.Init.Period = 501; 80013f4: 4b2c ldr r3, [pc, #176] ; (80014a8 <MX_TIM2_Init+0xf8>) 80013f6: f240 12f5 movw r2, #501 ; 0x1f5 80013fa: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80013fc: 4b2a ldr r3, [pc, #168] ; (80014a8 <MX_TIM2_Init+0xf8>) 80013fe: 2200 movs r2, #0 8001400: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001402: 4b29 ldr r3, [pc, #164] ; (80014a8 <MX_TIM2_Init+0xf8>) 8001404: 2200 movs r2, #0 8001406: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001408: 4827 ldr r0, [pc, #156] ; (80014a8 <MX_TIM2_Init+0xf8>) 800140a: f003 ff83 bl 8005314 <HAL_TIM_Base_Init> 800140e: 4603 mov r3, r0 8001410: 2b00 cmp r3, #0 8001412: d001 beq.n 8001418 <MX_TIM2_Init+0x68> { Error_Handler(); 8001414: f000 f924 bl 8001660 <Error_Handler> } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001418: f44f 5380 mov.w r3, #4096 ; 0x1000 800141c: 62bb str r3, [r7, #40] ; 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800141e: f107 0328 add.w r3, r7, #40 ; 0x28 8001422: 4619 mov r1, r3 8001424: 4820 ldr r0, [pc, #128] ; (80014a8 <MX_TIM2_Init+0xf8>) 8001426: f004 f9d5 bl 80057d4 <HAL_TIM_ConfigClockSource> 800142a: 4603 mov r3, r0 800142c: 2b00 cmp r3, #0 800142e: d001 beq.n 8001434 <MX_TIM2_Init+0x84> { Error_Handler(); 8001430: f000 f916 bl 8001660 <Error_Handler> } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8001434: 481c ldr r0, [pc, #112] ; (80014a8 <MX_TIM2_Init+0xf8>) 8001436: f004 f807 bl 8005448 <HAL_TIM_PWM_Init> 800143a: 4603 mov r3, r0 800143c: 2b00 cmp r3, #0 800143e: d001 beq.n 8001444 <MX_TIM2_Init+0x94> { Error_Handler(); 8001440: f000 f90e bl 8001660 <Error_Handler> } if (HAL_TIM_OnePulse_Init(&htim2, TIM_OPMODE_SINGLE) != HAL_OK) 8001444: 2108 movs r1, #8 8001446: 4818 ldr r0, [pc, #96] ; (80014a8 <MX_TIM2_Init+0xf8>) 8001448: f004 f856 bl 80054f8 <HAL_TIM_OnePulse_Init> 800144c: 4603 mov r3, r0 800144e: 2b00 cmp r3, #0 8001450: d001 beq.n 8001456 <MX_TIM2_Init+0xa6> { Error_Handler(); 8001452: f000 f905 bl 8001660 <Error_Handler> } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001456: 2300 movs r3, #0 8001458: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800145a: 2300 movs r3, #0 800145c: 627b str r3, [r7, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800145e: f107 0320 add.w r3, r7, #32 8001462: 4619 mov r1, r3 8001464: 4810 ldr r0, [pc, #64] ; (80014a8 <MX_TIM2_Init+0xf8>) 8001466: f004 fd1d bl 8005ea4 <HAL_TIMEx_MasterConfigSynchronization> 800146a: 4603 mov r3, r0 800146c: 2b00 cmp r3, #0 800146e: d001 beq.n 8001474 <MX_TIM2_Init+0xc4> { Error_Handler(); 8001470: f000 f8f6 bl 8001660 <Error_Handler> } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001474: 2360 movs r3, #96 ; 0x60 8001476: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 8001478: 2301 movs r3, #1 800147a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW; 800147c: 2302 movs r3, #2 800147e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001480: 2300 movs r3, #0 8001482: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001484: 1d3b adds r3, r7, #4 8001486: 2200 movs r2, #0 8001488: 4619 mov r1, r3 800148a: 4807 ldr r0, [pc, #28] ; (80014a8 <MX_TIM2_Init+0xf8>) 800148c: f004 f8e4 bl 8005658 <HAL_TIM_PWM_ConfigChannel> 8001490: 4603 mov r3, r0 8001492: 2b00 cmp r3, #0 8001494: d001 beq.n 800149a <MX_TIM2_Init+0xea> { Error_Handler(); 8001496: f000 f8e3 bl 8001660 <Error_Handler> } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800149a: 4803 ldr r0, [pc, #12] ; (80014a8 <MX_TIM2_Init+0xf8>) 800149c: f000 ff22 bl 80022e4 <HAL_TIM_MspPostInit> } 80014a0: bf00 nop 80014a2: 3738 adds r7, #56 ; 0x38 80014a4: 46bd mov sp, r7 80014a6: bd80 pop {r7, pc} 80014a8: 200006fc .word 0x200006fc 080014ac <MX_TIM3_Init>: * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80014ac: b580 push {r7, lr} 80014ae: b086 sub sp, #24 80014b0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80014b2: f107 0308 add.w r3, r7, #8 80014b6: 2200 movs r2, #0 80014b8: 601a str r2, [r3, #0] 80014ba: 605a str r2, [r3, #4] 80014bc: 609a str r2, [r3, #8] 80014be: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80014c0: 463b mov r3, r7 80014c2: 2200 movs r2, #0 80014c4: 601a str r2, [r3, #0] 80014c6: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80014c8: 4b1d ldr r3, [pc, #116] ; (8001540 <MX_TIM3_Init+0x94>) 80014ca: 4a1e ldr r2, [pc, #120] ; (8001544 <MX_TIM3_Init+0x98>) 80014cc: 601a str r2, [r3, #0] htim3.Init.Prescaler = 65535; 80014ce: 4b1c ldr r3, [pc, #112] ; (8001540 <MX_TIM3_Init+0x94>) 80014d0: f64f 72ff movw r2, #65535 ; 0xffff 80014d4: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80014d6: 4b1a ldr r3, [pc, #104] ; (8001540 <MX_TIM3_Init+0x94>) 80014d8: 2200 movs r2, #0 80014da: 609a str r2, [r3, #8] htim3.Init.Period = 30000; 80014dc: 4b18 ldr r3, [pc, #96] ; (8001540 <MX_TIM3_Init+0x94>) 80014de: f247 5230 movw r2, #30000 ; 0x7530 80014e2: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80014e4: 4b16 ldr r3, [pc, #88] ; (8001540 <MX_TIM3_Init+0x94>) 80014e6: 2200 movs r2, #0 80014e8: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80014ea: 4b15 ldr r3, [pc, #84] ; (8001540 <MX_TIM3_Init+0x94>) 80014ec: 2200 movs r2, #0 80014ee: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 80014f0: 4813 ldr r0, [pc, #76] ; (8001540 <MX_TIM3_Init+0x94>) 80014f2: f003 ff0f bl 8005314 <HAL_TIM_Base_Init> 80014f6: 4603 mov r3, r0 80014f8: 2b00 cmp r3, #0 80014fa: d001 beq.n 8001500 <MX_TIM3_Init+0x54> { Error_Handler(); 80014fc: f000 f8b0 bl 8001660 <Error_Handler> } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001500: f44f 5380 mov.w r3, #4096 ; 0x1000 8001504: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8001506: f107 0308 add.w r3, r7, #8 800150a: 4619 mov r1, r3 800150c: 480c ldr r0, [pc, #48] ; (8001540 <MX_TIM3_Init+0x94>) 800150e: f004 f961 bl 80057d4 <HAL_TIM_ConfigClockSource> 8001512: 4603 mov r3, r0 8001514: 2b00 cmp r3, #0 8001516: d001 beq.n 800151c <MX_TIM3_Init+0x70> { Error_Handler(); 8001518: f000 f8a2 bl 8001660 <Error_Handler> } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800151c: 2330 movs r3, #48 ; 0x30 800151e: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001520: 2300 movs r3, #0 8001522: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001524: 463b mov r3, r7 8001526: 4619 mov r1, r3 8001528: 4805 ldr r0, [pc, #20] ; (8001540 <MX_TIM3_Init+0x94>) 800152a: f004 fcbb bl 8005ea4 <HAL_TIMEx_MasterConfigSynchronization> 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 <MX_TIM3_Init+0x8c> { Error_Handler(); 8001534: f000 f894 bl 8001660 <Error_Handler> } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001538: bf00 nop 800153a: 3718 adds r7, #24 800153c: 46bd mov sp, r7 800153e: bd80 pop {r7, pc} 8001540: 20000744 .word 0x20000744 8001544: 40000400 .word 0x40000400 08001548 <MX_USART1_UART_Init>: * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001548: b580 push {r7, lr} 800154a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800154c: 4b11 ldr r3, [pc, #68] ; (8001594 <MX_USART1_UART_Init+0x4c>) 800154e: 4a12 ldr r2, [pc, #72] ; (8001598 <MX_USART1_UART_Init+0x50>) 8001550: 601a str r2, [r3, #0] huart1.Init.BaudRate = 256000; 8001552: 4b10 ldr r3, [pc, #64] ; (8001594 <MX_USART1_UART_Init+0x4c>) 8001554: f44f 327a mov.w r2, #256000 ; 0x3e800 8001558: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800155a: 4b0e ldr r3, [pc, #56] ; (8001594 <MX_USART1_UART_Init+0x4c>) 800155c: 2200 movs r2, #0 800155e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001560: 4b0c ldr r3, [pc, #48] ; (8001594 <MX_USART1_UART_Init+0x4c>) 8001562: 2200 movs r2, #0 8001564: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001566: 4b0b ldr r3, [pc, #44] ; (8001594 <MX_USART1_UART_Init+0x4c>) 8001568: 2200 movs r2, #0 800156a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800156c: 4b09 ldr r3, [pc, #36] ; (8001594 <MX_USART1_UART_Init+0x4c>) 800156e: 220c movs r2, #12 8001570: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001572: 4b08 ldr r3, [pc, #32] ; (8001594 <MX_USART1_UART_Init+0x4c>) 8001574: 2200 movs r2, #0 8001576: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001578: 4b06 ldr r3, [pc, #24] ; (8001594 <MX_USART1_UART_Init+0x4c>) 800157a: 2200 movs r2, #0 800157c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800157e: 4805 ldr r0, [pc, #20] ; (8001594 <MX_USART1_UART_Init+0x4c>) 8001580: f004 fcee bl 8005f60 <HAL_UART_Init> 8001584: 4603 mov r3, r0 8001586: 2b00 cmp r3, #0 8001588: d001 beq.n 800158e <MX_USART1_UART_Init+0x46> { Error_Handler(); 800158a: f000 f869 bl 8001660 <Error_Handler> } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800158e: bf00 nop 8001590: bd80 pop {r7, pc} 8001592: bf00 nop 8001594: 2000078c .word 0x2000078c 8001598: 40013800 .word 0x40013800 0800159c <MX_GPIO_Init>: * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800159c: b580 push {r7, lr} 800159e: b088 sub sp, #32 80015a0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015a2: f107 0310 add.w r3, r7, #16 80015a6: 2200 movs r2, #0 80015a8: 601a str r2, [r3, #0] 80015aa: 605a str r2, [r3, #4] 80015ac: 609a str r2, [r3, #8] 80015ae: 60da str r2, [r3, #12] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); 80015b0: 4b27 ldr r3, [pc, #156] ; (8001650 <MX_GPIO_Init+0xb4>) 80015b2: 699b ldr r3, [r3, #24] 80015b4: 4a26 ldr r2, [pc, #152] ; (8001650 <MX_GPIO_Init+0xb4>) 80015b6: f043 0320 orr.w r3, r3, #32 80015ba: 6193 str r3, [r2, #24] 80015bc: 4b24 ldr r3, [pc, #144] ; (8001650 <MX_GPIO_Init+0xb4>) 80015be: 699b ldr r3, [r3, #24] 80015c0: f003 0320 and.w r3, r3, #32 80015c4: 60fb str r3, [r7, #12] 80015c6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80015c8: 4b21 ldr r3, [pc, #132] ; (8001650 <MX_GPIO_Init+0xb4>) 80015ca: 699b ldr r3, [r3, #24] 80015cc: 4a20 ldr r2, [pc, #128] ; (8001650 <MX_GPIO_Init+0xb4>) 80015ce: f043 0304 orr.w r3, r3, #4 80015d2: 6193 str r3, [r2, #24] 80015d4: 4b1e ldr r3, [pc, #120] ; (8001650 <MX_GPIO_Init+0xb4>) 80015d6: 699b ldr r3, [r3, #24] 80015d8: f003 0304 and.w r3, r3, #4 80015dc: 60bb str r3, [r7, #8] 80015de: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80015e0: 4b1b ldr r3, [pc, #108] ; (8001650 <MX_GPIO_Init+0xb4>) 80015e2: 699b ldr r3, [r3, #24] 80015e4: 4a1a ldr r2, [pc, #104] ; (8001650 <MX_GPIO_Init+0xb4>) 80015e6: f043 0308 orr.w r3, r3, #8 80015ea: 6193 str r3, [r2, #24] 80015ec: 4b18 ldr r3, [pc, #96] ; (8001650 <MX_GPIO_Init+0xb4>) 80015ee: 699b ldr r3, [r3, #24] 80015f0: f003 0308 and.w r3, r3, #8 80015f4: 607b str r3, [r7, #4] 80015f6: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, LED_Out_Pin|FLASH_nRST_Pin|FLASH_CS_GPIO_Port_Pin, GPIO_PIN_RESET); 80015f8: 2200 movs r2, #0 80015fa: 211c movs r1, #28 80015fc: 4815 ldr r0, [pc, #84] ; (8001654 <MX_GPIO_Init+0xb8>) 80015fe: f002 f86e bl 80036de <HAL_GPIO_WritePin> /*Configure GPIO pins : LED_Out_Pin FLASH_nRST_Pin FLASH_CS_GPIO_Port_Pin */ GPIO_InitStruct.Pin = LED_Out_Pin|FLASH_nRST_Pin|FLASH_CS_GPIO_Port_Pin; 8001602: 231c movs r3, #28 8001604: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001606: 2301 movs r3, #1 8001608: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800160a: 2300 movs r3, #0 800160c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800160e: 2302 movs r3, #2 8001610: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001612: f107 0310 add.w r3, r7, #16 8001616: 4619 mov r1, r3 8001618: 480e ldr r0, [pc, #56] ; (8001654 <MX_GPIO_Init+0xb8>) 800161a: f001 fec5 bl 80033a8 <HAL_GPIO_Init> /*Configure GPIO pin : SPI2_CS_Pin */ GPIO_InitStruct.Pin = SPI2_CS_Pin; 800161e: f44f 5380 mov.w r3, #4096 ; 0x1000 8001622: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8001624: 4b0c ldr r3, [pc, #48] ; (8001658 <MX_GPIO_Init+0xbc>) 8001626: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001628: 2300 movs r3, #0 800162a: 61bb str r3, [r7, #24] HAL_GPIO_Init(SPI2_CS_GPIO_Port, &GPIO_InitStruct); 800162c: f107 0310 add.w r3, r7, #16 8001630: 4619 mov r1, r3 8001632: 480a ldr r0, [pc, #40] ; (800165c <MX_GPIO_Init+0xc0>) 8001634: f001 feb8 bl 80033a8 <HAL_GPIO_Init> /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 1, 0); 8001638: 2200 movs r2, #0 800163a: 2101 movs r1, #1 800163c: 2028 movs r0, #40 ; 0x28 800163e: f001 fe06 bl 800324e <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8001642: 2028 movs r0, #40 ; 0x28 8001644: f001 fe1f bl 8003286 <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001648: bf00 nop 800164a: 3720 adds r7, #32 800164c: 46bd mov sp, r7 800164e: bd80 pop {r7, pc} 8001650: 40021000 .word 0x40021000 8001654: 40010800 .word 0x40010800 8001658: 10210000 .word 0x10210000 800165c: 40010c00 .word 0x40010c00 08001660 <Error_Handler>: /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001660: b480 push {r7} 8001662: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001664: b672 cpsid i } 8001666: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001668: e7fe b.n 8001668 <Error_Handler+0x8> ... 0800166c <updateNumAvailableMeasData>: void sendRxCompleteCTRL(); /* реализация функций */ /* Вычисляет количество готовых байт данных измерения в пределах одной страницы флеш-памяти * и обновляет соответствующее поле структуры */ void updateNumAvailableMeasData() { 800166c: b480 push {r7} 800166e: b083 sub sp, #12 8001670: af00 add r7, sp, #0 uint8_t first_elem, curr_page_pos_ptr, curr_page_ptr; // сохранение последнего значения смещения записанных байт в странице curr_page_pos_ptr = page_pos_ptr; 8001672: 4b23 ldr r3, [pc, #140] ; (8001700 <updateNumAvailableMeasData+0x94>) 8001674: 781b ldrb r3, [r3, #0] 8001676: 71bb strb r3, [r7, #6] // сохранение последнего номера страницы, используемого для записи curr_page_ptr = page_ptr; 8001678: 4b22 ldr r3, [pc, #136] ; (8001704 <updateNumAvailableMeasData+0x98>) 800167a: 881b ldrh r3, [r3, #0] 800167c: b29b uxth r3, r3 800167e: 717b strb r3, [r7, #5] if (read.cur_page_num == curr_page_ptr && // если указатели записи и чтения на одной странице и совпадают 8001680: 4b21 ldr r3, [pc, #132] ; (8001708 <updateNumAvailableMeasData+0x9c>) 8001682: 681a ldr r2, [r3, #0] 8001684: 797b ldrb r3, [r7, #5] 8001686: 429a cmp r2, r3 8001688: d10a bne.n 80016a0 <updateNumAvailableMeasData+0x34> read.page_offset_read == curr_page_pos_ptr) { 800168a: 4b1f ldr r3, [pc, #124] ; (8001708 <updateNumAvailableMeasData+0x9c>) 800168c: f993 3004 ldrsb.w r3, [r3, #4] 8001690: 461a mov r2, r3 8001692: 79bb ldrb r3, [r7, #6] if (read.cur_page_num == curr_page_ptr && // если указатели записи и чтения на одной странице и совпадают 8001694: 429a cmp r2, r3 8001696: d103 bne.n 80016a0 <updateNumAvailableMeasData+0x34> read.num_ready_bytes = 0; 8001698: 4b1b ldr r3, [pc, #108] ; (8001708 <updateNumAvailableMeasData+0x9c>) 800169a: 2200 movs r2, #0 800169c: 715a strb r2, [r3, #5] return; 800169e: e02b b.n 80016f8 <updateNumAvailableMeasData+0x8c> } else if (read.cur_page_num == curr_page_ptr && curr_page_pos_ptr == 0) { 80016a0: 4b19 ldr r3, [pc, #100] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016a2: 681a ldr r2, [r3, #0] 80016a4: 797b ldrb r3, [r7, #5] 80016a6: 429a cmp r2, r3 80016a8: d106 bne.n 80016b8 <updateNumAvailableMeasData+0x4c> 80016aa: 79bb ldrb r3, [r7, #6] 80016ac: 2b00 cmp r3, #0 80016ae: d103 bne.n 80016b8 <updateNumAvailableMeasData+0x4c> read.num_ready_bytes = 0; 80016b0: 4b15 ldr r3, [pc, #84] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016b2: 2200 movs r2, #0 80016b4: 715a strb r2, [r3, #5] return; 80016b6: e01f b.n 80016f8 <updateNumAvailableMeasData+0x8c> } else if (read.cur_page_num != curr_page_ptr) { // если указатель записи на другой странице 80016b8: 4b13 ldr r3, [pc, #76] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016ba: 681a ldr r2, [r3, #0] 80016bc: 797b ldrb r3, [r7, #5] 80016be: 429a cmp r2, r3 80016c0: d001 beq.n 80016c6 <updateNumAvailableMeasData+0x5a> // будет выполняться чтение до конца текущей страницы curr_page_pos_ptr = 127; 80016c2: 237f movs r3, #127 ; 0x7f 80016c4: 71bb strb r3, [r7, #6] } // общий случай: если номер последней считанной страницы совпадает с номером страницы, куда выполнялась запись // определение первого элемента страницы, начиная с которого в странице находятся готовые данные if (read.page_offset_read == -1) { 80016c6: 4b10 ldr r3, [pc, #64] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016c8: f993 3004 ldrsb.w r3, [r3, #4] 80016cc: f1b3 3fff cmp.w r3, #4294967295 80016d0: d102 bne.n 80016d8 <updateNumAvailableMeasData+0x6c> first_elem = 0; 80016d2: 2300 movs r3, #0 80016d4: 71fb strb r3, [r7, #7] 80016d6: e006 b.n 80016e6 <updateNumAvailableMeasData+0x7a> } else { first_elem = (read.page_offset_read + 1) * 2; 80016d8: 4b0b ldr r3, [pc, #44] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016da: f993 3004 ldrsb.w r3, [r3, #4] 80016de: 3301 adds r3, #1 80016e0: b2db uxtb r3, r3 80016e2: 005b lsls r3, r3, #1 80016e4: 71fb strb r3, [r7, #7] } read.num_ready_bytes = (curr_page_pos_ptr * 2) - first_elem; 80016e6: 79bb ldrb r3, [r7, #6] 80016e8: 005b lsls r3, r3, #1 80016ea: b2da uxtb r2, r3 80016ec: 79fb ldrb r3, [r7, #7] 80016ee: 1ad3 subs r3, r2, r3 80016f0: b2da uxtb r2, r3 80016f2: 4b05 ldr r3, [pc, #20] ; (8001708 <updateNumAvailableMeasData+0x9c>) 80016f4: 715a strb r2, [r3, #5] return; 80016f6: bf00 nop } 80016f8: 370c adds r7, #12 80016fa: 46bd mov sp, r7 80016fc: bc80 pop {r7} 80016fe: 4770 bx lr 8001700: 200008d5 .word 0x200008d5 8001704: 200008d2 .word 0x200008d2 8001708: 20000028 .word 0x20000028 0800170c <setFSMProtocolState>: void setFSMProtocolState(uint8_t state) { 800170c: b480 push {r7} 800170e: b083 sub sp, #12 8001710: af00 add r7, sp, #0 8001712: 4603 mov r3, r0 8001714: 71fb strb r3, [r7, #7] FSM_state = state; 8001716: 4a04 ldr r2, [pc, #16] ; (8001728 <setFSMProtocolState+0x1c>) 8001718: 79fb ldrb r3, [r7, #7] 800171a: 7013 strb r3, [r2, #0] } 800171c: bf00 nop 800171e: 370c adds r7, #12 8001720: 46bd mov sp, r7 8001722: bc80 pop {r7} 8001724: 4770 bx lr 8001726: bf00 nop 8001728: 200009f4 .word 0x200009f4 0800172c <fillDataFrame>: /* Заполняет кадр ответа с данными измерения и уведомляет модуль SPI_connection * о готовности ответа к отправке */ void fillDataFrame() { 800172c: b580 push {r7, lr} 800172e: b082 sub sp, #8 8001730: af00 add r7, sp, #0 // формирование кадра ответа с данными memset(response,0,FRAME_LEN); 8001732: f44f 7284 mov.w r2, #264 ; 0x108 8001736: 2100 movs r1, #0 8001738: 481f ldr r0, [pc, #124] ; (80017b8 <fillDataFrame+0x8c>) 800173a: f005 f9a3 bl 8006a84 <memset> response[0] = 0xFA; 800173e: 4b1e ldr r3, [pc, #120] ; (80017b8 <fillDataFrame+0x8c>) 8001740: 22fa movs r2, #250 ; 0xfa 8001742: 701a strb r2, [r3, #0] response[1] = 0xAA; 8001744: 4b1c ldr r3, [pc, #112] ; (80017b8 <fillDataFrame+0x8c>) 8001746: 22aa movs r2, #170 ; 0xaa 8001748: 705a strb r2, [r3, #1] // заполнение поля данных fillDataField(); 800174a: f000 f83d bl 80017c8 <fillDataField> // определение наличия следующих байт данных, для следующего запроса на получение данных updateNumAvailableMeasData(); 800174e: f7ff ff8d bl 800166c <updateNumAvailableMeasData> response[2] = read.num_ready_bytes; 8001752: 4b1a ldr r3, [pc, #104] ; (80017bc <fillDataFrame+0x90>) 8001754: 795a ldrb r2, [r3, #5] 8001756: 4b18 ldr r3, [pc, #96] ; (80017b8 <fillDataFrame+0x8c>) 8001758: 709a strb r2, [r3, #2] response[258] = 0xFF; 800175a: 4b17 ldr r3, [pc, #92] ; (80017b8 <fillDataFrame+0x8c>) 800175c: 22ff movs r2, #255 ; 0xff 800175e: f883 2102 strb.w r2, [r3, #258] ; 0x102 response[259] = 0x0B; 8001762: 4b15 ldr r3, [pc, #84] ; (80017b8 <fillDataFrame+0x8c>) 8001764: 220b movs r2, #11 8001766: f883 2103 strb.w r2, [r3, #259] ; 0x103 //response[257] = FSM_state; // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 800176a: f44f 7182 mov.w r1, #260 ; 0x104 800176e: 4812 ldr r0, [pc, #72] ; (80017b8 <fillDataFrame+0x8c>) 8001770: f000 fb1e bl 8001db0 <calculateCRC32> 8001774: 6078 str r0, [r7, #4] response[260] = (crc >> 24) & 0xFF; 8001776: 687b ldr r3, [r7, #4] 8001778: 0e1b lsrs r3, r3, #24 800177a: b2da uxtb r2, r3 800177c: 4b0e ldr r3, [pc, #56] ; (80017b8 <fillDataFrame+0x8c>) 800177e: f883 2104 strb.w r2, [r3, #260] ; 0x104 response[261] = (crc >> 16) & 0xFF; 8001782: 687b ldr r3, [r7, #4] 8001784: 0c1b lsrs r3, r3, #16 8001786: b2da uxtb r2, r3 8001788: 4b0b ldr r3, [pc, #44] ; (80017b8 <fillDataFrame+0x8c>) 800178a: f883 2105 strb.w r2, [r3, #261] ; 0x105 response[262] = (crc >> 8) & 0xFF; 800178e: 687b ldr r3, [r7, #4] 8001790: 0a1b lsrs r3, r3, #8 8001792: b2da uxtb r2, r3 8001794: 4b08 ldr r3, [pc, #32] ; (80017b8 <fillDataFrame+0x8c>) 8001796: f883 2106 strb.w r2, [r3, #262] ; 0x106 response[263] = crc & 0xFF; 800179a: 687b ldr r3, [r7, #4] 800179c: b2da uxtb r2, r3 800179e: 4b06 ldr r3, [pc, #24] ; (80017b8 <fillDataFrame+0x8c>) 80017a0: f883 2107 strb.w r2, [r3, #263] ; 0x107 // устанавливаем указатель модуля приема/передачи на буфер с подготовленным ответом new_response_frame = response; 80017a4: 4b06 ldr r3, [pc, #24] ; (80017c0 <fillDataFrame+0x94>) 80017a6: 4a04 ldr r2, [pc, #16] ; (80017b8 <fillDataFrame+0x8c>) 80017a8: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 80017aa: 4b06 ldr r3, [pc, #24] ; (80017c4 <fillDataFrame+0x98>) 80017ac: 2201 movs r2, #1 80017ae: 701a strb r2, [r3, #0] }; 80017b0: bf00 nop 80017b2: 3708 adds r7, #8 80017b4: 46bd mov sp, r7 80017b6: bd80 pop {r7, pc} 80017b8: 200008ec .word 0x200008ec 80017bc: 20000028 .word 0x20000028 80017c0: 20000510 .word 0x20000510 80017c4: 200000e5 .word 0x200000e5 080017c8 <fillDataField>: void fillDataField() { 80017c8: b580 push {r7, lr} 80017ca: b082 sub sp, #8 80017cc: af00 add r7, sp, #0 uint8_t first_elem, last_elem; if (read.num_ready_bytes == 0) { 80017ce: 4b3b ldr r3, [pc, #236] ; (80018bc <fillDataField+0xf4>) 80017d0: 795b ldrb r3, [r3, #5] 80017d2: 2b00 cmp r3, #0 80017d4: d06e beq.n 80018b4 <fillDataField+0xec> return; } // чтение страницы флеш-памяти в буфер с данными HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 80017d6: 2201 movs r2, #1 80017d8: 2104 movs r1, #4 80017da: 4839 ldr r0, [pc, #228] ; (80018c0 <fillDataField+0xf8>) 80017dc: f001 ff7f bl 80036de <HAL_GPIO_WritePin> W25_Read_Page(data_buf, read.cur_page_num, 0, w25_info.PageSize); 80017e0: 4b36 ldr r3, [pc, #216] ; (80018bc <fillDataField+0xf4>) 80017e2: 6819 ldr r1, [r3, #0] 80017e4: 4b37 ldr r3, [pc, #220] ; (80018c4 <fillDataField+0xfc>) 80017e6: 881b ldrh r3, [r3, #0] 80017e8: 2200 movs r2, #0 80017ea: 4837 ldr r0, [pc, #220] ; (80018c8 <fillDataField+0x100>) 80017ec: f005 f896 bl 800691c <W25_Read_Page> // определение смещения, с которого необходимо добавлять байты в поле данных считанной страницы if (read.page_offset_read == -1) { 80017f0: 4b32 ldr r3, [pc, #200] ; (80018bc <fillDataField+0xf4>) 80017f2: f993 3004 ldrsb.w r3, [r3, #4] 80017f6: f1b3 3fff cmp.w r3, #4294967295 80017fa: d102 bne.n 8001802 <fillDataField+0x3a> first_elem = 0; 80017fc: 2300 movs r3, #0 80017fe: 71fb strb r3, [r7, #7] 8001800: e006 b.n 8001810 <fillDataField+0x48> } else { first_elem = (read.page_offset_read + 1) * 2; 8001802: 4b2e ldr r3, [pc, #184] ; (80018bc <fillDataField+0xf4>) 8001804: f993 3004 ldrsb.w r3, [r3, #4] 8001808: 3301 adds r3, #1 800180a: b2db uxtb r3, r3 800180c: 005b lsls r3, r3, #1 800180e: 71fb strb r3, [r7, #7] } // определение последнего номера элемента страницы, до которого необходимо выполнять считывание страницы last_elem = first_elem + read.num_ready_bytes - 1; 8001810: 4b2a ldr r3, [pc, #168] ; (80018bc <fillDataField+0xf4>) 8001812: 795a ldrb r2, [r3, #5] 8001814: 79fb ldrb r3, [r7, #7] 8001816: 4413 add r3, r2 8001818: b2db uxtb r3, r3 800181a: 3b01 subs r3, #1 800181c: 707b strb r3, [r7, #1] for (uint16_t k = 3, i = first_elem; i <= last_elem; i++, k++) { 800181e: 2303 movs r3, #3 8001820: 80bb strh r3, [r7, #4] 8001822: 79fb ldrb r3, [r7, #7] 8001824: 807b strh r3, [r7, #2] 8001826: e00b b.n 8001840 <fillDataField+0x78> response[k] = data_buf[i]; 8001828: 887a ldrh r2, [r7, #2] 800182a: 88bb ldrh r3, [r7, #4] 800182c: 4926 ldr r1, [pc, #152] ; (80018c8 <fillDataField+0x100>) 800182e: 5c89 ldrb r1, [r1, r2] 8001830: 4a26 ldr r2, [pc, #152] ; (80018cc <fillDataField+0x104>) 8001832: 54d1 strb r1, [r2, r3] for (uint16_t k = 3, i = first_elem; i <= last_elem; i++, k++) { 8001834: 887b ldrh r3, [r7, #2] 8001836: 3301 adds r3, #1 8001838: 807b strh r3, [r7, #2] 800183a: 88bb ldrh r3, [r7, #4] 800183c: 3301 adds r3, #1 800183e: 80bb strh r3, [r7, #4] 8001840: 787b ldrb r3, [r7, #1] 8001842: b29b uxth r3, r3 8001844: 887a ldrh r2, [r7, #2] 8001846: 429a cmp r2, r3 8001848: d9ee bls.n 8001828 <fillDataField+0x60> } // обновление номера последнего считанного слова страницы if (read.page_offset_read == -1) { 800184a: 4b1c ldr r3, [pc, #112] ; (80018bc <fillDataField+0xf4>) 800184c: f993 3004 ldrsb.w r3, [r3, #4] 8001850: f1b3 3fff cmp.w r3, #4294967295 8001854: d109 bne.n 800186a <fillDataField+0xa2> read.page_offset_read = (read.num_ready_bytes / 2) - 1; 8001856: 4b19 ldr r3, [pc, #100] ; (80018bc <fillDataField+0xf4>) 8001858: 795b ldrb r3, [r3, #5] 800185a: 085b lsrs r3, r3, #1 800185c: b2db uxtb r3, r3 800185e: 3b01 subs r3, #1 8001860: b2db uxtb r3, r3 8001862: b25a sxtb r2, r3 8001864: 4b15 ldr r3, [pc, #84] ; (80018bc <fillDataField+0xf4>) 8001866: 711a strb r2, [r3, #4] 8001868: e00c b.n 8001884 <fillDataField+0xbc> } else { read.page_offset_read += (read.num_ready_bytes / 2); 800186a: 4b14 ldr r3, [pc, #80] ; (80018bc <fillDataField+0xf4>) 800186c: f993 3004 ldrsb.w r3, [r3, #4] 8001870: b2da uxtb r2, r3 8001872: 4b12 ldr r3, [pc, #72] ; (80018bc <fillDataField+0xf4>) 8001874: 795b ldrb r3, [r3, #5] 8001876: 085b lsrs r3, r3, #1 8001878: b2db uxtb r3, r3 800187a: 4413 add r3, r2 800187c: b2db uxtb r3, r3 800187e: b25a sxtb r2, r3 8001880: 4b0e ldr r3, [pc, #56] ; (80018bc <fillDataField+0xf4>) 8001882: 711a strb r2, [r3, #4] } // обновление номера страницы флеш-памяти, которая будет считана в следующий раз если текущая считана полностью if (read.page_offset_read == 126) { 8001884: 4b0d ldr r3, [pc, #52] ; (80018bc <fillDataField+0xf4>) 8001886: f993 3004 ldrsb.w r3, [r3, #4] 800188a: 2b7e cmp r3, #126 ; 0x7e 800188c: d113 bne.n 80018b6 <fillDataField+0xee> if (read.cur_page_num == LIMIT_FLASH_PAGE_NUM - 1) { // текущая считанная страница последняя во флеш-памяти 800188e: 4b0b ldr r3, [pc, #44] ; (80018bc <fillDataField+0xf4>) 8001890: 681b ldr r3, [r3, #0] 8001892: f64f 72ff movw r2, #65535 ; 0xffff 8001896: 4293 cmp r3, r2 8001898: d103 bne.n 80018a2 <fillDataField+0xda> read.cur_page_num = 0; 800189a: 4b08 ldr r3, [pc, #32] ; (80018bc <fillDataField+0xf4>) 800189c: 2200 movs r2, #0 800189e: 601a str r2, [r3, #0] 80018a0: e004 b.n 80018ac <fillDataField+0xe4> } else { read.cur_page_num++; 80018a2: 4b06 ldr r3, [pc, #24] ; (80018bc <fillDataField+0xf4>) 80018a4: 681b ldr r3, [r3, #0] 80018a6: 3301 adds r3, #1 80018a8: 4a04 ldr r2, [pc, #16] ; (80018bc <fillDataField+0xf4>) 80018aa: 6013 str r3, [r2, #0] } // выполняется сброс смещения для чтения, поскольку было прочитано последнее слово страницы флеш-памяти read.page_offset_read = -1; 80018ac: 4b03 ldr r3, [pc, #12] ; (80018bc <fillDataField+0xf4>) 80018ae: 22ff movs r2, #255 ; 0xff 80018b0: 711a strb r2, [r3, #4] 80018b2: e000 b.n 80018b6 <fillDataField+0xee> return; 80018b4: bf00 nop } }; 80018b6: 3708 adds r7, #8 80018b8: 46bd mov sp, r7 80018ba: bd80 pop {r7, pc} 80018bc: 20000028 .word 0x20000028 80018c0: 40010800 .word 0x40010800 80018c4: 20000a0c .word 0x20000a0c 80018c8: 200007d0 .word 0x200007d0 80018cc: 200008ec .word 0x200008ec 080018d0 <fillResponseFrame>: /* Заполняет кадр ответа и уведомляет модуль SPI_connection о готовности ответа к отправке * Параметр 1: код состояния датчика по протоколу * Параметр 2: код команды, на которую дается ответ */ void fillResponseFrame(uint16_t response_code, uint16_t command_code) { 80018d0: b580 push {r7, lr} 80018d2: b084 sub sp, #16 80018d4: af00 add r7, sp, #0 80018d6: 4603 mov r3, r0 80018d8: 460a mov r2, r1 80018da: 80fb strh r3, [r7, #6] 80018dc: 4613 mov r3, r2 80018de: 80bb strh r3, [r7, #4] // формирование ответа memset(response,0,FRAME_LEN); 80018e0: f44f 7284 mov.w r2, #264 ; 0x108 80018e4: 2100 movs r1, #0 80018e6: 4821 ldr r0, [pc, #132] ; (800196c <fillResponseFrame+0x9c>) 80018e8: f005 f8cc bl 8006a84 <memset> response[0] = 0xFA; 80018ec: 4b1f ldr r3, [pc, #124] ; (800196c <fillResponseFrame+0x9c>) 80018ee: 22fa movs r2, #250 ; 0xfa 80018f0: 701a strb r2, [r3, #0] response[1] = 0xAF; 80018f2: 4b1e ldr r3, [pc, #120] ; (800196c <fillResponseFrame+0x9c>) 80018f4: 22af movs r2, #175 ; 0xaf 80018f6: 705a strb r2, [r3, #1] response[2] = response_code; 80018f8: 88fb ldrh r3, [r7, #6] 80018fa: b2da uxtb r2, r3 80018fc: 4b1b ldr r3, [pc, #108] ; (800196c <fillResponseFrame+0x9c>) 80018fe: 709a strb r2, [r3, #2] if (command_code == CMD_STATUS) { 8001900: 88bb ldrh r3, [r7, #4] 8001902: 2ba2 cmp r3, #162 ; 0xa2 8001904: d103 bne.n 800190e <fillResponseFrame+0x3e> // определение числа готовых данных измерения response[3] = read.num_ready_bytes; 8001906: 4b1a ldr r3, [pc, #104] ; (8001970 <fillResponseFrame+0xa0>) 8001908: 795a ldrb r2, [r3, #5] 800190a: 4b18 ldr r3, [pc, #96] ; (800196c <fillResponseFrame+0x9c>) 800190c: 70da strb r2, [r3, #3] response[255] = page_pos_ptr; response[256] = read.page_offset_read; response[257] = FSM_state; */ response[258] = 0xFF; 800190e: 4b17 ldr r3, [pc, #92] ; (800196c <fillResponseFrame+0x9c>) 8001910: 22ff movs r2, #255 ; 0xff 8001912: f883 2102 strb.w r2, [r3, #258] ; 0x102 response[259] = 0x0D; 8001916: 4b15 ldr r3, [pc, #84] ; (800196c <fillResponseFrame+0x9c>) 8001918: 220d movs r2, #13 800191a: f883 2103 strb.w r2, [r3, #259] ; 0x103 // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 800191e: f44f 7182 mov.w r1, #260 ; 0x104 8001922: 4812 ldr r0, [pc, #72] ; (800196c <fillResponseFrame+0x9c>) 8001924: f000 fa44 bl 8001db0 <calculateCRC32> 8001928: 60f8 str r0, [r7, #12] response[260] = (crc >> 24) & 0xFF; 800192a: 68fb ldr r3, [r7, #12] 800192c: 0e1b lsrs r3, r3, #24 800192e: b2da uxtb r2, r3 8001930: 4b0e ldr r3, [pc, #56] ; (800196c <fillResponseFrame+0x9c>) 8001932: f883 2104 strb.w r2, [r3, #260] ; 0x104 response[261] = (crc >> 16) & 0xFF; 8001936: 68fb ldr r3, [r7, #12] 8001938: 0c1b lsrs r3, r3, #16 800193a: b2da uxtb r2, r3 800193c: 4b0b ldr r3, [pc, #44] ; (800196c <fillResponseFrame+0x9c>) 800193e: f883 2105 strb.w r2, [r3, #261] ; 0x105 response[262] = (crc >> 8) & 0xFF; 8001942: 68fb ldr r3, [r7, #12] 8001944: 0a1b lsrs r3, r3, #8 8001946: b2da uxtb r2, r3 8001948: 4b08 ldr r3, [pc, #32] ; (800196c <fillResponseFrame+0x9c>) 800194a: f883 2106 strb.w r2, [r3, #262] ; 0x106 response[263] = crc & 0xFF; 800194e: 68fb ldr r3, [r7, #12] 8001950: b2da uxtb r2, r3 8001952: 4b06 ldr r3, [pc, #24] ; (800196c <fillResponseFrame+0x9c>) 8001954: f883 2107 strb.w r2, [r3, #263] ; 0x107 // устанавливаем указатель модуля приема/передачи на буфер с подготовленным ответом new_response_frame = response; 8001958: 4b06 ldr r3, [pc, #24] ; (8001974 <fillResponseFrame+0xa4>) 800195a: 4a04 ldr r2, [pc, #16] ; (800196c <fillResponseFrame+0x9c>) 800195c: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 800195e: 4b06 ldr r3, [pc, #24] ; (8001978 <fillResponseFrame+0xa8>) 8001960: 2201 movs r2, #1 8001962: 701a strb r2, [r3, #0] }; 8001964: bf00 nop 8001966: 3710 adds r7, #16 8001968: 46bd mov sp, r7 800196a: bd80 pop {r7, pc} 800196c: 200008ec .word 0x200008ec 8001970: 20000028 .word 0x20000028 8001974: 20000510 .word 0x20000510 8001978: 200000e5 .word 0x200000e5 0800197c <sendPreviousResponse>: /* Подготавливает к отправке предыдущий кадр ответа */ void sendPreviousResponse() { 800197c: b580 push {r7, lr} 800197e: af00 add r7, sp, #0 // обновление сохраненного ответа updateSavedResponse(response); 8001980: 4805 ldr r0, [pc, #20] ; (8001998 <sendPreviousResponse+0x1c>) 8001982: f000 f80f bl 80019a4 <updateSavedResponse> // устанавливаем указатель модуля приема/передачи на буфер с прошлым ответом для его передачи new_response_frame = response; 8001986: 4b05 ldr r3, [pc, #20] ; (800199c <sendPreviousResponse+0x20>) 8001988: 4a03 ldr r2, [pc, #12] ; (8001998 <sendPreviousResponse+0x1c>) 800198a: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 800198c: 4b04 ldr r3, [pc, #16] ; (80019a0 <sendPreviousResponse+0x24>) 800198e: 2201 movs r2, #1 8001990: 701a strb r2, [r3, #0] return; 8001992: bf00 nop }; 8001994: bd80 pop {r7, pc} 8001996: bf00 nop 8001998: 200008ec .word 0x200008ec 800199c: 20000510 .word 0x20000510 80019a0: 200000e5 .word 0x200000e5 080019a4 <updateSavedResponse>: void updateSavedResponse(uint8_t* response) { 80019a4: b580 push {r7, lr} 80019a6: b084 sub sp, #16 80019a8: af00 add r7, sp, #0 80019aa: 6078 str r0, [r7, #4] // определение типа сохраненного кадра ответа if (response[1] == 0xAA) { // сохраненный кадр - кадр ответа с данными (проверка 2-го байта старт-слова) 80019ac: 687b ldr r3, [r7, #4] 80019ae: 3301 adds r3, #1 80019b0: 781b ldrb r3, [r3, #0] 80019b2: 2baa cmp r3, #170 ; 0xaa 80019b4: d107 bne.n 80019c6 <updateSavedResponse+0x22> // обновления наличия следующих байт данных, для следующего запроса на получение данных updateNumAvailableMeasData(); 80019b6: f7ff fe59 bl 800166c <updateNumAvailableMeasData> response[2] = read.num_ready_bytes; 80019ba: 687b ldr r3, [r7, #4] 80019bc: 3302 adds r3, #2 80019be: 4a1a ldr r2, [pc, #104] ; (8001a28 <updateSavedResponse+0x84>) 80019c0: 7952 ldrb r2, [r2, #5] 80019c2: 701a strb r2, [r3, #0] 80019c4: e00b b.n 80019de <updateSavedResponse+0x3a> } else { // кадр ответа на команду if (response[2] == CMD_STATUS) { 80019c6: 687b ldr r3, [r7, #4] 80019c8: 3302 adds r3, #2 80019ca: 781b ldrb r3, [r3, #0] 80019cc: 2ba2 cmp r3, #162 ; 0xa2 80019ce: d106 bne.n 80019de <updateSavedResponse+0x3a> // обновление признака наличия результатов измерения updateNumAvailableMeasData(); 80019d0: f7ff fe4c bl 800166c <updateNumAvailableMeasData> response[3] = read.num_ready_bytes; 80019d4: 687b ldr r3, [r7, #4] 80019d6: 3303 adds r3, #3 80019d8: 4a13 ldr r2, [pc, #76] ; (8001a28 <updateSavedResponse+0x84>) 80019da: 7952 ldrb r2, [r2, #5] 80019dc: 701a strb r2, [r3, #0] } } // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 80019de: f44f 7182 mov.w r1, #260 ; 0x104 80019e2: 6878 ldr r0, [r7, #4] 80019e4: f000 f9e4 bl 8001db0 <calculateCRC32> 80019e8: 60f8 str r0, [r7, #12] response[260] = (crc >> 24) & 0xFF; 80019ea: 68fb ldr r3, [r7, #12] 80019ec: 0e1a lsrs r2, r3, #24 80019ee: 687b ldr r3, [r7, #4] 80019f0: f503 7382 add.w r3, r3, #260 ; 0x104 80019f4: b2d2 uxtb r2, r2 80019f6: 701a strb r2, [r3, #0] response[261] = (crc >> 16) & 0xFF; 80019f8: 68fb ldr r3, [r7, #12] 80019fa: 0c1a lsrs r2, r3, #16 80019fc: 687b ldr r3, [r7, #4] 80019fe: f203 1305 addw r3, r3, #261 ; 0x105 8001a02: b2d2 uxtb r2, r2 8001a04: 701a strb r2, [r3, #0] response[262] = (crc >> 8) & 0xFF; 8001a06: 68fb ldr r3, [r7, #12] 8001a08: 0a1a lsrs r2, r3, #8 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: f503 7383 add.w r3, r3, #262 ; 0x106 8001a10: b2d2 uxtb r2, r2 8001a12: 701a strb r2, [r3, #0] response[263] = crc & 0xFF; 8001a14: 687b ldr r3, [r7, #4] 8001a16: f203 1307 addw r3, r3, #263 ; 0x107 8001a1a: 68fa ldr r2, [r7, #12] 8001a1c: b2d2 uxtb r2, r2 8001a1e: 701a strb r2, [r3, #0] return; 8001a20: bf00 nop } 8001a22: 3710 adds r7, #16 8001a24: 46bd mov sp, r7 8001a26: bd80 pop {r7, pc} 8001a28: 20000028 .word 0x20000028 08001a2c <parserFSM>: void parserFSM() { 8001a2c: b580 push {r7, lr} 8001a2e: af00 add r7, sp, #0 #ifndef TEST_VER sendRxCompleteCTRL(); 8001a30: f000 fa12 bl 8001e58 <sendRxCompleteCTRL> // проверка контрольной суммы if(!checkCRC32(safe_command_frame, FRAME_LEN-4)) { 8001a34: f44f 7182 mov.w r1, #260 ; 0x104 8001a38: 48ba ldr r0, [pc, #744] ; (8001d24 <parserFSM+0x2f8>) 8001a3a: f000 f989 bl 8001d50 <checkCRC32> 8001a3e: 4603 mov r3, r0 8001a40: f083 0301 eor.w r3, r3, #1 8001a44: b2db uxtb r3, r3 8001a46: 2b00 cmp r3, #0 8001a48: d004 beq.n 8001a54 <parserFSM+0x28> // формирование ответа - ошибка CRC fillResponseFrame(CRC_ERROR, 0); 8001a4a: 2100 movs r1, #0 8001a4c: 20ff movs r0, #255 ; 0xff 8001a4e: f7ff ff3f bl 80018d0 <fillResponseFrame> return; 8001a52: e17c b.n 8001d4e <parserFSM+0x322> } #endif switch(FSM_state) { 8001a54: 4bb4 ldr r3, [pc, #720] ; (8001d28 <parserFSM+0x2fc>) 8001a56: 781b ldrb r3, [r3, #0] 8001a58: 2b05 cmp r3, #5 8001a5a: f200 8178 bhi.w 8001d4e <parserFSM+0x322> 8001a5e: a201 add r2, pc, #4 ; (adr r2, 8001a64 <parserFSM+0x38>) 8001a60: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001a64: 08001a7d .word 0x08001a7d 8001a68: 08001adb .word 0x08001adb 8001a6c: 08001b57 .word 0x08001b57 8001a70: 08001be5 .word 0x08001be5 8001a74: 08001c65 .word 0x08001c65 8001a78: 08001ced .word 0x08001ced case CONNECTED_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8001a7c: 4ba9 ldr r3, [pc, #676] ; (8001d24 <parserFSM+0x2f8>) 8001a7e: 789b ldrb r3, [r3, #2] 8001a80: 2bff cmp r3, #255 ; 0xff 8001a82: d026 beq.n 8001ad2 <parserFSM+0xa6> 8001a84: 2bff cmp r3, #255 ; 0xff 8001a86: f300 8159 bgt.w 8001d3c <parserFSM+0x310> 8001a8a: 2ba2 cmp r3, #162 ; 0xa2 8001a8c: d002 beq.n 8001a94 <parserFSM+0x68> 8001a8e: 2ba3 cmp r3, #163 ; 0xa3 8001a90: d01c beq.n 8001acc <parserFSM+0xa0> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8001a92: e153 b.n 8001d3c <parserFSM+0x310> if (sensorSelfCheck()) { // самопроверка датчика выполнилась успешно 8001a94: f000 fa7c bl 8001f90 <sensorSelfCheck> 8001a98: 4603 mov r3, r0 8001a9a: 2b00 cmp r3, #0 8001a9c: d011 beq.n 8001ac2 <parserFSM+0x96> updateNumAvailableMeasData(); 8001a9e: f7ff fde5 bl 800166c <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8001aa2: 4ba2 ldr r3, [pc, #648] ; (8001d2c <parserFSM+0x300>) 8001aa4: 795b ldrb r3, [r3, #5] 8001aa6: 2b00 cmp r3, #0 8001aa8: d003 beq.n 8001ab2 <parserFSM+0x86> setFSMProtocolState(EXCHANGE_STATE); 8001aaa: 2003 movs r0, #3 8001aac: f7ff fe2e bl 800170c <setFSMProtocolState> 8001ab0: e002 b.n 8001ab8 <parserFSM+0x8c> setFSMProtocolState(READY_STATE); 8001ab2: 2001 movs r0, #1 8001ab4: f7ff fe2a bl 800170c <setFSMProtocolState> fillResponseFrame(SENSOR_ID, CMD_STATUS); 8001ab8: 21a2 movs r1, #162 ; 0xa2 8001aba: 202c movs r0, #44 ; 0x2c 8001abc: f7ff ff08 bl 80018d0 <fillResponseFrame> break; 8001ac0: e00a b.n 8001ad8 <parserFSM+0xac> fillResponseFrame(STATE_ERROR, CMD_STATUS); 8001ac2: 21a2 movs r1, #162 ; 0xa2 8001ac4: 2008 movs r0, #8 8001ac6: f7ff ff03 bl 80018d0 <fillResponseFrame> break; 8001aca: e005 b.n 8001ad8 <parserFSM+0xac> resetSensor(); 8001acc: f000 fa9e bl 800200c <resetSensor> break; 8001ad0: e002 b.n 8001ad8 <parserFSM+0xac> sendPreviousResponse(); 8001ad2: f7ff ff53 bl 800197c <sendPreviousResponse> break; 8001ad6: bf00 nop break; 8001ad8: e130 b.n 8001d3c <parserFSM+0x310> case READY_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8001ada: 4b92 ldr r3, [pc, #584] ; (8001d24 <parserFSM+0x2f8>) 8001adc: 789b ldrb r3, [r3, #2] 8001ade: 2bff cmp r3, #255 ; 0xff 8001ae0: d035 beq.n 8001b4e <parserFSM+0x122> 8001ae2: 2bff cmp r3, #255 ; 0xff 8001ae4: f300 812c bgt.w 8001d40 <parserFSM+0x314> 8001ae8: 2ba4 cmp r3, #164 ; 0xa4 8001aea: d026 beq.n 8001b3a <parserFSM+0x10e> 8001aec: 2ba4 cmp r3, #164 ; 0xa4 8001aee: f300 8127 bgt.w 8001d40 <parserFSM+0x314> 8001af2: 2ba2 cmp r3, #162 ; 0xa2 8001af4: d002 beq.n 8001afc <parserFSM+0xd0> 8001af6: 2ba3 cmp r3, #163 ; 0xa3 8001af8: d01c beq.n 8001b34 <parserFSM+0x108> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8001afa: e121 b.n 8001d40 <parserFSM+0x314> if (sensorSelfCheck()) { // самопроверка датчика выполнилась успешно 8001afc: f000 fa48 bl 8001f90 <sensorSelfCheck> 8001b00: 4603 mov r3, r0 8001b02: 2b00 cmp r3, #0 8001b04: d011 beq.n 8001b2a <parserFSM+0xfe> updateNumAvailableMeasData(); 8001b06: f7ff fdb1 bl 800166c <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8001b0a: 4b88 ldr r3, [pc, #544] ; (8001d2c <parserFSM+0x300>) 8001b0c: 795b ldrb r3, [r3, #5] 8001b0e: 2b00 cmp r3, #0 8001b10: d003 beq.n 8001b1a <parserFSM+0xee> setFSMProtocolState(EXCHANGE_STATE); 8001b12: 2003 movs r0, #3 8001b14: f7ff fdfa bl 800170c <setFSMProtocolState> 8001b18: e002 b.n 8001b20 <parserFSM+0xf4> setFSMProtocolState(READY_STATE); 8001b1a: 2001 movs r0, #1 8001b1c: f7ff fdf6 bl 800170c <setFSMProtocolState> fillResponseFrame(SENSOR_ID, CMD_STATUS); 8001b20: 21a2 movs r1, #162 ; 0xa2 8001b22: 202c movs r0, #44 ; 0x2c 8001b24: f7ff fed4 bl 80018d0 <fillResponseFrame> break; 8001b28: e014 b.n 8001b54 <parserFSM+0x128> fillResponseFrame(STATE_ERROR, CMD_STATUS); 8001b2a: 21a2 movs r1, #162 ; 0xa2 8001b2c: 2008 movs r0, #8 8001b2e: f7ff fecf bl 80018d0 <fillResponseFrame> break; 8001b32: e00f b.n 8001b54 <parserFSM+0x128> resetSensor(); 8001b34: f000 fa6a bl 800200c <resetSensor> break; 8001b38: e00c b.n 8001b54 <parserFSM+0x128> fillResponseFrame(STATE_START_MEASURE, CMD_START_MEASURE); 8001b3a: 21a4 movs r1, #164 ; 0xa4 8001b3c: 2006 movs r0, #6 8001b3e: f7ff fec7 bl 80018d0 <fillResponseFrame> startMeasurement(); 8001b42: f000 fa83 bl 800204c <startMeasurement> setFSMProtocolState(MEASUREMENT_STATE); 8001b46: 2002 movs r0, #2 8001b48: f7ff fde0 bl 800170c <setFSMProtocolState> break; 8001b4c: e002 b.n 8001b54 <parserFSM+0x128> sendPreviousResponse(); 8001b4e: f7ff ff15 bl 800197c <sendPreviousResponse> break; 8001b52: bf00 nop break; 8001b54: e0f4 b.n 8001d40 <parserFSM+0x314> case MEASUREMENT_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8001b56: 4b73 ldr r3, [pc, #460] ; (8001d24 <parserFSM+0x2f8>) 8001b58: 789b ldrb r3, [r3, #2] 8001b5a: 2ba7 cmp r3, #167 ; 0xa7 8001b5c: dc18 bgt.n 8001b90 <parserFSM+0x164> 8001b5e: 2ba1 cmp r3, #161 ; 0xa1 8001b60: f2c0 80f0 blt.w 8001d44 <parserFSM+0x318> 8001b64: 3ba1 subs r3, #161 ; 0xa1 8001b66: 2b06 cmp r3, #6 8001b68: f200 80ec bhi.w 8001d44 <parserFSM+0x318> 8001b6c: a201 add r2, pc, #4 ; (adr r2, 8001b74 <parserFSM+0x148>) 8001b6e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001b72: bf00 nop 8001b74: 08001b97 .word 0x08001b97 8001b78: 08001ba3 .word 0x08001ba3 8001b7c: 08001bc3 .word 0x08001bc3 8001b80: 08001d45 .word 0x08001d45 8001b84: 08001d45 .word 0x08001d45 8001b88: 08001d45 .word 0x08001d45 8001b8c: 08001bc9 .word 0x08001bc9 8001b90: 2bff cmp r3, #255 ; 0xff 8001b92: d023 beq.n 8001bdc <parserFSM+0x1b0> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8001b94: e0d6 b.n 8001d44 <parserFSM+0x318> setFSMProtocolState(MEASUREMENT_EXCHANGE_STATE); 8001b96: 2004 movs r0, #4 8001b98: f7ff fdb8 bl 800170c <setFSMProtocolState> fillDataFrame(); 8001b9c: f7ff fdc6 bl 800172c <fillDataFrame> break; 8001ba0: e01f b.n 8001be2 <parserFSM+0x1b6> updateNumAvailableMeasData(); 8001ba2: f7ff fd63 bl 800166c <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8001ba6: 4b61 ldr r3, [pc, #388] ; (8001d2c <parserFSM+0x300>) 8001ba8: 795b ldrb r3, [r3, #5] 8001baa: 2b00 cmp r3, #0 8001bac: d004 beq.n 8001bb8 <parserFSM+0x18c> fillResponseFrame(STATE_READY, CMD_STATUS); 8001bae: 21a2 movs r1, #162 ; 0xa2 8001bb0: 2001 movs r0, #1 8001bb2: f7ff fe8d bl 80018d0 <fillResponseFrame> break; 8001bb6: e014 b.n 8001be2 <parserFSM+0x1b6> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 8001bb8: 21a2 movs r1, #162 ; 0xa2 8001bba: 2002 movs r0, #2 8001bbc: f7ff fe88 bl 80018d0 <fillResponseFrame> break; 8001bc0: e00f b.n 8001be2 <parserFSM+0x1b6> resetSensor(); 8001bc2: f000 fa23 bl 800200c <resetSensor> break; 8001bc6: e00c b.n 8001be2 <parserFSM+0x1b6> stopMeasurement(); 8001bc8: f000 fa4c bl 8002064 <stopMeasurement> fillResponseFrame(STATE_STOP_MEASURE, CMD_STOP_MEASURE); 8001bcc: 21a7 movs r1, #167 ; 0xa7 8001bce: 2007 movs r0, #7 8001bd0: f7ff fe7e bl 80018d0 <fillResponseFrame> setFSMProtocolState(READY_STATE); 8001bd4: 2001 movs r0, #1 8001bd6: f7ff fd99 bl 800170c <setFSMProtocolState> break; 8001bda: e002 b.n 8001be2 <parserFSM+0x1b6> sendPreviousResponse(); 8001bdc: f7ff fece bl 800197c <sendPreviousResponse> break; 8001be0: bf00 nop break; 8001be2: e0af b.n 8001d44 <parserFSM+0x318> case EXCHANGE_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8001be4: 4b4f ldr r3, [pc, #316] ; (8001d24 <parserFSM+0x2f8>) 8001be6: 789b ldrb r3, [r3, #2] 8001be8: 2ba4 cmp r3, #164 ; 0xa4 8001bea: dc11 bgt.n 8001c10 <parserFSM+0x1e4> 8001bec: 2ba1 cmp r3, #161 ; 0xa1 8001bee: f2c0 80ab blt.w 8001d48 <parserFSM+0x31c> 8001bf2: 3ba1 subs r3, #161 ; 0xa1 8001bf4: 2b03 cmp r3, #3 8001bf6: f200 80a7 bhi.w 8001d48 <parserFSM+0x31c> 8001bfa: a201 add r2, pc, #4 ; (adr r2, 8001c00 <parserFSM+0x1d4>) 8001bfc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001c00: 08001c17 .word 0x08001c17 8001c04: 08001c1d .word 0x08001c1d 8001c08: 08001c43 .word 0x08001c43 8001c0c: 08001c49 .word 0x08001c49 8001c10: 2bff cmp r3, #255 ; 0xff 8001c12: d023 beq.n 8001c5c <parserFSM+0x230> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8001c14: e098 b.n 8001d48 <parserFSM+0x31c> fillDataFrame(); 8001c16: f7ff fd89 bl 800172c <fillDataFrame> break; 8001c1a: e022 b.n 8001c62 <parserFSM+0x236> updateNumAvailableMeasData(); 8001c1c: f7ff fd26 bl 800166c <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8001c20: 4b42 ldr r3, [pc, #264] ; (8001d2c <parserFSM+0x300>) 8001c22: 795b ldrb r3, [r3, #5] 8001c24: 2b00 cmp r3, #0 8001c26: d004 beq.n 8001c32 <parserFSM+0x206> fillResponseFrame(STATE_READY, CMD_STATUS); 8001c28: 21a2 movs r1, #162 ; 0xa2 8001c2a: 2001 movs r0, #1 8001c2c: f7ff fe50 bl 80018d0 <fillResponseFrame> break; 8001c30: e017 b.n 8001c62 <parserFSM+0x236> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 8001c32: 21a2 movs r1, #162 ; 0xa2 8001c34: 2002 movs r0, #2 8001c36: f7ff fe4b bl 80018d0 <fillResponseFrame> setFSMProtocolState(READY_STATE); 8001c3a: 2001 movs r0, #1 8001c3c: f7ff fd66 bl 800170c <setFSMProtocolState> break; 8001c40: e00f b.n 8001c62 <parserFSM+0x236> resetSensor(); 8001c42: f000 f9e3 bl 800200c <resetSensor> break; 8001c46: e00c b.n 8001c62 <parserFSM+0x236> fillResponseFrame(STATE_START_MEASURE, CMD_START_MEASURE); 8001c48: 21a4 movs r1, #164 ; 0xa4 8001c4a: 2006 movs r0, #6 8001c4c: f7ff fe40 bl 80018d0 <fillResponseFrame> startMeasurement(); 8001c50: f000 f9fc bl 800204c <startMeasurement> setFSMProtocolState(MEASUREMENT_EXCHANGE_STATE); 8001c54: 2004 movs r0, #4 8001c56: f7ff fd59 bl 800170c <setFSMProtocolState> break; 8001c5a: e002 b.n 8001c62 <parserFSM+0x236> sendPreviousResponse(); 8001c5c: f7ff fe8e bl 800197c <sendPreviousResponse> break; 8001c60: bf00 nop break; 8001c62: e071 b.n 8001d48 <parserFSM+0x31c> case MEASUREMENT_EXCHANGE_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8001c64: 4b2f ldr r3, [pc, #188] ; (8001d24 <parserFSM+0x2f8>) 8001c66: 789b ldrb r3, [r3, #2] 8001c68: 2ba7 cmp r3, #167 ; 0xa7 8001c6a: dc15 bgt.n 8001c98 <parserFSM+0x26c> 8001c6c: 2ba1 cmp r3, #161 ; 0xa1 8001c6e: db6d blt.n 8001d4c <parserFSM+0x320> 8001c70: 3ba1 subs r3, #161 ; 0xa1 8001c72: 2b06 cmp r3, #6 8001c74: d86a bhi.n 8001d4c <parserFSM+0x320> 8001c76: a201 add r2, pc, #4 ; (adr r2, 8001c7c <parserFSM+0x250>) 8001c78: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001c7c: 08001c9f .word 0x08001c9f 8001c80: 08001ca5 .word 0x08001ca5 8001c84: 08001ccb .word 0x08001ccb 8001c88: 08001d4d .word 0x08001d4d 8001c8c: 08001d4d .word 0x08001d4d 8001c90: 08001d4d .word 0x08001d4d 8001c94: 08001cd1 .word 0x08001cd1 8001c98: 2bff cmp r3, #255 ; 0xff 8001c9a: d023 beq.n 8001ce4 <parserFSM+0x2b8> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8001c9c: e056 b.n 8001d4c <parserFSM+0x320> fillDataFrame(); 8001c9e: f7ff fd45 bl 800172c <fillDataFrame> break; 8001ca2: e022 b.n 8001cea <parserFSM+0x2be> updateNumAvailableMeasData(); 8001ca4: f7ff fce2 bl 800166c <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8001ca8: 4b20 ldr r3, [pc, #128] ; (8001d2c <parserFSM+0x300>) 8001caa: 795b ldrb r3, [r3, #5] 8001cac: 2b00 cmp r3, #0 8001cae: d004 beq.n 8001cba <parserFSM+0x28e> fillResponseFrame(STATE_READY, CMD_STATUS); 8001cb0: 21a2 movs r1, #162 ; 0xa2 8001cb2: 2001 movs r0, #1 8001cb4: f7ff fe0c bl 80018d0 <fillResponseFrame> break; 8001cb8: e017 b.n 8001cea <parserFSM+0x2be> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 8001cba: 21a2 movs r1, #162 ; 0xa2 8001cbc: 2002 movs r0, #2 8001cbe: f7ff fe07 bl 80018d0 <fillResponseFrame> setFSMProtocolState(MEASUREMENT_STATE); 8001cc2: 2002 movs r0, #2 8001cc4: f7ff fd22 bl 800170c <setFSMProtocolState> break; 8001cc8: e00f b.n 8001cea <parserFSM+0x2be> resetSensor(); 8001cca: f000 f99f bl 800200c <resetSensor> break; 8001cce: e00c b.n 8001cea <parserFSM+0x2be> stopMeasurement(); 8001cd0: f000 f9c8 bl 8002064 <stopMeasurement> fillResponseFrame(STATE_STOP_MEASURE, CMD_STOP_MEASURE); 8001cd4: 21a7 movs r1, #167 ; 0xa7 8001cd6: 2007 movs r0, #7 8001cd8: f7ff fdfa bl 80018d0 <fillResponseFrame> setFSMProtocolState(EXCHANGE_STATE); 8001cdc: 2003 movs r0, #3 8001cde: f7ff fd15 bl 800170c <setFSMProtocolState> break; 8001ce2: e002 b.n 8001cea <parserFSM+0x2be> sendPreviousResponse(); 8001ce4: f7ff fe4a bl 800197c <sendPreviousResponse> break; 8001ce8: bf00 nop break; 8001cea: e02f b.n 8001d4c <parserFSM+0x320> case RESET_STATE: if(safe_command_frame[2] == CMD_STATUS) { 8001cec: 4b0d ldr r3, [pc, #52] ; (8001d24 <parserFSM+0x2f8>) 8001cee: 789b ldrb r3, [r3, #2] 8001cf0: 2ba2 cmp r3, #162 ; 0xa2 8001cf2: d12c bne.n 8001d4e <parserFSM+0x322> if (reset_ready) { 8001cf4: 4b0e ldr r3, [pc, #56] ; (8001d30 <parserFSM+0x304>) 8001cf6: 781b ldrb r3, [r3, #0] 8001cf8: 2b00 cmp r3, #0 8001cfa: d00f beq.n 8001d1c <parserFSM+0x2f0> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET); 8001cfc: 2200 movs r2, #0 8001cfe: 2104 movs r1, #4 8001d00: 480c ldr r0, [pc, #48] ; (8001d34 <parserFSM+0x308>) 8001d02: f001 fcec bl 80036de <HAL_GPIO_WritePin> fillResponseFrame(STATE_RESET, CMD_RESET); 8001d06: 21a3 movs r1, #163 ; 0xa3 8001d08: 2005 movs r0, #5 8001d0a: f7ff fde1 bl 80018d0 <fillResponseFrame> setFSMProtocolState(CONNECTED_STATE); 8001d0e: 2000 movs r0, #0 8001d10: f7ff fcfc bl 800170c <setFSMProtocolState> reset_ready = 0; 8001d14: 4b06 ldr r3, [pc, #24] ; (8001d30 <parserFSM+0x304>) 8001d16: 2200 movs r2, #0 8001d18: 701a strb r2, [r3, #0] 8001d1a: e018 b.n 8001d4e <parserFSM+0x322> } else { response_ready = 0; 8001d1c: 4b06 ldr r3, [pc, #24] ; (8001d38 <parserFSM+0x30c>) 8001d1e: 2200 movs r2, #0 8001d20: 701a strb r2, [r3, #0] 8001d22: e014 b.n 8001d4e <parserFSM+0x322> 8001d24: 200001f0 .word 0x200001f0 8001d28: 200009f4 .word 0x200009f4 8001d2c: 20000028 .word 0x20000028 8001d30: 200009f5 .word 0x200009f5 8001d34: 40010800 .word 0x40010800 8001d38: 200000e5 .word 0x200000e5 break; 8001d3c: bf00 nop 8001d3e: e006 b.n 8001d4e <parserFSM+0x322> break; 8001d40: bf00 nop 8001d42: e004 b.n 8001d4e <parserFSM+0x322> break; 8001d44: bf00 nop 8001d46: e002 b.n 8001d4e <parserFSM+0x322> break; 8001d48: bf00 nop 8001d4a: e000 b.n 8001d4e <parserFSM+0x322> break; 8001d4c: bf00 nop } } } }; 8001d4e: bd80 pop {r7, pc} 08001d50 <checkCRC32>: bool checkCRC32(uint8_t* command_frame, uint16_t length) { 8001d50: b580 push {r7, lr} 8001d52: b084 sub sp, #16 8001d54: af00 add r7, sp, #0 8001d56: 6078 str r0, [r7, #4] 8001d58: 460b mov r3, r1 8001d5a: 807b strh r3, [r7, #2] // получение CRC полученного кадра uint32_t command_crc = (uint32_t)command_frame[263] | 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: f203 1307 addw r3, r3, #263 ; 0x107 8001d62: 781b ldrb r3, [r3, #0] 8001d64: 461a mov r2, r3 ((uint32_t)command_frame[262] << 8) | 8001d66: 687b ldr r3, [r7, #4] 8001d68: f503 7383 add.w r3, r3, #262 ; 0x106 8001d6c: 781b ldrb r3, [r3, #0] 8001d6e: 021b lsls r3, r3, #8 uint32_t command_crc = (uint32_t)command_frame[263] | 8001d70: 431a orrs r2, r3 ((uint32_t)command_frame[261] << 16) | 8001d72: 687b ldr r3, [r7, #4] 8001d74: f203 1305 addw r3, r3, #261 ; 0x105 8001d78: 781b ldrb r3, [r3, #0] 8001d7a: 041b lsls r3, r3, #16 ((uint32_t)command_frame[262] << 8) | 8001d7c: 431a orrs r2, r3 ((uint32_t)command_frame[260] << 24); 8001d7e: 687b ldr r3, [r7, #4] 8001d80: f503 7382 add.w r3, r3, #260 ; 0x104 8001d84: 781b ldrb r3, [r3, #0] 8001d86: 061b lsls r3, r3, #24 uint32_t command_crc = (uint32_t)command_frame[263] | 8001d88: 4313 orrs r3, r2 8001d8a: 60fb str r3, [r7, #12] // расчет ожидаемой CRC для полученного кадра uint32_t calc_crc = calculateCRC32(command_frame, FRAME_LEN-4); 8001d8c: f44f 7182 mov.w r1, #260 ; 0x104 8001d90: 6878 ldr r0, [r7, #4] 8001d92: f000 f80d bl 8001db0 <calculateCRC32> 8001d96: 60b8 str r0, [r7, #8] // сравнение полученной и ожидаемой CRC if (command_crc != calc_crc) { 8001d98: 68fa ldr r2, [r7, #12] 8001d9a: 68bb ldr r3, [r7, #8] 8001d9c: 429a cmp r2, r3 8001d9e: d001 beq.n 8001da4 <checkCRC32+0x54> return false; 8001da0: 2300 movs r3, #0 8001da2: e000 b.n 8001da6 <checkCRC32+0x56> } else { return true; 8001da4: 2301 movs r3, #1 } }; 8001da6: 4618 mov r0, r3 8001da8: 3710 adds r7, #16 8001daa: 46bd mov sp, r7 8001dac: bd80 pop {r7, pc} ... 08001db0 <calculateCRC32>: uint32_t calculateCRC32(uint8_t* arg,uint16_t length) { 8001db0: b480 push {r7} 8001db2: b085 sub sp, #20 8001db4: af00 add r7, sp, #0 8001db6: 6078 str r0, [r7, #4] 8001db8: 460b mov r3, r1 8001dba: 807b strh r3, [r7, #2] uint32_t crc_f = 0xFFFFFFFF; // Начальное значение CRC 8001dbc: f04f 33ff mov.w r3, #4294967295 8001dc0: 60fb str r3, [r7, #12] for (int i=0;i<length;i++) 8001dc2: 2300 movs r3, #0 8001dc4: 60bb str r3, [r7, #8] 8001dc6: e011 b.n 8001dec <calculateCRC32+0x3c> {crc_f=crc32_table[(crc_f ^ arg[i]) & 0xFF] ^ (crc_f >> 8);} 8001dc8: 68bb ldr r3, [r7, #8] 8001dca: 687a ldr r2, [r7, #4] 8001dcc: 4413 add r3, r2 8001dce: 781b ldrb r3, [r3, #0] 8001dd0: 461a mov r2, r3 8001dd2: 68fb ldr r3, [r7, #12] 8001dd4: 4053 eors r3, r2 8001dd6: b2db uxtb r3, r3 8001dd8: 4a0a ldr r2, [pc, #40] ; (8001e04 <calculateCRC32+0x54>) 8001dda: f852 2023 ldr.w r2, [r2, r3, lsl #2] 8001dde: 68fb ldr r3, [r7, #12] 8001de0: 0a1b lsrs r3, r3, #8 8001de2: 4053 eors r3, r2 8001de4: 60fb str r3, [r7, #12] for (int i=0;i<length;i++) 8001de6: 68bb ldr r3, [r7, #8] 8001de8: 3301 adds r3, #1 8001dea: 60bb str r3, [r7, #8] 8001dec: 887b ldrh r3, [r7, #2] 8001dee: 68ba ldr r2, [r7, #8] 8001df0: 429a cmp r2, r3 8001df2: dbe9 blt.n 8001dc8 <calculateCRC32+0x18> return ~crc_f; 8001df4: 68fb ldr r3, [r7, #12] 8001df6: 43db mvns r3, r3 } 8001df8: 4618 mov r0, r3 8001dfa: 3714 adds r7, #20 8001dfc: 46bd mov sp, r7 8001dfe: bc80 pop {r7} 8001e00: 4770 bx lr 8001e02: bf00 nop 8001e04: 080076e0 .word 0x080076e0 08001e08 <sensorInit>: /* Инициализация датчика при его подключении */ void sensorInit() { 8001e08: b580 push {r7, lr} 8001e0a: af00 add r7, sp, #0 // инициализация флеш-памяти W25_Ini(0); 8001e0c: 2000 movs r0, #0 8001e0e: f004 fbdf bl 80065d0 <W25_Ini> // инициализация SPI-соединения initSPIConnection(); 8001e12: f7fe ffdb bl 8000dcc <initSPIConnection> // включение таймера формирования сигнала CTRL HAL_TIM_OnePulse_Start(&htim2, TIM_CHANNEL_1); 8001e16: 2100 movs r1, #0 8001e18: 4806 ldr r0, [pc, #24] ; (8001e34 <sensorInit+0x2c>) 8001e1a: f003 fbc7 bl 80055ac <HAL_TIM_OnePulse_Start> // задержка для удержания линии в активном уровне HAL_Delay(1); 8001e1e: 2001 movs r0, #1 8001e20: f000 fc08 bl 8002634 <HAL_Delay> // отправка сигнала на CTRL для уведомления мастера о подключении датчика sendInitCTRL(); 8001e24: f000 f808 bl 8001e38 <sendInitCTRL> // установка состояния датчика "датчик подключен" setFSMProtocolState(CONNECTED_STATE); 8001e28: 2000 movs r0, #0 8001e2a: f7ff fc6f bl 800170c <setFSMProtocolState> } 8001e2e: bf00 nop 8001e30: bd80 pop {r7, pc} 8001e32: bf00 nop 8001e34: 200006fc .word 0x200006fc 08001e38 <sendInitCTRL>: /* Формирует сигнал CTRL для уведомления мастера о подключении датчика */ void sendInitCTRL() { 8001e38: b480 push {r7} 8001e3a: af00 add r7, sp, #0 __HAL_TIM_ENABLE(&htim2); 8001e3c: 4b05 ldr r3, [pc, #20] ; (8001e54 <sendInitCTRL+0x1c>) 8001e3e: 681b ldr r3, [r3, #0] 8001e40: 681a ldr r2, [r3, #0] 8001e42: 4b04 ldr r3, [pc, #16] ; (8001e54 <sendInitCTRL+0x1c>) 8001e44: 681b ldr r3, [r3, #0] 8001e46: f042 0201 orr.w r2, r2, #1 8001e4a: 601a str r2, [r3, #0] return; 8001e4c: bf00 nop } 8001e4e: 46bd mov sp, r7 8001e50: bc80 pop {r7} 8001e52: 4770 bx lr 8001e54: 200006fc .word 0x200006fc 08001e58 <sendRxCompleteCTRL>: /* Формирует сигнал CTRL для уведомления мастера о получении команды */ void sendRxCompleteCTRL() { 8001e58: b480 push {r7} 8001e5a: af00 add r7, sp, #0 __HAL_TIM_ENABLE(&htim2); 8001e5c: 4b05 ldr r3, [pc, #20] ; (8001e74 <sendRxCompleteCTRL+0x1c>) 8001e5e: 681b ldr r3, [r3, #0] 8001e60: 681a ldr r2, [r3, #0] 8001e62: 4b04 ldr r3, [pc, #16] ; (8001e74 <sendRxCompleteCTRL+0x1c>) 8001e64: 681b ldr r3, [r3, #0] 8001e66: f042 0201 orr.w r2, r2, #1 8001e6a: 601a str r2, [r3, #0] return; 8001e6c: bf00 nop } 8001e6e: 46bd mov sp, r7 8001e70: bc80 pop {r7} 8001e72: 4770 bx lr 8001e74: 200006fc .word 0x200006fc 08001e78 <resetFSMProtocol>: void resetFSMProtocol() { 8001e78: b580 push {r7, lr} 8001e7a: af00 add r7, sp, #0 setFSMProtocolState(RESET_STATE); 8001e7c: 2005 movs r0, #5 8001e7e: f7ff fc45 bl 800170c <setFSMProtocolState> read.cur_page_num = 0; 8001e82: 4b07 ldr r3, [pc, #28] ; (8001ea0 <resetFSMProtocol+0x28>) 8001e84: 2200 movs r2, #0 8001e86: 601a str r2, [r3, #0] read.page_offset_read = -1; 8001e88: 4b05 ldr r3, [pc, #20] ; (8001ea0 <resetFSMProtocol+0x28>) 8001e8a: 22ff movs r2, #255 ; 0xff 8001e8c: 711a strb r2, [r3, #4] read.num_ready_bytes = 0; 8001e8e: 4b04 ldr r3, [pc, #16] ; (8001ea0 <resetFSMProtocol+0x28>) 8001e90: 2200 movs r2, #0 8001e92: 715a strb r2, [r3, #5] response_ready = 0; 8001e94: 4b03 ldr r3, [pc, #12] ; (8001ea4 <resetFSMProtocol+0x2c>) 8001e96: 2200 movs r2, #0 8001e98: 701a strb r2, [r3, #0] } 8001e9a: bf00 nop 8001e9c: bd80 pop {r7, pc} 8001e9e: bf00 nop 8001ea0: 20000028 .word 0x20000028 8001ea4: 200000e5 .word 0x200000e5 08001ea8 <getTempVal>: bool need_selfcheck = 0; static float Krt_r25[10] = {4.232, 3.265, 2.539, 1.99, 1.571, 1.249, 1.0, 0.8057, 0.6531, 0.5327}; float temp_val = 0; float getTempVal() { 8001ea8: b590 push {r4, r7, lr} 8001eaa: b087 sub sp, #28 8001eac: af00 add r7, sp, #0 float RT_R25 = (float)(ADC_data_safe)/(float)(4095-ADC_data_safe); //R_t/R25 8001eae: 4b35 ldr r3, [pc, #212] ; (8001f84 <getTempVal+0xdc>) 8001eb0: 881b ldrh r3, [r3, #0] 8001eb2: b29b uxth r3, r3 8001eb4: 4618 mov r0, r3 8001eb6: f7fe fd0d bl 80008d4 <__aeabi_ui2f> 8001eba: 4604 mov r4, r0 8001ebc: 4b31 ldr r3, [pc, #196] ; (8001f84 <getTempVal+0xdc>) 8001ebe: 881b ldrh r3, [r3, #0] 8001ec0: b29b uxth r3, r3 8001ec2: f5c3 637f rsb r3, r3, #4080 ; 0xff0 8001ec6: 330f adds r3, #15 8001ec8: 4618 mov r0, r3 8001eca: f7fe fd07 bl 80008dc <__aeabi_i2f> 8001ece: 4603 mov r3, r0 8001ed0: 4619 mov r1, r3 8001ed2: 4620 mov r0, r4 8001ed4: f7fe fe0a bl 8000aec <__aeabi_fdiv> 8001ed8: 4603 mov r3, r0 8001eda: 60fb str r3, [r7, #12] float t = 0; 8001edc: f04f 0300 mov.w r3, #0 8001ee0: 617b str r3, [r7, #20] for ( int i = 9; i >= 0; i-- ) 8001ee2: 2309 movs r3, #9 8001ee4: 613b str r3, [r7, #16] 8001ee6: e045 b.n 8001f74 <getTempVal+0xcc> { if ( Krt_r25[i] >= RT_R25 ) //we are in true band 8001ee8: 4a27 ldr r2, [pc, #156] ; (8001f88 <getTempVal+0xe0>) 8001eea: 693b ldr r3, [r7, #16] 8001eec: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001ef0: 4619 mov r1, r3 8001ef2: 68f8 ldr r0, [r7, #12] 8001ef4: f7fe feee bl 8000cd4 <__aeabi_fcmple> 8001ef8: 4603 mov r3, r0 8001efa: 2b00 cmp r3, #0 8001efc: d037 beq.n 8001f6e <getTempVal+0xc6> { float tga = 5/(Krt_r25[i+1] - Krt_r25[i]); //k = calc td(a) 8001efe: 693b ldr r3, [r7, #16] 8001f00: 3301 adds r3, #1 8001f02: 4a21 ldr r2, [pc, #132] ; (8001f88 <getTempVal+0xe0>) 8001f04: f852 2023 ldr.w r2, [r2, r3, lsl #2] 8001f08: 491f ldr r1, [pc, #124] ; (8001f88 <getTempVal+0xe0>) 8001f0a: 693b ldr r3, [r7, #16] 8001f0c: f851 3023 ldr.w r3, [r1, r3, lsl #2] 8001f10: 4619 mov r1, r3 8001f12: 4610 mov r0, r2 8001f14: f7fe fc2c bl 8000770 <__aeabi_fsub> 8001f18: 4603 mov r3, r0 8001f1a: 4619 mov r1, r3 8001f1c: 481b ldr r0, [pc, #108] ; (8001f8c <getTempVal+0xe4>) 8001f1e: f7fe fde5 bl 8000aec <__aeabi_fdiv> 8001f22: 4603 mov r3, r0 8001f24: 60bb str r3, [r7, #8] float b = (i-1)*5 - tga*Krt_r25[i]; // calc b = offset 8001f26: 693b ldr r3, [r7, #16] 8001f28: 1e5a subs r2, r3, #1 8001f2a: 4613 mov r3, r2 8001f2c: 009b lsls r3, r3, #2 8001f2e: 4413 add r3, r2 8001f30: 4618 mov r0, r3 8001f32: f7fe fcd3 bl 80008dc <__aeabi_i2f> 8001f36: 4604 mov r4, r0 8001f38: 4a13 ldr r2, [pc, #76] ; (8001f88 <getTempVal+0xe0>) 8001f3a: 693b ldr r3, [r7, #16] 8001f3c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001f40: 68b9 ldr r1, [r7, #8] 8001f42: 4618 mov r0, r3 8001f44: f7fe fd1e bl 8000984 <__aeabi_fmul> 8001f48: 4603 mov r3, r0 8001f4a: 4619 mov r1, r3 8001f4c: 4620 mov r0, r4 8001f4e: f7fe fc0f bl 8000770 <__aeabi_fsub> 8001f52: 4603 mov r3, r0 8001f54: 607b str r3, [r7, #4] t = tga * RT_R25 + b; 8001f56: 68f9 ldr r1, [r7, #12] 8001f58: 68b8 ldr r0, [r7, #8] 8001f5a: f7fe fd13 bl 8000984 <__aeabi_fmul> 8001f5e: 4603 mov r3, r0 8001f60: 4619 mov r1, r3 8001f62: 6878 ldr r0, [r7, #4] 8001f64: f7fe fc06 bl 8000774 <__addsf3> 8001f68: 4603 mov r3, r0 8001f6a: 617b str r3, [r7, #20] break; 8001f6c: e005 b.n 8001f7a <getTempVal+0xd2> for ( int i = 9; i >= 0; i-- ) 8001f6e: 693b ldr r3, [r7, #16] 8001f70: 3b01 subs r3, #1 8001f72: 613b str r3, [r7, #16] 8001f74: 693b ldr r3, [r7, #16] 8001f76: 2b00 cmp r3, #0 8001f78: dab6 bge.n 8001ee8 <getTempVal+0x40> } } return t; 8001f7a: 697b ldr r3, [r7, #20] } 8001f7c: 4618 mov r0, r3 8001f7e: 371c adds r7, #28 8001f80: 46bd mov sp, r7 8001f82: bd90 pop {r4, r7, pc} 8001f84: 200009f6 .word 0x200009f6 8001f88: 20000030 .word 0x20000030 8001f8c: 40a00000 .word 0x40a00000 08001f90 <sensorSelfCheck>: /* Выполняет проверку работоспособности датчика * Возврат: 1 - датчик работоспособен * 0 - датчик не работоспособен */ bool sensorSelfCheck() { 8001f90: b580 push {r7, lr} 8001f92: af00 add r7, sp, #0 #ifdef TEST_VERSION return true; #endif // устанавливаем блокировку от перезаписи последнего полученного значения АЦП need_selfcheck = 1; 8001f94: 4b18 ldr r3, [pc, #96] ; (8001ff8 <sensorSelfCheck+0x68>) 8001f96: 2201 movs r2, #1 8001f98: 701a strb r2, [r3, #0] // проверка на работоспособность АЦП if (ADC_data_safe == 4095) { 8001f9a: 4b18 ldr r3, [pc, #96] ; (8001ffc <sensorSelfCheck+0x6c>) 8001f9c: 881b ldrh r3, [r3, #0] 8001f9e: b29b uxth r3, r3 8001fa0: f640 72ff movw r2, #4095 ; 0xfff 8001fa4: 4293 cmp r3, r2 8001fa6: d104 bne.n 8001fb2 <sensorSelfCheck+0x22> need_selfcheck = 0; 8001fa8: 4b13 ldr r3, [pc, #76] ; (8001ff8 <sensorSelfCheck+0x68>) 8001faa: 2200 movs r2, #0 8001fac: 701a strb r2, [r3, #0] return false; 8001fae: 2300 movs r3, #0 8001fb0: e01f b.n 8001ff2 <sensorSelfCheck+0x62> } temp_val = getTempVal(); 8001fb2: f7ff ff79 bl 8001ea8 <getTempVal> 8001fb6: 4603 mov r3, r0 8001fb8: 4a11 ldr r2, [pc, #68] ; (8002000 <sensorSelfCheck+0x70>) 8001fba: 6013 str r3, [r2, #0] if (temp_val < 30.0f || temp_val > 50.0f) { 8001fbc: 4b10 ldr r3, [pc, #64] ; (8002000 <sensorSelfCheck+0x70>) 8001fbe: 681b ldr r3, [r3, #0] 8001fc0: 4910 ldr r1, [pc, #64] ; (8002004 <sensorSelfCheck+0x74>) 8001fc2: 4618 mov r0, r3 8001fc4: f7fe fe7c bl 8000cc0 <__aeabi_fcmplt> 8001fc8: 4603 mov r3, r0 8001fca: 2b00 cmp r3, #0 8001fcc: d108 bne.n 8001fe0 <sensorSelfCheck+0x50> 8001fce: 4b0c ldr r3, [pc, #48] ; (8002000 <sensorSelfCheck+0x70>) 8001fd0: 681b ldr r3, [r3, #0] 8001fd2: 490d ldr r1, [pc, #52] ; (8002008 <sensorSelfCheck+0x78>) 8001fd4: 4618 mov r0, r3 8001fd6: f7fe fe91 bl 8000cfc <__aeabi_fcmpgt> 8001fda: 4603 mov r3, r0 8001fdc: 2b00 cmp r3, #0 8001fde: d004 beq.n 8001fea <sensorSelfCheck+0x5a> need_selfcheck = 0; 8001fe0: 4b05 ldr r3, [pc, #20] ; (8001ff8 <sensorSelfCheck+0x68>) 8001fe2: 2200 movs r2, #0 8001fe4: 701a strb r2, [r3, #0] return false; 8001fe6: 2300 movs r3, #0 8001fe8: e003 b.n 8001ff2 <sensorSelfCheck+0x62> } need_selfcheck = 0; 8001fea: 4b03 ldr r3, [pc, #12] ; (8001ff8 <sensorSelfCheck+0x68>) 8001fec: 2200 movs r2, #0 8001fee: 701a strb r2, [r3, #0] return true; 8001ff0: 2301 movs r3, #1 } 8001ff2: 4618 mov r0, r3 8001ff4: bd80 pop {r7, pc} 8001ff6: bf00 nop 8001ff8: 200009f8 .word 0x200009f8 8001ffc: 200009f6 .word 0x200009f6 8002000: 200009fc .word 0x200009fc 8002004: 41f00000 .word 0x41f00000 8002008: 42480000 .word 0x42480000 0800200c <resetSensor>: /* Выполняет сброс датчика */ void resetSensor() { 800200c: b580 push {r7, lr} 800200e: af00 add r7, sp, #0 stopMeasurement(); 8002010: f000 f828 bl 8002064 <stopMeasurement> // сброс внутреннего состояния датчика resetFSMProtocol(); 8002014: f7ff ff30 bl 8001e78 <resetFSMProtocol> // сброс переменных page_pos_ptr = 0; 8002018: 4b08 ldr r3, [pc, #32] ; (800203c <resetSensor+0x30>) 800201a: 2200 movs r2, #0 800201c: 701a strb r2, [r3, #0] page_ptr = 0; 800201e: 4b08 ldr r3, [pc, #32] ; (8002040 <resetSensor+0x34>) 8002020: 2200 movs r2, #0 8002022: 801a strh r2, [r3, #0] // очистка флеш-памяти HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8002024: 2201 movs r2, #1 8002026: 2104 movs r1, #4 8002028: 4806 ldr r0, [pc, #24] ; (8002044 <resetSensor+0x38>) 800202a: f001 fb58 bl 80036de <HAL_GPIO_WritePin> W25_Erase_Chip(); 800202e: f004 fa03 bl 8006438 <W25_Erase_Chip> reset_ready = true; 8002032: 4b05 ldr r3, [pc, #20] ; (8002048 <resetSensor+0x3c>) 8002034: 2201 movs r2, #1 8002036: 701a strb r2, [r3, #0] // сброс SPI-соединения с мастером //resetSPIConnection(); return; 8002038: bf00 nop } 800203a: bd80 pop {r7, pc} 800203c: 200008d5 .word 0x200008d5 8002040: 200008d2 .word 0x200008d2 8002044: 40010800 .word 0x40010800 8002048: 200009f5 .word 0x200009f5 0800204c <startMeasurement>: /* Запуск измерения */ void startMeasurement() { 800204c: b480 push {r7} 800204e: af00 add r7, sp, #0 dt1[0] = '1'; 8002050: 4b03 ldr r3, [pc, #12] ; (8002060 <startMeasurement+0x14>) 8002052: 2231 movs r2, #49 ; 0x31 8002054: 701a strb r2, [r3, #0] return; 8002056: bf00 nop } 8002058: 46bd mov sp, r7 800205a: bc80 pop {r7} 800205c: 4770 bx lr 800205e: bf00 nop 8002060: 200008d8 .word 0x200008d8 08002064 <stopMeasurement>: /* Остановка измерения */ void stopMeasurement() { 8002064: b480 push {r7} 8002066: af00 add r7, sp, #0 dt1[0] = '2'; 8002068: 4b03 ldr r3, [pc, #12] ; (8002078 <stopMeasurement+0x14>) 800206a: 2232 movs r2, #50 ; 0x32 800206c: 701a strb r2, [r3, #0] return; 800206e: bf00 nop } 8002070: 46bd mov sp, r7 8002072: bc80 pop {r7} 8002074: 4770 bx lr 8002076: bf00 nop 8002078: 200008d8 .word 0x200008d8 0800207c <HAL_MspInit>: void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800207c: b480 push {r7} 800207e: b085 sub sp, #20 8002080: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8002082: 4b15 ldr r3, [pc, #84] ; (80020d8 <HAL_MspInit+0x5c>) 8002084: 699b ldr r3, [r3, #24] 8002086: 4a14 ldr r2, [pc, #80] ; (80020d8 <HAL_MspInit+0x5c>) 8002088: f043 0301 orr.w r3, r3, #1 800208c: 6193 str r3, [r2, #24] 800208e: 4b12 ldr r3, [pc, #72] ; (80020d8 <HAL_MspInit+0x5c>) 8002090: 699b ldr r3, [r3, #24] 8002092: f003 0301 and.w r3, r3, #1 8002096: 60bb str r3, [r7, #8] 8002098: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800209a: 4b0f ldr r3, [pc, #60] ; (80020d8 <HAL_MspInit+0x5c>) 800209c: 69db ldr r3, [r3, #28] 800209e: 4a0e ldr r2, [pc, #56] ; (80020d8 <HAL_MspInit+0x5c>) 80020a0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80020a4: 61d3 str r3, [r2, #28] 80020a6: 4b0c ldr r3, [pc, #48] ; (80020d8 <HAL_MspInit+0x5c>) 80020a8: 69db ldr r3, [r3, #28] 80020aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80020ae: 607b str r3, [r7, #4] 80020b0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80020b2: 4b0a ldr r3, [pc, #40] ; (80020dc <HAL_MspInit+0x60>) 80020b4: 685b ldr r3, [r3, #4] 80020b6: 60fb str r3, [r7, #12] 80020b8: 68fb ldr r3, [r7, #12] 80020ba: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80020be: 60fb str r3, [r7, #12] 80020c0: 68fb ldr r3, [r7, #12] 80020c2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80020c6: 60fb str r3, [r7, #12] 80020c8: 4a04 ldr r2, [pc, #16] ; (80020dc <HAL_MspInit+0x60>) 80020ca: 68fb ldr r3, [r7, #12] 80020cc: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80020ce: bf00 nop 80020d0: 3714 adds r7, #20 80020d2: 46bd mov sp, r7 80020d4: bc80 pop {r7} 80020d6: 4770 bx lr 80020d8: 40021000 .word 0x40021000 80020dc: 40010000 .word 0x40010000 080020e0 <HAL_ADC_MspInit>: * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80020e0: b580 push {r7, lr} 80020e2: b088 sub sp, #32 80020e4: af00 add r7, sp, #0 80020e6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80020e8: f107 0310 add.w r3, r7, #16 80020ec: 2200 movs r2, #0 80020ee: 601a str r2, [r3, #0] 80020f0: 605a str r2, [r3, #4] 80020f2: 609a str r2, [r3, #8] 80020f4: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 80020f6: 687b ldr r3, [r7, #4] 80020f8: 681b ldr r3, [r3, #0] 80020fa: 4a18 ldr r2, [pc, #96] ; (800215c <HAL_ADC_MspInit+0x7c>) 80020fc: 4293 cmp r3, r2 80020fe: d129 bne.n 8002154 <HAL_ADC_MspInit+0x74> { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8002100: 4b17 ldr r3, [pc, #92] ; (8002160 <HAL_ADC_MspInit+0x80>) 8002102: 699b ldr r3, [r3, #24] 8002104: 4a16 ldr r2, [pc, #88] ; (8002160 <HAL_ADC_MspInit+0x80>) 8002106: f443 7300 orr.w r3, r3, #512 ; 0x200 800210a: 6193 str r3, [r2, #24] 800210c: 4b14 ldr r3, [pc, #80] ; (8002160 <HAL_ADC_MspInit+0x80>) 800210e: 699b ldr r3, [r3, #24] 8002110: f403 7300 and.w r3, r3, #512 ; 0x200 8002114: 60fb str r3, [r7, #12] 8002116: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002118: 4b11 ldr r3, [pc, #68] ; (8002160 <HAL_ADC_MspInit+0x80>) 800211a: 699b ldr r3, [r3, #24] 800211c: 4a10 ldr r2, [pc, #64] ; (8002160 <HAL_ADC_MspInit+0x80>) 800211e: f043 0304 orr.w r3, r3, #4 8002122: 6193 str r3, [r2, #24] 8002124: 4b0e ldr r3, [pc, #56] ; (8002160 <HAL_ADC_MspInit+0x80>) 8002126: 699b ldr r3, [r3, #24] 8002128: f003 0304 and.w r3, r3, #4 800212c: 60bb str r3, [r7, #8] 800212e: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA1 ------> ADC1_IN1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; 8002130: 2302 movs r3, #2 8002132: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002134: 2303 movs r3, #3 8002136: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002138: f107 0310 add.w r3, r7, #16 800213c: 4619 mov r1, r3 800213e: 4809 ldr r0, [pc, #36] ; (8002164 <HAL_ADC_MspInit+0x84>) 8002140: f001 f932 bl 80033a8 <HAL_GPIO_Init> /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 1, 0); 8002144: 2200 movs r2, #0 8002146: 2101 movs r1, #1 8002148: 2012 movs r0, #18 800214a: f001 f880 bl 800324e <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 800214e: 2012 movs r0, #18 8002150: f001 f899 bl 8003286 <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8002154: bf00 nop 8002156: 3720 adds r7, #32 8002158: 46bd mov sp, r7 800215a: bd80 pop {r7, pc} 800215c: 40012400 .word 0x40012400 8002160: 40021000 .word 0x40021000 8002164: 40010800 .word 0x40010800 08002168 <HAL_SPI_MspInit>: * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8002168: b580 push {r7, lr} 800216a: b08a sub sp, #40 ; 0x28 800216c: af00 add r7, sp, #0 800216e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002170: f107 0318 add.w r3, r7, #24 8002174: 2200 movs r2, #0 8002176: 601a str r2, [r3, #0] 8002178: 605a str r2, [r3, #4] 800217a: 609a str r2, [r3, #8] 800217c: 60da str r2, [r3, #12] if(hspi->Instance==SPI1) 800217e: 687b ldr r3, [r7, #4] 8002180: 681b ldr r3, [r3, #0] 8002182: 4a3b ldr r2, [pc, #236] ; (8002270 <HAL_SPI_MspInit+0x108>) 8002184: 4293 cmp r3, r2 8002186: d130 bne.n 80021ea <HAL_SPI_MspInit+0x82> { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8002188: 4b3a ldr r3, [pc, #232] ; (8002274 <HAL_SPI_MspInit+0x10c>) 800218a: 699b ldr r3, [r3, #24] 800218c: 4a39 ldr r2, [pc, #228] ; (8002274 <HAL_SPI_MspInit+0x10c>) 800218e: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8002192: 6193 str r3, [r2, #24] 8002194: 4b37 ldr r3, [pc, #220] ; (8002274 <HAL_SPI_MspInit+0x10c>) 8002196: 699b ldr r3, [r3, #24] 8002198: f403 5380 and.w r3, r3, #4096 ; 0x1000 800219c: 617b str r3, [r7, #20] 800219e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80021a0: 4b34 ldr r3, [pc, #208] ; (8002274 <HAL_SPI_MspInit+0x10c>) 80021a2: 699b ldr r3, [r3, #24] 80021a4: 4a33 ldr r2, [pc, #204] ; (8002274 <HAL_SPI_MspInit+0x10c>) 80021a6: f043 0304 orr.w r3, r3, #4 80021aa: 6193 str r3, [r2, #24] 80021ac: 4b31 ldr r3, [pc, #196] ; (8002274 <HAL_SPI_MspInit+0x10c>) 80021ae: 699b ldr r3, [r3, #24] 80021b0: f003 0304 and.w r3, r3, #4 80021b4: 613b str r3, [r7, #16] 80021b6: 693b ldr r3, [r7, #16] /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; 80021b8: 23a0 movs r3, #160 ; 0xa0 80021ba: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80021bc: 2302 movs r3, #2 80021be: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80021c0: 2303 movs r3, #3 80021c2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021c4: f107 0318 add.w r3, r7, #24 80021c8: 4619 mov r1, r3 80021ca: 482b ldr r0, [pc, #172] ; (8002278 <HAL_SPI_MspInit+0x110>) 80021cc: f001 f8ec bl 80033a8 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_6; 80021d0: 2340 movs r3, #64 ; 0x40 80021d2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80021d4: 2300 movs r3, #0 80021d6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021d8: 2300 movs r3, #0 80021da: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021dc: f107 0318 add.w r3, r7, #24 80021e0: 4619 mov r1, r3 80021e2: 4825 ldr r0, [pc, #148] ; (8002278 <HAL_SPI_MspInit+0x110>) 80021e4: f001 f8e0 bl 80033a8 <HAL_GPIO_Init> /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 80021e8: e03e b.n 8002268 <HAL_SPI_MspInit+0x100> else if(hspi->Instance==SPI2) 80021ea: 687b ldr r3, [r7, #4] 80021ec: 681b ldr r3, [r3, #0] 80021ee: 4a23 ldr r2, [pc, #140] ; (800227c <HAL_SPI_MspInit+0x114>) 80021f0: 4293 cmp r3, r2 80021f2: d139 bne.n 8002268 <HAL_SPI_MspInit+0x100> __HAL_RCC_SPI2_CLK_ENABLE(); 80021f4: 4b1f ldr r3, [pc, #124] ; (8002274 <HAL_SPI_MspInit+0x10c>) 80021f6: 69db ldr r3, [r3, #28] 80021f8: 4a1e ldr r2, [pc, #120] ; (8002274 <HAL_SPI_MspInit+0x10c>) 80021fa: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80021fe: 61d3 str r3, [r2, #28] 8002200: 4b1c ldr r3, [pc, #112] ; (8002274 <HAL_SPI_MspInit+0x10c>) 8002202: 69db ldr r3, [r3, #28] 8002204: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002208: 60fb str r3, [r7, #12] 800220a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800220c: 4b19 ldr r3, [pc, #100] ; (8002274 <HAL_SPI_MspInit+0x10c>) 800220e: 699b ldr r3, [r3, #24] 8002210: 4a18 ldr r2, [pc, #96] ; (8002274 <HAL_SPI_MspInit+0x10c>) 8002212: f043 0308 orr.w r3, r3, #8 8002216: 6193 str r3, [r2, #24] 8002218: 4b16 ldr r3, [pc, #88] ; (8002274 <HAL_SPI_MspInit+0x10c>) 800221a: 699b ldr r3, [r3, #24] 800221c: f003 0308 and.w r3, r3, #8 8002220: 60bb str r3, [r7, #8] 8002222: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; 8002224: f44f 4320 mov.w r3, #40960 ; 0xa000 8002228: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800222a: 2300 movs r3, #0 800222c: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800222e: 2300 movs r3, #0 8002230: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002232: f107 0318 add.w r3, r7, #24 8002236: 4619 mov r1, r3 8002238: 4811 ldr r0, [pc, #68] ; (8002280 <HAL_SPI_MspInit+0x118>) 800223a: f001 f8b5 bl 80033a8 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_14; 800223e: f44f 4380 mov.w r3, #16384 ; 0x4000 8002242: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002244: 2302 movs r3, #2 8002246: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8002248: 2303 movs r3, #3 800224a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800224c: f107 0318 add.w r3, r7, #24 8002250: 4619 mov r1, r3 8002252: 480b ldr r0, [pc, #44] ; (8002280 <HAL_SPI_MspInit+0x118>) 8002254: f001 f8a8 bl 80033a8 <HAL_GPIO_Init> HAL_NVIC_SetPriority(SPI2_IRQn, 1, 0); 8002258: 2200 movs r2, #0 800225a: 2101 movs r1, #1 800225c: 2024 movs r0, #36 ; 0x24 800225e: f000 fff6 bl 800324e <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(SPI2_IRQn); 8002262: 2024 movs r0, #36 ; 0x24 8002264: f001 f80f bl 8003286 <HAL_NVIC_EnableIRQ> } 8002268: bf00 nop 800226a: 3728 adds r7, #40 ; 0x28 800226c: 46bd mov sp, r7 800226e: bd80 pop {r7, pc} 8002270: 40013000 .word 0x40013000 8002274: 40021000 .word 0x40021000 8002278: 40010800 .word 0x40010800 800227c: 40003800 .word 0x40003800 8002280: 40010c00 .word 0x40010c00 08002284 <HAL_TIM_Base_MspInit>: * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8002284: b480 push {r7} 8002286: b085 sub sp, #20 8002288: af00 add r7, sp, #0 800228a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) 800228c: 687b ldr r3, [r7, #4] 800228e: 681b ldr r3, [r3, #0] 8002290: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8002294: d10c bne.n 80022b0 <HAL_TIM_Base_MspInit+0x2c> { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8002296: 4b11 ldr r3, [pc, #68] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 8002298: 69db ldr r3, [r3, #28] 800229a: 4a10 ldr r2, [pc, #64] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 800229c: f043 0301 orr.w r3, r3, #1 80022a0: 61d3 str r3, [r2, #28] 80022a2: 4b0e ldr r3, [pc, #56] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 80022a4: 69db ldr r3, [r3, #28] 80022a6: f003 0301 and.w r3, r3, #1 80022aa: 60fb str r3, [r7, #12] 80022ac: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80022ae: e010 b.n 80022d2 <HAL_TIM_Base_MspInit+0x4e> else if(htim_base->Instance==TIM3) 80022b0: 687b ldr r3, [r7, #4] 80022b2: 681b ldr r3, [r3, #0] 80022b4: 4a0a ldr r2, [pc, #40] ; (80022e0 <HAL_TIM_Base_MspInit+0x5c>) 80022b6: 4293 cmp r3, r2 80022b8: d10b bne.n 80022d2 <HAL_TIM_Base_MspInit+0x4e> __HAL_RCC_TIM3_CLK_ENABLE(); 80022ba: 4b08 ldr r3, [pc, #32] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 80022bc: 69db ldr r3, [r3, #28] 80022be: 4a07 ldr r2, [pc, #28] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 80022c0: f043 0302 orr.w r3, r3, #2 80022c4: 61d3 str r3, [r2, #28] 80022c6: 4b05 ldr r3, [pc, #20] ; (80022dc <HAL_TIM_Base_MspInit+0x58>) 80022c8: 69db ldr r3, [r3, #28] 80022ca: f003 0302 and.w r3, r3, #2 80022ce: 60bb str r3, [r7, #8] 80022d0: 68bb ldr r3, [r7, #8] } 80022d2: bf00 nop 80022d4: 3714 adds r7, #20 80022d6: 46bd mov sp, r7 80022d8: bc80 pop {r7} 80022da: 4770 bx lr 80022dc: 40021000 .word 0x40021000 80022e0: 40000400 .word 0x40000400 080022e4 <HAL_TIM_MspPostInit>: void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80022e4: b580 push {r7, lr} 80022e6: b088 sub sp, #32 80022e8: af00 add r7, sp, #0 80022ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80022ec: f107 0310 add.w r3, r7, #16 80022f0: 2200 movs r2, #0 80022f2: 601a str r2, [r3, #0] 80022f4: 605a str r2, [r3, #4] 80022f6: 609a str r2, [r3, #8] 80022f8: 60da str r2, [r3, #12] if(htim->Instance==TIM2) 80022fa: 687b ldr r3, [r7, #4] 80022fc: 681b ldr r3, [r3, #0] 80022fe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8002302: d117 bne.n 8002334 <HAL_TIM_MspPostInit+0x50> { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002304: 4b0d ldr r3, [pc, #52] ; (800233c <HAL_TIM_MspPostInit+0x58>) 8002306: 699b ldr r3, [r3, #24] 8002308: 4a0c ldr r2, [pc, #48] ; (800233c <HAL_TIM_MspPostInit+0x58>) 800230a: f043 0304 orr.w r3, r3, #4 800230e: 6193 str r3, [r2, #24] 8002310: 4b0a ldr r3, [pc, #40] ; (800233c <HAL_TIM_MspPostInit+0x58>) 8002312: 699b ldr r3, [r3, #24] 8002314: f003 0304 and.w r3, r3, #4 8002318: 60fb str r3, [r7, #12] 800231a: 68fb ldr r3, [r7, #12] /**TIM2 GPIO Configuration PA0-WKUP ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; 800231c: 2301 movs r3, #1 800231e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002320: 2302 movs r3, #2 8002322: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002324: 2302 movs r3, #2 8002326: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002328: f107 0310 add.w r3, r7, #16 800232c: 4619 mov r1, r3 800232e: 4804 ldr r0, [pc, #16] ; (8002340 <HAL_TIM_MspPostInit+0x5c>) 8002330: f001 f83a bl 80033a8 <HAL_GPIO_Init> /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8002334: bf00 nop 8002336: 3720 adds r7, #32 8002338: 46bd mov sp, r7 800233a: bd80 pop {r7, pc} 800233c: 40021000 .word 0x40021000 8002340: 40010800 .word 0x40010800 08002344 <HAL_UART_MspInit>: * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8002344: b580 push {r7, lr} 8002346: b088 sub sp, #32 8002348: af00 add r7, sp, #0 800234a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800234c: f107 0310 add.w r3, r7, #16 8002350: 2200 movs r2, #0 8002352: 601a str r2, [r3, #0] 8002354: 605a str r2, [r3, #4] 8002356: 609a str r2, [r3, #8] 8002358: 60da str r2, [r3, #12] if(huart->Instance==USART1) 800235a: 687b ldr r3, [r7, #4] 800235c: 681b ldr r3, [r3, #0] 800235e: 4a1c ldr r2, [pc, #112] ; (80023d0 <HAL_UART_MspInit+0x8c>) 8002360: 4293 cmp r3, r2 8002362: d131 bne.n 80023c8 <HAL_UART_MspInit+0x84> { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8002364: 4b1b ldr r3, [pc, #108] ; (80023d4 <HAL_UART_MspInit+0x90>) 8002366: 699b ldr r3, [r3, #24] 8002368: 4a1a ldr r2, [pc, #104] ; (80023d4 <HAL_UART_MspInit+0x90>) 800236a: f443 4380 orr.w r3, r3, #16384 ; 0x4000 800236e: 6193 str r3, [r2, #24] 8002370: 4b18 ldr r3, [pc, #96] ; (80023d4 <HAL_UART_MspInit+0x90>) 8002372: 699b ldr r3, [r3, #24] 8002374: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002378: 60fb str r3, [r7, #12] 800237a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800237c: 4b15 ldr r3, [pc, #84] ; (80023d4 <HAL_UART_MspInit+0x90>) 800237e: 699b ldr r3, [r3, #24] 8002380: 4a14 ldr r2, [pc, #80] ; (80023d4 <HAL_UART_MspInit+0x90>) 8002382: f043 0304 orr.w r3, r3, #4 8002386: 6193 str r3, [r2, #24] 8002388: 4b12 ldr r3, [pc, #72] ; (80023d4 <HAL_UART_MspInit+0x90>) 800238a: 699b ldr r3, [r3, #24] 800238c: f003 0304 and.w r3, r3, #4 8002390: 60bb str r3, [r7, #8] 8002392: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8002394: f44f 7300 mov.w r3, #512 ; 0x200 8002398: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800239a: 2302 movs r3, #2 800239c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800239e: 2303 movs r3, #3 80023a0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80023a2: f107 0310 add.w r3, r7, #16 80023a6: 4619 mov r1, r3 80023a8: 480b ldr r0, [pc, #44] ; (80023d8 <HAL_UART_MspInit+0x94>) 80023aa: f000 fffd bl 80033a8 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_10; 80023ae: f44f 6380 mov.w r3, #1024 ; 0x400 80023b2: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80023b4: 2300 movs r3, #0 80023b6: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80023b8: 2300 movs r3, #0 80023ba: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80023bc: f107 0310 add.w r3, r7, #16 80023c0: 4619 mov r1, r3 80023c2: 4805 ldr r0, [pc, #20] ; (80023d8 <HAL_UART_MspInit+0x94>) 80023c4: f000 fff0 bl 80033a8 <HAL_GPIO_Init> /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 80023c8: bf00 nop 80023ca: 3720 adds r7, #32 80023cc: 46bd mov sp, r7 80023ce: bd80 pop {r7, pc} 80023d0: 40013800 .word 0x40013800 80023d4: 40021000 .word 0x40021000 80023d8: 40010800 .word 0x40010800 080023dc <NMI_Handler>: /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80023dc: b480 push {r7} 80023de: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80023e0: e7fe b.n 80023e0 <NMI_Handler+0x4> 080023e2 <HardFault_Handler>: /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80023e2: b480 push {r7} 80023e4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80023e6: e7fe b.n 80023e6 <HardFault_Handler+0x4> 080023e8 <MemManage_Handler>: /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80023e8: b480 push {r7} 80023ea: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80023ec: e7fe b.n 80023ec <MemManage_Handler+0x4> 080023ee <BusFault_Handler>: /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80023ee: b480 push {r7} 80023f0: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80023f2: e7fe b.n 80023f2 <BusFault_Handler+0x4> 080023f4 <UsageFault_Handler>: /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80023f4: b480 push {r7} 80023f6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80023f8: e7fe b.n 80023f8 <UsageFault_Handler+0x4> 080023fa <SVC_Handler>: /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80023fa: b480 push {r7} 80023fc: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80023fe: bf00 nop 8002400: 46bd mov sp, r7 8002402: bc80 pop {r7} 8002404: 4770 bx lr 08002406 <DebugMon_Handler>: /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002406: b480 push {r7} 8002408: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800240a: bf00 nop 800240c: 46bd mov sp, r7 800240e: bc80 pop {r7} 8002410: 4770 bx lr 08002412 <PendSV_Handler>: /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002412: b480 push {r7} 8002414: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002416: bf00 nop 8002418: 46bd mov sp, r7 800241a: bc80 pop {r7} 800241c: 4770 bx lr 0800241e <SysTick_Handler>: /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800241e: b580 push {r7, lr} 8002420: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002422: f000 f8eb bl 80025fc <HAL_IncTick> /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002426: bf00 nop 8002428: bd80 pop {r7, pc} ... 0800242c <ADC1_2_IRQHandler>: /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800242c: b580 push {r7, lr} 800242e: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_2_IRQn 0 */ ADC_data = HAL_ADC_GetValue(&hadc1); 8002430: 480f ldr r0, [pc, #60] ; (8002470 <ADC1_2_IRQHandler+0x44>) 8002432: f000 fbb7 bl 8002ba4 <HAL_ADC_GetValue> 8002436: 4603 mov r3, r0 8002438: b29a uxth r2, r3 800243a: 4b0e ldr r3, [pc, #56] ; (8002474 <ADC1_2_IRQHandler+0x48>) 800243c: 801a strh r2, [r3, #0] if (need_save) 800243e: 4b0e ldr r3, [pc, #56] ; (8002478 <ADC1_2_IRQHandler+0x4c>) 8002440: 781b ldrb r3, [r3, #0] 8002442: 2b00 cmp r3, #0 8002444: d002 beq.n 800244c <ADC1_2_IRQHandler+0x20> { new_conv = 1; //set flag for new conversion 8002446: 4b0d ldr r3, [pc, #52] ; (800247c <ADC1_2_IRQHandler+0x50>) 8002448: 2201 movs r2, #1 800244a: 701a strb r2, [r3, #0] } if (!need_selfcheck) { 800244c: 4b0c ldr r3, [pc, #48] ; (8002480 <ADC1_2_IRQHandler+0x54>) 800244e: 781b ldrb r3, [r3, #0] 8002450: f083 0301 eor.w r3, r3, #1 8002454: b2db uxtb r3, r3 8002456: 2b00 cmp r3, #0 8002458: d004 beq.n 8002464 <ADC1_2_IRQHandler+0x38> ADC_data_safe = ADC_data; 800245a: 4b06 ldr r3, [pc, #24] ; (8002474 <ADC1_2_IRQHandler+0x48>) 800245c: 881b ldrh r3, [r3, #0] 800245e: b29a uxth r2, r3 8002460: 4b08 ldr r3, [pc, #32] ; (8002484 <ADC1_2_IRQHandler+0x58>) 8002462: 801a strh r2, [r3, #0] } /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8002464: 4802 ldr r0, [pc, #8] ; (8002470 <ADC1_2_IRQHandler+0x44>) 8002466: f000 fba9 bl 8002bbc <HAL_ADC_IRQHandler> /* USER CODE BEGIN ADC1_2_IRQn 1 */ /* USER CODE END ADC1_2_IRQn 1 */ } 800246a: bf00 nop 800246c: bd80 pop {r7, pc} 800246e: bf00 nop 8002470: 2000061c .word 0x2000061c 8002474: 20000a00 .word 0x20000a00 8002478: 200008d0 .word 0x200008d0 800247c: 200008d4 .word 0x200008d4 8002480: 200009f8 .word 0x200009f8 8002484: 200009f6 .word 0x200009f6 08002488 <SPI2_IRQHandler>: /** * @brief This function handles SPI2 global interrupt. */ void SPI2_IRQHandler(void) { 8002488: b580 push {r7, lr} 800248a: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_IRQn 0 */ /* USER CODE END SPI2_IRQn 0 */ HAL_SPI_IRQHandler(&hspi2); 800248c: 4802 ldr r0, [pc, #8] ; (8002498 <SPI2_IRQHandler+0x10>) 800248e: f002 fc07 bl 8004ca0 <HAL_SPI_IRQHandler> /* USER CODE BEGIN SPI2_IRQn 1 */ /* USER CODE END SPI2_IRQn 1 */ } 8002492: bf00 nop 8002494: bd80 pop {r7, pc} 8002496: bf00 nop 8002498: 200006a4 .word 0x200006a4 0800249c <EXTI15_10_IRQHandler>: /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 800249c: b580 push {r7, lr} 800249e: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(SPI2_CS_Pin); 80024a0: f44f 5080 mov.w r0, #4096 ; 0x1000 80024a4: f001 f94c bl 8003740 <HAL_GPIO_EXTI_IRQHandler> /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 80024a8: bf00 nop 80024aa: bd80 pop {r7, pc} 080024ac <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80024ac: b580 push {r7, lr} 80024ae: b086 sub sp, #24 80024b0: af00 add r7, sp, #0 80024b2: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80024b4: 4a14 ldr r2, [pc, #80] ; (8002508 <_sbrk+0x5c>) 80024b6: 4b15 ldr r3, [pc, #84] ; (800250c <_sbrk+0x60>) 80024b8: 1ad3 subs r3, r2, r3 80024ba: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80024bc: 697b ldr r3, [r7, #20] 80024be: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80024c0: 4b13 ldr r3, [pc, #76] ; (8002510 <_sbrk+0x64>) 80024c2: 681b ldr r3, [r3, #0] 80024c4: 2b00 cmp r3, #0 80024c6: d102 bne.n 80024ce <_sbrk+0x22> { __sbrk_heap_end = &_end; 80024c8: 4b11 ldr r3, [pc, #68] ; (8002510 <_sbrk+0x64>) 80024ca: 4a12 ldr r2, [pc, #72] ; (8002514 <_sbrk+0x68>) 80024cc: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80024ce: 4b10 ldr r3, [pc, #64] ; (8002510 <_sbrk+0x64>) 80024d0: 681a ldr r2, [r3, #0] 80024d2: 687b ldr r3, [r7, #4] 80024d4: 4413 add r3, r2 80024d6: 693a ldr r2, [r7, #16] 80024d8: 429a cmp r2, r3 80024da: d207 bcs.n 80024ec <_sbrk+0x40> { errno = ENOMEM; 80024dc: f004 fa9a bl 8006a14 <__errno> 80024e0: 4603 mov r3, r0 80024e2: 220c movs r2, #12 80024e4: 601a str r2, [r3, #0] return (void *)-1; 80024e6: f04f 33ff mov.w r3, #4294967295 80024ea: e009 b.n 8002500 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80024ec: 4b08 ldr r3, [pc, #32] ; (8002510 <_sbrk+0x64>) 80024ee: 681b ldr r3, [r3, #0] 80024f0: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80024f2: 4b07 ldr r3, [pc, #28] ; (8002510 <_sbrk+0x64>) 80024f4: 681a ldr r2, [r3, #0] 80024f6: 687b ldr r3, [r7, #4] 80024f8: 4413 add r3, r2 80024fa: 4a05 ldr r2, [pc, #20] ; (8002510 <_sbrk+0x64>) 80024fc: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80024fe: 68fb ldr r3, [r7, #12] } 8002500: 4618 mov r0, r3 8002502: 3718 adds r7, #24 8002504: 46bd mov sp, r7 8002506: bd80 pop {r7, pc} 8002508: 20005000 .word 0x20005000 800250c: 00000400 .word 0x00000400 8002510: 20000a04 .word 0x20000a04 8002514: 20000a70 .word 0x20000a70 08002518 <SystemInit>: * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002518: b480 push {r7} 800251a: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800251c: bf00 nop 800251e: 46bd mov sp, r7 8002520: bc80 pop {r7} 8002522: 4770 bx lr 08002524 <Reset_Handler>: .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002524: 480c ldr r0, [pc, #48] ; (8002558 <LoopFillZerobss+0x12>) ldr r1, =_edata 8002526: 490d ldr r1, [pc, #52] ; (800255c <LoopFillZerobss+0x16>) ldr r2, =_sidata 8002528: 4a0d ldr r2, [pc, #52] ; (8002560 <LoopFillZerobss+0x1a>) movs r3, #0 800252a: 2300 movs r3, #0 b LoopCopyDataInit 800252c: e002 b.n 8002534 <LoopCopyDataInit> 0800252e <CopyDataInit>: CopyDataInit: ldr r4, [r2, r3] 800252e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002530: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002532: 3304 adds r3, #4 08002534 <LoopCopyDataInit>: LoopCopyDataInit: adds r4, r0, r3 8002534: 18c4 adds r4, r0, r3 cmp r4, r1 8002536: 428c cmp r4, r1 bcc CopyDataInit 8002538: d3f9 bcc.n 800252e <CopyDataInit> /* Zero fill the bss segment. */ ldr r2, =_sbss 800253a: 4a0a ldr r2, [pc, #40] ; (8002564 <LoopFillZerobss+0x1e>) ldr r4, =_ebss 800253c: 4c0a ldr r4, [pc, #40] ; (8002568 <LoopFillZerobss+0x22>) movs r3, #0 800253e: 2300 movs r3, #0 b LoopFillZerobss 8002540: e001 b.n 8002546 <LoopFillZerobss> 08002542 <FillZerobss>: FillZerobss: str r3, [r2] 8002542: 6013 str r3, [r2, #0] adds r2, r2, #4 8002544: 3204 adds r2, #4 08002546 <LoopFillZerobss>: LoopFillZerobss: cmp r2, r4 8002546: 42a2 cmp r2, r4 bcc FillZerobss 8002548: d3fb bcc.n 8002542 <FillZerobss> /* Call the clock system intitialization function.*/ bl SystemInit 800254a: f7ff ffe5 bl 8002518 <SystemInit> /* Call static constructors */ bl __libc_init_array 800254e: f004 fa67 bl 8006a20 <__libc_init_array> /* Call the application's entry point.*/ bl main 8002552: f7fe fcdf bl 8000f14 <main> bx lr 8002556: 4770 bx lr ldr r0, =_sdata 8002558: 20000000 .word 0x20000000 ldr r1, =_edata 800255c: 200000c8 .word 0x200000c8 ldr r2, =_sidata 8002560: 08007b34 .word 0x08007b34 ldr r2, =_sbss 8002564: 200000c8 .word 0x200000c8 ldr r4, =_ebss 8002568: 20000a6c .word 0x20000a6c 0800256c <CAN1_RX1_IRQHandler>: * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800256c: e7fe b.n 800256c <CAN1_RX1_IRQHandler> ... 08002570 <HAL_Init>: * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002570: b580 push {r7, lr} 8002572: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002574: 4b08 ldr r3, [pc, #32] ; (8002598 <HAL_Init+0x28>) 8002576: 681b ldr r3, [r3, #0] 8002578: 4a07 ldr r2, [pc, #28] ; (8002598 <HAL_Init+0x28>) 800257a: f043 0310 orr.w r3, r3, #16 800257e: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002580: 2003 movs r0, #3 8002582: f000 fe59 bl 8003238 <HAL_NVIC_SetPriorityGrouping> /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002586: 2000 movs r0, #0 8002588: f000 f808 bl 800259c <HAL_InitTick> /* Init the low level hardware */ HAL_MspInit(); 800258c: f7ff fd76 bl 800207c <HAL_MspInit> /* Return function status */ return HAL_OK; 8002590: 2300 movs r3, #0 } 8002592: 4618 mov r0, r3 8002594: bd80 pop {r7, pc} 8002596: bf00 nop 8002598: 40022000 .word 0x40022000 0800259c <HAL_InitTick>: * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800259c: b580 push {r7, lr} 800259e: b082 sub sp, #8 80025a0: af00 add r7, sp, #0 80025a2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80025a4: 4b12 ldr r3, [pc, #72] ; (80025f0 <HAL_InitTick+0x54>) 80025a6: 681a ldr r2, [r3, #0] 80025a8: 4b12 ldr r3, [pc, #72] ; (80025f4 <HAL_InitTick+0x58>) 80025aa: 781b ldrb r3, [r3, #0] 80025ac: 4619 mov r1, r3 80025ae: f44f 737a mov.w r3, #1000 ; 0x3e8 80025b2: fbb3 f3f1 udiv r3, r3, r1 80025b6: fbb2 f3f3 udiv r3, r2, r3 80025ba: 4618 mov r0, r3 80025bc: f000 fe71 bl 80032a2 <HAL_SYSTICK_Config> 80025c0: 4603 mov r3, r0 80025c2: 2b00 cmp r3, #0 80025c4: d001 beq.n 80025ca <HAL_InitTick+0x2e> { return HAL_ERROR; 80025c6: 2301 movs r3, #1 80025c8: e00e b.n 80025e8 <HAL_InitTick+0x4c> } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80025ca: 687b ldr r3, [r7, #4] 80025cc: 2b0f cmp r3, #15 80025ce: d80a bhi.n 80025e6 <HAL_InitTick+0x4a> { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80025d0: 2200 movs r2, #0 80025d2: 6879 ldr r1, [r7, #4] 80025d4: f04f 30ff mov.w r0, #4294967295 80025d8: f000 fe39 bl 800324e <HAL_NVIC_SetPriority> uwTickPrio = TickPriority; 80025dc: 4a06 ldr r2, [pc, #24] ; (80025f8 <HAL_InitTick+0x5c>) 80025de: 687b ldr r3, [r7, #4] 80025e0: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80025e2: 2300 movs r3, #0 80025e4: e000 b.n 80025e8 <HAL_InitTick+0x4c> return HAL_ERROR; 80025e6: 2301 movs r3, #1 } 80025e8: 4618 mov r0, r3 80025ea: 3708 adds r7, #8 80025ec: 46bd mov sp, r7 80025ee: bd80 pop {r7, pc} 80025f0: 20000058 .word 0x20000058 80025f4: 20000060 .word 0x20000060 80025f8: 2000005c .word 0x2000005c 080025fc <HAL_IncTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80025fc: b480 push {r7} 80025fe: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002600: 4b05 ldr r3, [pc, #20] ; (8002618 <HAL_IncTick+0x1c>) 8002602: 781b ldrb r3, [r3, #0] 8002604: 461a mov r2, r3 8002606: 4b05 ldr r3, [pc, #20] ; (800261c <HAL_IncTick+0x20>) 8002608: 681b ldr r3, [r3, #0] 800260a: 4413 add r3, r2 800260c: 4a03 ldr r2, [pc, #12] ; (800261c <HAL_IncTick+0x20>) 800260e: 6013 str r3, [r2, #0] } 8002610: bf00 nop 8002612: 46bd mov sp, r7 8002614: bc80 pop {r7} 8002616: 4770 bx lr 8002618: 20000060 .word 0x20000060 800261c: 20000a08 .word 0x20000a08 08002620 <HAL_GetTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002620: b480 push {r7} 8002622: af00 add r7, sp, #0 return uwTick; 8002624: 4b02 ldr r3, [pc, #8] ; (8002630 <HAL_GetTick+0x10>) 8002626: 681b ldr r3, [r3, #0] } 8002628: 4618 mov r0, r3 800262a: 46bd mov sp, r7 800262c: bc80 pop {r7} 800262e: 4770 bx lr 8002630: 20000a08 .word 0x20000a08 08002634 <HAL_Delay>: * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8002634: b580 push {r7, lr} 8002636: b084 sub sp, #16 8002638: af00 add r7, sp, #0 800263a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800263c: f7ff fff0 bl 8002620 <HAL_GetTick> 8002640: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8002642: 687b ldr r3, [r7, #4] 8002644: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8002646: 68fb ldr r3, [r7, #12] 8002648: f1b3 3fff cmp.w r3, #4294967295 800264c: d005 beq.n 800265a <HAL_Delay+0x26> { wait += (uint32_t)(uwTickFreq); 800264e: 4b0a ldr r3, [pc, #40] ; (8002678 <HAL_Delay+0x44>) 8002650: 781b ldrb r3, [r3, #0] 8002652: 461a mov r2, r3 8002654: 68fb ldr r3, [r7, #12] 8002656: 4413 add r3, r2 8002658: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800265a: bf00 nop 800265c: f7ff ffe0 bl 8002620 <HAL_GetTick> 8002660: 4602 mov r2, r0 8002662: 68bb ldr r3, [r7, #8] 8002664: 1ad3 subs r3, r2, r3 8002666: 68fa ldr r2, [r7, #12] 8002668: 429a cmp r2, r3 800266a: d8f7 bhi.n 800265c <HAL_Delay+0x28> { } } 800266c: bf00 nop 800266e: bf00 nop 8002670: 3710 adds r7, #16 8002672: 46bd mov sp, r7 8002674: bd80 pop {r7, pc} 8002676: bf00 nop 8002678: 20000060 .word 0x20000060 0800267c <HAL_ADC_Init>: * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800267c: b580 push {r7, lr} 800267e: b086 sub sp, #24 8002680: af00 add r7, sp, #0 8002682: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002684: 2300 movs r3, #0 8002686: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8002688: 2300 movs r3, #0 800268a: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800268c: 2300 movs r3, #0 800268e: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8002690: 2300 movs r3, #0 8002692: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8002694: 687b ldr r3, [r7, #4] 8002696: 2b00 cmp r3, #0 8002698: d101 bne.n 800269e <HAL_ADC_Init+0x22> { return HAL_ERROR; 800269a: 2301 movs r3, #1 800269c: e0be b.n 800281c <HAL_ADC_Init+0x1a0> assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800269e: 687b ldr r3, [r7, #4] 80026a0: 689b ldr r3, [r3, #8] 80026a2: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80026a4: 687b ldr r3, [r7, #4] 80026a6: 6a9b ldr r3, [r3, #40] ; 0x28 80026a8: 2b00 cmp r3, #0 80026aa: d109 bne.n 80026c0 <HAL_ADC_Init+0x44> { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 80026ac: 687b ldr r3, [r7, #4] 80026ae: 2200 movs r2, #0 80026b0: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 80026b2: 687b ldr r3, [r7, #4] 80026b4: 2200 movs r2, #0 80026b6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80026ba: 6878 ldr r0, [r7, #4] 80026bc: f7ff fd10 bl 80020e0 <HAL_ADC_MspInit> /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80026c0: 6878 ldr r0, [r7, #4] 80026c2: f000 fca3 bl 800300c <ADC_ConversionStop_Disable> 80026c6: 4603 mov r3, r0 80026c8: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80026ca: 687b ldr r3, [r7, #4] 80026cc: 6a9b ldr r3, [r3, #40] ; 0x28 80026ce: f003 0310 and.w r3, r3, #16 80026d2: 2b00 cmp r3, #0 80026d4: f040 8099 bne.w 800280a <HAL_ADC_Init+0x18e> 80026d8: 7dfb ldrb r3, [r7, #23] 80026da: 2b00 cmp r3, #0 80026dc: f040 8095 bne.w 800280a <HAL_ADC_Init+0x18e> (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80026e0: 687b ldr r3, [r7, #4] 80026e2: 6a9b ldr r3, [r3, #40] ; 0x28 80026e4: f423 5388 bic.w r3, r3, #4352 ; 0x1100 80026e8: f023 0302 bic.w r3, r3, #2 80026ec: f043 0202 orr.w r2, r3, #2 80026f0: 687b ldr r3, [r7, #4] 80026f2: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 80026f4: 687b ldr r3, [r7, #4] 80026f6: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80026f8: 687b ldr r3, [r7, #4] 80026fa: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 80026fc: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 80026fe: 687b ldr r3, [r7, #4] 8002700: 7b1b ldrb r3, [r3, #12] 8002702: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002704: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8002706: 68ba ldr r2, [r7, #8] 8002708: 4313 orrs r3, r2 800270a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800270c: 687b ldr r3, [r7, #4] 800270e: 689b ldr r3, [r3, #8] 8002710: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002714: d003 beq.n 800271e <HAL_ADC_Init+0xa2> 8002716: 687b ldr r3, [r7, #4] 8002718: 689b ldr r3, [r3, #8] 800271a: 2b01 cmp r3, #1 800271c: d102 bne.n 8002724 <HAL_ADC_Init+0xa8> 800271e: f44f 7380 mov.w r3, #256 ; 0x100 8002722: e000 b.n 8002726 <HAL_ADC_Init+0xaa> 8002724: 2300 movs r3, #0 8002726: 693a ldr r2, [r7, #16] 8002728: 4313 orrs r3, r2 800272a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800272c: 687b ldr r3, [r7, #4] 800272e: 7d1b ldrb r3, [r3, #20] 8002730: 2b01 cmp r3, #1 8002732: d119 bne.n 8002768 <HAL_ADC_Init+0xec> { if (hadc->Init.ContinuousConvMode == DISABLE) 8002734: 687b ldr r3, [r7, #4] 8002736: 7b1b ldrb r3, [r3, #12] 8002738: 2b00 cmp r3, #0 800273a: d109 bne.n 8002750 <HAL_ADC_Init+0xd4> { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800273c: 687b ldr r3, [r7, #4] 800273e: 699b ldr r3, [r3, #24] 8002740: 3b01 subs r3, #1 8002742: 035a lsls r2, r3, #13 8002744: 693b ldr r3, [r7, #16] 8002746: 4313 orrs r3, r2 8002748: f443 6300 orr.w r3, r3, #2048 ; 0x800 800274c: 613b str r3, [r7, #16] 800274e: e00b b.n 8002768 <HAL_ADC_Init+0xec> { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002750: 687b ldr r3, [r7, #4] 8002752: 6a9b ldr r3, [r3, #40] ; 0x28 8002754: f043 0220 orr.w r2, r3, #32 8002758: 687b ldr r3, [r7, #4] 800275a: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800275c: 687b ldr r3, [r7, #4] 800275e: 6adb ldr r3, [r3, #44] ; 0x2c 8002760: f043 0201 orr.w r2, r3, #1 8002764: 687b ldr r3, [r7, #4] 8002766: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8002768: 687b ldr r3, [r7, #4] 800276a: 681b ldr r3, [r3, #0] 800276c: 685b ldr r3, [r3, #4] 800276e: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8002772: 687b ldr r3, [r7, #4] 8002774: 681b ldr r3, [r3, #0] 8002776: 693a ldr r2, [r7, #16] 8002778: 430a orrs r2, r1 800277a: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800277c: 687b ldr r3, [r7, #4] 800277e: 681b ldr r3, [r3, #0] 8002780: 689a ldr r2, [r3, #8] 8002782: 4b28 ldr r3, [pc, #160] ; (8002824 <HAL_ADC_Init+0x1a8>) 8002784: 4013 ands r3, r2 8002786: 687a ldr r2, [r7, #4] 8002788: 6812 ldr r2, [r2, #0] 800278a: 68b9 ldr r1, [r7, #8] 800278c: 430b orrs r3, r1 800278e: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8002790: 687b ldr r3, [r7, #4] 8002792: 689b ldr r3, [r3, #8] 8002794: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002798: d003 beq.n 80027a2 <HAL_ADC_Init+0x126> 800279a: 687b ldr r3, [r7, #4] 800279c: 689b ldr r3, [r3, #8] 800279e: 2b01 cmp r3, #1 80027a0: d104 bne.n 80027ac <HAL_ADC_Init+0x130> { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 80027a2: 687b ldr r3, [r7, #4] 80027a4: 691b ldr r3, [r3, #16] 80027a6: 3b01 subs r3, #1 80027a8: 051b lsls r3, r3, #20 80027aa: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 80027ac: 687b ldr r3, [r7, #4] 80027ae: 681b ldr r3, [r3, #0] 80027b0: 6adb ldr r3, [r3, #44] ; 0x2c 80027b2: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 80027b6: 687b ldr r3, [r7, #4] 80027b8: 681b ldr r3, [r3, #0] 80027ba: 68fa ldr r2, [r7, #12] 80027bc: 430a orrs r2, r1 80027be: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80027c0: 687b ldr r3, [r7, #4] 80027c2: 681b ldr r3, [r3, #0] 80027c4: 689a ldr r2, [r3, #8] 80027c6: 4b18 ldr r3, [pc, #96] ; (8002828 <HAL_ADC_Init+0x1ac>) 80027c8: 4013 ands r3, r2 80027ca: 68ba ldr r2, [r7, #8] 80027cc: 429a cmp r2, r3 80027ce: d10b bne.n 80027e8 <HAL_ADC_Init+0x16c> ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 80027d0: 687b ldr r3, [r7, #4] 80027d2: 2200 movs r2, #0 80027d4: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 80027d6: 687b ldr r3, [r7, #4] 80027d8: 6a9b ldr r3, [r3, #40] ; 0x28 80027da: f023 0303 bic.w r3, r3, #3 80027de: f043 0201 orr.w r2, r3, #1 80027e2: 687b ldr r3, [r7, #4] 80027e4: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80027e6: e018 b.n 800281a <HAL_ADC_Init+0x19e> HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80027e8: 687b ldr r3, [r7, #4] 80027ea: 6a9b ldr r3, [r3, #40] ; 0x28 80027ec: f023 0312 bic.w r3, r3, #18 80027f0: f043 0210 orr.w r2, r3, #16 80027f4: 687b ldr r3, [r7, #4] 80027f6: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80027f8: 687b ldr r3, [r7, #4] 80027fa: 6adb ldr r3, [r3, #44] ; 0x2c 80027fc: f043 0201 orr.w r2, r3, #1 8002800: 687b ldr r3, [r7, #4] 8002802: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8002804: 2301 movs r3, #1 8002806: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002808: e007 b.n 800281a <HAL_ADC_Init+0x19e> } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800280a: 687b ldr r3, [r7, #4] 800280c: 6a9b ldr r3, [r3, #40] ; 0x28 800280e: f043 0210 orr.w r2, r3, #16 8002812: 687b ldr r3, [r7, #4] 8002814: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8002816: 2301 movs r3, #1 8002818: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800281a: 7dfb ldrb r3, [r7, #23] } 800281c: 4618 mov r0, r3 800281e: 3718 adds r7, #24 8002820: 46bd mov sp, r7 8002822: bd80 pop {r7, pc} 8002824: ffe1f7fd .word 0xffe1f7fd 8002828: ff1f0efe .word 0xff1f0efe 0800282c <HAL_ADC_PollForConversion>: * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 800282c: b590 push {r4, r7, lr} 800282e: b087 sub sp, #28 8002830: af00 add r7, sp, #0 8002832: 6078 str r0, [r7, #4] 8002834: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8002836: 2300 movs r3, #0 8002838: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800283a: 2300 movs r3, #0 800283c: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 800283e: 2300 movs r3, #0 8002840: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 8002842: f7ff feed bl 8002620 <HAL_GetTick> 8002846: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 8002848: 687b ldr r3, [r7, #4] 800284a: 681b ldr r3, [r3, #0] 800284c: 689b ldr r3, [r3, #8] 800284e: f403 7380 and.w r3, r3, #256 ; 0x100 8002852: 2b00 cmp r3, #0 8002854: d00b beq.n 800286e <HAL_ADC_PollForConversion+0x42> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002856: 687b ldr r3, [r7, #4] 8002858: 6a9b ldr r3, [r3, #40] ; 0x28 800285a: f043 0220 orr.w r2, r3, #32 800285e: 687b ldr r3, [r7, #4] 8002860: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8002862: 687b ldr r3, [r7, #4] 8002864: 2200 movs r2, #0 8002866: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 800286a: 2301 movs r3, #1 800286c: e0d3 b.n 8002a16 <HAL_ADC_PollForConversion+0x1ea> /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800286e: 687b ldr r3, [r7, #4] 8002870: 681b ldr r3, [r3, #0] 8002872: 685b ldr r3, [r3, #4] 8002874: f403 7380 and.w r3, r3, #256 ; 0x100 8002878: 2b00 cmp r3, #0 800287a: d131 bne.n 80028e0 <HAL_ADC_PollForConversion+0xb4> HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 800287c: 687b ldr r3, [r7, #4] 800287e: 681b ldr r3, [r3, #0] 8002880: 6adb ldr r3, [r3, #44] ; 0x2c 8002882: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8002886: 2b00 cmp r3, #0 8002888: d12a bne.n 80028e0 <HAL_ADC_PollForConversion+0xb4> { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800288a: e021 b.n 80028d0 <HAL_ADC_PollForConversion+0xa4> { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800288c: 683b ldr r3, [r7, #0] 800288e: f1b3 3fff cmp.w r3, #4294967295 8002892: d01d beq.n 80028d0 <HAL_ADC_PollForConversion+0xa4> { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 8002894: 683b ldr r3, [r7, #0] 8002896: 2b00 cmp r3, #0 8002898: d007 beq.n 80028aa <HAL_ADC_PollForConversion+0x7e> 800289a: f7ff fec1 bl 8002620 <HAL_GetTick> 800289e: 4602 mov r2, r0 80028a0: 697b ldr r3, [r7, #20] 80028a2: 1ad3 subs r3, r2, r3 80028a4: 683a ldr r2, [r7, #0] 80028a6: 429a cmp r2, r3 80028a8: d212 bcs.n 80028d0 <HAL_ADC_PollForConversion+0xa4> { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80028aa: 687b ldr r3, [r7, #4] 80028ac: 681b ldr r3, [r3, #0] 80028ae: 681b ldr r3, [r3, #0] 80028b0: f003 0302 and.w r3, r3, #2 80028b4: 2b00 cmp r3, #0 80028b6: d10b bne.n 80028d0 <HAL_ADC_PollForConversion+0xa4> { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 80028b8: 687b ldr r3, [r7, #4] 80028ba: 6a9b ldr r3, [r3, #40] ; 0x28 80028bc: f043 0204 orr.w r2, r3, #4 80028c0: 687b ldr r3, [r7, #4] 80028c2: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80028c4: 687b ldr r3, [r7, #4] 80028c6: 2200 movs r2, #0 80028c8: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80028cc: 2303 movs r3, #3 80028ce: e0a2 b.n 8002a16 <HAL_ADC_PollForConversion+0x1ea> while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80028d0: 687b ldr r3, [r7, #4] 80028d2: 681b ldr r3, [r3, #0] 80028d4: 681b ldr r3, [r3, #0] 80028d6: f003 0302 and.w r3, r3, #2 80028da: 2b00 cmp r3, #0 80028dc: d0d6 beq.n 800288c <HAL_ADC_PollForConversion+0x60> if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 80028de: e070 b.n 80029c2 <HAL_ADC_PollForConversion+0x196> /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80028e0: 4b4f ldr r3, [pc, #316] ; (8002a20 <HAL_ADC_PollForConversion+0x1f4>) 80028e2: 681c ldr r4, [r3, #0] 80028e4: 2002 movs r0, #2 80028e6: f001 fc13 bl 8004110 <HAL_RCCEx_GetPeriphCLKFreq> 80028ea: 4603 mov r3, r0 80028ec: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 80028f0: 687b ldr r3, [r7, #4] 80028f2: 681b ldr r3, [r3, #0] 80028f4: 6919 ldr r1, [r3, #16] 80028f6: 4b4b ldr r3, [pc, #300] ; (8002a24 <HAL_ADC_PollForConversion+0x1f8>) 80028f8: 400b ands r3, r1 80028fa: 2b00 cmp r3, #0 80028fc: d118 bne.n 8002930 <HAL_ADC_PollForConversion+0x104> 80028fe: 687b ldr r3, [r7, #4] 8002900: 681b ldr r3, [r3, #0] 8002902: 68d9 ldr r1, [r3, #12] 8002904: 4b48 ldr r3, [pc, #288] ; (8002a28 <HAL_ADC_PollForConversion+0x1fc>) 8002906: 400b ands r3, r1 8002908: 2b00 cmp r3, #0 800290a: d111 bne.n 8002930 <HAL_ADC_PollForConversion+0x104> 800290c: 687b ldr r3, [r7, #4] 800290e: 681b ldr r3, [r3, #0] 8002910: 6919 ldr r1, [r3, #16] 8002912: 4b46 ldr r3, [pc, #280] ; (8002a2c <HAL_ADC_PollForConversion+0x200>) 8002914: 400b ands r3, r1 8002916: 2b00 cmp r3, #0 8002918: d108 bne.n 800292c <HAL_ADC_PollForConversion+0x100> 800291a: 687b ldr r3, [r7, #4] 800291c: 681b ldr r3, [r3, #0] 800291e: 68d9 ldr r1, [r3, #12] 8002920: 4b43 ldr r3, [pc, #268] ; (8002a30 <HAL_ADC_PollForConversion+0x204>) 8002922: 400b ands r3, r1 8002924: 2b00 cmp r3, #0 8002926: d101 bne.n 800292c <HAL_ADC_PollForConversion+0x100> 8002928: 2314 movs r3, #20 800292a: e020 b.n 800296e <HAL_ADC_PollForConversion+0x142> 800292c: 2329 movs r3, #41 ; 0x29 800292e: e01e b.n 800296e <HAL_ADC_PollForConversion+0x142> 8002930: 687b ldr r3, [r7, #4] 8002932: 681b ldr r3, [r3, #0] 8002934: 6919 ldr r1, [r3, #16] 8002936: 4b3d ldr r3, [pc, #244] ; (8002a2c <HAL_ADC_PollForConversion+0x200>) 8002938: 400b ands r3, r1 800293a: 2b00 cmp r3, #0 800293c: d106 bne.n 800294c <HAL_ADC_PollForConversion+0x120> 800293e: 687b ldr r3, [r7, #4] 8002940: 681b ldr r3, [r3, #0] 8002942: 68d9 ldr r1, [r3, #12] 8002944: 4b3a ldr r3, [pc, #232] ; (8002a30 <HAL_ADC_PollForConversion+0x204>) 8002946: 400b ands r3, r1 8002948: 2b00 cmp r3, #0 800294a: d00d beq.n 8002968 <HAL_ADC_PollForConversion+0x13c> 800294c: 687b ldr r3, [r7, #4] 800294e: 681b ldr r3, [r3, #0] 8002950: 6919 ldr r1, [r3, #16] 8002952: 4b38 ldr r3, [pc, #224] ; (8002a34 <HAL_ADC_PollForConversion+0x208>) 8002954: 400b ands r3, r1 8002956: 2b00 cmp r3, #0 8002958: d108 bne.n 800296c <HAL_ADC_PollForConversion+0x140> 800295a: 687b ldr r3, [r7, #4] 800295c: 681b ldr r3, [r3, #0] 800295e: 68d9 ldr r1, [r3, #12] 8002960: 4b34 ldr r3, [pc, #208] ; (8002a34 <HAL_ADC_PollForConversion+0x208>) 8002962: 400b ands r3, r1 8002964: 2b00 cmp r3, #0 8002966: d101 bne.n 800296c <HAL_ADC_PollForConversion+0x140> 8002968: 2354 movs r3, #84 ; 0x54 800296a: e000 b.n 800296e <HAL_ADC_PollForConversion+0x142> 800296c: 23fc movs r3, #252 ; 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 800296e: fb02 f303 mul.w r3, r2, r3 8002972: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8002974: e021 b.n 80029ba <HAL_ADC_PollForConversion+0x18e> { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8002976: 683b ldr r3, [r7, #0] 8002978: f1b3 3fff cmp.w r3, #4294967295 800297c: d01a beq.n 80029b4 <HAL_ADC_PollForConversion+0x188> { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 800297e: 683b ldr r3, [r7, #0] 8002980: 2b00 cmp r3, #0 8002982: d007 beq.n 8002994 <HAL_ADC_PollForConversion+0x168> 8002984: f7ff fe4c bl 8002620 <HAL_GetTick> 8002988: 4602 mov r2, r0 800298a: 697b ldr r3, [r7, #20] 800298c: 1ad3 subs r3, r2, r3 800298e: 683a ldr r2, [r7, #0] 8002990: 429a cmp r2, r3 8002992: d20f bcs.n 80029b4 <HAL_ADC_PollForConversion+0x188> { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8002994: 68fb ldr r3, [r7, #12] 8002996: 693a ldr r2, [r7, #16] 8002998: 429a cmp r2, r3 800299a: d90b bls.n 80029b4 <HAL_ADC_PollForConversion+0x188> { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800299c: 687b ldr r3, [r7, #4] 800299e: 6a9b ldr r3, [r3, #40] ; 0x28 80029a0: f043 0204 orr.w r2, r3, #4 80029a4: 687b ldr r3, [r7, #4] 80029a6: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80029a8: 687b ldr r3, [r7, #4] 80029aa: 2200 movs r2, #0 80029ac: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80029b0: 2303 movs r3, #3 80029b2: e030 b.n 8002a16 <HAL_ADC_PollForConversion+0x1ea> } } } Conversion_Timeout_CPU_cycles ++; 80029b4: 68fb ldr r3, [r7, #12] 80029b6: 3301 adds r3, #1 80029b8: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 80029ba: 68fb ldr r3, [r7, #12] 80029bc: 693a ldr r2, [r7, #16] 80029be: 429a cmp r2, r3 80029c0: d8d9 bhi.n 8002976 <HAL_ADC_PollForConversion+0x14a> } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 80029c2: 687b ldr r3, [r7, #4] 80029c4: 681b ldr r3, [r3, #0] 80029c6: f06f 0212 mvn.w r2, #18 80029ca: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80029cc: 687b ldr r3, [r7, #4] 80029ce: 6a9b ldr r3, [r3, #40] ; 0x28 80029d0: f443 7200 orr.w r2, r3, #512 ; 0x200 80029d4: 687b ldr r3, [r7, #4] 80029d6: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80029d8: 687b ldr r3, [r7, #4] 80029da: 681b ldr r3, [r3, #0] 80029dc: 689b ldr r3, [r3, #8] 80029de: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80029e2: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80029e6: d115 bne.n 8002a14 <HAL_ADC_PollForConversion+0x1e8> (hadc->Init.ContinuousConvMode == DISABLE) ) 80029e8: 687b ldr r3, [r7, #4] 80029ea: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80029ec: 2b00 cmp r3, #0 80029ee: d111 bne.n 8002a14 <HAL_ADC_PollForConversion+0x1e8> { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80029f0: 687b ldr r3, [r7, #4] 80029f2: 6a9b ldr r3, [r3, #40] ; 0x28 80029f4: f423 7280 bic.w r2, r3, #256 ; 0x100 80029f8: 687b ldr r3, [r7, #4] 80029fa: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80029fc: 687b ldr r3, [r7, #4] 80029fe: 6a9b ldr r3, [r3, #40] ; 0x28 8002a00: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002a04: 2b00 cmp r3, #0 8002a06: d105 bne.n 8002a14 <HAL_ADC_PollForConversion+0x1e8> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002a08: 687b ldr r3, [r7, #4] 8002a0a: 6a9b ldr r3, [r3, #40] ; 0x28 8002a0c: f043 0201 orr.w r2, r3, #1 8002a10: 687b ldr r3, [r7, #4] 8002a12: 629a str r2, [r3, #40] ; 0x28 } } /* Return ADC state */ return HAL_OK; 8002a14: 2300 movs r3, #0 } 8002a16: 4618 mov r0, r3 8002a18: 371c adds r7, #28 8002a1a: 46bd mov sp, r7 8002a1c: bd90 pop {r4, r7, pc} 8002a1e: bf00 nop 8002a20: 20000058 .word 0x20000058 8002a24: 24924924 .word 0x24924924 8002a28: 00924924 .word 0x00924924 8002a2c: 12492492 .word 0x12492492 8002a30: 00492492 .word 0x00492492 8002a34: 00249249 .word 0x00249249 08002a38 <HAL_ADC_Start_IT>: * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { 8002a38: b580 push {r7, lr} 8002a3a: b084 sub sp, #16 8002a3c: af00 add r7, sp, #0 8002a3e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002a40: 2300 movs r3, #0 8002a42: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8002a44: 687b ldr r3, [r7, #4] 8002a46: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8002a4a: 2b01 cmp r3, #1 8002a4c: d101 bne.n 8002a52 <HAL_ADC_Start_IT+0x1a> 8002a4e: 2302 movs r3, #2 8002a50: e0a0 b.n 8002b94 <HAL_ADC_Start_IT+0x15c> 8002a52: 687b ldr r3, [r7, #4] 8002a54: 2201 movs r2, #1 8002a56: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8002a5a: 6878 ldr r0, [r7, #4] 8002a5c: f000 fa7c bl 8002f58 <ADC_Enable> 8002a60: 4603 mov r3, r0 8002a62: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8002a64: 7bfb ldrb r3, [r7, #15] 8002a66: 2b00 cmp r3, #0 8002a68: f040 808f bne.w 8002b8a <HAL_ADC_Start_IT+0x152> { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8002a6c: 687b ldr r3, [r7, #4] 8002a6e: 6a9b ldr r3, [r3, #40] ; 0x28 8002a70: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8002a74: f023 0301 bic.w r3, r3, #1 8002a78: f443 7280 orr.w r2, r3, #256 ; 0x100 8002a7c: 687b ldr r3, [r7, #4] 8002a7e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8002a80: 687b ldr r3, [r7, #4] 8002a82: 681b ldr r3, [r3, #0] 8002a84: 4a45 ldr r2, [pc, #276] ; (8002b9c <HAL_ADC_Start_IT+0x164>) 8002a86: 4293 cmp r3, r2 8002a88: d105 bne.n 8002a96 <HAL_ADC_Start_IT+0x5e> 8002a8a: 4b45 ldr r3, [pc, #276] ; (8002ba0 <HAL_ADC_Start_IT+0x168>) 8002a8c: 685b ldr r3, [r3, #4] 8002a8e: f403 2370 and.w r3, r3, #983040 ; 0xf0000 8002a92: 2b00 cmp r3, #0 8002a94: d115 bne.n 8002ac2 <HAL_ADC_Start_IT+0x8a> { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002a96: 687b ldr r3, [r7, #4] 8002a98: 6a9b ldr r3, [r3, #40] ; 0x28 8002a9a: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8002a9e: 687b ldr r3, [r7, #4] 8002aa0: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8002aa2: 687b ldr r3, [r7, #4] 8002aa4: 681b ldr r3, [r3, #0] 8002aa6: 685b ldr r3, [r3, #4] 8002aa8: f403 6380 and.w r3, r3, #1024 ; 0x400 8002aac: 2b00 cmp r3, #0 8002aae: d026 beq.n 8002afe <HAL_ADC_Start_IT+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8002ab0: 687b ldr r3, [r7, #4] 8002ab2: 6a9b ldr r3, [r3, #40] ; 0x28 8002ab4: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8002ab8: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8002abc: 687b ldr r3, [r7, #4] 8002abe: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8002ac0: e01d b.n 8002afe <HAL_ADC_Start_IT+0xc6> } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002ac2: 687b ldr r3, [r7, #4] 8002ac4: 6a9b ldr r3, [r3, #40] ; 0x28 8002ac6: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8002aca: 687b ldr r3, [r7, #4] 8002acc: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8002ace: 687b ldr r3, [r7, #4] 8002ad0: 681b ldr r3, [r3, #0] 8002ad2: 4a33 ldr r2, [pc, #204] ; (8002ba0 <HAL_ADC_Start_IT+0x168>) 8002ad4: 4293 cmp r3, r2 8002ad6: d004 beq.n 8002ae2 <HAL_ADC_Start_IT+0xaa> 8002ad8: 687b ldr r3, [r7, #4] 8002ada: 681b ldr r3, [r3, #0] 8002adc: 4a2f ldr r2, [pc, #188] ; (8002b9c <HAL_ADC_Start_IT+0x164>) 8002ade: 4293 cmp r3, r2 8002ae0: d10d bne.n 8002afe <HAL_ADC_Start_IT+0xc6> 8002ae2: 4b2f ldr r3, [pc, #188] ; (8002ba0 <HAL_ADC_Start_IT+0x168>) 8002ae4: 685b ldr r3, [r3, #4] 8002ae6: f403 6380 and.w r3, r3, #1024 ; 0x400 8002aea: 2b00 cmp r3, #0 8002aec: d007 beq.n 8002afe <HAL_ADC_Start_IT+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8002aee: 687b ldr r3, [r7, #4] 8002af0: 6a9b ldr r3, [r3, #40] ; 0x28 8002af2: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8002af6: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8002afa: 687b ldr r3, [r7, #4] 8002afc: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002afe: 687b ldr r3, [r7, #4] 8002b00: 6a9b ldr r3, [r3, #40] ; 0x28 8002b02: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002b06: 2b00 cmp r3, #0 8002b08: d006 beq.n 8002b18 <HAL_ADC_Start_IT+0xe0> { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8002b0a: 687b ldr r3, [r7, #4] 8002b0c: 6adb ldr r3, [r3, #44] ; 0x2c 8002b0e: f023 0206 bic.w r2, r3, #6 8002b12: 687b ldr r3, [r7, #4] 8002b14: 62da str r2, [r3, #44] ; 0x2c 8002b16: e002 b.n 8002b1e <HAL_ADC_Start_IT+0xe6> } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8002b18: 687b ldr r3, [r7, #4] 8002b1a: 2200 movs r2, #0 8002b1c: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8002b1e: 687b ldr r3, [r7, #4] 8002b20: 2200 movs r2, #0 8002b22: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8002b26: 687b ldr r3, [r7, #4] 8002b28: 681b ldr r3, [r3, #0] 8002b2a: f06f 0202 mvn.w r2, #2 8002b2e: 601a str r2, [r3, #0] /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); 8002b30: 687b ldr r3, [r7, #4] 8002b32: 681b ldr r3, [r3, #0] 8002b34: 685a ldr r2, [r3, #4] 8002b36: 687b ldr r3, [r7, #4] 8002b38: 681b ldr r3, [r3, #0] 8002b3a: f042 0220 orr.w r2, r2, #32 8002b3e: 605a str r2, [r3, #4] /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002b40: 687b ldr r3, [r7, #4] 8002b42: 681b ldr r3, [r3, #0] 8002b44: 689b ldr r3, [r3, #8] 8002b46: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8002b4a: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002b4e: d113 bne.n 8002b78 <HAL_ADC_Start_IT+0x140> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8002b50: 687b ldr r3, [r7, #4] 8002b52: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002b54: 4a11 ldr r2, [pc, #68] ; (8002b9c <HAL_ADC_Start_IT+0x164>) 8002b56: 4293 cmp r3, r2 8002b58: d105 bne.n 8002b66 <HAL_ADC_Start_IT+0x12e> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8002b5a: 4b11 ldr r3, [pc, #68] ; (8002ba0 <HAL_ADC_Start_IT+0x168>) 8002b5c: 685b ldr r3, [r3, #4] 8002b5e: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002b62: 2b00 cmp r3, #0 8002b64: d108 bne.n 8002b78 <HAL_ADC_Start_IT+0x140> { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8002b66: 687b ldr r3, [r7, #4] 8002b68: 681b ldr r3, [r3, #0] 8002b6a: 689a ldr r2, [r3, #8] 8002b6c: 687b ldr r3, [r7, #4] 8002b6e: 681b ldr r3, [r3, #0] 8002b70: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8002b74: 609a str r2, [r3, #8] 8002b76: e00c b.n 8002b92 <HAL_ADC_Start_IT+0x15a> } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8002b78: 687b ldr r3, [r7, #4] 8002b7a: 681b ldr r3, [r3, #0] 8002b7c: 689a ldr r2, [r3, #8] 8002b7e: 687b ldr r3, [r7, #4] 8002b80: 681b ldr r3, [r3, #0] 8002b82: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8002b86: 609a str r2, [r3, #8] 8002b88: e003 b.n 8002b92 <HAL_ADC_Start_IT+0x15a> } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8002b8a: 687b ldr r3, [r7, #4] 8002b8c: 2200 movs r2, #0 8002b8e: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 8002b92: 7bfb ldrb r3, [r7, #15] } 8002b94: 4618 mov r0, r3 8002b96: 3710 adds r7, #16 8002b98: 46bd mov sp, r7 8002b9a: bd80 pop {r7, pc} 8002b9c: 40012800 .word 0x40012800 8002ba0: 40012400 .word 0x40012400 08002ba4 <HAL_ADC_GetValue>: * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8002ba4: b480 push {r7} 8002ba6: b083 sub sp, #12 8002ba8: af00 add r7, sp, #0 8002baa: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8002bac: 687b ldr r3, [r7, #4] 8002bae: 681b ldr r3, [r3, #0] 8002bb0: 6cdb ldr r3, [r3, #76] ; 0x4c } 8002bb2: 4618 mov r0, r3 8002bb4: 370c adds r7, #12 8002bb6: 46bd mov sp, r7 8002bb8: bc80 pop {r7} 8002bba: 4770 bx lr 08002bbc <HAL_ADC_IRQHandler>: * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 8002bbc: b580 push {r7, lr} 8002bbe: b082 sub sp, #8 8002bc0: af00 add r7, sp, #0 8002bc2: 6078 str r0, [r7, #4] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) 8002bc4: 687b ldr r3, [r7, #4] 8002bc6: 681b ldr r3, [r3, #0] 8002bc8: 685b ldr r3, [r3, #4] 8002bca: f003 0320 and.w r3, r3, #32 8002bce: 2b20 cmp r3, #32 8002bd0: d140 bne.n 8002c54 <HAL_ADC_IRQHandler+0x98> { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) 8002bd2: 687b ldr r3, [r7, #4] 8002bd4: 681b ldr r3, [r3, #0] 8002bd6: 681b ldr r3, [r3, #0] 8002bd8: f003 0302 and.w r3, r3, #2 8002bdc: 2b02 cmp r3, #2 8002bde: d139 bne.n 8002c54 <HAL_ADC_IRQHandler+0x98> { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8002be0: 687b ldr r3, [r7, #4] 8002be2: 6a9b ldr r3, [r3, #40] ; 0x28 8002be4: f003 0310 and.w r3, r3, #16 8002be8: 2b00 cmp r3, #0 8002bea: d105 bne.n 8002bf8 <HAL_ADC_IRQHandler+0x3c> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002bec: 687b ldr r3, [r7, #4] 8002bee: 6a9b ldr r3, [r3, #40] ; 0x28 8002bf0: f443 7200 orr.w r2, r3, #512 ; 0x200 8002bf4: 687b ldr r3, [r7, #4] 8002bf6: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002bf8: 687b ldr r3, [r7, #4] 8002bfa: 681b ldr r3, [r3, #0] 8002bfc: 689b ldr r3, [r3, #8] 8002bfe: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8002c02: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002c06: d11d bne.n 8002c44 <HAL_ADC_IRQHandler+0x88> (hadc->Init.ContinuousConvMode == DISABLE) ) 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002c0c: 2b00 cmp r3, #0 8002c0e: d119 bne.n 8002c44 <HAL_ADC_IRQHandler+0x88> { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 8002c10: 687b ldr r3, [r7, #4] 8002c12: 681b ldr r3, [r3, #0] 8002c14: 685a ldr r2, [r3, #4] 8002c16: 687b ldr r3, [r7, #4] 8002c18: 681b ldr r3, [r3, #0] 8002c1a: f022 0220 bic.w r2, r2, #32 8002c1e: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8002c20: 687b ldr r3, [r7, #4] 8002c22: 6a9b ldr r3, [r3, #40] ; 0x28 8002c24: f423 7280 bic.w r2, r3, #256 ; 0x100 8002c28: 687b ldr r3, [r7, #4] 8002c2a: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002c2c: 687b ldr r3, [r7, #4] 8002c2e: 6a9b ldr r3, [r3, #40] ; 0x28 8002c30: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002c34: 2b00 cmp r3, #0 8002c36: d105 bne.n 8002c44 <HAL_ADC_IRQHandler+0x88> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002c38: 687b ldr r3, [r7, #4] 8002c3a: 6a9b ldr r3, [r3, #40] ; 0x28 8002c3c: f043 0201 orr.w r2, r3, #1 8002c40: 687b ldr r3, [r7, #4] 8002c42: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8002c44: 6878 ldr r0, [r7, #4] 8002c46: f000 f87c bl 8002d42 <HAL_ADC_ConvCpltCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 681b ldr r3, [r3, #0] 8002c4e: f06f 0212 mvn.w r2, #18 8002c52: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) 8002c54: 687b ldr r3, [r7, #4] 8002c56: 681b ldr r3, [r3, #0] 8002c58: 685b ldr r3, [r3, #4] 8002c5a: f003 0380 and.w r3, r3, #128 ; 0x80 8002c5e: 2b80 cmp r3, #128 ; 0x80 8002c60: d14f bne.n 8002d02 <HAL_ADC_IRQHandler+0x146> { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) 8002c62: 687b ldr r3, [r7, #4] 8002c64: 681b ldr r3, [r3, #0] 8002c66: 681b ldr r3, [r3, #0] 8002c68: f003 0304 and.w r3, r3, #4 8002c6c: 2b04 cmp r3, #4 8002c6e: d148 bne.n 8002d02 <HAL_ADC_IRQHandler+0x146> { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8002c70: 687b ldr r3, [r7, #4] 8002c72: 6a9b ldr r3, [r3, #40] ; 0x28 8002c74: f003 0310 and.w r3, r3, #16 8002c78: 2b00 cmp r3, #0 8002c7a: d105 bne.n 8002c88 <HAL_ADC_IRQHandler+0xcc> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 8002c7c: 687b ldr r3, [r7, #4] 8002c7e: 6a9b ldr r3, [r3, #40] ; 0x28 8002c80: f443 5200 orr.w r2, r3, #8192 ; 0x2000 8002c84: 687b ldr r3, [r7, #4] 8002c86: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 8002c88: 687b ldr r3, [r7, #4] 8002c8a: 681b ldr r3, [r3, #0] 8002c8c: 689b ldr r3, [r3, #8] 8002c8e: f403 43e0 and.w r3, r3, #28672 ; 0x7000 8002c92: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 8002c96: d012 beq.n 8002cbe <HAL_ADC_IRQHandler+0x102> (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 8002c98: 687b ldr r3, [r7, #4] 8002c9a: 681b ldr r3, [r3, #0] 8002c9c: 685b ldr r3, [r3, #4] 8002c9e: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 8002ca2: 2b00 cmp r3, #0 8002ca4: d125 bne.n 8002cf2 <HAL_ADC_IRQHandler+0x136> (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: 681b ldr r3, [r3, #0] 8002caa: 689b ldr r3, [r3, #8] 8002cac: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 8002cb0: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002cb4: d11d bne.n 8002cf2 <HAL_ADC_IRQHandler+0x136> (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 8002cb6: 687b ldr r3, [r7, #4] 8002cb8: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002cba: 2b00 cmp r3, #0 8002cbc: d119 bne.n 8002cf2 <HAL_ADC_IRQHandler+0x136> { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 8002cbe: 687b ldr r3, [r7, #4] 8002cc0: 681b ldr r3, [r3, #0] 8002cc2: 685a ldr r2, [r3, #4] 8002cc4: 687b ldr r3, [r7, #4] 8002cc6: 681b ldr r3, [r3, #0] 8002cc8: f022 0280 bic.w r2, r2, #128 ; 0x80 8002ccc: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 8002cce: 687b ldr r3, [r7, #4] 8002cd0: 6a9b ldr r3, [r3, #40] ; 0x28 8002cd2: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8002cd6: 687b ldr r3, [r7, #4] 8002cd8: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 8002cda: 687b ldr r3, [r7, #4] 8002cdc: 6a9b ldr r3, [r3, #40] ; 0x28 8002cde: f403 7380 and.w r3, r3, #256 ; 0x100 8002ce2: 2b00 cmp r3, #0 8002ce4: d105 bne.n 8002cf2 <HAL_ADC_IRQHandler+0x136> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 6a9b ldr r3, [r3, #40] ; 0x28 8002cea: f043 0201 orr.w r2, r3, #1 8002cee: 687b ldr r3, [r7, #4] 8002cf0: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 8002cf2: 6878 ldr r0, [r7, #4] 8002cf4: f000 f9cb bl 800308e <HAL_ADCEx_InjectedConvCpltCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 681b ldr r3, [r3, #0] 8002cfc: f06f 020c mvn.w r2, #12 8002d00: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) 8002d02: 687b ldr r3, [r7, #4] 8002d04: 681b ldr r3, [r3, #0] 8002d06: 685b ldr r3, [r3, #4] 8002d08: f003 0340 and.w r3, r3, #64 ; 0x40 8002d0c: 2b40 cmp r3, #64 ; 0x40 8002d0e: d114 bne.n 8002d3a <HAL_ADC_IRQHandler+0x17e> { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 8002d10: 687b ldr r3, [r7, #4] 8002d12: 681b ldr r3, [r3, #0] 8002d14: 681b ldr r3, [r3, #0] 8002d16: f003 0301 and.w r3, r3, #1 8002d1a: 2b01 cmp r3, #1 8002d1c: d10d bne.n 8002d3a <HAL_ADC_IRQHandler+0x17e> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 6a9b ldr r3, [r3, #40] ; 0x28 8002d22: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8002d26: 687b ldr r3, [r7, #4] 8002d28: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8002d2a: 6878 ldr r0, [r7, #4] 8002d2c: f000 f812 bl 8002d54 <HAL_ADC_LevelOutOfWindowCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 8002d30: 687b ldr r3, [r7, #4] 8002d32: 681b ldr r3, [r3, #0] 8002d34: f06f 0201 mvn.w r2, #1 8002d38: 601a str r2, [r3, #0] } } } 8002d3a: bf00 nop 8002d3c: 3708 adds r7, #8 8002d3e: 46bd mov sp, r7 8002d40: bd80 pop {r7, pc} 08002d42 <HAL_ADC_ConvCpltCallback>: * @brief Conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 8002d42: b480 push {r7} 8002d44: b083 sub sp, #12 8002d46: af00 add r7, sp, #0 8002d48: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } 8002d4a: bf00 nop 8002d4c: 370c adds r7, #12 8002d4e: 46bd mov sp, r7 8002d50: bc80 pop {r7} 8002d52: 4770 bx lr 08002d54 <HAL_ADC_LevelOutOfWindowCallback>: * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 8002d54: b480 push {r7} 8002d56: b083 sub sp, #12 8002d58: af00 add r7, sp, #0 8002d5a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 8002d5c: bf00 nop 8002d5e: 370c adds r7, #12 8002d60: 46bd mov sp, r7 8002d62: bc80 pop {r7} 8002d64: 4770 bx lr ... 08002d68 <HAL_ADC_ConfigChannel>: * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002d68: b480 push {r7} 8002d6a: b085 sub sp, #20 8002d6c: af00 add r7, sp, #0 8002d6e: 6078 str r0, [r7, #4] 8002d70: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002d72: 2300 movs r3, #0 8002d74: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8002d76: 2300 movs r3, #0 8002d78: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8002d80: 2b01 cmp r3, #1 8002d82: d101 bne.n 8002d88 <HAL_ADC_ConfigChannel+0x20> 8002d84: 2302 movs r3, #2 8002d86: e0dc b.n 8002f42 <HAL_ADC_ConfigChannel+0x1da> 8002d88: 687b ldr r3, [r7, #4] 8002d8a: 2201 movs r2, #1 8002d8c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8002d90: 683b ldr r3, [r7, #0] 8002d92: 685b ldr r3, [r3, #4] 8002d94: 2b06 cmp r3, #6 8002d96: d81c bhi.n 8002dd2 <HAL_ADC_ConfigChannel+0x6a> { MODIFY_REG(hadc->Instance->SQR3 , 8002d98: 687b ldr r3, [r7, #4] 8002d9a: 681b ldr r3, [r3, #0] 8002d9c: 6b59 ldr r1, [r3, #52] ; 0x34 8002d9e: 683b ldr r3, [r7, #0] 8002da0: 685a ldr r2, [r3, #4] 8002da2: 4613 mov r3, r2 8002da4: 009b lsls r3, r3, #2 8002da6: 4413 add r3, r2 8002da8: 3b05 subs r3, #5 8002daa: 221f movs r2, #31 8002dac: fa02 f303 lsl.w r3, r2, r3 8002db0: 43db mvns r3, r3 8002db2: 4019 ands r1, r3 8002db4: 683b ldr r3, [r7, #0] 8002db6: 6818 ldr r0, [r3, #0] 8002db8: 683b ldr r3, [r7, #0] 8002dba: 685a ldr r2, [r3, #4] 8002dbc: 4613 mov r3, r2 8002dbe: 009b lsls r3, r3, #2 8002dc0: 4413 add r3, r2 8002dc2: 3b05 subs r3, #5 8002dc4: fa00 f203 lsl.w r2, r0, r3 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 430a orrs r2, r1 8002dce: 635a str r2, [r3, #52] ; 0x34 8002dd0: e03c b.n 8002e4c <HAL_ADC_ConfigChannel+0xe4> ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8002dd2: 683b ldr r3, [r7, #0] 8002dd4: 685b ldr r3, [r3, #4] 8002dd6: 2b0c cmp r3, #12 8002dd8: d81c bhi.n 8002e14 <HAL_ADC_ConfigChannel+0xac> { MODIFY_REG(hadc->Instance->SQR2 , 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 681b ldr r3, [r3, #0] 8002dde: 6b19 ldr r1, [r3, #48] ; 0x30 8002de0: 683b ldr r3, [r7, #0] 8002de2: 685a ldr r2, [r3, #4] 8002de4: 4613 mov r3, r2 8002de6: 009b lsls r3, r3, #2 8002de8: 4413 add r3, r2 8002dea: 3b23 subs r3, #35 ; 0x23 8002dec: 221f movs r2, #31 8002dee: fa02 f303 lsl.w r3, r2, r3 8002df2: 43db mvns r3, r3 8002df4: 4019 ands r1, r3 8002df6: 683b ldr r3, [r7, #0] 8002df8: 6818 ldr r0, [r3, #0] 8002dfa: 683b ldr r3, [r7, #0] 8002dfc: 685a ldr r2, [r3, #4] 8002dfe: 4613 mov r3, r2 8002e00: 009b lsls r3, r3, #2 8002e02: 4413 add r3, r2 8002e04: 3b23 subs r3, #35 ; 0x23 8002e06: fa00 f203 lsl.w r2, r0, r3 8002e0a: 687b ldr r3, [r7, #4] 8002e0c: 681b ldr r3, [r3, #0] 8002e0e: 430a orrs r2, r1 8002e10: 631a str r2, [r3, #48] ; 0x30 8002e12: e01b b.n 8002e4c <HAL_ADC_ConfigChannel+0xe4> ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8002e14: 687b ldr r3, [r7, #4] 8002e16: 681b ldr r3, [r3, #0] 8002e18: 6ad9 ldr r1, [r3, #44] ; 0x2c 8002e1a: 683b ldr r3, [r7, #0] 8002e1c: 685a ldr r2, [r3, #4] 8002e1e: 4613 mov r3, r2 8002e20: 009b lsls r3, r3, #2 8002e22: 4413 add r3, r2 8002e24: 3b41 subs r3, #65 ; 0x41 8002e26: 221f movs r2, #31 8002e28: fa02 f303 lsl.w r3, r2, r3 8002e2c: 43db mvns r3, r3 8002e2e: 4019 ands r1, r3 8002e30: 683b ldr r3, [r7, #0] 8002e32: 6818 ldr r0, [r3, #0] 8002e34: 683b ldr r3, [r7, #0] 8002e36: 685a ldr r2, [r3, #4] 8002e38: 4613 mov r3, r2 8002e3a: 009b lsls r3, r3, #2 8002e3c: 4413 add r3, r2 8002e3e: 3b41 subs r3, #65 ; 0x41 8002e40: fa00 f203 lsl.w r2, r0, r3 8002e44: 687b ldr r3, [r7, #4] 8002e46: 681b ldr r3, [r3, #0] 8002e48: 430a orrs r2, r1 8002e4a: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8002e4c: 683b ldr r3, [r7, #0] 8002e4e: 681b ldr r3, [r3, #0] 8002e50: 2b09 cmp r3, #9 8002e52: d91c bls.n 8002e8e <HAL_ADC_ConfigChannel+0x126> { MODIFY_REG(hadc->Instance->SMPR1 , 8002e54: 687b ldr r3, [r7, #4] 8002e56: 681b ldr r3, [r3, #0] 8002e58: 68d9 ldr r1, [r3, #12] 8002e5a: 683b ldr r3, [r7, #0] 8002e5c: 681a ldr r2, [r3, #0] 8002e5e: 4613 mov r3, r2 8002e60: 005b lsls r3, r3, #1 8002e62: 4413 add r3, r2 8002e64: 3b1e subs r3, #30 8002e66: 2207 movs r2, #7 8002e68: fa02 f303 lsl.w r3, r2, r3 8002e6c: 43db mvns r3, r3 8002e6e: 4019 ands r1, r3 8002e70: 683b ldr r3, [r7, #0] 8002e72: 6898 ldr r0, [r3, #8] 8002e74: 683b ldr r3, [r7, #0] 8002e76: 681a ldr r2, [r3, #0] 8002e78: 4613 mov r3, r2 8002e7a: 005b lsls r3, r3, #1 8002e7c: 4413 add r3, r2 8002e7e: 3b1e subs r3, #30 8002e80: fa00 f203 lsl.w r2, r0, r3 8002e84: 687b ldr r3, [r7, #4] 8002e86: 681b ldr r3, [r3, #0] 8002e88: 430a orrs r2, r1 8002e8a: 60da str r2, [r3, #12] 8002e8c: e019 b.n 8002ec2 <HAL_ADC_ConfigChannel+0x15a> ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8002e8e: 687b ldr r3, [r7, #4] 8002e90: 681b ldr r3, [r3, #0] 8002e92: 6919 ldr r1, [r3, #16] 8002e94: 683b ldr r3, [r7, #0] 8002e96: 681a ldr r2, [r3, #0] 8002e98: 4613 mov r3, r2 8002e9a: 005b lsls r3, r3, #1 8002e9c: 4413 add r3, r2 8002e9e: 2207 movs r2, #7 8002ea0: fa02 f303 lsl.w r3, r2, r3 8002ea4: 43db mvns r3, r3 8002ea6: 4019 ands r1, r3 8002ea8: 683b ldr r3, [r7, #0] 8002eaa: 6898 ldr r0, [r3, #8] 8002eac: 683b ldr r3, [r7, #0] 8002eae: 681a ldr r2, [r3, #0] 8002eb0: 4613 mov r3, r2 8002eb2: 005b lsls r3, r3, #1 8002eb4: 4413 add r3, r2 8002eb6: fa00 f203 lsl.w r2, r0, r3 8002eba: 687b ldr r3, [r7, #4] 8002ebc: 681b ldr r3, [r3, #0] 8002ebe: 430a orrs r2, r1 8002ec0: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002ec2: 683b ldr r3, [r7, #0] 8002ec4: 681b ldr r3, [r3, #0] 8002ec6: 2b10 cmp r3, #16 8002ec8: d003 beq.n 8002ed2 <HAL_ADC_ConfigChannel+0x16a> (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8002eca: 683b ldr r3, [r7, #0] 8002ecc: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002ece: 2b11 cmp r3, #17 8002ed0: d132 bne.n 8002f38 <HAL_ADC_ConfigChannel+0x1d0> { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8002ed2: 687b ldr r3, [r7, #4] 8002ed4: 681b ldr r3, [r3, #0] 8002ed6: 4a1d ldr r2, [pc, #116] ; (8002f4c <HAL_ADC_ConfigChannel+0x1e4>) 8002ed8: 4293 cmp r3, r2 8002eda: d125 bne.n 8002f28 <HAL_ADC_ConfigChannel+0x1c0> { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8002edc: 687b ldr r3, [r7, #4] 8002ede: 681b ldr r3, [r3, #0] 8002ee0: 689b ldr r3, [r3, #8] 8002ee2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8002ee6: 2b00 cmp r3, #0 8002ee8: d126 bne.n 8002f38 <HAL_ADC_ConfigChannel+0x1d0> { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8002eea: 687b ldr r3, [r7, #4] 8002eec: 681b ldr r3, [r3, #0] 8002eee: 689a ldr r2, [r3, #8] 8002ef0: 687b ldr r3, [r7, #4] 8002ef2: 681b ldr r3, [r3, #0] 8002ef4: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8002ef8: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8002efa: 683b ldr r3, [r7, #0] 8002efc: 681b ldr r3, [r3, #0] 8002efe: 2b10 cmp r3, #16 8002f00: d11a bne.n 8002f38 <HAL_ADC_ConfigChannel+0x1d0> { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8002f02: 4b13 ldr r3, [pc, #76] ; (8002f50 <HAL_ADC_ConfigChannel+0x1e8>) 8002f04: 681b ldr r3, [r3, #0] 8002f06: 4a13 ldr r2, [pc, #76] ; (8002f54 <HAL_ADC_ConfigChannel+0x1ec>) 8002f08: fba2 2303 umull r2, r3, r2, r3 8002f0c: 0c9a lsrs r2, r3, #18 8002f0e: 4613 mov r3, r2 8002f10: 009b lsls r3, r3, #2 8002f12: 4413 add r3, r2 8002f14: 005b lsls r3, r3, #1 8002f16: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f18: e002 b.n 8002f20 <HAL_ADC_ConfigChannel+0x1b8> { wait_loop_index--; 8002f1a: 68bb ldr r3, [r7, #8] 8002f1c: 3b01 subs r3, #1 8002f1e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f20: 68bb ldr r3, [r7, #8] 8002f22: 2b00 cmp r3, #0 8002f24: d1f9 bne.n 8002f1a <HAL_ADC_ConfigChannel+0x1b2> 8002f26: e007 b.n 8002f38 <HAL_ADC_ConfigChannel+0x1d0> } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002f28: 687b ldr r3, [r7, #4] 8002f2a: 6a9b ldr r3, [r3, #40] ; 0x28 8002f2c: f043 0220 orr.w r2, r3, #32 8002f30: 687b ldr r3, [r7, #4] 8002f32: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8002f34: 2301 movs r3, #1 8002f36: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002f38: 687b ldr r3, [r7, #4] 8002f3a: 2200 movs r2, #0 8002f3c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8002f40: 7bfb ldrb r3, [r7, #15] } 8002f42: 4618 mov r0, r3 8002f44: 3714 adds r7, #20 8002f46: 46bd mov sp, r7 8002f48: bc80 pop {r7} 8002f4a: 4770 bx lr 8002f4c: 40012400 .word 0x40012400 8002f50: 20000058 .word 0x20000058 8002f54: 431bde83 .word 0x431bde83 08002f58 <ADC_Enable>: * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8002f58: b580 push {r7, lr} 8002f5a: b084 sub sp, #16 8002f5c: af00 add r7, sp, #0 8002f5e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002f60: 2300 movs r3, #0 8002f62: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8002f64: 2300 movs r3, #0 8002f66: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8002f68: 687b ldr r3, [r7, #4] 8002f6a: 681b ldr r3, [r3, #0] 8002f6c: 689b ldr r3, [r3, #8] 8002f6e: f003 0301 and.w r3, r3, #1 8002f72: 2b01 cmp r3, #1 8002f74: d040 beq.n 8002ff8 <ADC_Enable+0xa0> { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8002f76: 687b ldr r3, [r7, #4] 8002f78: 681b ldr r3, [r3, #0] 8002f7a: 689a ldr r2, [r3, #8] 8002f7c: 687b ldr r3, [r7, #4] 8002f7e: 681b ldr r3, [r3, #0] 8002f80: f042 0201 orr.w r2, r2, #1 8002f84: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8002f86: 4b1f ldr r3, [pc, #124] ; (8003004 <ADC_Enable+0xac>) 8002f88: 681b ldr r3, [r3, #0] 8002f8a: 4a1f ldr r2, [pc, #124] ; (8003008 <ADC_Enable+0xb0>) 8002f8c: fba2 2303 umull r2, r3, r2, r3 8002f90: 0c9b lsrs r3, r3, #18 8002f92: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f94: e002 b.n 8002f9c <ADC_Enable+0x44> { wait_loop_index--; 8002f96: 68bb ldr r3, [r7, #8] 8002f98: 3b01 subs r3, #1 8002f9a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f9c: 68bb ldr r3, [r7, #8] 8002f9e: 2b00 cmp r3, #0 8002fa0: d1f9 bne.n 8002f96 <ADC_Enable+0x3e> } /* Get tick count */ tickstart = HAL_GetTick(); 8002fa2: f7ff fb3d bl 8002620 <HAL_GetTick> 8002fa6: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8002fa8: e01f b.n 8002fea <ADC_Enable+0x92> { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8002faa: f7ff fb39 bl 8002620 <HAL_GetTick> 8002fae: 4602 mov r2, r0 8002fb0: 68fb ldr r3, [r7, #12] 8002fb2: 1ad3 subs r3, r2, r3 8002fb4: 2b02 cmp r3, #2 8002fb6: d918 bls.n 8002fea <ADC_Enable+0x92> { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 8002fb8: 687b ldr r3, [r7, #4] 8002fba: 681b ldr r3, [r3, #0] 8002fbc: 689b ldr r3, [r3, #8] 8002fbe: f003 0301 and.w r3, r3, #1 8002fc2: 2b01 cmp r3, #1 8002fc4: d011 beq.n 8002fea <ADC_Enable+0x92> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 6a9b ldr r3, [r3, #40] ; 0x28 8002fca: f043 0210 orr.w r2, r3, #16 8002fce: 687b ldr r3, [r7, #4] 8002fd0: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002fd2: 687b ldr r3, [r7, #4] 8002fd4: 6adb ldr r3, [r3, #44] ; 0x2c 8002fd6: f043 0201 orr.w r2, r3, #1 8002fda: 687b ldr r3, [r7, #4] 8002fdc: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 2200 movs r2, #0 8002fe2: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002fe6: 2301 movs r3, #1 8002fe8: e007 b.n 8002ffa <ADC_Enable+0xa2> while(ADC_IS_ENABLE(hadc) == RESET) 8002fea: 687b ldr r3, [r7, #4] 8002fec: 681b ldr r3, [r3, #0] 8002fee: 689b ldr r3, [r3, #8] 8002ff0: f003 0301 and.w r3, r3, #1 8002ff4: 2b01 cmp r3, #1 8002ff6: d1d8 bne.n 8002faa <ADC_Enable+0x52> } } } /* Return HAL status */ return HAL_OK; 8002ff8: 2300 movs r3, #0 } 8002ffa: 4618 mov r0, r3 8002ffc: 3710 adds r7, #16 8002ffe: 46bd mov sp, r7 8003000: bd80 pop {r7, pc} 8003002: bf00 nop 8003004: 20000058 .word 0x20000058 8003008: 431bde83 .word 0x431bde83 0800300c <ADC_ConversionStop_Disable>: * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800300c: b580 push {r7, lr} 800300e: b084 sub sp, #16 8003010: af00 add r7, sp, #0 8003012: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003014: 2300 movs r3, #0 8003016: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8003018: 687b ldr r3, [r7, #4] 800301a: 681b ldr r3, [r3, #0] 800301c: 689b ldr r3, [r3, #8] 800301e: f003 0301 and.w r3, r3, #1 8003022: 2b01 cmp r3, #1 8003024: d12e bne.n 8003084 <ADC_ConversionStop_Disable+0x78> { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8003026: 687b ldr r3, [r7, #4] 8003028: 681b ldr r3, [r3, #0] 800302a: 689a ldr r2, [r3, #8] 800302c: 687b ldr r3, [r7, #4] 800302e: 681b ldr r3, [r3, #0] 8003030: f022 0201 bic.w r2, r2, #1 8003034: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8003036: f7ff faf3 bl 8002620 <HAL_GetTick> 800303a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800303c: e01b b.n 8003076 <ADC_ConversionStop_Disable+0x6a> { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800303e: f7ff faef bl 8002620 <HAL_GetTick> 8003042: 4602 mov r2, r0 8003044: 68fb ldr r3, [r7, #12] 8003046: 1ad3 subs r3, r2, r3 8003048: 2b02 cmp r3, #2 800304a: d914 bls.n 8003076 <ADC_ConversionStop_Disable+0x6a> { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800304c: 687b ldr r3, [r7, #4] 800304e: 681b ldr r3, [r3, #0] 8003050: 689b ldr r3, [r3, #8] 8003052: f003 0301 and.w r3, r3, #1 8003056: 2b01 cmp r3, #1 8003058: d10d bne.n 8003076 <ADC_ConversionStop_Disable+0x6a> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800305a: 687b ldr r3, [r7, #4] 800305c: 6a9b ldr r3, [r3, #40] ; 0x28 800305e: f043 0210 orr.w r2, r3, #16 8003062: 687b ldr r3, [r7, #4] 8003064: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003066: 687b ldr r3, [r7, #4] 8003068: 6adb ldr r3, [r3, #44] ; 0x2c 800306a: f043 0201 orr.w r2, r3, #1 800306e: 687b ldr r3, [r7, #4] 8003070: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8003072: 2301 movs r3, #1 8003074: e007 b.n 8003086 <ADC_ConversionStop_Disable+0x7a> while(ADC_IS_ENABLE(hadc) != RESET) 8003076: 687b ldr r3, [r7, #4] 8003078: 681b ldr r3, [r3, #0] 800307a: 689b ldr r3, [r3, #8] 800307c: f003 0301 and.w r3, r3, #1 8003080: 2b01 cmp r3, #1 8003082: d0dc beq.n 800303e <ADC_ConversionStop_Disable+0x32> } } } /* Return HAL status */ return HAL_OK; 8003084: 2300 movs r3, #0 } 8003086: 4618 mov r0, r3 8003088: 3710 adds r7, #16 800308a: 46bd mov sp, r7 800308c: bd80 pop {r7, pc} 0800308e <HAL_ADCEx_InjectedConvCpltCallback>: * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800308e: b480 push {r7} 8003090: b083 sub sp, #12 8003092: af00 add r7, sp, #0 8003094: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 8003096: bf00 nop 8003098: 370c adds r7, #12 800309a: 46bd mov sp, r7 800309c: bc80 pop {r7} 800309e: 4770 bx lr 080030a0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80030a0: b480 push {r7} 80030a2: b085 sub sp, #20 80030a4: af00 add r7, sp, #0 80030a6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80030a8: 687b ldr r3, [r7, #4] 80030aa: f003 0307 and.w r3, r3, #7 80030ae: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80030b0: 4b0c ldr r3, [pc, #48] ; (80030e4 <__NVIC_SetPriorityGrouping+0x44>) 80030b2: 68db ldr r3, [r3, #12] 80030b4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80030b6: 68ba ldr r2, [r7, #8] 80030b8: f64f 03ff movw r3, #63743 ; 0xf8ff 80030bc: 4013 ands r3, r2 80030be: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80030c0: 68fb ldr r3, [r7, #12] 80030c2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80030c4: 68bb ldr r3, [r7, #8] 80030c6: 4313 orrs r3, r2 reg_value = (reg_value | 80030c8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80030cc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80030d0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80030d2: 4a04 ldr r2, [pc, #16] ; (80030e4 <__NVIC_SetPriorityGrouping+0x44>) 80030d4: 68bb ldr r3, [r7, #8] 80030d6: 60d3 str r3, [r2, #12] } 80030d8: bf00 nop 80030da: 3714 adds r7, #20 80030dc: 46bd mov sp, r7 80030de: bc80 pop {r7} 80030e0: 4770 bx lr 80030e2: bf00 nop 80030e4: e000ed00 .word 0xe000ed00 080030e8 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80030e8: b480 push {r7} 80030ea: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80030ec: 4b04 ldr r3, [pc, #16] ; (8003100 <__NVIC_GetPriorityGrouping+0x18>) 80030ee: 68db ldr r3, [r3, #12] 80030f0: 0a1b lsrs r3, r3, #8 80030f2: f003 0307 and.w r3, r3, #7 } 80030f6: 4618 mov r0, r3 80030f8: 46bd mov sp, r7 80030fa: bc80 pop {r7} 80030fc: 4770 bx lr 80030fe: bf00 nop 8003100: e000ed00 .word 0xe000ed00 08003104 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8003104: b480 push {r7} 8003106: b083 sub sp, #12 8003108: af00 add r7, sp, #0 800310a: 4603 mov r3, r0 800310c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800310e: f997 3007 ldrsb.w r3, [r7, #7] 8003112: 2b00 cmp r3, #0 8003114: db0b blt.n 800312e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8003116: 79fb ldrb r3, [r7, #7] 8003118: f003 021f and.w r2, r3, #31 800311c: 4906 ldr r1, [pc, #24] ; (8003138 <__NVIC_EnableIRQ+0x34>) 800311e: f997 3007 ldrsb.w r3, [r7, #7] 8003122: 095b lsrs r3, r3, #5 8003124: 2001 movs r0, #1 8003126: fa00 f202 lsl.w r2, r0, r2 800312a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 800312e: bf00 nop 8003130: 370c adds r7, #12 8003132: 46bd mov sp, r7 8003134: bc80 pop {r7} 8003136: 4770 bx lr 8003138: e000e100 .word 0xe000e100 0800313c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800313c: b480 push {r7} 800313e: b083 sub sp, #12 8003140: af00 add r7, sp, #0 8003142: 4603 mov r3, r0 8003144: 6039 str r1, [r7, #0] 8003146: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003148: f997 3007 ldrsb.w r3, [r7, #7] 800314c: 2b00 cmp r3, #0 800314e: db0a blt.n 8003166 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003150: 683b ldr r3, [r7, #0] 8003152: b2da uxtb r2, r3 8003154: 490c ldr r1, [pc, #48] ; (8003188 <__NVIC_SetPriority+0x4c>) 8003156: f997 3007 ldrsb.w r3, [r7, #7] 800315a: 0112 lsls r2, r2, #4 800315c: b2d2 uxtb r2, r2 800315e: 440b add r3, r1 8003160: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8003164: e00a b.n 800317c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003166: 683b ldr r3, [r7, #0] 8003168: b2da uxtb r2, r3 800316a: 4908 ldr r1, [pc, #32] ; (800318c <__NVIC_SetPriority+0x50>) 800316c: 79fb ldrb r3, [r7, #7] 800316e: f003 030f and.w r3, r3, #15 8003172: 3b04 subs r3, #4 8003174: 0112 lsls r2, r2, #4 8003176: b2d2 uxtb r2, r2 8003178: 440b add r3, r1 800317a: 761a strb r2, [r3, #24] } 800317c: bf00 nop 800317e: 370c adds r7, #12 8003180: 46bd mov sp, r7 8003182: bc80 pop {r7} 8003184: 4770 bx lr 8003186: bf00 nop 8003188: e000e100 .word 0xe000e100 800318c: e000ed00 .word 0xe000ed00 08003190 <NVIC_EncodePriority>: \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8003190: b480 push {r7} 8003192: b089 sub sp, #36 ; 0x24 8003194: af00 add r7, sp, #0 8003196: 60f8 str r0, [r7, #12] 8003198: 60b9 str r1, [r7, #8] 800319a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800319c: 68fb ldr r3, [r7, #12] 800319e: f003 0307 and.w r3, r3, #7 80031a2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80031a4: 69fb ldr r3, [r7, #28] 80031a6: f1c3 0307 rsb r3, r3, #7 80031aa: 2b04 cmp r3, #4 80031ac: bf28 it cs 80031ae: 2304 movcs r3, #4 80031b0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80031b2: 69fb ldr r3, [r7, #28] 80031b4: 3304 adds r3, #4 80031b6: 2b06 cmp r3, #6 80031b8: d902 bls.n 80031c0 <NVIC_EncodePriority+0x30> 80031ba: 69fb ldr r3, [r7, #28] 80031bc: 3b03 subs r3, #3 80031be: e000 b.n 80031c2 <NVIC_EncodePriority+0x32> 80031c0: 2300 movs r3, #0 80031c2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80031c4: f04f 32ff mov.w r2, #4294967295 80031c8: 69bb ldr r3, [r7, #24] 80031ca: fa02 f303 lsl.w r3, r2, r3 80031ce: 43da mvns r2, r3 80031d0: 68bb ldr r3, [r7, #8] 80031d2: 401a ands r2, r3 80031d4: 697b ldr r3, [r7, #20] 80031d6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80031d8: f04f 31ff mov.w r1, #4294967295 80031dc: 697b ldr r3, [r7, #20] 80031de: fa01 f303 lsl.w r3, r1, r3 80031e2: 43d9 mvns r1, r3 80031e4: 687b ldr r3, [r7, #4] 80031e6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80031e8: 4313 orrs r3, r2 ); } 80031ea: 4618 mov r0, r3 80031ec: 3724 adds r7, #36 ; 0x24 80031ee: 46bd mov sp, r7 80031f0: bc80 pop {r7} 80031f2: 4770 bx lr 080031f4 <SysTick_Config>: \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80031f4: b580 push {r7, lr} 80031f6: b082 sub sp, #8 80031f8: af00 add r7, sp, #0 80031fa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80031fc: 687b ldr r3, [r7, #4] 80031fe: 3b01 subs r3, #1 8003200: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8003204: d301 bcc.n 800320a <SysTick_Config+0x16> { return (1UL); /* Reload value impossible */ 8003206: 2301 movs r3, #1 8003208: e00f b.n 800322a <SysTick_Config+0x36> } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800320a: 4a0a ldr r2, [pc, #40] ; (8003234 <SysTick_Config+0x40>) 800320c: 687b ldr r3, [r7, #4] 800320e: 3b01 subs r3, #1 8003210: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8003212: 210f movs r1, #15 8003214: f04f 30ff mov.w r0, #4294967295 8003218: f7ff ff90 bl 800313c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800321c: 4b05 ldr r3, [pc, #20] ; (8003234 <SysTick_Config+0x40>) 800321e: 2200 movs r2, #0 8003220: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8003222: 4b04 ldr r3, [pc, #16] ; (8003234 <SysTick_Config+0x40>) 8003224: 2207 movs r2, #7 8003226: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003228: 2300 movs r3, #0 } 800322a: 4618 mov r0, r3 800322c: 3708 adds r7, #8 800322e: 46bd mov sp, r7 8003230: bd80 pop {r7, pc} 8003232: bf00 nop 8003234: e000e010 .word 0xe000e010 08003238 <HAL_NVIC_SetPriorityGrouping>: * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003238: b580 push {r7, lr} 800323a: b082 sub sp, #8 800323c: af00 add r7, sp, #0 800323e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8003240: 6878 ldr r0, [r7, #4] 8003242: f7ff ff2d bl 80030a0 <__NVIC_SetPriorityGrouping> } 8003246: bf00 nop 8003248: 3708 adds r7, #8 800324a: 46bd mov sp, r7 800324c: bd80 pop {r7, pc} 0800324e <HAL_NVIC_SetPriority>: * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800324e: b580 push {r7, lr} 8003250: b086 sub sp, #24 8003252: af00 add r7, sp, #0 8003254: 4603 mov r3, r0 8003256: 60b9 str r1, [r7, #8] 8003258: 607a str r2, [r7, #4] 800325a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800325c: 2300 movs r3, #0 800325e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8003260: f7ff ff42 bl 80030e8 <__NVIC_GetPriorityGrouping> 8003264: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8003266: 687a ldr r2, [r7, #4] 8003268: 68b9 ldr r1, [r7, #8] 800326a: 6978 ldr r0, [r7, #20] 800326c: f7ff ff90 bl 8003190 <NVIC_EncodePriority> 8003270: 4602 mov r2, r0 8003272: f997 300f ldrsb.w r3, [r7, #15] 8003276: 4611 mov r1, r2 8003278: 4618 mov r0, r3 800327a: f7ff ff5f bl 800313c <__NVIC_SetPriority> } 800327e: bf00 nop 8003280: 3718 adds r7, #24 8003282: 46bd mov sp, r7 8003284: bd80 pop {r7, pc} 08003286 <HAL_NVIC_EnableIRQ>: * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8003286: b580 push {r7, lr} 8003288: b082 sub sp, #8 800328a: af00 add r7, sp, #0 800328c: 4603 mov r3, r0 800328e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8003290: f997 3007 ldrsb.w r3, [r7, #7] 8003294: 4618 mov r0, r3 8003296: f7ff ff35 bl 8003104 <__NVIC_EnableIRQ> } 800329a: bf00 nop 800329c: 3708 adds r7, #8 800329e: 46bd mov sp, r7 80032a0: bd80 pop {r7, pc} 080032a2 <HAL_SYSTICK_Config>: * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80032a2: b580 push {r7, lr} 80032a4: b082 sub sp, #8 80032a6: af00 add r7, sp, #0 80032a8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80032aa: 6878 ldr r0, [r7, #4] 80032ac: f7ff ffa2 bl 80031f4 <SysTick_Config> 80032b0: 4603 mov r3, r0 } 80032b2: 4618 mov r0, r3 80032b4: 3708 adds r7, #8 80032b6: 46bd mov sp, r7 80032b8: bd80 pop {r7, pc} ... 080032bc <HAL_DMA_Abort_IT>: * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80032bc: b580 push {r7, lr} 80032be: b084 sub sp, #16 80032c0: af00 add r7, sp, #0 80032c2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80032c4: 2300 movs r3, #0 80032c6: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 80032c8: 687b ldr r3, [r7, #4] 80032ca: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 80032ce: 2b02 cmp r3, #2 80032d0: d005 beq.n 80032de <HAL_DMA_Abort_IT+0x22> { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80032d2: 687b ldr r3, [r7, #4] 80032d4: 2204 movs r2, #4 80032d6: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 80032d8: 2301 movs r3, #1 80032da: 73fb strb r3, [r7, #15] 80032dc: e051 b.n 8003382 <HAL_DMA_Abort_IT+0xc6> } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80032de: 687b ldr r3, [r7, #4] 80032e0: 681b ldr r3, [r3, #0] 80032e2: 681a ldr r2, [r3, #0] 80032e4: 687b ldr r3, [r7, #4] 80032e6: 681b ldr r3, [r3, #0] 80032e8: f022 020e bic.w r2, r2, #14 80032ec: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80032ee: 687b ldr r3, [r7, #4] 80032f0: 681b ldr r3, [r3, #0] 80032f2: 681a ldr r2, [r3, #0] 80032f4: 687b ldr r3, [r7, #4] 80032f6: 681b ldr r3, [r3, #0] 80032f8: f022 0201 bic.w r2, r2, #1 80032fc: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80032fe: 687b ldr r3, [r7, #4] 8003300: 681b ldr r3, [r3, #0] 8003302: 4a22 ldr r2, [pc, #136] ; (800338c <HAL_DMA_Abort_IT+0xd0>) 8003304: 4293 cmp r3, r2 8003306: d029 beq.n 800335c <HAL_DMA_Abort_IT+0xa0> 8003308: 687b ldr r3, [r7, #4] 800330a: 681b ldr r3, [r3, #0] 800330c: 4a20 ldr r2, [pc, #128] ; (8003390 <HAL_DMA_Abort_IT+0xd4>) 800330e: 4293 cmp r3, r2 8003310: d022 beq.n 8003358 <HAL_DMA_Abort_IT+0x9c> 8003312: 687b ldr r3, [r7, #4] 8003314: 681b ldr r3, [r3, #0] 8003316: 4a1f ldr r2, [pc, #124] ; (8003394 <HAL_DMA_Abort_IT+0xd8>) 8003318: 4293 cmp r3, r2 800331a: d01a beq.n 8003352 <HAL_DMA_Abort_IT+0x96> 800331c: 687b ldr r3, [r7, #4] 800331e: 681b ldr r3, [r3, #0] 8003320: 4a1d ldr r2, [pc, #116] ; (8003398 <HAL_DMA_Abort_IT+0xdc>) 8003322: 4293 cmp r3, r2 8003324: d012 beq.n 800334c <HAL_DMA_Abort_IT+0x90> 8003326: 687b ldr r3, [r7, #4] 8003328: 681b ldr r3, [r3, #0] 800332a: 4a1c ldr r2, [pc, #112] ; (800339c <HAL_DMA_Abort_IT+0xe0>) 800332c: 4293 cmp r3, r2 800332e: d00a beq.n 8003346 <HAL_DMA_Abort_IT+0x8a> 8003330: 687b ldr r3, [r7, #4] 8003332: 681b ldr r3, [r3, #0] 8003334: 4a1a ldr r2, [pc, #104] ; (80033a0 <HAL_DMA_Abort_IT+0xe4>) 8003336: 4293 cmp r3, r2 8003338: d102 bne.n 8003340 <HAL_DMA_Abort_IT+0x84> 800333a: f44f 1380 mov.w r3, #1048576 ; 0x100000 800333e: e00e b.n 800335e <HAL_DMA_Abort_IT+0xa2> 8003340: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003344: e00b b.n 800335e <HAL_DMA_Abort_IT+0xa2> 8003346: f44f 3380 mov.w r3, #65536 ; 0x10000 800334a: e008 b.n 800335e <HAL_DMA_Abort_IT+0xa2> 800334c: f44f 5380 mov.w r3, #4096 ; 0x1000 8003350: e005 b.n 800335e <HAL_DMA_Abort_IT+0xa2> 8003352: f44f 7380 mov.w r3, #256 ; 0x100 8003356: e002 b.n 800335e <HAL_DMA_Abort_IT+0xa2> 8003358: 2310 movs r3, #16 800335a: e000 b.n 800335e <HAL_DMA_Abort_IT+0xa2> 800335c: 2301 movs r3, #1 800335e: 4a11 ldr r2, [pc, #68] ; (80033a4 <HAL_DMA_Abort_IT+0xe8>) 8003360: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003362: 687b ldr r3, [r7, #4] 8003364: 2201 movs r2, #1 8003366: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800336a: 687b ldr r3, [r7, #4] 800336c: 2200 movs r2, #0 800336e: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8003372: 687b ldr r3, [r7, #4] 8003374: 6b5b ldr r3, [r3, #52] ; 0x34 8003376: 2b00 cmp r3, #0 8003378: d003 beq.n 8003382 <HAL_DMA_Abort_IT+0xc6> { hdma->XferAbortCallback(hdma); 800337a: 687b ldr r3, [r7, #4] 800337c: 6b5b ldr r3, [r3, #52] ; 0x34 800337e: 6878 ldr r0, [r7, #4] 8003380: 4798 blx r3 } } return status; 8003382: 7bfb ldrb r3, [r7, #15] } 8003384: 4618 mov r0, r3 8003386: 3710 adds r7, #16 8003388: 46bd mov sp, r7 800338a: bd80 pop {r7, pc} 800338c: 40020008 .word 0x40020008 8003390: 4002001c .word 0x4002001c 8003394: 40020030 .word 0x40020030 8003398: 40020044 .word 0x40020044 800339c: 40020058 .word 0x40020058 80033a0: 4002006c .word 0x4002006c 80033a4: 40020000 .word 0x40020000 080033a8 <HAL_GPIO_Init>: * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80033a8: b480 push {r7} 80033aa: b08b sub sp, #44 ; 0x2c 80033ac: af00 add r7, sp, #0 80033ae: 6078 str r0, [r7, #4] 80033b0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80033b2: 2300 movs r3, #0 80033b4: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80033b6: 2300 movs r3, #0 80033b8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80033ba: e169 b.n 8003690 <HAL_GPIO_Init+0x2e8> { /* Get the IO position */ ioposition = (0x01uL << position); 80033bc: 2201 movs r2, #1 80033be: 6a7b ldr r3, [r7, #36] ; 0x24 80033c0: fa02 f303 lsl.w r3, r2, r3 80033c4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80033c6: 683b ldr r3, [r7, #0] 80033c8: 681b ldr r3, [r3, #0] 80033ca: 69fa ldr r2, [r7, #28] 80033cc: 4013 ands r3, r2 80033ce: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80033d0: 69ba ldr r2, [r7, #24] 80033d2: 69fb ldr r3, [r7, #28] 80033d4: 429a cmp r2, r3 80033d6: f040 8158 bne.w 800368a <HAL_GPIO_Init+0x2e2> { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80033da: 683b ldr r3, [r7, #0] 80033dc: 685b ldr r3, [r3, #4] 80033de: 4a9a ldr r2, [pc, #616] ; (8003648 <HAL_GPIO_Init+0x2a0>) 80033e0: 4293 cmp r3, r2 80033e2: d05e beq.n 80034a2 <HAL_GPIO_Init+0xfa> 80033e4: 4a98 ldr r2, [pc, #608] ; (8003648 <HAL_GPIO_Init+0x2a0>) 80033e6: 4293 cmp r3, r2 80033e8: d875 bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 80033ea: 4a98 ldr r2, [pc, #608] ; (800364c <HAL_GPIO_Init+0x2a4>) 80033ec: 4293 cmp r3, r2 80033ee: d058 beq.n 80034a2 <HAL_GPIO_Init+0xfa> 80033f0: 4a96 ldr r2, [pc, #600] ; (800364c <HAL_GPIO_Init+0x2a4>) 80033f2: 4293 cmp r3, r2 80033f4: d86f bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 80033f6: 4a96 ldr r2, [pc, #600] ; (8003650 <HAL_GPIO_Init+0x2a8>) 80033f8: 4293 cmp r3, r2 80033fa: d052 beq.n 80034a2 <HAL_GPIO_Init+0xfa> 80033fc: 4a94 ldr r2, [pc, #592] ; (8003650 <HAL_GPIO_Init+0x2a8>) 80033fe: 4293 cmp r3, r2 8003400: d869 bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 8003402: 4a94 ldr r2, [pc, #592] ; (8003654 <HAL_GPIO_Init+0x2ac>) 8003404: 4293 cmp r3, r2 8003406: d04c beq.n 80034a2 <HAL_GPIO_Init+0xfa> 8003408: 4a92 ldr r2, [pc, #584] ; (8003654 <HAL_GPIO_Init+0x2ac>) 800340a: 4293 cmp r3, r2 800340c: d863 bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 800340e: 4a92 ldr r2, [pc, #584] ; (8003658 <HAL_GPIO_Init+0x2b0>) 8003410: 4293 cmp r3, r2 8003412: d046 beq.n 80034a2 <HAL_GPIO_Init+0xfa> 8003414: 4a90 ldr r2, [pc, #576] ; (8003658 <HAL_GPIO_Init+0x2b0>) 8003416: 4293 cmp r3, r2 8003418: d85d bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 800341a: 2b12 cmp r3, #18 800341c: d82a bhi.n 8003474 <HAL_GPIO_Init+0xcc> 800341e: 2b12 cmp r3, #18 8003420: d859 bhi.n 80034d6 <HAL_GPIO_Init+0x12e> 8003422: a201 add r2, pc, #4 ; (adr r2, 8003428 <HAL_GPIO_Init+0x80>) 8003424: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003428: 080034a3 .word 0x080034a3 800342c: 0800347d .word 0x0800347d 8003430: 0800348f .word 0x0800348f 8003434: 080034d1 .word 0x080034d1 8003438: 080034d7 .word 0x080034d7 800343c: 080034d7 .word 0x080034d7 8003440: 080034d7 .word 0x080034d7 8003444: 080034d7 .word 0x080034d7 8003448: 080034d7 .word 0x080034d7 800344c: 080034d7 .word 0x080034d7 8003450: 080034d7 .word 0x080034d7 8003454: 080034d7 .word 0x080034d7 8003458: 080034d7 .word 0x080034d7 800345c: 080034d7 .word 0x080034d7 8003460: 080034d7 .word 0x080034d7 8003464: 080034d7 .word 0x080034d7 8003468: 080034d7 .word 0x080034d7 800346c: 08003485 .word 0x08003485 8003470: 08003499 .word 0x08003499 8003474: 4a79 ldr r2, [pc, #484] ; (800365c <HAL_GPIO_Init+0x2b4>) 8003476: 4293 cmp r3, r2 8003478: d013 beq.n 80034a2 <HAL_GPIO_Init+0xfa> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800347a: e02c b.n 80034d6 <HAL_GPIO_Init+0x12e> config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800347c: 683b ldr r3, [r7, #0] 800347e: 68db ldr r3, [r3, #12] 8003480: 623b str r3, [r7, #32] break; 8003482: e029 b.n 80034d8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8003484: 683b ldr r3, [r7, #0] 8003486: 68db ldr r3, [r3, #12] 8003488: 3304 adds r3, #4 800348a: 623b str r3, [r7, #32] break; 800348c: e024 b.n 80034d8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800348e: 683b ldr r3, [r7, #0] 8003490: 68db ldr r3, [r3, #12] 8003492: 3308 adds r3, #8 8003494: 623b str r3, [r7, #32] break; 8003496: e01f b.n 80034d8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8003498: 683b ldr r3, [r7, #0] 800349a: 68db ldr r3, [r3, #12] 800349c: 330c adds r3, #12 800349e: 623b str r3, [r7, #32] break; 80034a0: e01a b.n 80034d8 <HAL_GPIO_Init+0x130> if (GPIO_Init->Pull == GPIO_NOPULL) 80034a2: 683b ldr r3, [r7, #0] 80034a4: 689b ldr r3, [r3, #8] 80034a6: 2b00 cmp r3, #0 80034a8: d102 bne.n 80034b0 <HAL_GPIO_Init+0x108> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80034aa: 2304 movs r3, #4 80034ac: 623b str r3, [r7, #32] break; 80034ae: e013 b.n 80034d8 <HAL_GPIO_Init+0x130> else if (GPIO_Init->Pull == GPIO_PULLUP) 80034b0: 683b ldr r3, [r7, #0] 80034b2: 689b ldr r3, [r3, #8] 80034b4: 2b01 cmp r3, #1 80034b6: d105 bne.n 80034c4 <HAL_GPIO_Init+0x11c> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80034b8: 2308 movs r3, #8 80034ba: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80034bc: 687b ldr r3, [r7, #4] 80034be: 69fa ldr r2, [r7, #28] 80034c0: 611a str r2, [r3, #16] break; 80034c2: e009 b.n 80034d8 <HAL_GPIO_Init+0x130> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80034c4: 2308 movs r3, #8 80034c6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80034c8: 687b ldr r3, [r7, #4] 80034ca: 69fa ldr r2, [r7, #28] 80034cc: 615a str r2, [r3, #20] break; 80034ce: e003 b.n 80034d8 <HAL_GPIO_Init+0x130> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80034d0: 2300 movs r3, #0 80034d2: 623b str r3, [r7, #32] break; 80034d4: e000 b.n 80034d8 <HAL_GPIO_Init+0x130> break; 80034d6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80034d8: 69bb ldr r3, [r7, #24] 80034da: 2bff cmp r3, #255 ; 0xff 80034dc: d801 bhi.n 80034e2 <HAL_GPIO_Init+0x13a> 80034de: 687b ldr r3, [r7, #4] 80034e0: e001 b.n 80034e6 <HAL_GPIO_Init+0x13e> 80034e2: 687b ldr r3, [r7, #4] 80034e4: 3304 adds r3, #4 80034e6: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80034e8: 69bb ldr r3, [r7, #24] 80034ea: 2bff cmp r3, #255 ; 0xff 80034ec: d802 bhi.n 80034f4 <HAL_GPIO_Init+0x14c> 80034ee: 6a7b ldr r3, [r7, #36] ; 0x24 80034f0: 009b lsls r3, r3, #2 80034f2: e002 b.n 80034fa <HAL_GPIO_Init+0x152> 80034f4: 6a7b ldr r3, [r7, #36] ; 0x24 80034f6: 3b08 subs r3, #8 80034f8: 009b lsls r3, r3, #2 80034fa: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80034fc: 697b ldr r3, [r7, #20] 80034fe: 681a ldr r2, [r3, #0] 8003500: 210f movs r1, #15 8003502: 693b ldr r3, [r7, #16] 8003504: fa01 f303 lsl.w r3, r1, r3 8003508: 43db mvns r3, r3 800350a: 401a ands r2, r3 800350c: 6a39 ldr r1, [r7, #32] 800350e: 693b ldr r3, [r7, #16] 8003510: fa01 f303 lsl.w r3, r1, r3 8003514: 431a orrs r2, r3 8003516: 697b ldr r3, [r7, #20] 8003518: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800351a: 683b ldr r3, [r7, #0] 800351c: 685b ldr r3, [r3, #4] 800351e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003522: 2b00 cmp r3, #0 8003524: f000 80b1 beq.w 800368a <HAL_GPIO_Init+0x2e2> { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8003528: 4b4d ldr r3, [pc, #308] ; (8003660 <HAL_GPIO_Init+0x2b8>) 800352a: 699b ldr r3, [r3, #24] 800352c: 4a4c ldr r2, [pc, #304] ; (8003660 <HAL_GPIO_Init+0x2b8>) 800352e: f043 0301 orr.w r3, r3, #1 8003532: 6193 str r3, [r2, #24] 8003534: 4b4a ldr r3, [pc, #296] ; (8003660 <HAL_GPIO_Init+0x2b8>) 8003536: 699b ldr r3, [r3, #24] 8003538: f003 0301 and.w r3, r3, #1 800353c: 60bb str r3, [r7, #8] 800353e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8003540: 4a48 ldr r2, [pc, #288] ; (8003664 <HAL_GPIO_Init+0x2bc>) 8003542: 6a7b ldr r3, [r7, #36] ; 0x24 8003544: 089b lsrs r3, r3, #2 8003546: 3302 adds r3, #2 8003548: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800354c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800354e: 6a7b ldr r3, [r7, #36] ; 0x24 8003550: f003 0303 and.w r3, r3, #3 8003554: 009b lsls r3, r3, #2 8003556: 220f movs r2, #15 8003558: fa02 f303 lsl.w r3, r2, r3 800355c: 43db mvns r3, r3 800355e: 68fa ldr r2, [r7, #12] 8003560: 4013 ands r3, r2 8003562: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8003564: 687b ldr r3, [r7, #4] 8003566: 4a40 ldr r2, [pc, #256] ; (8003668 <HAL_GPIO_Init+0x2c0>) 8003568: 4293 cmp r3, r2 800356a: d013 beq.n 8003594 <HAL_GPIO_Init+0x1ec> 800356c: 687b ldr r3, [r7, #4] 800356e: 4a3f ldr r2, [pc, #252] ; (800366c <HAL_GPIO_Init+0x2c4>) 8003570: 4293 cmp r3, r2 8003572: d00d beq.n 8003590 <HAL_GPIO_Init+0x1e8> 8003574: 687b ldr r3, [r7, #4] 8003576: 4a3e ldr r2, [pc, #248] ; (8003670 <HAL_GPIO_Init+0x2c8>) 8003578: 4293 cmp r3, r2 800357a: d007 beq.n 800358c <HAL_GPIO_Init+0x1e4> 800357c: 687b ldr r3, [r7, #4] 800357e: 4a3d ldr r2, [pc, #244] ; (8003674 <HAL_GPIO_Init+0x2cc>) 8003580: 4293 cmp r3, r2 8003582: d101 bne.n 8003588 <HAL_GPIO_Init+0x1e0> 8003584: 2303 movs r3, #3 8003586: e006 b.n 8003596 <HAL_GPIO_Init+0x1ee> 8003588: 2304 movs r3, #4 800358a: e004 b.n 8003596 <HAL_GPIO_Init+0x1ee> 800358c: 2302 movs r3, #2 800358e: e002 b.n 8003596 <HAL_GPIO_Init+0x1ee> 8003590: 2301 movs r3, #1 8003592: e000 b.n 8003596 <HAL_GPIO_Init+0x1ee> 8003594: 2300 movs r3, #0 8003596: 6a7a ldr r2, [r7, #36] ; 0x24 8003598: f002 0203 and.w r2, r2, #3 800359c: 0092 lsls r2, r2, #2 800359e: 4093 lsls r3, r2 80035a0: 68fa ldr r2, [r7, #12] 80035a2: 4313 orrs r3, r2 80035a4: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80035a6: 492f ldr r1, [pc, #188] ; (8003664 <HAL_GPIO_Init+0x2bc>) 80035a8: 6a7b ldr r3, [r7, #36] ; 0x24 80035aa: 089b lsrs r3, r3, #2 80035ac: 3302 adds r3, #2 80035ae: 68fa ldr r2, [r7, #12] 80035b0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80035b4: 683b ldr r3, [r7, #0] 80035b6: 685b ldr r3, [r3, #4] 80035b8: f403 3380 and.w r3, r3, #65536 ; 0x10000 80035bc: 2b00 cmp r3, #0 80035be: d006 beq.n 80035ce <HAL_GPIO_Init+0x226> { SET_BIT(EXTI->IMR, iocurrent); 80035c0: 4b2d ldr r3, [pc, #180] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035c2: 681a ldr r2, [r3, #0] 80035c4: 492c ldr r1, [pc, #176] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035c6: 69bb ldr r3, [r7, #24] 80035c8: 4313 orrs r3, r2 80035ca: 600b str r3, [r1, #0] 80035cc: e006 b.n 80035dc <HAL_GPIO_Init+0x234> } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80035ce: 4b2a ldr r3, [pc, #168] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035d0: 681a ldr r2, [r3, #0] 80035d2: 69bb ldr r3, [r7, #24] 80035d4: 43db mvns r3, r3 80035d6: 4928 ldr r1, [pc, #160] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035d8: 4013 ands r3, r2 80035da: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80035dc: 683b ldr r3, [r7, #0] 80035de: 685b ldr r3, [r3, #4] 80035e0: f403 3300 and.w r3, r3, #131072 ; 0x20000 80035e4: 2b00 cmp r3, #0 80035e6: d006 beq.n 80035f6 <HAL_GPIO_Init+0x24e> { SET_BIT(EXTI->EMR, iocurrent); 80035e8: 4b23 ldr r3, [pc, #140] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035ea: 685a ldr r2, [r3, #4] 80035ec: 4922 ldr r1, [pc, #136] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035ee: 69bb ldr r3, [r7, #24] 80035f0: 4313 orrs r3, r2 80035f2: 604b str r3, [r1, #4] 80035f4: e006 b.n 8003604 <HAL_GPIO_Init+0x25c> } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80035f6: 4b20 ldr r3, [pc, #128] ; (8003678 <HAL_GPIO_Init+0x2d0>) 80035f8: 685a ldr r2, [r3, #4] 80035fa: 69bb ldr r3, [r7, #24] 80035fc: 43db mvns r3, r3 80035fe: 491e ldr r1, [pc, #120] ; (8003678 <HAL_GPIO_Init+0x2d0>) 8003600: 4013 ands r3, r2 8003602: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8003604: 683b ldr r3, [r7, #0] 8003606: 685b ldr r3, [r3, #4] 8003608: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800360c: 2b00 cmp r3, #0 800360e: d006 beq.n 800361e <HAL_GPIO_Init+0x276> { SET_BIT(EXTI->RTSR, iocurrent); 8003610: 4b19 ldr r3, [pc, #100] ; (8003678 <HAL_GPIO_Init+0x2d0>) 8003612: 689a ldr r2, [r3, #8] 8003614: 4918 ldr r1, [pc, #96] ; (8003678 <HAL_GPIO_Init+0x2d0>) 8003616: 69bb ldr r3, [r7, #24] 8003618: 4313 orrs r3, r2 800361a: 608b str r3, [r1, #8] 800361c: e006 b.n 800362c <HAL_GPIO_Init+0x284> } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800361e: 4b16 ldr r3, [pc, #88] ; (8003678 <HAL_GPIO_Init+0x2d0>) 8003620: 689a ldr r2, [r3, #8] 8003622: 69bb ldr r3, [r7, #24] 8003624: 43db mvns r3, r3 8003626: 4914 ldr r1, [pc, #80] ; (8003678 <HAL_GPIO_Init+0x2d0>) 8003628: 4013 ands r3, r2 800362a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800362c: 683b ldr r3, [r7, #0] 800362e: 685b ldr r3, [r3, #4] 8003630: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8003634: 2b00 cmp r3, #0 8003636: d021 beq.n 800367c <HAL_GPIO_Init+0x2d4> { SET_BIT(EXTI->FTSR, iocurrent); 8003638: 4b0f ldr r3, [pc, #60] ; (8003678 <HAL_GPIO_Init+0x2d0>) 800363a: 68da ldr r2, [r3, #12] 800363c: 490e ldr r1, [pc, #56] ; (8003678 <HAL_GPIO_Init+0x2d0>) 800363e: 69bb ldr r3, [r7, #24] 8003640: 4313 orrs r3, r2 8003642: 60cb str r3, [r1, #12] 8003644: e021 b.n 800368a <HAL_GPIO_Init+0x2e2> 8003646: bf00 nop 8003648: 10320000 .word 0x10320000 800364c: 10310000 .word 0x10310000 8003650: 10220000 .word 0x10220000 8003654: 10210000 .word 0x10210000 8003658: 10120000 .word 0x10120000 800365c: 10110000 .word 0x10110000 8003660: 40021000 .word 0x40021000 8003664: 40010000 .word 0x40010000 8003668: 40010800 .word 0x40010800 800366c: 40010c00 .word 0x40010c00 8003670: 40011000 .word 0x40011000 8003674: 40011400 .word 0x40011400 8003678: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800367c: 4b0b ldr r3, [pc, #44] ; (80036ac <HAL_GPIO_Init+0x304>) 800367e: 68da ldr r2, [r3, #12] 8003680: 69bb ldr r3, [r7, #24] 8003682: 43db mvns r3, r3 8003684: 4909 ldr r1, [pc, #36] ; (80036ac <HAL_GPIO_Init+0x304>) 8003686: 4013 ands r3, r2 8003688: 60cb str r3, [r1, #12] } } } position++; 800368a: 6a7b ldr r3, [r7, #36] ; 0x24 800368c: 3301 adds r3, #1 800368e: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8003690: 683b ldr r3, [r7, #0] 8003692: 681a ldr r2, [r3, #0] 8003694: 6a7b ldr r3, [r7, #36] ; 0x24 8003696: fa22 f303 lsr.w r3, r2, r3 800369a: 2b00 cmp r3, #0 800369c: f47f ae8e bne.w 80033bc <HAL_GPIO_Init+0x14> } } 80036a0: bf00 nop 80036a2: bf00 nop 80036a4: 372c adds r7, #44 ; 0x2c 80036a6: 46bd mov sp, r7 80036a8: bc80 pop {r7} 80036aa: 4770 bx lr 80036ac: 40010400 .word 0x40010400 080036b0 <HAL_GPIO_ReadPin>: * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80036b0: b480 push {r7} 80036b2: b085 sub sp, #20 80036b4: af00 add r7, sp, #0 80036b6: 6078 str r0, [r7, #4] 80036b8: 460b mov r3, r1 80036ba: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80036bc: 687b ldr r3, [r7, #4] 80036be: 689a ldr r2, [r3, #8] 80036c0: 887b ldrh r3, [r7, #2] 80036c2: 4013 ands r3, r2 80036c4: 2b00 cmp r3, #0 80036c6: d002 beq.n 80036ce <HAL_GPIO_ReadPin+0x1e> { bitstatus = GPIO_PIN_SET; 80036c8: 2301 movs r3, #1 80036ca: 73fb strb r3, [r7, #15] 80036cc: e001 b.n 80036d2 <HAL_GPIO_ReadPin+0x22> } else { bitstatus = GPIO_PIN_RESET; 80036ce: 2300 movs r3, #0 80036d0: 73fb strb r3, [r7, #15] } return bitstatus; 80036d2: 7bfb ldrb r3, [r7, #15] } 80036d4: 4618 mov r0, r3 80036d6: 3714 adds r7, #20 80036d8: 46bd mov sp, r7 80036da: bc80 pop {r7} 80036dc: 4770 bx lr 080036de <HAL_GPIO_WritePin>: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80036de: b480 push {r7} 80036e0: b083 sub sp, #12 80036e2: af00 add r7, sp, #0 80036e4: 6078 str r0, [r7, #4] 80036e6: 460b mov r3, r1 80036e8: 807b strh r3, [r7, #2] 80036ea: 4613 mov r3, r2 80036ec: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80036ee: 787b ldrb r3, [r7, #1] 80036f0: 2b00 cmp r3, #0 80036f2: d003 beq.n 80036fc <HAL_GPIO_WritePin+0x1e> { GPIOx->BSRR = GPIO_Pin; 80036f4: 887a ldrh r2, [r7, #2] 80036f6: 687b ldr r3, [r7, #4] 80036f8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 80036fa: e003 b.n 8003704 <HAL_GPIO_WritePin+0x26> GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 80036fc: 887b ldrh r3, [r7, #2] 80036fe: 041a lsls r2, r3, #16 8003700: 687b ldr r3, [r7, #4] 8003702: 611a str r2, [r3, #16] } 8003704: bf00 nop 8003706: 370c adds r7, #12 8003708: 46bd mov sp, r7 800370a: bc80 pop {r7} 800370c: 4770 bx lr 0800370e <HAL_GPIO_TogglePin>: * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800370e: b480 push {r7} 8003710: b085 sub sp, #20 8003712: af00 add r7, sp, #0 8003714: 6078 str r0, [r7, #4] 8003716: 460b mov r3, r1 8003718: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Ouput Data Register value */ odr = GPIOx->ODR; 800371a: 687b ldr r3, [r7, #4] 800371c: 68db ldr r3, [r3, #12] 800371e: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8003720: 887a ldrh r2, [r7, #2] 8003722: 68fb ldr r3, [r7, #12] 8003724: 4013 ands r3, r2 8003726: 041a lsls r2, r3, #16 8003728: 68fb ldr r3, [r7, #12] 800372a: 43d9 mvns r1, r3 800372c: 887b ldrh r3, [r7, #2] 800372e: 400b ands r3, r1 8003730: 431a orrs r2, r3 8003732: 687b ldr r3, [r7, #4] 8003734: 611a str r2, [r3, #16] } 8003736: bf00 nop 8003738: 3714 adds r7, #20 800373a: 46bd mov sp, r7 800373c: bc80 pop {r7} 800373e: 4770 bx lr 08003740 <HAL_GPIO_EXTI_IRQHandler>: * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8003740: b580 push {r7, lr} 8003742: b082 sub sp, #8 8003744: af00 add r7, sp, #0 8003746: 4603 mov r3, r0 8003748: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 800374a: 4b08 ldr r3, [pc, #32] ; (800376c <HAL_GPIO_EXTI_IRQHandler+0x2c>) 800374c: 695a ldr r2, [r3, #20] 800374e: 88fb ldrh r3, [r7, #6] 8003750: 4013 ands r3, r2 8003752: 2b00 cmp r3, #0 8003754: d006 beq.n 8003764 <HAL_GPIO_EXTI_IRQHandler+0x24> { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8003756: 4a05 ldr r2, [pc, #20] ; (800376c <HAL_GPIO_EXTI_IRQHandler+0x2c>) 8003758: 88fb ldrh r3, [r7, #6] 800375a: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 800375c: 88fb ldrh r3, [r7, #6] 800375e: 4618 mov r0, r3 8003760: f7fd fad6 bl 8000d10 <HAL_GPIO_EXTI_Callback> } } 8003764: bf00 nop 8003766: 3708 adds r7, #8 8003768: 46bd mov sp, r7 800376a: bd80 pop {r7, pc} 800376c: 40010400 .word 0x40010400 08003770 <HAL_RCC_OscConfig>: * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003770: b580 push {r7, lr} 8003772: b086 sub sp, #24 8003774: af00 add r7, sp, #0 8003776: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003778: 687b ldr r3, [r7, #4] 800377a: 2b00 cmp r3, #0 800377c: d101 bne.n 8003782 <HAL_RCC_OscConfig+0x12> { return HAL_ERROR; 800377e: 2301 movs r3, #1 8003780: e272 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003782: 687b ldr r3, [r7, #4] 8003784: 681b ldr r3, [r3, #0] 8003786: f003 0301 and.w r3, r3, #1 800378a: 2b00 cmp r3, #0 800378c: f000 8087 beq.w 800389e <HAL_RCC_OscConfig+0x12e> { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8003790: 4b92 ldr r3, [pc, #584] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003792: 685b ldr r3, [r3, #4] 8003794: f003 030c and.w r3, r3, #12 8003798: 2b04 cmp r3, #4 800379a: d00c beq.n 80037b6 <HAL_RCC_OscConfig+0x46> || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800379c: 4b8f ldr r3, [pc, #572] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 800379e: 685b ldr r3, [r3, #4] 80037a0: f003 030c and.w r3, r3, #12 80037a4: 2b08 cmp r3, #8 80037a6: d112 bne.n 80037ce <HAL_RCC_OscConfig+0x5e> 80037a8: 4b8c ldr r3, [pc, #560] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037aa: 685b ldr r3, [r3, #4] 80037ac: f403 3380 and.w r3, r3, #65536 ; 0x10000 80037b0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80037b4: d10b bne.n 80037ce <HAL_RCC_OscConfig+0x5e> { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80037b6: 4b89 ldr r3, [pc, #548] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037b8: 681b ldr r3, [r3, #0] 80037ba: f403 3300 and.w r3, r3, #131072 ; 0x20000 80037be: 2b00 cmp r3, #0 80037c0: d06c beq.n 800389c <HAL_RCC_OscConfig+0x12c> 80037c2: 687b ldr r3, [r7, #4] 80037c4: 685b ldr r3, [r3, #4] 80037c6: 2b00 cmp r3, #0 80037c8: d168 bne.n 800389c <HAL_RCC_OscConfig+0x12c> { return HAL_ERROR; 80037ca: 2301 movs r3, #1 80037cc: e24c b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80037ce: 687b ldr r3, [r7, #4] 80037d0: 685b ldr r3, [r3, #4] 80037d2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80037d6: d106 bne.n 80037e6 <HAL_RCC_OscConfig+0x76> 80037d8: 4b80 ldr r3, [pc, #512] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037da: 681b ldr r3, [r3, #0] 80037dc: 4a7f ldr r2, [pc, #508] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037de: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80037e2: 6013 str r3, [r2, #0] 80037e4: e02e b.n 8003844 <HAL_RCC_OscConfig+0xd4> 80037e6: 687b ldr r3, [r7, #4] 80037e8: 685b ldr r3, [r3, #4] 80037ea: 2b00 cmp r3, #0 80037ec: d10c bne.n 8003808 <HAL_RCC_OscConfig+0x98> 80037ee: 4b7b ldr r3, [pc, #492] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037f0: 681b ldr r3, [r3, #0] 80037f2: 4a7a ldr r2, [pc, #488] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037f4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80037f8: 6013 str r3, [r2, #0] 80037fa: 4b78 ldr r3, [pc, #480] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80037fc: 681b ldr r3, [r3, #0] 80037fe: 4a77 ldr r2, [pc, #476] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003800: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003804: 6013 str r3, [r2, #0] 8003806: e01d b.n 8003844 <HAL_RCC_OscConfig+0xd4> 8003808: 687b ldr r3, [r7, #4] 800380a: 685b ldr r3, [r3, #4] 800380c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003810: d10c bne.n 800382c <HAL_RCC_OscConfig+0xbc> 8003812: 4b72 ldr r3, [pc, #456] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003814: 681b ldr r3, [r3, #0] 8003816: 4a71 ldr r2, [pc, #452] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003818: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800381c: 6013 str r3, [r2, #0] 800381e: 4b6f ldr r3, [pc, #444] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003820: 681b ldr r3, [r3, #0] 8003822: 4a6e ldr r2, [pc, #440] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003824: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003828: 6013 str r3, [r2, #0] 800382a: e00b b.n 8003844 <HAL_RCC_OscConfig+0xd4> 800382c: 4b6b ldr r3, [pc, #428] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 800382e: 681b ldr r3, [r3, #0] 8003830: 4a6a ldr r2, [pc, #424] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003832: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003836: 6013 str r3, [r2, #0] 8003838: 4b68 ldr r3, [pc, #416] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 800383a: 681b ldr r3, [r3, #0] 800383c: 4a67 ldr r2, [pc, #412] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 800383e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003842: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003844: 687b ldr r3, [r7, #4] 8003846: 685b ldr r3, [r3, #4] 8003848: 2b00 cmp r3, #0 800384a: d013 beq.n 8003874 <HAL_RCC_OscConfig+0x104> { /* Get Start Tick */ tickstart = HAL_GetTick(); 800384c: f7fe fee8 bl 8002620 <HAL_GetTick> 8003850: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003852: e008 b.n 8003866 <HAL_RCC_OscConfig+0xf6> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003854: f7fe fee4 bl 8002620 <HAL_GetTick> 8003858: 4602 mov r2, r0 800385a: 693b ldr r3, [r7, #16] 800385c: 1ad3 subs r3, r2, r3 800385e: 2b64 cmp r3, #100 ; 0x64 8003860: d901 bls.n 8003866 <HAL_RCC_OscConfig+0xf6> { return HAL_TIMEOUT; 8003862: 2303 movs r3, #3 8003864: e200 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003866: 4b5d ldr r3, [pc, #372] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003868: 681b ldr r3, [r3, #0] 800386a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800386e: 2b00 cmp r3, #0 8003870: d0f0 beq.n 8003854 <HAL_RCC_OscConfig+0xe4> 8003872: e014 b.n 800389e <HAL_RCC_OscConfig+0x12e> } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003874: f7fe fed4 bl 8002620 <HAL_GetTick> 8003878: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800387a: e008 b.n 800388e <HAL_RCC_OscConfig+0x11e> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800387c: f7fe fed0 bl 8002620 <HAL_GetTick> 8003880: 4602 mov r2, r0 8003882: 693b ldr r3, [r7, #16] 8003884: 1ad3 subs r3, r2, r3 8003886: 2b64 cmp r3, #100 ; 0x64 8003888: d901 bls.n 800388e <HAL_RCC_OscConfig+0x11e> { return HAL_TIMEOUT; 800388a: 2303 movs r3, #3 800388c: e1ec b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800388e: 4b53 ldr r3, [pc, #332] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003890: 681b ldr r3, [r3, #0] 8003892: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003896: 2b00 cmp r3, #0 8003898: d1f0 bne.n 800387c <HAL_RCC_OscConfig+0x10c> 800389a: e000 b.n 800389e <HAL_RCC_OscConfig+0x12e> if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800389c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800389e: 687b ldr r3, [r7, #4] 80038a0: 681b ldr r3, [r3, #0] 80038a2: f003 0302 and.w r3, r3, #2 80038a6: 2b00 cmp r3, #0 80038a8: d063 beq.n 8003972 <HAL_RCC_OscConfig+0x202> /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80038aa: 4b4c ldr r3, [pc, #304] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038ac: 685b ldr r3, [r3, #4] 80038ae: f003 030c and.w r3, r3, #12 80038b2: 2b00 cmp r3, #0 80038b4: d00b beq.n 80038ce <HAL_RCC_OscConfig+0x15e> || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80038b6: 4b49 ldr r3, [pc, #292] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038b8: 685b ldr r3, [r3, #4] 80038ba: f003 030c and.w r3, r3, #12 80038be: 2b08 cmp r3, #8 80038c0: d11c bne.n 80038fc <HAL_RCC_OscConfig+0x18c> 80038c2: 4b46 ldr r3, [pc, #280] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038c4: 685b ldr r3, [r3, #4] 80038c6: f403 3380 and.w r3, r3, #65536 ; 0x10000 80038ca: 2b00 cmp r3, #0 80038cc: d116 bne.n 80038fc <HAL_RCC_OscConfig+0x18c> { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80038ce: 4b43 ldr r3, [pc, #268] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038d0: 681b ldr r3, [r3, #0] 80038d2: f003 0302 and.w r3, r3, #2 80038d6: 2b00 cmp r3, #0 80038d8: d005 beq.n 80038e6 <HAL_RCC_OscConfig+0x176> 80038da: 687b ldr r3, [r7, #4] 80038dc: 691b ldr r3, [r3, #16] 80038de: 2b01 cmp r3, #1 80038e0: d001 beq.n 80038e6 <HAL_RCC_OscConfig+0x176> { return HAL_ERROR; 80038e2: 2301 movs r3, #1 80038e4: e1c0 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80038e6: 4b3d ldr r3, [pc, #244] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038e8: 681b ldr r3, [r3, #0] 80038ea: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80038ee: 687b ldr r3, [r7, #4] 80038f0: 695b ldr r3, [r3, #20] 80038f2: 00db lsls r3, r3, #3 80038f4: 4939 ldr r1, [pc, #228] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80038f6: 4313 orrs r3, r2 80038f8: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80038fa: e03a b.n 8003972 <HAL_RCC_OscConfig+0x202> } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80038fc: 687b ldr r3, [r7, #4] 80038fe: 691b ldr r3, [r3, #16] 8003900: 2b00 cmp r3, #0 8003902: d020 beq.n 8003946 <HAL_RCC_OscConfig+0x1d6> { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003904: 4b36 ldr r3, [pc, #216] ; (80039e0 <HAL_RCC_OscConfig+0x270>) 8003906: 2201 movs r2, #1 8003908: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800390a: f7fe fe89 bl 8002620 <HAL_GetTick> 800390e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003910: e008 b.n 8003924 <HAL_RCC_OscConfig+0x1b4> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003912: f7fe fe85 bl 8002620 <HAL_GetTick> 8003916: 4602 mov r2, r0 8003918: 693b ldr r3, [r7, #16] 800391a: 1ad3 subs r3, r2, r3 800391c: 2b02 cmp r3, #2 800391e: d901 bls.n 8003924 <HAL_RCC_OscConfig+0x1b4> { return HAL_TIMEOUT; 8003920: 2303 movs r3, #3 8003922: e1a1 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003924: 4b2d ldr r3, [pc, #180] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003926: 681b ldr r3, [r3, #0] 8003928: f003 0302 and.w r3, r3, #2 800392c: 2b00 cmp r3, #0 800392e: d0f0 beq.n 8003912 <HAL_RCC_OscConfig+0x1a2> } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003930: 4b2a ldr r3, [pc, #168] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003932: 681b ldr r3, [r3, #0] 8003934: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003938: 687b ldr r3, [r7, #4] 800393a: 695b ldr r3, [r3, #20] 800393c: 00db lsls r3, r3, #3 800393e: 4927 ldr r1, [pc, #156] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003940: 4313 orrs r3, r2 8003942: 600b str r3, [r1, #0] 8003944: e015 b.n 8003972 <HAL_RCC_OscConfig+0x202> } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003946: 4b26 ldr r3, [pc, #152] ; (80039e0 <HAL_RCC_OscConfig+0x270>) 8003948: 2200 movs r2, #0 800394a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800394c: f7fe fe68 bl 8002620 <HAL_GetTick> 8003950: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003952: e008 b.n 8003966 <HAL_RCC_OscConfig+0x1f6> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003954: f7fe fe64 bl 8002620 <HAL_GetTick> 8003958: 4602 mov r2, r0 800395a: 693b ldr r3, [r7, #16] 800395c: 1ad3 subs r3, r2, r3 800395e: 2b02 cmp r3, #2 8003960: d901 bls.n 8003966 <HAL_RCC_OscConfig+0x1f6> { return HAL_TIMEOUT; 8003962: 2303 movs r3, #3 8003964: e180 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003966: 4b1d ldr r3, [pc, #116] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 8003968: 681b ldr r3, [r3, #0] 800396a: f003 0302 and.w r3, r3, #2 800396e: 2b00 cmp r3, #0 8003970: d1f0 bne.n 8003954 <HAL_RCC_OscConfig+0x1e4> } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003972: 687b ldr r3, [r7, #4] 8003974: 681b ldr r3, [r3, #0] 8003976: f003 0308 and.w r3, r3, #8 800397a: 2b00 cmp r3, #0 800397c: d03a beq.n 80039f4 <HAL_RCC_OscConfig+0x284> { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800397e: 687b ldr r3, [r7, #4] 8003980: 699b ldr r3, [r3, #24] 8003982: 2b00 cmp r3, #0 8003984: d019 beq.n 80039ba <HAL_RCC_OscConfig+0x24a> { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003986: 4b17 ldr r3, [pc, #92] ; (80039e4 <HAL_RCC_OscConfig+0x274>) 8003988: 2201 movs r2, #1 800398a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800398c: f7fe fe48 bl 8002620 <HAL_GetTick> 8003990: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8003992: e008 b.n 80039a6 <HAL_RCC_OscConfig+0x236> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003994: f7fe fe44 bl 8002620 <HAL_GetTick> 8003998: 4602 mov r2, r0 800399a: 693b ldr r3, [r7, #16] 800399c: 1ad3 subs r3, r2, r3 800399e: 2b02 cmp r3, #2 80039a0: d901 bls.n 80039a6 <HAL_RCC_OscConfig+0x236> { return HAL_TIMEOUT; 80039a2: 2303 movs r3, #3 80039a4: e160 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80039a6: 4b0d ldr r3, [pc, #52] ; (80039dc <HAL_RCC_OscConfig+0x26c>) 80039a8: 6a5b ldr r3, [r3, #36] ; 0x24 80039aa: f003 0302 and.w r3, r3, #2 80039ae: 2b00 cmp r3, #0 80039b0: d0f0 beq.n 8003994 <HAL_RCC_OscConfig+0x224> } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80039b2: 2001 movs r0, #1 80039b4: f000 fad8 bl 8003f68 <RCC_Delay> 80039b8: e01c b.n 80039f4 <HAL_RCC_OscConfig+0x284> } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80039ba: 4b0a ldr r3, [pc, #40] ; (80039e4 <HAL_RCC_OscConfig+0x274>) 80039bc: 2200 movs r2, #0 80039be: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80039c0: f7fe fe2e bl 8002620 <HAL_GetTick> 80039c4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80039c6: e00f b.n 80039e8 <HAL_RCC_OscConfig+0x278> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80039c8: f7fe fe2a bl 8002620 <HAL_GetTick> 80039cc: 4602 mov r2, r0 80039ce: 693b ldr r3, [r7, #16] 80039d0: 1ad3 subs r3, r2, r3 80039d2: 2b02 cmp r3, #2 80039d4: d908 bls.n 80039e8 <HAL_RCC_OscConfig+0x278> { return HAL_TIMEOUT; 80039d6: 2303 movs r3, #3 80039d8: e146 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> 80039da: bf00 nop 80039dc: 40021000 .word 0x40021000 80039e0: 42420000 .word 0x42420000 80039e4: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80039e8: 4b92 ldr r3, [pc, #584] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 80039ea: 6a5b ldr r3, [r3, #36] ; 0x24 80039ec: f003 0302 and.w r3, r3, #2 80039f0: 2b00 cmp r3, #0 80039f2: d1e9 bne.n 80039c8 <HAL_RCC_OscConfig+0x258> } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80039f4: 687b ldr r3, [r7, #4] 80039f6: 681b ldr r3, [r3, #0] 80039f8: f003 0304 and.w r3, r3, #4 80039fc: 2b00 cmp r3, #0 80039fe: f000 80a6 beq.w 8003b4e <HAL_RCC_OscConfig+0x3de> { FlagStatus pwrclkchanged = RESET; 8003a02: 2300 movs r3, #0 8003a04: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003a06: 4b8b ldr r3, [pc, #556] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a08: 69db ldr r3, [r3, #28] 8003a0a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003a0e: 2b00 cmp r3, #0 8003a10: d10d bne.n 8003a2e <HAL_RCC_OscConfig+0x2be> { __HAL_RCC_PWR_CLK_ENABLE(); 8003a12: 4b88 ldr r3, [pc, #544] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a14: 69db ldr r3, [r3, #28] 8003a16: 4a87 ldr r2, [pc, #540] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a18: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003a1c: 61d3 str r3, [r2, #28] 8003a1e: 4b85 ldr r3, [pc, #532] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a20: 69db ldr r3, [r3, #28] 8003a22: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003a26: 60bb str r3, [r7, #8] 8003a28: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003a2a: 2301 movs r3, #1 8003a2c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003a2e: 4b82 ldr r3, [pc, #520] ; (8003c38 <HAL_RCC_OscConfig+0x4c8>) 8003a30: 681b ldr r3, [r3, #0] 8003a32: f403 7380 and.w r3, r3, #256 ; 0x100 8003a36: 2b00 cmp r3, #0 8003a38: d118 bne.n 8003a6c <HAL_RCC_OscConfig+0x2fc> { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003a3a: 4b7f ldr r3, [pc, #508] ; (8003c38 <HAL_RCC_OscConfig+0x4c8>) 8003a3c: 681b ldr r3, [r3, #0] 8003a3e: 4a7e ldr r2, [pc, #504] ; (8003c38 <HAL_RCC_OscConfig+0x4c8>) 8003a40: f443 7380 orr.w r3, r3, #256 ; 0x100 8003a44: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003a46: f7fe fdeb bl 8002620 <HAL_GetTick> 8003a4a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003a4c: e008 b.n 8003a60 <HAL_RCC_OscConfig+0x2f0> { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003a4e: f7fe fde7 bl 8002620 <HAL_GetTick> 8003a52: 4602 mov r2, r0 8003a54: 693b ldr r3, [r7, #16] 8003a56: 1ad3 subs r3, r2, r3 8003a58: 2b64 cmp r3, #100 ; 0x64 8003a5a: d901 bls.n 8003a60 <HAL_RCC_OscConfig+0x2f0> { return HAL_TIMEOUT; 8003a5c: 2303 movs r3, #3 8003a5e: e103 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003a60: 4b75 ldr r3, [pc, #468] ; (8003c38 <HAL_RCC_OscConfig+0x4c8>) 8003a62: 681b ldr r3, [r3, #0] 8003a64: f403 7380 and.w r3, r3, #256 ; 0x100 8003a68: 2b00 cmp r3, #0 8003a6a: d0f0 beq.n 8003a4e <HAL_RCC_OscConfig+0x2de> } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003a6c: 687b ldr r3, [r7, #4] 8003a6e: 68db ldr r3, [r3, #12] 8003a70: 2b01 cmp r3, #1 8003a72: d106 bne.n 8003a82 <HAL_RCC_OscConfig+0x312> 8003a74: 4b6f ldr r3, [pc, #444] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a76: 6a1b ldr r3, [r3, #32] 8003a78: 4a6e ldr r2, [pc, #440] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a7a: f043 0301 orr.w r3, r3, #1 8003a7e: 6213 str r3, [r2, #32] 8003a80: e02d b.n 8003ade <HAL_RCC_OscConfig+0x36e> 8003a82: 687b ldr r3, [r7, #4] 8003a84: 68db ldr r3, [r3, #12] 8003a86: 2b00 cmp r3, #0 8003a88: d10c bne.n 8003aa4 <HAL_RCC_OscConfig+0x334> 8003a8a: 4b6a ldr r3, [pc, #424] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a8c: 6a1b ldr r3, [r3, #32] 8003a8e: 4a69 ldr r2, [pc, #420] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a90: f023 0301 bic.w r3, r3, #1 8003a94: 6213 str r3, [r2, #32] 8003a96: 4b67 ldr r3, [pc, #412] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a98: 6a1b ldr r3, [r3, #32] 8003a9a: 4a66 ldr r2, [pc, #408] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003a9c: f023 0304 bic.w r3, r3, #4 8003aa0: 6213 str r3, [r2, #32] 8003aa2: e01c b.n 8003ade <HAL_RCC_OscConfig+0x36e> 8003aa4: 687b ldr r3, [r7, #4] 8003aa6: 68db ldr r3, [r3, #12] 8003aa8: 2b05 cmp r3, #5 8003aaa: d10c bne.n 8003ac6 <HAL_RCC_OscConfig+0x356> 8003aac: 4b61 ldr r3, [pc, #388] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003aae: 6a1b ldr r3, [r3, #32] 8003ab0: 4a60 ldr r2, [pc, #384] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003ab2: f043 0304 orr.w r3, r3, #4 8003ab6: 6213 str r3, [r2, #32] 8003ab8: 4b5e ldr r3, [pc, #376] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003aba: 6a1b ldr r3, [r3, #32] 8003abc: 4a5d ldr r2, [pc, #372] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003abe: f043 0301 orr.w r3, r3, #1 8003ac2: 6213 str r3, [r2, #32] 8003ac4: e00b b.n 8003ade <HAL_RCC_OscConfig+0x36e> 8003ac6: 4b5b ldr r3, [pc, #364] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003ac8: 6a1b ldr r3, [r3, #32] 8003aca: 4a5a ldr r2, [pc, #360] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003acc: f023 0301 bic.w r3, r3, #1 8003ad0: 6213 str r3, [r2, #32] 8003ad2: 4b58 ldr r3, [pc, #352] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003ad4: 6a1b ldr r3, [r3, #32] 8003ad6: 4a57 ldr r2, [pc, #348] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003ad8: f023 0304 bic.w r3, r3, #4 8003adc: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003ade: 687b ldr r3, [r7, #4] 8003ae0: 68db ldr r3, [r3, #12] 8003ae2: 2b00 cmp r3, #0 8003ae4: d015 beq.n 8003b12 <HAL_RCC_OscConfig+0x3a2> { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003ae6: f7fe fd9b bl 8002620 <HAL_GetTick> 8003aea: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003aec: e00a b.n 8003b04 <HAL_RCC_OscConfig+0x394> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003aee: f7fe fd97 bl 8002620 <HAL_GetTick> 8003af2: 4602 mov r2, r0 8003af4: 693b ldr r3, [r7, #16] 8003af6: 1ad3 subs r3, r2, r3 8003af8: f241 3288 movw r2, #5000 ; 0x1388 8003afc: 4293 cmp r3, r2 8003afe: d901 bls.n 8003b04 <HAL_RCC_OscConfig+0x394> { return HAL_TIMEOUT; 8003b00: 2303 movs r3, #3 8003b02: e0b1 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003b04: 4b4b ldr r3, [pc, #300] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b06: 6a1b ldr r3, [r3, #32] 8003b08: f003 0302 and.w r3, r3, #2 8003b0c: 2b00 cmp r3, #0 8003b0e: d0ee beq.n 8003aee <HAL_RCC_OscConfig+0x37e> 8003b10: e014 b.n 8003b3c <HAL_RCC_OscConfig+0x3cc> } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003b12: f7fe fd85 bl 8002620 <HAL_GetTick> 8003b16: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003b18: e00a b.n 8003b30 <HAL_RCC_OscConfig+0x3c0> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003b1a: f7fe fd81 bl 8002620 <HAL_GetTick> 8003b1e: 4602 mov r2, r0 8003b20: 693b ldr r3, [r7, #16] 8003b22: 1ad3 subs r3, r2, r3 8003b24: f241 3288 movw r2, #5000 ; 0x1388 8003b28: 4293 cmp r3, r2 8003b2a: d901 bls.n 8003b30 <HAL_RCC_OscConfig+0x3c0> { return HAL_TIMEOUT; 8003b2c: 2303 movs r3, #3 8003b2e: e09b b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003b30: 4b40 ldr r3, [pc, #256] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b32: 6a1b ldr r3, [r3, #32] 8003b34: f003 0302 and.w r3, r3, #2 8003b38: 2b00 cmp r3, #0 8003b3a: d1ee bne.n 8003b1a <HAL_RCC_OscConfig+0x3aa> } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8003b3c: 7dfb ldrb r3, [r7, #23] 8003b3e: 2b01 cmp r3, #1 8003b40: d105 bne.n 8003b4e <HAL_RCC_OscConfig+0x3de> { __HAL_RCC_PWR_CLK_DISABLE(); 8003b42: 4b3c ldr r3, [pc, #240] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b44: 69db ldr r3, [r3, #28] 8003b46: 4a3b ldr r2, [pc, #236] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b48: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003b4c: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8003b4e: 687b ldr r3, [r7, #4] 8003b50: 69db ldr r3, [r3, #28] 8003b52: 2b00 cmp r3, #0 8003b54: f000 8087 beq.w 8003c66 <HAL_RCC_OscConfig+0x4f6> { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003b58: 4b36 ldr r3, [pc, #216] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b5a: 685b ldr r3, [r3, #4] 8003b5c: f003 030c and.w r3, r3, #12 8003b60: 2b08 cmp r3, #8 8003b62: d061 beq.n 8003c28 <HAL_RCC_OscConfig+0x4b8> { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003b64: 687b ldr r3, [r7, #4] 8003b66: 69db ldr r3, [r3, #28] 8003b68: 2b02 cmp r3, #2 8003b6a: d146 bne.n 8003bfa <HAL_RCC_OscConfig+0x48a> /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003b6c: 4b33 ldr r3, [pc, #204] ; (8003c3c <HAL_RCC_OscConfig+0x4cc>) 8003b6e: 2200 movs r2, #0 8003b70: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003b72: f7fe fd55 bl 8002620 <HAL_GetTick> 8003b76: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003b78: e008 b.n 8003b8c <HAL_RCC_OscConfig+0x41c> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003b7a: f7fe fd51 bl 8002620 <HAL_GetTick> 8003b7e: 4602 mov r2, r0 8003b80: 693b ldr r3, [r7, #16] 8003b82: 1ad3 subs r3, r2, r3 8003b84: 2b02 cmp r3, #2 8003b86: d901 bls.n 8003b8c <HAL_RCC_OscConfig+0x41c> { return HAL_TIMEOUT; 8003b88: 2303 movs r3, #3 8003b8a: e06d b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003b8c: 4b29 ldr r3, [pc, #164] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003b8e: 681b ldr r3, [r3, #0] 8003b90: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003b94: 2b00 cmp r3, #0 8003b96: d1f0 bne.n 8003b7a <HAL_RCC_OscConfig+0x40a> } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8003b98: 687b ldr r3, [r7, #4] 8003b9a: 6a1b ldr r3, [r3, #32] 8003b9c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003ba0: d108 bne.n 8003bb4 <HAL_RCC_OscConfig+0x444> /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8003ba2: 4b24 ldr r3, [pc, #144] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003ba4: 685b ldr r3, [r3, #4] 8003ba6: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8003baa: 687b ldr r3, [r7, #4] 8003bac: 689b ldr r3, [r3, #8] 8003bae: 4921 ldr r1, [pc, #132] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003bb0: 4313 orrs r3, r2 8003bb2: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003bb4: 4b1f ldr r3, [pc, #124] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003bb6: 685b ldr r3, [r3, #4] 8003bb8: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 8003bbc: 687b ldr r3, [r7, #4] 8003bbe: 6a19 ldr r1, [r3, #32] 8003bc0: 687b ldr r3, [r7, #4] 8003bc2: 6a5b ldr r3, [r3, #36] ; 0x24 8003bc4: 430b orrs r3, r1 8003bc6: 491b ldr r1, [pc, #108] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003bc8: 4313 orrs r3, r2 8003bca: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003bcc: 4b1b ldr r3, [pc, #108] ; (8003c3c <HAL_RCC_OscConfig+0x4cc>) 8003bce: 2201 movs r2, #1 8003bd0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003bd2: f7fe fd25 bl 8002620 <HAL_GetTick> 8003bd6: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003bd8: e008 b.n 8003bec <HAL_RCC_OscConfig+0x47c> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003bda: f7fe fd21 bl 8002620 <HAL_GetTick> 8003bde: 4602 mov r2, r0 8003be0: 693b ldr r3, [r7, #16] 8003be2: 1ad3 subs r3, r2, r3 8003be4: 2b02 cmp r3, #2 8003be6: d901 bls.n 8003bec <HAL_RCC_OscConfig+0x47c> { return HAL_TIMEOUT; 8003be8: 2303 movs r3, #3 8003bea: e03d b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003bec: 4b11 ldr r3, [pc, #68] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003bee: 681b ldr r3, [r3, #0] 8003bf0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003bf4: 2b00 cmp r3, #0 8003bf6: d0f0 beq.n 8003bda <HAL_RCC_OscConfig+0x46a> 8003bf8: e035 b.n 8003c66 <HAL_RCC_OscConfig+0x4f6> } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003bfa: 4b10 ldr r3, [pc, #64] ; (8003c3c <HAL_RCC_OscConfig+0x4cc>) 8003bfc: 2200 movs r2, #0 8003bfe: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003c00: f7fe fd0e bl 8002620 <HAL_GetTick> 8003c04: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003c06: e008 b.n 8003c1a <HAL_RCC_OscConfig+0x4aa> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003c08: f7fe fd0a bl 8002620 <HAL_GetTick> 8003c0c: 4602 mov r2, r0 8003c0e: 693b ldr r3, [r7, #16] 8003c10: 1ad3 subs r3, r2, r3 8003c12: 2b02 cmp r3, #2 8003c14: d901 bls.n 8003c1a <HAL_RCC_OscConfig+0x4aa> { return HAL_TIMEOUT; 8003c16: 2303 movs r3, #3 8003c18: e026 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003c1a: 4b06 ldr r3, [pc, #24] ; (8003c34 <HAL_RCC_OscConfig+0x4c4>) 8003c1c: 681b ldr r3, [r3, #0] 8003c1e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003c22: 2b00 cmp r3, #0 8003c24: d1f0 bne.n 8003c08 <HAL_RCC_OscConfig+0x498> 8003c26: e01e b.n 8003c66 <HAL_RCC_OscConfig+0x4f6> } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003c28: 687b ldr r3, [r7, #4] 8003c2a: 69db ldr r3, [r3, #28] 8003c2c: 2b01 cmp r3, #1 8003c2e: d107 bne.n 8003c40 <HAL_RCC_OscConfig+0x4d0> { return HAL_ERROR; 8003c30: 2301 movs r3, #1 8003c32: e019 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> 8003c34: 40021000 .word 0x40021000 8003c38: 40007000 .word 0x40007000 8003c3c: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8003c40: 4b0b ldr r3, [pc, #44] ; (8003c70 <HAL_RCC_OscConfig+0x500>) 8003c42: 685b ldr r3, [r3, #4] 8003c44: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003c46: 68fb ldr r3, [r7, #12] 8003c48: f403 3280 and.w r2, r3, #65536 ; 0x10000 8003c4c: 687b ldr r3, [r7, #4] 8003c4e: 6a1b ldr r3, [r3, #32] 8003c50: 429a cmp r2, r3 8003c52: d106 bne.n 8003c62 <HAL_RCC_OscConfig+0x4f2> (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8003c54: 68fb ldr r3, [r7, #12] 8003c56: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8003c5a: 687b ldr r3, [r7, #4] 8003c5c: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003c5e: 429a cmp r2, r3 8003c60: d001 beq.n 8003c66 <HAL_RCC_OscConfig+0x4f6> { return HAL_ERROR; 8003c62: 2301 movs r3, #1 8003c64: e000 b.n 8003c68 <HAL_RCC_OscConfig+0x4f8> } } } } return HAL_OK; 8003c66: 2300 movs r3, #0 } 8003c68: 4618 mov r0, r3 8003c6a: 3718 adds r7, #24 8003c6c: 46bd mov sp, r7 8003c6e: bd80 pop {r7, pc} 8003c70: 40021000 .word 0x40021000 08003c74 <HAL_RCC_ClockConfig>: * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003c74: b580 push {r7, lr} 8003c76: b084 sub sp, #16 8003c78: af00 add r7, sp, #0 8003c7a: 6078 str r0, [r7, #4] 8003c7c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003c7e: 687b ldr r3, [r7, #4] 8003c80: 2b00 cmp r3, #0 8003c82: d101 bne.n 8003c88 <HAL_RCC_ClockConfig+0x14> { return HAL_ERROR; 8003c84: 2301 movs r3, #1 8003c86: e0d0 b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003c88: 4b6a ldr r3, [pc, #424] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003c8a: 681b ldr r3, [r3, #0] 8003c8c: f003 0307 and.w r3, r3, #7 8003c90: 683a ldr r2, [r7, #0] 8003c92: 429a cmp r2, r3 8003c94: d910 bls.n 8003cb8 <HAL_RCC_ClockConfig+0x44> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003c96: 4b67 ldr r3, [pc, #412] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003c98: 681b ldr r3, [r3, #0] 8003c9a: f023 0207 bic.w r2, r3, #7 8003c9e: 4965 ldr r1, [pc, #404] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003ca0: 683b ldr r3, [r7, #0] 8003ca2: 4313 orrs r3, r2 8003ca4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003ca6: 4b63 ldr r3, [pc, #396] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003ca8: 681b ldr r3, [r3, #0] 8003caa: f003 0307 and.w r3, r3, #7 8003cae: 683a ldr r2, [r7, #0] 8003cb0: 429a cmp r2, r3 8003cb2: d001 beq.n 8003cb8 <HAL_RCC_ClockConfig+0x44> { return HAL_ERROR; 8003cb4: 2301 movs r3, #1 8003cb6: e0b8 b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003cb8: 687b ldr r3, [r7, #4] 8003cba: 681b ldr r3, [r3, #0] 8003cbc: f003 0302 and.w r3, r3, #2 8003cc0: 2b00 cmp r3, #0 8003cc2: d020 beq.n 8003d06 <HAL_RCC_ClockConfig+0x92> { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003cc4: 687b ldr r3, [r7, #4] 8003cc6: 681b ldr r3, [r3, #0] 8003cc8: f003 0304 and.w r3, r3, #4 8003ccc: 2b00 cmp r3, #0 8003cce: d005 beq.n 8003cdc <HAL_RCC_ClockConfig+0x68> { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003cd0: 4b59 ldr r3, [pc, #356] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003cd2: 685b ldr r3, [r3, #4] 8003cd4: 4a58 ldr r2, [pc, #352] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003cd6: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8003cda: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003cdc: 687b ldr r3, [r7, #4] 8003cde: 681b ldr r3, [r3, #0] 8003ce0: f003 0308 and.w r3, r3, #8 8003ce4: 2b00 cmp r3, #0 8003ce6: d005 beq.n 8003cf4 <HAL_RCC_ClockConfig+0x80> { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003ce8: 4b53 ldr r3, [pc, #332] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003cea: 685b ldr r3, [r3, #4] 8003cec: 4a52 ldr r2, [pc, #328] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003cee: f443 5360 orr.w r3, r3, #14336 ; 0x3800 8003cf2: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003cf4: 4b50 ldr r3, [pc, #320] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003cf6: 685b ldr r3, [r3, #4] 8003cf8: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8003cfc: 687b ldr r3, [r7, #4] 8003cfe: 689b ldr r3, [r3, #8] 8003d00: 494d ldr r1, [pc, #308] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d02: 4313 orrs r3, r2 8003d04: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003d06: 687b ldr r3, [r7, #4] 8003d08: 681b ldr r3, [r3, #0] 8003d0a: f003 0301 and.w r3, r3, #1 8003d0e: 2b00 cmp r3, #0 8003d10: d040 beq.n 8003d94 <HAL_RCC_ClockConfig+0x120> { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003d12: 687b ldr r3, [r7, #4] 8003d14: 685b ldr r3, [r3, #4] 8003d16: 2b01 cmp r3, #1 8003d18: d107 bne.n 8003d2a <HAL_RCC_ClockConfig+0xb6> { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003d1a: 4b47 ldr r3, [pc, #284] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d1c: 681b ldr r3, [r3, #0] 8003d1e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003d22: 2b00 cmp r3, #0 8003d24: d115 bne.n 8003d52 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 8003d26: 2301 movs r3, #1 8003d28: e07f b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003d2a: 687b ldr r3, [r7, #4] 8003d2c: 685b ldr r3, [r3, #4] 8003d2e: 2b02 cmp r3, #2 8003d30: d107 bne.n 8003d42 <HAL_RCC_ClockConfig+0xce> { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003d32: 4b41 ldr r3, [pc, #260] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d34: 681b ldr r3, [r3, #0] 8003d36: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003d3a: 2b00 cmp r3, #0 8003d3c: d109 bne.n 8003d52 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 8003d3e: 2301 movs r3, #1 8003d40: e073 b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003d42: 4b3d ldr r3, [pc, #244] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d44: 681b ldr r3, [r3, #0] 8003d46: f003 0302 and.w r3, r3, #2 8003d4a: 2b00 cmp r3, #0 8003d4c: d101 bne.n 8003d52 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 8003d4e: 2301 movs r3, #1 8003d50: e06b b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8003d52: 4b39 ldr r3, [pc, #228] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d54: 685b ldr r3, [r3, #4] 8003d56: f023 0203 bic.w r2, r3, #3 8003d5a: 687b ldr r3, [r7, #4] 8003d5c: 685b ldr r3, [r3, #4] 8003d5e: 4936 ldr r1, [pc, #216] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d60: 4313 orrs r3, r2 8003d62: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003d64: f7fe fc5c bl 8002620 <HAL_GetTick> 8003d68: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003d6a: e00a b.n 8003d82 <HAL_RCC_ClockConfig+0x10e> { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003d6c: f7fe fc58 bl 8002620 <HAL_GetTick> 8003d70: 4602 mov r2, r0 8003d72: 68fb ldr r3, [r7, #12] 8003d74: 1ad3 subs r3, r2, r3 8003d76: f241 3288 movw r2, #5000 ; 0x1388 8003d7a: 4293 cmp r3, r2 8003d7c: d901 bls.n 8003d82 <HAL_RCC_ClockConfig+0x10e> { return HAL_TIMEOUT; 8003d7e: 2303 movs r3, #3 8003d80: e053 b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003d82: 4b2d ldr r3, [pc, #180] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003d84: 685b ldr r3, [r3, #4] 8003d86: f003 020c and.w r2, r3, #12 8003d8a: 687b ldr r3, [r7, #4] 8003d8c: 685b ldr r3, [r3, #4] 8003d8e: 009b lsls r3, r3, #2 8003d90: 429a cmp r2, r3 8003d92: d1eb bne.n 8003d6c <HAL_RCC_ClockConfig+0xf8> } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003d94: 4b27 ldr r3, [pc, #156] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003d96: 681b ldr r3, [r3, #0] 8003d98: f003 0307 and.w r3, r3, #7 8003d9c: 683a ldr r2, [r7, #0] 8003d9e: 429a cmp r2, r3 8003da0: d210 bcs.n 8003dc4 <HAL_RCC_ClockConfig+0x150> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003da2: 4b24 ldr r3, [pc, #144] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003da4: 681b ldr r3, [r3, #0] 8003da6: f023 0207 bic.w r2, r3, #7 8003daa: 4922 ldr r1, [pc, #136] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003dac: 683b ldr r3, [r7, #0] 8003dae: 4313 orrs r3, r2 8003db0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003db2: 4b20 ldr r3, [pc, #128] ; (8003e34 <HAL_RCC_ClockConfig+0x1c0>) 8003db4: 681b ldr r3, [r3, #0] 8003db6: f003 0307 and.w r3, r3, #7 8003dba: 683a ldr r2, [r7, #0] 8003dbc: 429a cmp r2, r3 8003dbe: d001 beq.n 8003dc4 <HAL_RCC_ClockConfig+0x150> { return HAL_ERROR; 8003dc0: 2301 movs r3, #1 8003dc2: e032 b.n 8003e2a <HAL_RCC_ClockConfig+0x1b6> } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003dc4: 687b ldr r3, [r7, #4] 8003dc6: 681b ldr r3, [r3, #0] 8003dc8: f003 0304 and.w r3, r3, #4 8003dcc: 2b00 cmp r3, #0 8003dce: d008 beq.n 8003de2 <HAL_RCC_ClockConfig+0x16e> { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003dd0: 4b19 ldr r3, [pc, #100] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003dd2: 685b ldr r3, [r3, #4] 8003dd4: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003dd8: 687b ldr r3, [r7, #4] 8003dda: 68db ldr r3, [r3, #12] 8003ddc: 4916 ldr r1, [pc, #88] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003dde: 4313 orrs r3, r2 8003de0: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003de2: 687b ldr r3, [r7, #4] 8003de4: 681b ldr r3, [r3, #0] 8003de6: f003 0308 and.w r3, r3, #8 8003dea: 2b00 cmp r3, #0 8003dec: d009 beq.n 8003e02 <HAL_RCC_ClockConfig+0x18e> { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8003dee: 4b12 ldr r3, [pc, #72] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003df0: 685b ldr r3, [r3, #4] 8003df2: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8003df6: 687b ldr r3, [r7, #4] 8003df8: 691b ldr r3, [r3, #16] 8003dfa: 00db lsls r3, r3, #3 8003dfc: 490e ldr r1, [pc, #56] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003dfe: 4313 orrs r3, r2 8003e00: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8003e02: f000 f821 bl 8003e48 <HAL_RCC_GetSysClockFreq> 8003e06: 4602 mov r2, r0 8003e08: 4b0b ldr r3, [pc, #44] ; (8003e38 <HAL_RCC_ClockConfig+0x1c4>) 8003e0a: 685b ldr r3, [r3, #4] 8003e0c: 091b lsrs r3, r3, #4 8003e0e: f003 030f and.w r3, r3, #15 8003e12: 490a ldr r1, [pc, #40] ; (8003e3c <HAL_RCC_ClockConfig+0x1c8>) 8003e14: 5ccb ldrb r3, [r1, r3] 8003e16: fa22 f303 lsr.w r3, r2, r3 8003e1a: 4a09 ldr r2, [pc, #36] ; (8003e40 <HAL_RCC_ClockConfig+0x1cc>) 8003e1c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8003e1e: 4b09 ldr r3, [pc, #36] ; (8003e44 <HAL_RCC_ClockConfig+0x1d0>) 8003e20: 681b ldr r3, [r3, #0] 8003e22: 4618 mov r0, r3 8003e24: f7fe fbba bl 800259c <HAL_InitTick> return HAL_OK; 8003e28: 2300 movs r3, #0 } 8003e2a: 4618 mov r0, r3 8003e2c: 3710 adds r7, #16 8003e2e: 46bd mov sp, r7 8003e30: bd80 pop {r7, pc} 8003e32: bf00 nop 8003e34: 40022000 .word 0x40022000 8003e38: 40021000 .word 0x40021000 8003e3c: 08007ae0 .word 0x08007ae0 8003e40: 20000058 .word 0x20000058 8003e44: 2000005c .word 0x2000005c 08003e48 <HAL_RCC_GetSysClockFreq>: * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003e48: b490 push {r4, r7} 8003e4a: b08a sub sp, #40 ; 0x28 8003e4c: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8003e4e: 4b29 ldr r3, [pc, #164] ; (8003ef4 <HAL_RCC_GetSysClockFreq+0xac>) 8003e50: 1d3c adds r4, r7, #4 8003e52: cb0f ldmia r3, {r0, r1, r2, r3} 8003e54: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; 8003e58: f240 2301 movw r3, #513 ; 0x201 8003e5c: 803b strh r3, [r7, #0] #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8003e5e: 2300 movs r3, #0 8003e60: 61fb str r3, [r7, #28] 8003e62: 2300 movs r3, #0 8003e64: 61bb str r3, [r7, #24] 8003e66: 2300 movs r3, #0 8003e68: 627b str r3, [r7, #36] ; 0x24 8003e6a: 2300 movs r3, #0 8003e6c: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 8003e6e: 2300 movs r3, #0 8003e70: 623b str r3, [r7, #32] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8003e72: 4b21 ldr r3, [pc, #132] ; (8003ef8 <HAL_RCC_GetSysClockFreq+0xb0>) 8003e74: 685b ldr r3, [r3, #4] 8003e76: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8003e78: 69fb ldr r3, [r7, #28] 8003e7a: f003 030c and.w r3, r3, #12 8003e7e: 2b04 cmp r3, #4 8003e80: d002 beq.n 8003e88 <HAL_RCC_GetSysClockFreq+0x40> 8003e82: 2b08 cmp r3, #8 8003e84: d003 beq.n 8003e8e <HAL_RCC_GetSysClockFreq+0x46> 8003e86: e02b b.n 8003ee0 <HAL_RCC_GetSysClockFreq+0x98> { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8003e88: 4b1c ldr r3, [pc, #112] ; (8003efc <HAL_RCC_GetSysClockFreq+0xb4>) 8003e8a: 623b str r3, [r7, #32] break; 8003e8c: e02b b.n 8003ee6 <HAL_RCC_GetSysClockFreq+0x9e> } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8003e8e: 69fb ldr r3, [r7, #28] 8003e90: 0c9b lsrs r3, r3, #18 8003e92: f003 030f and.w r3, r3, #15 8003e96: 3328 adds r3, #40 ; 0x28 8003e98: 443b add r3, r7 8003e9a: f813 3c24 ldrb.w r3, [r3, #-36] 8003e9e: 617b str r3, [r7, #20] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8003ea0: 69fb ldr r3, [r7, #28] 8003ea2: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003ea6: 2b00 cmp r3, #0 8003ea8: d012 beq.n 8003ed0 <HAL_RCC_GetSysClockFreq+0x88> { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8003eaa: 4b13 ldr r3, [pc, #76] ; (8003ef8 <HAL_RCC_GetSysClockFreq+0xb0>) 8003eac: 685b ldr r3, [r3, #4] 8003eae: 0c5b lsrs r3, r3, #17 8003eb0: f003 0301 and.w r3, r3, #1 8003eb4: 3328 adds r3, #40 ; 0x28 8003eb6: 443b add r3, r7 8003eb8: f813 3c28 ldrb.w r3, [r3, #-40] 8003ebc: 61bb str r3, [r7, #24] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8003ebe: 697b ldr r3, [r7, #20] 8003ec0: 4a0e ldr r2, [pc, #56] ; (8003efc <HAL_RCC_GetSysClockFreq+0xb4>) 8003ec2: fb03 f202 mul.w r2, r3, r2 8003ec6: 69bb ldr r3, [r7, #24] 8003ec8: fbb2 f3f3 udiv r3, r2, r3 8003ecc: 627b str r3, [r7, #36] ; 0x24 8003ece: e004 b.n 8003eda <HAL_RCC_GetSysClockFreq+0x92> #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8003ed0: 697b ldr r3, [r7, #20] 8003ed2: 4a0b ldr r2, [pc, #44] ; (8003f00 <HAL_RCC_GetSysClockFreq+0xb8>) 8003ed4: fb02 f303 mul.w r3, r2, r3 8003ed8: 627b str r3, [r7, #36] ; 0x24 } sysclockfreq = pllclk; 8003eda: 6a7b ldr r3, [r7, #36] ; 0x24 8003edc: 623b str r3, [r7, #32] break; 8003ede: e002 b.n 8003ee6 <HAL_RCC_GetSysClockFreq+0x9e> } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8003ee0: 4b06 ldr r3, [pc, #24] ; (8003efc <HAL_RCC_GetSysClockFreq+0xb4>) 8003ee2: 623b str r3, [r7, #32] break; 8003ee4: bf00 nop } } return sysclockfreq; 8003ee6: 6a3b ldr r3, [r7, #32] } 8003ee8: 4618 mov r0, r3 8003eea: 3728 adds r7, #40 ; 0x28 8003eec: 46bd mov sp, r7 8003eee: bc90 pop {r4, r7} 8003ef0: 4770 bx lr 8003ef2: bf00 nop 8003ef4: 08007384 .word 0x08007384 8003ef8: 40021000 .word 0x40021000 8003efc: 007a1200 .word 0x007a1200 8003f00: 003d0900 .word 0x003d0900 08003f04 <HAL_RCC_GetHCLKFreq>: * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003f04: b480 push {r7} 8003f06: af00 add r7, sp, #0 return SystemCoreClock; 8003f08: 4b02 ldr r3, [pc, #8] ; (8003f14 <HAL_RCC_GetHCLKFreq+0x10>) 8003f0a: 681b ldr r3, [r3, #0] } 8003f0c: 4618 mov r0, r3 8003f0e: 46bd mov sp, r7 8003f10: bc80 pop {r7} 8003f12: 4770 bx lr 8003f14: 20000058 .word 0x20000058 08003f18 <HAL_RCC_GetPCLK1Freq>: * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003f18: b580 push {r7, lr} 8003f1a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8003f1c: f7ff fff2 bl 8003f04 <HAL_RCC_GetHCLKFreq> 8003f20: 4602 mov r2, r0 8003f22: 4b05 ldr r3, [pc, #20] ; (8003f38 <HAL_RCC_GetPCLK1Freq+0x20>) 8003f24: 685b ldr r3, [r3, #4] 8003f26: 0a1b lsrs r3, r3, #8 8003f28: f003 0307 and.w r3, r3, #7 8003f2c: 4903 ldr r1, [pc, #12] ; (8003f3c <HAL_RCC_GetPCLK1Freq+0x24>) 8003f2e: 5ccb ldrb r3, [r1, r3] 8003f30: fa22 f303 lsr.w r3, r2, r3 } 8003f34: 4618 mov r0, r3 8003f36: bd80 pop {r7, pc} 8003f38: 40021000 .word 0x40021000 8003f3c: 08007af0 .word 0x08007af0 08003f40 <HAL_RCC_GetPCLK2Freq>: * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003f40: b580 push {r7, lr} 8003f42: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8003f44: f7ff ffde bl 8003f04 <HAL_RCC_GetHCLKFreq> 8003f48: 4602 mov r2, r0 8003f4a: 4b05 ldr r3, [pc, #20] ; (8003f60 <HAL_RCC_GetPCLK2Freq+0x20>) 8003f4c: 685b ldr r3, [r3, #4] 8003f4e: 0adb lsrs r3, r3, #11 8003f50: f003 0307 and.w r3, r3, #7 8003f54: 4903 ldr r1, [pc, #12] ; (8003f64 <HAL_RCC_GetPCLK2Freq+0x24>) 8003f56: 5ccb ldrb r3, [r1, r3] 8003f58: fa22 f303 lsr.w r3, r2, r3 } 8003f5c: 4618 mov r0, r3 8003f5e: bd80 pop {r7, pc} 8003f60: 40021000 .word 0x40021000 8003f64: 08007af0 .word 0x08007af0 08003f68 <RCC_Delay>: * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8003f68: b480 push {r7} 8003f6a: b085 sub sp, #20 8003f6c: af00 add r7, sp, #0 8003f6e: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8003f70: 4b0a ldr r3, [pc, #40] ; (8003f9c <RCC_Delay+0x34>) 8003f72: 681b ldr r3, [r3, #0] 8003f74: 4a0a ldr r2, [pc, #40] ; (8003fa0 <RCC_Delay+0x38>) 8003f76: fba2 2303 umull r2, r3, r2, r3 8003f7a: 0a5b lsrs r3, r3, #9 8003f7c: 687a ldr r2, [r7, #4] 8003f7e: fb02 f303 mul.w r3, r2, r3 8003f82: 60fb str r3, [r7, #12] do { __NOP(); 8003f84: bf00 nop } while (Delay --); 8003f86: 68fb ldr r3, [r7, #12] 8003f88: 1e5a subs r2, r3, #1 8003f8a: 60fa str r2, [r7, #12] 8003f8c: 2b00 cmp r3, #0 8003f8e: d1f9 bne.n 8003f84 <RCC_Delay+0x1c> } 8003f90: bf00 nop 8003f92: bf00 nop 8003f94: 3714 adds r7, #20 8003f96: 46bd mov sp, r7 8003f98: bc80 pop {r7} 8003f9a: 4770 bx lr 8003f9c: 20000058 .word 0x20000058 8003fa0: 10624dd3 .word 0x10624dd3 08003fa4 <HAL_RCCEx_PeriphCLKConfig>: * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003fa4: b580 push {r7, lr} 8003fa6: b086 sub sp, #24 8003fa8: af00 add r7, sp, #0 8003faa: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8003fac: 2300 movs r3, #0 8003fae: 613b str r3, [r7, #16] 8003fb0: 2300 movs r3, #0 8003fb2: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8003fb4: 687b ldr r3, [r7, #4] 8003fb6: 681b ldr r3, [r3, #0] 8003fb8: f003 0301 and.w r3, r3, #1 8003fbc: 2b00 cmp r3, #0 8003fbe: d07d beq.n 80040bc <HAL_RCCEx_PeriphCLKConfig+0x118> { FlagStatus pwrclkchanged = RESET; 8003fc0: 2300 movs r3, #0 8003fc2: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003fc4: 4b4f ldr r3, [pc, #316] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8003fc6: 69db ldr r3, [r3, #28] 8003fc8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003fcc: 2b00 cmp r3, #0 8003fce: d10d bne.n 8003fec <HAL_RCCEx_PeriphCLKConfig+0x48> { __HAL_RCC_PWR_CLK_ENABLE(); 8003fd0: 4b4c ldr r3, [pc, #304] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8003fd2: 69db ldr r3, [r3, #28] 8003fd4: 4a4b ldr r2, [pc, #300] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8003fd6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003fda: 61d3 str r3, [r2, #28] 8003fdc: 4b49 ldr r3, [pc, #292] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8003fde: 69db ldr r3, [r3, #28] 8003fe0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003fe4: 60bb str r3, [r7, #8] 8003fe6: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003fe8: 2301 movs r3, #1 8003fea: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003fec: 4b46 ldr r3, [pc, #280] ; (8004108 <HAL_RCCEx_PeriphCLKConfig+0x164>) 8003fee: 681b ldr r3, [r3, #0] 8003ff0: f403 7380 and.w r3, r3, #256 ; 0x100 8003ff4: 2b00 cmp r3, #0 8003ff6: d118 bne.n 800402a <HAL_RCCEx_PeriphCLKConfig+0x86> { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003ff8: 4b43 ldr r3, [pc, #268] ; (8004108 <HAL_RCCEx_PeriphCLKConfig+0x164>) 8003ffa: 681b ldr r3, [r3, #0] 8003ffc: 4a42 ldr r2, [pc, #264] ; (8004108 <HAL_RCCEx_PeriphCLKConfig+0x164>) 8003ffe: f443 7380 orr.w r3, r3, #256 ; 0x100 8004002: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004004: f7fe fb0c bl 8002620 <HAL_GetTick> 8004008: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800400a: e008 b.n 800401e <HAL_RCCEx_PeriphCLKConfig+0x7a> { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800400c: f7fe fb08 bl 8002620 <HAL_GetTick> 8004010: 4602 mov r2, r0 8004012: 693b ldr r3, [r7, #16] 8004014: 1ad3 subs r3, r2, r3 8004016: 2b64 cmp r3, #100 ; 0x64 8004018: d901 bls.n 800401e <HAL_RCCEx_PeriphCLKConfig+0x7a> { return HAL_TIMEOUT; 800401a: 2303 movs r3, #3 800401c: e06d b.n 80040fa <HAL_RCCEx_PeriphCLKConfig+0x156> while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800401e: 4b3a ldr r3, [pc, #232] ; (8004108 <HAL_RCCEx_PeriphCLKConfig+0x164>) 8004020: 681b ldr r3, [r3, #0] 8004022: f403 7380 and.w r3, r3, #256 ; 0x100 8004026: 2b00 cmp r3, #0 8004028: d0f0 beq.n 800400c <HAL_RCCEx_PeriphCLKConfig+0x68> } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 800402a: 4b36 ldr r3, [pc, #216] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800402c: 6a1b ldr r3, [r3, #32] 800402e: f403 7340 and.w r3, r3, #768 ; 0x300 8004032: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8004034: 68fb ldr r3, [r7, #12] 8004036: 2b00 cmp r3, #0 8004038: d02e beq.n 8004098 <HAL_RCCEx_PeriphCLKConfig+0xf4> 800403a: 687b ldr r3, [r7, #4] 800403c: 685b ldr r3, [r3, #4] 800403e: f403 7340 and.w r3, r3, #768 ; 0x300 8004042: 68fa ldr r2, [r7, #12] 8004044: 429a cmp r2, r3 8004046: d027 beq.n 8004098 <HAL_RCCEx_PeriphCLKConfig+0xf4> { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8004048: 4b2e ldr r3, [pc, #184] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800404a: 6a1b ldr r3, [r3, #32] 800404c: f423 7340 bic.w r3, r3, #768 ; 0x300 8004050: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004052: 4b2e ldr r3, [pc, #184] ; (800410c <HAL_RCCEx_PeriphCLKConfig+0x168>) 8004054: 2201 movs r2, #1 8004056: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8004058: 4b2c ldr r3, [pc, #176] ; (800410c <HAL_RCCEx_PeriphCLKConfig+0x168>) 800405a: 2200 movs r2, #0 800405c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 800405e: 4a29 ldr r2, [pc, #164] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004060: 68fb ldr r3, [r7, #12] 8004062: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8004064: 68fb ldr r3, [r7, #12] 8004066: f003 0301 and.w r3, r3, #1 800406a: 2b00 cmp r3, #0 800406c: d014 beq.n 8004098 <HAL_RCCEx_PeriphCLKConfig+0xf4> { /* Get Start Tick */ tickstart = HAL_GetTick(); 800406e: f7fe fad7 bl 8002620 <HAL_GetTick> 8004072: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004074: e00a b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0xe8> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004076: f7fe fad3 bl 8002620 <HAL_GetTick> 800407a: 4602 mov r2, r0 800407c: 693b ldr r3, [r7, #16] 800407e: 1ad3 subs r3, r2, r3 8004080: f241 3288 movw r2, #5000 ; 0x1388 8004084: 4293 cmp r3, r2 8004086: d901 bls.n 800408c <HAL_RCCEx_PeriphCLKConfig+0xe8> { return HAL_TIMEOUT; 8004088: 2303 movs r3, #3 800408a: e036 b.n 80040fa <HAL_RCCEx_PeriphCLKConfig+0x156> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800408c: 4b1d ldr r3, [pc, #116] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800408e: 6a1b ldr r3, [r3, #32] 8004090: f003 0302 and.w r3, r3, #2 8004094: 2b00 cmp r3, #0 8004096: d0ee beq.n 8004076 <HAL_RCCEx_PeriphCLKConfig+0xd2> } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004098: 4b1a ldr r3, [pc, #104] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800409a: 6a1b ldr r3, [r3, #32] 800409c: f423 7240 bic.w r2, r3, #768 ; 0x300 80040a0: 687b ldr r3, [r7, #4] 80040a2: 685b ldr r3, [r3, #4] 80040a4: 4917 ldr r1, [pc, #92] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040a6: 4313 orrs r3, r2 80040a8: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80040aa: 7dfb ldrb r3, [r7, #23] 80040ac: 2b01 cmp r3, #1 80040ae: d105 bne.n 80040bc <HAL_RCCEx_PeriphCLKConfig+0x118> { __HAL_RCC_PWR_CLK_DISABLE(); 80040b0: 4b14 ldr r3, [pc, #80] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040b2: 69db ldr r3, [r3, #28] 80040b4: 4a13 ldr r2, [pc, #76] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040b6: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 80040ba: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80040bc: 687b ldr r3, [r7, #4] 80040be: 681b ldr r3, [r3, #0] 80040c0: f003 0302 and.w r3, r3, #2 80040c4: 2b00 cmp r3, #0 80040c6: d008 beq.n 80040da <HAL_RCCEx_PeriphCLKConfig+0x136> { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80040c8: 4b0e ldr r3, [pc, #56] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040ca: 685b ldr r3, [r3, #4] 80040cc: f423 4240 bic.w r2, r3, #49152 ; 0xc000 80040d0: 687b ldr r3, [r7, #4] 80040d2: 689b ldr r3, [r3, #8] 80040d4: 490b ldr r1, [pc, #44] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040d6: 4313 orrs r3, r2 80040d8: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80040da: 687b ldr r3, [r7, #4] 80040dc: 681b ldr r3, [r3, #0] 80040de: f003 0310 and.w r3, r3, #16 80040e2: 2b00 cmp r3, #0 80040e4: d008 beq.n 80040f8 <HAL_RCCEx_PeriphCLKConfig+0x154> { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80040e6: 4b07 ldr r3, [pc, #28] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040e8: 685b ldr r3, [r3, #4] 80040ea: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 80040ee: 687b ldr r3, [r7, #4] 80040f0: 68db ldr r3, [r3, #12] 80040f2: 4904 ldr r1, [pc, #16] ; (8004104 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80040f4: 4313 orrs r3, r2 80040f6: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80040f8: 2300 movs r3, #0 } 80040fa: 4618 mov r0, r3 80040fc: 3718 adds r7, #24 80040fe: 46bd mov sp, r7 8004100: bd80 pop {r7, pc} 8004102: bf00 nop 8004104: 40021000 .word 0x40021000 8004108: 40007000 .word 0x40007000 800410c: 42420440 .word 0x42420440 08004110 <HAL_RCCEx_GetPeriphCLKFreq>: * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8004110: b590 push {r4, r7, lr} 8004112: b08d sub sp, #52 ; 0x34 8004114: af00 add r7, sp, #0 8004116: 6078 str r0, [r7, #4] uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8004118: 4b58 ldr r3, [pc, #352] ; (800427c <HAL_RCCEx_GetPeriphCLKFreq+0x16c>) 800411a: f107 040c add.w r4, r7, #12 800411e: cb0f ldmia r3, {r0, r1, r2, r3} 8004120: e884 000f stmia.w r4, {r0, r1, r2, r3} const uint8_t aPredivFactorTable[2] = {1, 2}; 8004124: f240 2301 movw r3, #513 ; 0x201 8004128: 813b strh r3, [r7, #8] uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 800412a: 2300 movs r3, #0 800412c: 627b str r3, [r7, #36] ; 0x24 800412e: 2300 movs r3, #0 8004130: 62fb str r3, [r7, #44] ; 0x2c 8004132: 2300 movs r3, #0 8004134: 623b str r3, [r7, #32] #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8004136: 2300 movs r3, #0 8004138: 61fb str r3, [r7, #28] 800413a: 2300 movs r3, #0 800413c: 62bb str r3, [r7, #40] ; 0x28 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 800413e: 687b ldr r3, [r7, #4] 8004140: 2b10 cmp r3, #16 8004142: d00a beq.n 800415a <HAL_RCCEx_GetPeriphCLKFreq+0x4a> 8004144: 687b ldr r3, [r7, #4] 8004146: 2b10 cmp r3, #16 8004148: f200 808e bhi.w 8004268 <HAL_RCCEx_GetPeriphCLKFreq+0x158> 800414c: 687b ldr r3, [r7, #4] 800414e: 2b01 cmp r3, #1 8004150: d049 beq.n 80041e6 <HAL_RCCEx_GetPeriphCLKFreq+0xd6> 8004152: 687b ldr r3, [r7, #4] 8004154: 2b02 cmp r3, #2 8004156: d079 beq.n 800424c <HAL_RCCEx_GetPeriphCLKFreq+0x13c> frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8004158: e086 b.n 8004268 <HAL_RCCEx_GetPeriphCLKFreq+0x158> temp_reg = RCC->CFGR; 800415a: 4b49 ldr r3, [pc, #292] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 800415c: 685b ldr r3, [r3, #4] 800415e: 61fb str r3, [r7, #28] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8004160: 4b47 ldr r3, [pc, #284] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 8004162: 681b ldr r3, [r3, #0] 8004164: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004168: 2b00 cmp r3, #0 800416a: d07f beq.n 800426c <HAL_RCCEx_GetPeriphCLKFreq+0x15c> pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 800416c: 69fb ldr r3, [r7, #28] 800416e: 0c9b lsrs r3, r3, #18 8004170: f003 030f and.w r3, r3, #15 8004174: 3330 adds r3, #48 ; 0x30 8004176: 443b add r3, r7 8004178: f813 3c24 ldrb.w r3, [r3, #-36] 800417c: 623b str r3, [r7, #32] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 800417e: 69fb ldr r3, [r7, #28] 8004180: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004184: 2b00 cmp r3, #0 8004186: d017 beq.n 80041b8 <HAL_RCCEx_GetPeriphCLKFreq+0xa8> prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004188: 4b3d ldr r3, [pc, #244] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 800418a: 685b ldr r3, [r3, #4] 800418c: 0c5b lsrs r3, r3, #17 800418e: f003 0301 and.w r3, r3, #1 8004192: 3330 adds r3, #48 ; 0x30 8004194: 443b add r3, r7 8004196: f813 3c28 ldrb.w r3, [r3, #-40] 800419a: 627b str r3, [r7, #36] ; 0x24 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 800419c: 69fb ldr r3, [r7, #28] 800419e: f403 3380 and.w r3, r3, #65536 ; 0x10000 80041a2: 2b00 cmp r3, #0 80041a4: d00d beq.n 80041c2 <HAL_RCCEx_GetPeriphCLKFreq+0xb2> pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 80041a6: 4a37 ldr r2, [pc, #220] ; (8004284 <HAL_RCCEx_GetPeriphCLKFreq+0x174>) 80041a8: 6a7b ldr r3, [r7, #36] ; 0x24 80041aa: fbb2 f2f3 udiv r2, r2, r3 80041ae: 6a3b ldr r3, [r7, #32] 80041b0: fb02 f303 mul.w r3, r2, r3 80041b4: 62fb str r3, [r7, #44] ; 0x2c 80041b6: e004 b.n 80041c2 <HAL_RCCEx_GetPeriphCLKFreq+0xb2> pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80041b8: 6a3b ldr r3, [r7, #32] 80041ba: 4a33 ldr r2, [pc, #204] ; (8004288 <HAL_RCCEx_GetPeriphCLKFreq+0x178>) 80041bc: fb02 f303 mul.w r3, r2, r3 80041c0: 62fb str r3, [r7, #44] ; 0x2c if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) 80041c2: 4b2f ldr r3, [pc, #188] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 80041c4: 685b ldr r3, [r3, #4] 80041c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80041ca: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80041ce: d102 bne.n 80041d6 <HAL_RCCEx_GetPeriphCLKFreq+0xc6> frequency = pllclk; 80041d0: 6afb ldr r3, [r7, #44] ; 0x2c 80041d2: 62bb str r3, [r7, #40] ; 0x28 break; 80041d4: e04a b.n 800426c <HAL_RCCEx_GetPeriphCLKFreq+0x15c> frequency = (pllclk * 2) / 3; 80041d6: 6afb ldr r3, [r7, #44] ; 0x2c 80041d8: 005b lsls r3, r3, #1 80041da: 4a2c ldr r2, [pc, #176] ; (800428c <HAL_RCCEx_GetPeriphCLKFreq+0x17c>) 80041dc: fba2 2303 umull r2, r3, r2, r3 80041e0: 085b lsrs r3, r3, #1 80041e2: 62bb str r3, [r7, #40] ; 0x28 break; 80041e4: e042 b.n 800426c <HAL_RCCEx_GetPeriphCLKFreq+0x15c> temp_reg = RCC->BDCR; 80041e6: 4b26 ldr r3, [pc, #152] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 80041e8: 6a1b ldr r3, [r3, #32] 80041ea: 61fb str r3, [r7, #28] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 80041ec: 69fb ldr r3, [r7, #28] 80041ee: f403 7340 and.w r3, r3, #768 ; 0x300 80041f2: f5b3 7f80 cmp.w r3, #256 ; 0x100 80041f6: d108 bne.n 800420a <HAL_RCCEx_GetPeriphCLKFreq+0xfa> 80041f8: 69fb ldr r3, [r7, #28] 80041fa: f003 0302 and.w r3, r3, #2 80041fe: 2b00 cmp r3, #0 8004200: d003 beq.n 800420a <HAL_RCCEx_GetPeriphCLKFreq+0xfa> frequency = LSE_VALUE; 8004202: f44f 4300 mov.w r3, #32768 ; 0x8000 8004206: 62bb str r3, [r7, #40] ; 0x28 8004208: e01f b.n 800424a <HAL_RCCEx_GetPeriphCLKFreq+0x13a> else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 800420a: 69fb ldr r3, [r7, #28] 800420c: f403 7340 and.w r3, r3, #768 ; 0x300 8004210: f5b3 7f00 cmp.w r3, #512 ; 0x200 8004214: d109 bne.n 800422a <HAL_RCCEx_GetPeriphCLKFreq+0x11a> 8004216: 4b1a ldr r3, [pc, #104] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 8004218: 6a5b ldr r3, [r3, #36] ; 0x24 800421a: f003 0302 and.w r3, r3, #2 800421e: 2b00 cmp r3, #0 8004220: d003 beq.n 800422a <HAL_RCCEx_GetPeriphCLKFreq+0x11a> frequency = LSI_VALUE; 8004222: f649 4340 movw r3, #40000 ; 0x9c40 8004226: 62bb str r3, [r7, #40] ; 0x28 8004228: e00f b.n 800424a <HAL_RCCEx_GetPeriphCLKFreq+0x13a> else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 800422a: 69fb ldr r3, [r7, #28] 800422c: f403 7340 and.w r3, r3, #768 ; 0x300 8004230: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004234: d11c bne.n 8004270 <HAL_RCCEx_GetPeriphCLKFreq+0x160> 8004236: 4b12 ldr r3, [pc, #72] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 8004238: 681b ldr r3, [r3, #0] 800423a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800423e: 2b00 cmp r3, #0 8004240: d016 beq.n 8004270 <HAL_RCCEx_GetPeriphCLKFreq+0x160> frequency = HSE_VALUE / 128U; 8004242: f24f 4324 movw r3, #62500 ; 0xf424 8004246: 62bb str r3, [r7, #40] ; 0x28 break; 8004248: e012 b.n 8004270 <HAL_RCCEx_GetPeriphCLKFreq+0x160> 800424a: e011 b.n 8004270 <HAL_RCCEx_GetPeriphCLKFreq+0x160> frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 800424c: f7ff fe78 bl 8003f40 <HAL_RCC_GetPCLK2Freq> 8004250: 4602 mov r2, r0 8004252: 4b0b ldr r3, [pc, #44] ; (8004280 <HAL_RCCEx_GetPeriphCLKFreq+0x170>) 8004254: 685b ldr r3, [r3, #4] 8004256: 0b9b lsrs r3, r3, #14 8004258: f003 0303 and.w r3, r3, #3 800425c: 3301 adds r3, #1 800425e: 005b lsls r3, r3, #1 8004260: fbb2 f3f3 udiv r3, r2, r3 8004264: 62bb str r3, [r7, #40] ; 0x28 break; 8004266: e004 b.n 8004272 <HAL_RCCEx_GetPeriphCLKFreq+0x162> break; 8004268: bf00 nop 800426a: e002 b.n 8004272 <HAL_RCCEx_GetPeriphCLKFreq+0x162> break; 800426c: bf00 nop 800426e: e000 b.n 8004272 <HAL_RCCEx_GetPeriphCLKFreq+0x162> break; 8004270: bf00 nop } } return (frequency); 8004272: 6abb ldr r3, [r7, #40] ; 0x28 } 8004274: 4618 mov r0, r3 8004276: 3734 adds r7, #52 ; 0x34 8004278: 46bd mov sp, r7 800427a: bd90 pop {r4, r7, pc} 800427c: 08007394 .word 0x08007394 8004280: 40021000 .word 0x40021000 8004284: 007a1200 .word 0x007a1200 8004288: 003d0900 .word 0x003d0900 800428c: aaaaaaab .word 0xaaaaaaab 08004290 <HAL_SPI_Init>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8004290: b580 push {r7, lr} 8004292: b082 sub sp, #8 8004294: af00 add r7, sp, #0 8004296: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) 8004298: 687b ldr r3, [r7, #4] 800429a: 2b00 cmp r3, #0 800429c: d101 bne.n 80042a2 <HAL_SPI_Init+0x12> { return HAL_ERROR; 800429e: 2301 movs r3, #1 80042a0: e076 b.n 8004390 <HAL_SPI_Init+0x100> assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); /* TI mode is not supported on this device. TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 80042a2: 687b ldr r3, [r7, #4] 80042a4: 6a5b ldr r3, [r3, #36] ; 0x24 80042a6: 2b00 cmp r3, #0 80042a8: d108 bne.n 80042bc <HAL_SPI_Init+0x2c> { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 80042aa: 687b ldr r3, [r7, #4] 80042ac: 685b ldr r3, [r3, #4] 80042ae: f5b3 7f82 cmp.w r3, #260 ; 0x104 80042b2: d009 beq.n 80042c8 <HAL_SPI_Init+0x38> assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 80042b4: 687b ldr r3, [r7, #4] 80042b6: 2200 movs r2, #0 80042b8: 61da str r2, [r3, #28] 80042ba: e005 b.n 80042c8 <HAL_SPI_Init+0x38> else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 80042bc: 687b ldr r3, [r7, #4] 80042be: 2200 movs r2, #0 80042c0: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 80042c2: 687b ldr r3, [r7, #4] 80042c4: 2200 movs r2, #0 80042c6: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80042c8: 687b ldr r3, [r7, #4] 80042ca: 2200 movs r2, #0 80042cc: 629a str r2, [r3, #40] ; 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 80042ce: 687b ldr r3, [r7, #4] 80042d0: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80042d4: b2db uxtb r3, r3 80042d6: 2b00 cmp r3, #0 80042d8: d106 bne.n 80042e8 <HAL_SPI_Init+0x58> { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 80042da: 687b ldr r3, [r7, #4] 80042dc: 2200 movs r2, #0 80042de: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 80042e2: 6878 ldr r0, [r7, #4] 80042e4: f7fd ff40 bl 8002168 <HAL_SPI_MspInit> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 80042e8: 687b ldr r3, [r7, #4] 80042ea: 2202 movs r2, #2 80042ec: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80042f0: 687b ldr r3, [r7, #4] 80042f2: 681b ldr r3, [r3, #0] 80042f4: 681a ldr r2, [r3, #0] 80042f6: 687b ldr r3, [r7, #4] 80042f8: 681b ldr r3, [r3, #0] 80042fa: f022 0240 bic.w r2, r2, #64 ; 0x40 80042fe: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8004300: 687b ldr r3, [r7, #4] 8004302: 685b ldr r3, [r3, #4] 8004304: f403 7282 and.w r2, r3, #260 ; 0x104 8004308: 687b ldr r3, [r7, #4] 800430a: 689b ldr r3, [r3, #8] 800430c: f403 4304 and.w r3, r3, #33792 ; 0x8400 8004310: 431a orrs r2, r3 8004312: 687b ldr r3, [r7, #4] 8004314: 68db ldr r3, [r3, #12] 8004316: f403 6300 and.w r3, r3, #2048 ; 0x800 800431a: 431a orrs r2, r3 800431c: 687b ldr r3, [r7, #4] 800431e: 691b ldr r3, [r3, #16] 8004320: f003 0302 and.w r3, r3, #2 8004324: 431a orrs r2, r3 8004326: 687b ldr r3, [r7, #4] 8004328: 695b ldr r3, [r3, #20] 800432a: f003 0301 and.w r3, r3, #1 800432e: 431a orrs r2, r3 8004330: 687b ldr r3, [r7, #4] 8004332: 699b ldr r3, [r3, #24] 8004334: f403 7300 and.w r3, r3, #512 ; 0x200 8004338: 431a orrs r2, r3 800433a: 687b ldr r3, [r7, #4] 800433c: 69db ldr r3, [r3, #28] 800433e: f003 0338 and.w r3, r3, #56 ; 0x38 8004342: 431a orrs r2, r3 8004344: 687b ldr r3, [r7, #4] 8004346: 6a1b ldr r3, [r3, #32] 8004348: f003 0380 and.w r3, r3, #128 ; 0x80 800434c: ea42 0103 orr.w r1, r2, r3 8004350: 687b ldr r3, [r7, #4] 8004352: 6a9b ldr r3, [r3, #40] ; 0x28 8004354: f403 5200 and.w r2, r3, #8192 ; 0x2000 8004358: 687b ldr r3, [r7, #4] 800435a: 681b ldr r3, [r3, #0] 800435c: 430a orrs r2, r1 800435e: 601a str r2, [r3, #0] (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management */ WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); 8004360: 687b ldr r3, [r7, #4] 8004362: 699b ldr r3, [r3, #24] 8004364: 0c1a lsrs r2, r3, #16 8004366: 687b ldr r3, [r7, #4] 8004368: 681b ldr r3, [r3, #0] 800436a: f002 0204 and.w r2, r2, #4 800436e: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8004370: 687b ldr r3, [r7, #4] 8004372: 681b ldr r3, [r3, #0] 8004374: 69da ldr r2, [r3, #28] 8004376: 687b ldr r3, [r7, #4] 8004378: 681b ldr r3, [r3, #0] 800437a: f422 6200 bic.w r2, r2, #2048 ; 0x800 800437e: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004380: 687b ldr r3, [r7, #4] 8004382: 2200 movs r2, #0 8004384: 655a str r2, [r3, #84] ; 0x54 hspi->State = HAL_SPI_STATE_READY; 8004386: 687b ldr r3, [r7, #4] 8004388: 2201 movs r2, #1 800438a: f883 2051 strb.w r2, [r3, #81] ; 0x51 return HAL_OK; 800438e: 2300 movs r3, #0 } 8004390: 4618 mov r0, r3 8004392: 3708 adds r7, #8 8004394: 46bd mov sp, r7 8004396: bd80 pop {r7, pc} 08004398 <HAL_SPI_Transmit>: * @param Size amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004398: b580 push {r7, lr} 800439a: b088 sub sp, #32 800439c: af00 add r7, sp, #0 800439e: 60f8 str r0, [r7, #12] 80043a0: 60b9 str r1, [r7, #8] 80043a2: 603b str r3, [r7, #0] 80043a4: 4613 mov r3, r2 80043a6: 80fb strh r3, [r7, #6] uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; 80043a8: 2300 movs r3, #0 80043aa: 77fb strb r3, [r7, #31] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); 80043ac: 68fb ldr r3, [r7, #12] 80043ae: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 80043b2: 2b01 cmp r3, #1 80043b4: d101 bne.n 80043ba <HAL_SPI_Transmit+0x22> 80043b6: 2302 movs r3, #2 80043b8: e126 b.n 8004608 <HAL_SPI_Transmit+0x270> 80043ba: 68fb ldr r3, [r7, #12] 80043bc: 2201 movs r2, #1 80043be: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 80043c2: f7fe f92d bl 8002620 <HAL_GetTick> 80043c6: 61b8 str r0, [r7, #24] initial_TxXferCount = Size; 80043c8: 88fb ldrh r3, [r7, #6] 80043ca: 82fb strh r3, [r7, #22] if (hspi->State != HAL_SPI_STATE_READY) 80043cc: 68fb ldr r3, [r7, #12] 80043ce: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80043d2: b2db uxtb r3, r3 80043d4: 2b01 cmp r3, #1 80043d6: d002 beq.n 80043de <HAL_SPI_Transmit+0x46> { errorcode = HAL_BUSY; 80043d8: 2302 movs r3, #2 80043da: 77fb strb r3, [r7, #31] goto error; 80043dc: e10b b.n 80045f6 <HAL_SPI_Transmit+0x25e> } if ((pData == NULL) || (Size == 0U)) 80043de: 68bb ldr r3, [r7, #8] 80043e0: 2b00 cmp r3, #0 80043e2: d002 beq.n 80043ea <HAL_SPI_Transmit+0x52> 80043e4: 88fb ldrh r3, [r7, #6] 80043e6: 2b00 cmp r3, #0 80043e8: d102 bne.n 80043f0 <HAL_SPI_Transmit+0x58> { errorcode = HAL_ERROR; 80043ea: 2301 movs r3, #1 80043ec: 77fb strb r3, [r7, #31] goto error; 80043ee: e102 b.n 80045f6 <HAL_SPI_Transmit+0x25e> } /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 80043f0: 68fb ldr r3, [r7, #12] 80043f2: 2203 movs r2, #3 80043f4: f883 2051 strb.w r2, [r3, #81] ; 0x51 hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80043f8: 68fb ldr r3, [r7, #12] 80043fa: 2200 movs r2, #0 80043fc: 655a str r2, [r3, #84] ; 0x54 hspi->pTxBuffPtr = (uint8_t *)pData; 80043fe: 68fb ldr r3, [r7, #12] 8004400: 68ba ldr r2, [r7, #8] 8004402: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = Size; 8004404: 68fb ldr r3, [r7, #12] 8004406: 88fa ldrh r2, [r7, #6] 8004408: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = Size; 800440a: 68fb ldr r3, [r7, #12] 800440c: 88fa ldrh r2, [r7, #6] 800440e: 86da strh r2, [r3, #54] ; 0x36 /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 8004410: 68fb ldr r3, [r7, #12] 8004412: 2200 movs r2, #0 8004414: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = 0U; 8004416: 68fb ldr r3, [r7, #12] 8004418: 2200 movs r2, #0 800441a: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = 0U; 800441c: 68fb ldr r3, [r7, #12] 800441e: 2200 movs r2, #0 8004420: 87da strh r2, [r3, #62] ; 0x3e hspi->TxISR = NULL; 8004422: 68fb ldr r3, [r7, #12] 8004424: 2200 movs r2, #0 8004426: 645a str r2, [r3, #68] ; 0x44 hspi->RxISR = NULL; 8004428: 68fb ldr r3, [r7, #12] 800442a: 2200 movs r2, #0 800442c: 641a str r2, [r3, #64] ; 0x40 /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 800442e: 68fb ldr r3, [r7, #12] 8004430: 689b ldr r3, [r3, #8] 8004432: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004436: d10f bne.n 8004458 <HAL_SPI_Transmit+0xc0> { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8004438: 68fb ldr r3, [r7, #12] 800443a: 681b ldr r3, [r3, #0] 800443c: 681a ldr r2, [r3, #0] 800443e: 68fb ldr r3, [r7, #12] 8004440: 681b ldr r3, [r3, #0] 8004442: f022 0240 bic.w r2, r2, #64 ; 0x40 8004446: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 8004448: 68fb ldr r3, [r7, #12] 800444a: 681b ldr r3, [r3, #0] 800444c: 681a ldr r2, [r3, #0] 800444e: 68fb ldr r3, [r7, #12] 8004450: 681b ldr r3, [r3, #0] 8004452: f442 4280 orr.w r2, r2, #16384 ; 0x4000 8004456: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004458: 68fb ldr r3, [r7, #12] 800445a: 681b ldr r3, [r3, #0] 800445c: 681b ldr r3, [r3, #0] 800445e: f003 0340 and.w r3, r3, #64 ; 0x40 8004462: 2b40 cmp r3, #64 ; 0x40 8004464: d007 beq.n 8004476 <HAL_SPI_Transmit+0xde> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004466: 68fb ldr r3, [r7, #12] 8004468: 681b ldr r3, [r3, #0] 800446a: 681a ldr r2, [r3, #0] 800446c: 68fb ldr r3, [r7, #12] 800446e: 681b ldr r3, [r3, #0] 8004470: f042 0240 orr.w r2, r2, #64 ; 0x40 8004474: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) 8004476: 68fb ldr r3, [r7, #12] 8004478: 68db ldr r3, [r3, #12] 800447a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800447e: d14b bne.n 8004518 <HAL_SPI_Transmit+0x180> { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004480: 68fb ldr r3, [r7, #12] 8004482: 685b ldr r3, [r3, #4] 8004484: 2b00 cmp r3, #0 8004486: d002 beq.n 800448e <HAL_SPI_Transmit+0xf6> 8004488: 8afb ldrh r3, [r7, #22] 800448a: 2b01 cmp r3, #1 800448c: d13e bne.n 800450c <HAL_SPI_Transmit+0x174> { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 800448e: 68fb ldr r3, [r7, #12] 8004490: 6b1b ldr r3, [r3, #48] ; 0x30 8004492: 881a ldrh r2, [r3, #0] 8004494: 68fb ldr r3, [r7, #12] 8004496: 681b ldr r3, [r3, #0] 8004498: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800449a: 68fb ldr r3, [r7, #12] 800449c: 6b1b ldr r3, [r3, #48] ; 0x30 800449e: 1c9a adds r2, r3, #2 80044a0: 68fb ldr r3, [r7, #12] 80044a2: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 80044a4: 68fb ldr r3, [r7, #12] 80044a6: 8edb ldrh r3, [r3, #54] ; 0x36 80044a8: b29b uxth r3, r3 80044aa: 3b01 subs r3, #1 80044ac: b29a uxth r2, r3 80044ae: 68fb ldr r3, [r7, #12] 80044b0: 86da strh r2, [r3, #54] ; 0x36 } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 80044b2: e02b b.n 800450c <HAL_SPI_Transmit+0x174> { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 80044b4: 68fb ldr r3, [r7, #12] 80044b6: 681b ldr r3, [r3, #0] 80044b8: 689b ldr r3, [r3, #8] 80044ba: f003 0302 and.w r3, r3, #2 80044be: 2b02 cmp r3, #2 80044c0: d112 bne.n 80044e8 <HAL_SPI_Transmit+0x150> { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 80044c2: 68fb ldr r3, [r7, #12] 80044c4: 6b1b ldr r3, [r3, #48] ; 0x30 80044c6: 881a ldrh r2, [r3, #0] 80044c8: 68fb ldr r3, [r7, #12] 80044ca: 681b ldr r3, [r3, #0] 80044cc: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 80044ce: 68fb ldr r3, [r7, #12] 80044d0: 6b1b ldr r3, [r3, #48] ; 0x30 80044d2: 1c9a adds r2, r3, #2 80044d4: 68fb ldr r3, [r7, #12] 80044d6: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 80044d8: 68fb ldr r3, [r7, #12] 80044da: 8edb ldrh r3, [r3, #54] ; 0x36 80044dc: b29b uxth r3, r3 80044de: 3b01 subs r3, #1 80044e0: b29a uxth r2, r3 80044e2: 68fb ldr r3, [r7, #12] 80044e4: 86da strh r2, [r3, #54] ; 0x36 80044e6: e011 b.n 800450c <HAL_SPI_Transmit+0x174> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 80044e8: f7fe f89a bl 8002620 <HAL_GetTick> 80044ec: 4602 mov r2, r0 80044ee: 69bb ldr r3, [r7, #24] 80044f0: 1ad3 subs r3, r2, r3 80044f2: 683a ldr r2, [r7, #0] 80044f4: 429a cmp r2, r3 80044f6: d803 bhi.n 8004500 <HAL_SPI_Transmit+0x168> 80044f8: 683b ldr r3, [r7, #0] 80044fa: f1b3 3fff cmp.w r3, #4294967295 80044fe: d102 bne.n 8004506 <HAL_SPI_Transmit+0x16e> 8004500: 683b ldr r3, [r7, #0] 8004502: 2b00 cmp r3, #0 8004504: d102 bne.n 800450c <HAL_SPI_Transmit+0x174> { errorcode = HAL_TIMEOUT; 8004506: 2303 movs r3, #3 8004508: 77fb strb r3, [r7, #31] goto error; 800450a: e074 b.n 80045f6 <HAL_SPI_Transmit+0x25e> while (hspi->TxXferCount > 0U) 800450c: 68fb ldr r3, [r7, #12] 800450e: 8edb ldrh r3, [r3, #54] ; 0x36 8004510: b29b uxth r3, r3 8004512: 2b00 cmp r3, #0 8004514: d1ce bne.n 80044b4 <HAL_SPI_Transmit+0x11c> 8004516: e04c b.n 80045b2 <HAL_SPI_Transmit+0x21a> } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004518: 68fb ldr r3, [r7, #12] 800451a: 685b ldr r3, [r3, #4] 800451c: 2b00 cmp r3, #0 800451e: d002 beq.n 8004526 <HAL_SPI_Transmit+0x18e> 8004520: 8afb ldrh r3, [r7, #22] 8004522: 2b01 cmp r3, #1 8004524: d140 bne.n 80045a8 <HAL_SPI_Transmit+0x210> { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 8004526: 68fb ldr r3, [r7, #12] 8004528: 6b1a ldr r2, [r3, #48] ; 0x30 800452a: 68fb ldr r3, [r7, #12] 800452c: 681b ldr r3, [r3, #0] 800452e: 330c adds r3, #12 8004530: 7812 ldrb r2, [r2, #0] 8004532: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8004534: 68fb ldr r3, [r7, #12] 8004536: 6b1b ldr r3, [r3, #48] ; 0x30 8004538: 1c5a adds r2, r3, #1 800453a: 68fb ldr r3, [r7, #12] 800453c: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 800453e: 68fb ldr r3, [r7, #12] 8004540: 8edb ldrh r3, [r3, #54] ; 0x36 8004542: b29b uxth r3, r3 8004544: 3b01 subs r3, #1 8004546: b29a uxth r2, r3 8004548: 68fb ldr r3, [r7, #12] 800454a: 86da strh r2, [r3, #54] ; 0x36 } while (hspi->TxXferCount > 0U) 800454c: e02c b.n 80045a8 <HAL_SPI_Transmit+0x210> { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 800454e: 68fb ldr r3, [r7, #12] 8004550: 681b ldr r3, [r3, #0] 8004552: 689b ldr r3, [r3, #8] 8004554: f003 0302 and.w r3, r3, #2 8004558: 2b02 cmp r3, #2 800455a: d113 bne.n 8004584 <HAL_SPI_Transmit+0x1ec> { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 800455c: 68fb ldr r3, [r7, #12] 800455e: 6b1a ldr r2, [r3, #48] ; 0x30 8004560: 68fb ldr r3, [r7, #12] 8004562: 681b ldr r3, [r3, #0] 8004564: 330c adds r3, #12 8004566: 7812 ldrb r2, [r2, #0] 8004568: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 800456a: 68fb ldr r3, [r7, #12] 800456c: 6b1b ldr r3, [r3, #48] ; 0x30 800456e: 1c5a adds r2, r3, #1 8004570: 68fb ldr r3, [r7, #12] 8004572: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004574: 68fb ldr r3, [r7, #12] 8004576: 8edb ldrh r3, [r3, #54] ; 0x36 8004578: b29b uxth r3, r3 800457a: 3b01 subs r3, #1 800457c: b29a uxth r2, r3 800457e: 68fb ldr r3, [r7, #12] 8004580: 86da strh r2, [r3, #54] ; 0x36 8004582: e011 b.n 80045a8 <HAL_SPI_Transmit+0x210> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8004584: f7fe f84c bl 8002620 <HAL_GetTick> 8004588: 4602 mov r2, r0 800458a: 69bb ldr r3, [r7, #24] 800458c: 1ad3 subs r3, r2, r3 800458e: 683a ldr r2, [r7, #0] 8004590: 429a cmp r2, r3 8004592: d803 bhi.n 800459c <HAL_SPI_Transmit+0x204> 8004594: 683b ldr r3, [r7, #0] 8004596: f1b3 3fff cmp.w r3, #4294967295 800459a: d102 bne.n 80045a2 <HAL_SPI_Transmit+0x20a> 800459c: 683b ldr r3, [r7, #0] 800459e: 2b00 cmp r3, #0 80045a0: d102 bne.n 80045a8 <HAL_SPI_Transmit+0x210> { errorcode = HAL_TIMEOUT; 80045a2: 2303 movs r3, #3 80045a4: 77fb strb r3, [r7, #31] goto error; 80045a6: e026 b.n 80045f6 <HAL_SPI_Transmit+0x25e> while (hspi->TxXferCount > 0U) 80045a8: 68fb ldr r3, [r7, #12] 80045aa: 8edb ldrh r3, [r3, #54] ; 0x36 80045ac: b29b uxth r3, r3 80045ae: 2b00 cmp r3, #0 80045b0: d1cd bne.n 800454e <HAL_SPI_Transmit+0x1b6> SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 80045b2: 69ba ldr r2, [r7, #24] 80045b4: 6839 ldr r1, [r7, #0] 80045b6: 68f8 ldr r0, [r7, #12] 80045b8: f000 fe1a bl 80051f0 <SPI_EndRxTxTransaction> 80045bc: 4603 mov r3, r0 80045be: 2b00 cmp r3, #0 80045c0: d002 beq.n 80045c8 <HAL_SPI_Transmit+0x230> { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 80045c2: 68fb ldr r3, [r7, #12] 80045c4: 2220 movs r2, #32 80045c6: 655a str r2, [r3, #84] ; 0x54 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 80045c8: 68fb ldr r3, [r7, #12] 80045ca: 689b ldr r3, [r3, #8] 80045cc: 2b00 cmp r3, #0 80045ce: d10a bne.n 80045e6 <HAL_SPI_Transmit+0x24e> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 80045d0: 2300 movs r3, #0 80045d2: 613b str r3, [r7, #16] 80045d4: 68fb ldr r3, [r7, #12] 80045d6: 681b ldr r3, [r3, #0] 80045d8: 68db ldr r3, [r3, #12] 80045da: 613b str r3, [r7, #16] 80045dc: 68fb ldr r3, [r7, #12] 80045de: 681b ldr r3, [r3, #0] 80045e0: 689b ldr r3, [r3, #8] 80045e2: 613b str r3, [r7, #16] 80045e4: 693b ldr r3, [r7, #16] } if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 80045e6: 68fb ldr r3, [r7, #12] 80045e8: 6d5b ldr r3, [r3, #84] ; 0x54 80045ea: 2b00 cmp r3, #0 80045ec: d002 beq.n 80045f4 <HAL_SPI_Transmit+0x25c> { errorcode = HAL_ERROR; 80045ee: 2301 movs r3, #1 80045f0: 77fb strb r3, [r7, #31] 80045f2: e000 b.n 80045f6 <HAL_SPI_Transmit+0x25e> } error: 80045f4: bf00 nop hspi->State = HAL_SPI_STATE_READY; 80045f6: 68fb ldr r3, [r7, #12] 80045f8: 2201 movs r2, #1 80045fa: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); 80045fe: 68fb ldr r3, [r7, #12] 8004600: 2200 movs r2, #0 8004602: f883 2050 strb.w r2, [r3, #80] ; 0x50 return errorcode; 8004606: 7ffb ldrb r3, [r7, #31] } 8004608: 4618 mov r0, r3 800460a: 3720 adds r7, #32 800460c: 46bd mov sp, r7 800460e: bd80 pop {r7, pc} 08004610 <HAL_SPI_Receive>: * @param Size amount of data to be received * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004610: b580 push {r7, lr} 8004612: b088 sub sp, #32 8004614: af02 add r7, sp, #8 8004616: 60f8 str r0, [r7, #12] 8004618: 60b9 str r1, [r7, #8] 800461a: 603b str r3, [r7, #0] 800461c: 4613 mov r3, r2 800461e: 80fb strh r3, [r7, #6] #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; 8004620: 2300 movs r3, #0 8004622: 75fb strb r3, [r7, #23] if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) 8004624: 68fb ldr r3, [r7, #12] 8004626: 685b ldr r3, [r3, #4] 8004628: f5b3 7f82 cmp.w r3, #260 ; 0x104 800462c: d112 bne.n 8004654 <HAL_SPI_Receive+0x44> 800462e: 68fb ldr r3, [r7, #12] 8004630: 689b ldr r3, [r3, #8] 8004632: 2b00 cmp r3, #0 8004634: d10e bne.n 8004654 <HAL_SPI_Receive+0x44> { hspi->State = HAL_SPI_STATE_BUSY_RX; 8004636: 68fb ldr r3, [r7, #12] 8004638: 2204 movs r2, #4 800463a: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); 800463e: 88fa ldrh r2, [r7, #6] 8004640: 683b ldr r3, [r7, #0] 8004642: 9300 str r3, [sp, #0] 8004644: 4613 mov r3, r2 8004646: 68ba ldr r2, [r7, #8] 8004648: 68b9 ldr r1, [r7, #8] 800464a: 68f8 ldr r0, [r7, #12] 800464c: f000 f8f1 bl 8004832 <HAL_SPI_TransmitReceive> 8004650: 4603 mov r3, r0 8004652: e0ea b.n 800482a <HAL_SPI_Receive+0x21a> } /* Process Locked */ __HAL_LOCK(hspi); 8004654: 68fb ldr r3, [r7, #12] 8004656: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 800465a: 2b01 cmp r3, #1 800465c: d101 bne.n 8004662 <HAL_SPI_Receive+0x52> 800465e: 2302 movs r3, #2 8004660: e0e3 b.n 800482a <HAL_SPI_Receive+0x21a> 8004662: 68fb ldr r3, [r7, #12] 8004664: 2201 movs r2, #1 8004666: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800466a: f7fd ffd9 bl 8002620 <HAL_GetTick> 800466e: 6138 str r0, [r7, #16] if (hspi->State != HAL_SPI_STATE_READY) 8004670: 68fb ldr r3, [r7, #12] 8004672: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004676: b2db uxtb r3, r3 8004678: 2b01 cmp r3, #1 800467a: d002 beq.n 8004682 <HAL_SPI_Receive+0x72> { errorcode = HAL_BUSY; 800467c: 2302 movs r3, #2 800467e: 75fb strb r3, [r7, #23] goto error; 8004680: e0ca b.n 8004818 <HAL_SPI_Receive+0x208> } if ((pData == NULL) || (Size == 0U)) 8004682: 68bb ldr r3, [r7, #8] 8004684: 2b00 cmp r3, #0 8004686: d002 beq.n 800468e <HAL_SPI_Receive+0x7e> 8004688: 88fb ldrh r3, [r7, #6] 800468a: 2b00 cmp r3, #0 800468c: d102 bne.n 8004694 <HAL_SPI_Receive+0x84> { errorcode = HAL_ERROR; 800468e: 2301 movs r3, #1 8004690: 75fb strb r3, [r7, #23] goto error; 8004692: e0c1 b.n 8004818 <HAL_SPI_Receive+0x208> } /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; 8004694: 68fb ldr r3, [r7, #12] 8004696: 2204 movs r2, #4 8004698: f883 2051 strb.w r2, [r3, #81] ; 0x51 hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800469c: 68fb ldr r3, [r7, #12] 800469e: 2200 movs r2, #0 80046a0: 655a str r2, [r3, #84] ; 0x54 hspi->pRxBuffPtr = (uint8_t *)pData; 80046a2: 68fb ldr r3, [r7, #12] 80046a4: 68ba ldr r2, [r7, #8] 80046a6: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = Size; 80046a8: 68fb ldr r3, [r7, #12] 80046aa: 88fa ldrh r2, [r7, #6] 80046ac: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = Size; 80046ae: 68fb ldr r3, [r7, #12] 80046b0: 88fa ldrh r2, [r7, #6] 80046b2: 87da strh r2, [r3, #62] ; 0x3e /*Init field not used in handle to zero */ hspi->pTxBuffPtr = (uint8_t *)NULL; 80046b4: 68fb ldr r3, [r7, #12] 80046b6: 2200 movs r2, #0 80046b8: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = 0U; 80046ba: 68fb ldr r3, [r7, #12] 80046bc: 2200 movs r2, #0 80046be: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = 0U; 80046c0: 68fb ldr r3, [r7, #12] 80046c2: 2200 movs r2, #0 80046c4: 86da strh r2, [r3, #54] ; 0x36 hspi->RxISR = NULL; 80046c6: 68fb ldr r3, [r7, #12] 80046c8: 2200 movs r2, #0 80046ca: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = NULL; 80046cc: 68fb ldr r3, [r7, #12] 80046ce: 2200 movs r2, #0 80046d0: 645a str r2, [r3, #68] ; 0x44 hspi->RxXferCount--; } #endif /* USE_SPI_CRC */ /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 80046d2: 68fb ldr r3, [r7, #12] 80046d4: 689b ldr r3, [r3, #8] 80046d6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 80046da: d10f bne.n 80046fc <HAL_SPI_Receive+0xec> { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 80046dc: 68fb ldr r3, [r7, #12] 80046de: 681b ldr r3, [r3, #0] 80046e0: 681a ldr r2, [r3, #0] 80046e2: 68fb ldr r3, [r7, #12] 80046e4: 681b ldr r3, [r3, #0] 80046e6: f022 0240 bic.w r2, r2, #64 ; 0x40 80046ea: 601a str r2, [r3, #0] SPI_1LINE_RX(hspi); 80046ec: 68fb ldr r3, [r7, #12] 80046ee: 681b ldr r3, [r3, #0] 80046f0: 681a ldr r2, [r3, #0] 80046f2: 68fb ldr r3, [r7, #12] 80046f4: 681b ldr r3, [r3, #0] 80046f6: f422 4280 bic.w r2, r2, #16384 ; 0x4000 80046fa: 601a str r2, [r3, #0] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 80046fc: 68fb ldr r3, [r7, #12] 80046fe: 681b ldr r3, [r3, #0] 8004700: 681b ldr r3, [r3, #0] 8004702: f003 0340 and.w r3, r3, #64 ; 0x40 8004706: 2b40 cmp r3, #64 ; 0x40 8004708: d007 beq.n 800471a <HAL_SPI_Receive+0x10a> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800470a: 68fb ldr r3, [r7, #12] 800470c: 681b ldr r3, [r3, #0] 800470e: 681a ldr r2, [r3, #0] 8004710: 68fb ldr r3, [r7, #12] 8004712: 681b ldr r3, [r3, #0] 8004714: f042 0240 orr.w r2, r2, #64 ; 0x40 8004718: 601a str r2, [r3, #0] } /* Receive data in 8 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) 800471a: 68fb ldr r3, [r7, #12] 800471c: 68db ldr r3, [r3, #12] 800471e: 2b00 cmp r3, #0 8004720: d162 bne.n 80047e8 <HAL_SPI_Receive+0x1d8> { /* Transfer loop */ while (hspi->RxXferCount > 0U) 8004722: e02e b.n 8004782 <HAL_SPI_Receive+0x172> { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 8004724: 68fb ldr r3, [r7, #12] 8004726: 681b ldr r3, [r3, #0] 8004728: 689b ldr r3, [r3, #8] 800472a: f003 0301 and.w r3, r3, #1 800472e: 2b01 cmp r3, #1 8004730: d115 bne.n 800475e <HAL_SPI_Receive+0x14e> { /* read the received data */ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 8004732: 68fb ldr r3, [r7, #12] 8004734: 681b ldr r3, [r3, #0] 8004736: f103 020c add.w r2, r3, #12 800473a: 68fb ldr r3, [r7, #12] 800473c: 6b9b ldr r3, [r3, #56] ; 0x38 800473e: 7812 ldrb r2, [r2, #0] 8004740: b2d2 uxtb r2, r2 8004742: 701a strb r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint8_t); 8004744: 68fb ldr r3, [r7, #12] 8004746: 6b9b ldr r3, [r3, #56] ; 0x38 8004748: 1c5a adds r2, r3, #1 800474a: 68fb ldr r3, [r7, #12] 800474c: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 800474e: 68fb ldr r3, [r7, #12] 8004750: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004752: b29b uxth r3, r3 8004754: 3b01 subs r3, #1 8004756: b29a uxth r2, r3 8004758: 68fb ldr r3, [r7, #12] 800475a: 87da strh r2, [r3, #62] ; 0x3e 800475c: e011 b.n 8004782 <HAL_SPI_Receive+0x172> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 800475e: f7fd ff5f bl 8002620 <HAL_GetTick> 8004762: 4602 mov r2, r0 8004764: 693b ldr r3, [r7, #16] 8004766: 1ad3 subs r3, r2, r3 8004768: 683a ldr r2, [r7, #0] 800476a: 429a cmp r2, r3 800476c: d803 bhi.n 8004776 <HAL_SPI_Receive+0x166> 800476e: 683b ldr r3, [r7, #0] 8004770: f1b3 3fff cmp.w r3, #4294967295 8004774: d102 bne.n 800477c <HAL_SPI_Receive+0x16c> 8004776: 683b ldr r3, [r7, #0] 8004778: 2b00 cmp r3, #0 800477a: d102 bne.n 8004782 <HAL_SPI_Receive+0x172> { errorcode = HAL_TIMEOUT; 800477c: 2303 movs r3, #3 800477e: 75fb strb r3, [r7, #23] goto error; 8004780: e04a b.n 8004818 <HAL_SPI_Receive+0x208> while (hspi->RxXferCount > 0U) 8004782: 68fb ldr r3, [r7, #12] 8004784: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004786: b29b uxth r3, r3 8004788: 2b00 cmp r3, #0 800478a: d1cb bne.n 8004724 <HAL_SPI_Receive+0x114> 800478c: e031 b.n 80047f2 <HAL_SPI_Receive+0x1e2> { /* Transfer loop */ while (hspi->RxXferCount > 0U) { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 800478e: 68fb ldr r3, [r7, #12] 8004790: 681b ldr r3, [r3, #0] 8004792: 689b ldr r3, [r3, #8] 8004794: f003 0301 and.w r3, r3, #1 8004798: 2b01 cmp r3, #1 800479a: d113 bne.n 80047c4 <HAL_SPI_Receive+0x1b4> { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800479c: 68fb ldr r3, [r7, #12] 800479e: 681b ldr r3, [r3, #0] 80047a0: 68da ldr r2, [r3, #12] 80047a2: 68fb ldr r3, [r7, #12] 80047a4: 6b9b ldr r3, [r3, #56] ; 0x38 80047a6: b292 uxth r2, r2 80047a8: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 80047aa: 68fb ldr r3, [r7, #12] 80047ac: 6b9b ldr r3, [r3, #56] ; 0x38 80047ae: 1c9a adds r2, r3, #2 80047b0: 68fb ldr r3, [r7, #12] 80047b2: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 80047b4: 68fb ldr r3, [r7, #12] 80047b6: 8fdb ldrh r3, [r3, #62] ; 0x3e 80047b8: b29b uxth r3, r3 80047ba: 3b01 subs r3, #1 80047bc: b29a uxth r2, r3 80047be: 68fb ldr r3, [r7, #12] 80047c0: 87da strh r2, [r3, #62] ; 0x3e 80047c2: e011 b.n 80047e8 <HAL_SPI_Receive+0x1d8> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 80047c4: f7fd ff2c bl 8002620 <HAL_GetTick> 80047c8: 4602 mov r2, r0 80047ca: 693b ldr r3, [r7, #16] 80047cc: 1ad3 subs r3, r2, r3 80047ce: 683a ldr r2, [r7, #0] 80047d0: 429a cmp r2, r3 80047d2: d803 bhi.n 80047dc <HAL_SPI_Receive+0x1cc> 80047d4: 683b ldr r3, [r7, #0] 80047d6: f1b3 3fff cmp.w r3, #4294967295 80047da: d102 bne.n 80047e2 <HAL_SPI_Receive+0x1d2> 80047dc: 683b ldr r3, [r7, #0] 80047de: 2b00 cmp r3, #0 80047e0: d102 bne.n 80047e8 <HAL_SPI_Receive+0x1d8> { errorcode = HAL_TIMEOUT; 80047e2: 2303 movs r3, #3 80047e4: 75fb strb r3, [r7, #23] goto error; 80047e6: e017 b.n 8004818 <HAL_SPI_Receive+0x208> while (hspi->RxXferCount > 0U) 80047e8: 68fb ldr r3, [r7, #12] 80047ea: 8fdb ldrh r3, [r3, #62] ; 0x3e 80047ec: b29b uxth r3, r3 80047ee: 2b00 cmp r3, #0 80047f0: d1cd bne.n 800478e <HAL_SPI_Receive+0x17e> UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) 80047f2: 693a ldr r2, [r7, #16] 80047f4: 6839 ldr r1, [r7, #0] 80047f6: 68f8 ldr r0, [r7, #12] 80047f8: f000 fca8 bl 800514c <SPI_EndRxTransaction> 80047fc: 4603 mov r3, r0 80047fe: 2b00 cmp r3, #0 8004800: d002 beq.n 8004808 <HAL_SPI_Receive+0x1f8> { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8004802: 68fb ldr r3, [r7, #12] 8004804: 2220 movs r2, #32 8004806: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8004808: 68fb ldr r3, [r7, #12] 800480a: 6d5b ldr r3, [r3, #84] ; 0x54 800480c: 2b00 cmp r3, #0 800480e: d002 beq.n 8004816 <HAL_SPI_Receive+0x206> { errorcode = HAL_ERROR; 8004810: 2301 movs r3, #1 8004812: 75fb strb r3, [r7, #23] 8004814: e000 b.n 8004818 <HAL_SPI_Receive+0x208> } error : 8004816: bf00 nop hspi->State = HAL_SPI_STATE_READY; 8004818: 68fb ldr r3, [r7, #12] 800481a: 2201 movs r2, #1 800481c: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004820: 68fb ldr r3, [r7, #12] 8004822: 2200 movs r2, #0 8004824: f883 2050 strb.w r2, [r3, #80] ; 0x50 return errorcode; 8004828: 7dfb ldrb r3, [r7, #23] } 800482a: 4618 mov r0, r3 800482c: 3718 adds r7, #24 800482e: 46bd mov sp, r7 8004830: bd80 pop {r7, pc} 08004832 <HAL_SPI_TransmitReceive>: * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 8004832: b580 push {r7, lr} 8004834: b08c sub sp, #48 ; 0x30 8004836: af00 add r7, sp, #0 8004838: 60f8 str r0, [r7, #12] 800483a: 60b9 str r1, [r7, #8] 800483c: 607a str r2, [r7, #4] 800483e: 807b strh r3, [r7, #2] #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 8004840: 2301 movs r3, #1 8004842: 62fb str r3, [r7, #44] ; 0x2c HAL_StatusTypeDef errorcode = HAL_OK; 8004844: 2300 movs r3, #0 8004846: f887 302b strb.w r3, [r7, #43] ; 0x2b /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); 800484a: 68fb ldr r3, [r7, #12] 800484c: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 8004850: 2b01 cmp r3, #1 8004852: d101 bne.n 8004858 <HAL_SPI_TransmitReceive+0x26> 8004854: 2302 movs r3, #2 8004856: e18a b.n 8004b6e <HAL_SPI_TransmitReceive+0x33c> 8004858: 68fb ldr r3, [r7, #12] 800485a: 2201 movs r2, #1 800485c: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8004860: f7fd fede bl 8002620 <HAL_GetTick> 8004864: 6278 str r0, [r7, #36] ; 0x24 /* Init temporary variables */ tmp_state = hspi->State; 8004866: 68fb ldr r3, [r7, #12] 8004868: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 800486c: f887 3023 strb.w r3, [r7, #35] ; 0x23 tmp_mode = hspi->Init.Mode; 8004870: 68fb ldr r3, [r7, #12] 8004872: 685b ldr r3, [r3, #4] 8004874: 61fb str r3, [r7, #28] initial_TxXferCount = Size; 8004876: 887b ldrh r3, [r7, #2] 8004878: 837b strh r3, [r7, #26] if (!((tmp_state == HAL_SPI_STATE_READY) || \ 800487a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 800487e: 2b01 cmp r3, #1 8004880: d00f beq.n 80048a2 <HAL_SPI_TransmitReceive+0x70> 8004882: 69fb ldr r3, [r7, #28] 8004884: f5b3 7f82 cmp.w r3, #260 ; 0x104 8004888: d107 bne.n 800489a <HAL_SPI_TransmitReceive+0x68> ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) 800488a: 68fb ldr r3, [r7, #12] 800488c: 689b ldr r3, [r3, #8] 800488e: 2b00 cmp r3, #0 8004890: d103 bne.n 800489a <HAL_SPI_TransmitReceive+0x68> 8004892: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 8004896: 2b04 cmp r3, #4 8004898: d003 beq.n 80048a2 <HAL_SPI_TransmitReceive+0x70> { errorcode = HAL_BUSY; 800489a: 2302 movs r3, #2 800489c: f887 302b strb.w r3, [r7, #43] ; 0x2b goto error; 80048a0: e15b b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 80048a2: 68bb ldr r3, [r7, #8] 80048a4: 2b00 cmp r3, #0 80048a6: d005 beq.n 80048b4 <HAL_SPI_TransmitReceive+0x82> 80048a8: 687b ldr r3, [r7, #4] 80048aa: 2b00 cmp r3, #0 80048ac: d002 beq.n 80048b4 <HAL_SPI_TransmitReceive+0x82> 80048ae: 887b ldrh r3, [r7, #2] 80048b0: 2b00 cmp r3, #0 80048b2: d103 bne.n 80048bc <HAL_SPI_TransmitReceive+0x8a> { errorcode = HAL_ERROR; 80048b4: 2301 movs r3, #1 80048b6: f887 302b strb.w r3, [r7, #43] ; 0x2b goto error; 80048ba: e14e b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> } /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 80048bc: 68fb ldr r3, [r7, #12] 80048be: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80048c2: b2db uxtb r3, r3 80048c4: 2b04 cmp r3, #4 80048c6: d003 beq.n 80048d0 <HAL_SPI_TransmitReceive+0x9e> { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 80048c8: 68fb ldr r3, [r7, #12] 80048ca: 2205 movs r2, #5 80048cc: f883 2051 strb.w r2, [r3, #81] ; 0x51 } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80048d0: 68fb ldr r3, [r7, #12] 80048d2: 2200 movs r2, #0 80048d4: 655a str r2, [r3, #84] ; 0x54 hspi->pRxBuffPtr = (uint8_t *)pRxData; 80048d6: 68fb ldr r3, [r7, #12] 80048d8: 687a ldr r2, [r7, #4] 80048da: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount = Size; 80048dc: 68fb ldr r3, [r7, #12] 80048de: 887a ldrh r2, [r7, #2] 80048e0: 87da strh r2, [r3, #62] ; 0x3e hspi->RxXferSize = Size; 80048e2: 68fb ldr r3, [r7, #12] 80048e4: 887a ldrh r2, [r7, #2] 80048e6: 879a strh r2, [r3, #60] ; 0x3c hspi->pTxBuffPtr = (uint8_t *)pTxData; 80048e8: 68fb ldr r3, [r7, #12] 80048ea: 68ba ldr r2, [r7, #8] 80048ec: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount = Size; 80048ee: 68fb ldr r3, [r7, #12] 80048f0: 887a ldrh r2, [r7, #2] 80048f2: 86da strh r2, [r3, #54] ; 0x36 hspi->TxXferSize = Size; 80048f4: 68fb ldr r3, [r7, #12] 80048f6: 887a ldrh r2, [r7, #2] 80048f8: 869a strh r2, [r3, #52] ; 0x34 /*Init field not used in handle to zero */ hspi->RxISR = NULL; 80048fa: 68fb ldr r3, [r7, #12] 80048fc: 2200 movs r2, #0 80048fe: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = NULL; 8004900: 68fb ldr r3, [r7, #12] 8004902: 2200 movs r2, #0 8004904: 645a str r2, [r3, #68] ; 0x44 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004906: 68fb ldr r3, [r7, #12] 8004908: 681b ldr r3, [r3, #0] 800490a: 681b ldr r3, [r3, #0] 800490c: f003 0340 and.w r3, r3, #64 ; 0x40 8004910: 2b40 cmp r3, #64 ; 0x40 8004912: d007 beq.n 8004924 <HAL_SPI_TransmitReceive+0xf2> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004914: 68fb ldr r3, [r7, #12] 8004916: 681b ldr r3, [r3, #0] 8004918: 681a ldr r2, [r3, #0] 800491a: 68fb ldr r3, [r7, #12] 800491c: 681b ldr r3, [r3, #0] 800491e: f042 0240 orr.w r2, r2, #64 ; 0x40 8004922: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) 8004924: 68fb ldr r3, [r7, #12] 8004926: 68db ldr r3, [r3, #12] 8004928: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800492c: d178 bne.n 8004a20 <HAL_SPI_TransmitReceive+0x1ee> { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800492e: 68fb ldr r3, [r7, #12] 8004930: 685b ldr r3, [r3, #4] 8004932: 2b00 cmp r3, #0 8004934: d002 beq.n 800493c <HAL_SPI_TransmitReceive+0x10a> 8004936: 8b7b ldrh r3, [r7, #26] 8004938: 2b01 cmp r3, #1 800493a: d166 bne.n 8004a0a <HAL_SPI_TransmitReceive+0x1d8> { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 800493c: 68fb ldr r3, [r7, #12] 800493e: 6b1b ldr r3, [r3, #48] ; 0x30 8004940: 881a ldrh r2, [r3, #0] 8004942: 68fb ldr r3, [r7, #12] 8004944: 681b ldr r3, [r3, #0] 8004946: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8004948: 68fb ldr r3, [r7, #12] 800494a: 6b1b ldr r3, [r3, #48] ; 0x30 800494c: 1c9a adds r2, r3, #2 800494e: 68fb ldr r3, [r7, #12] 8004950: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004952: 68fb ldr r3, [r7, #12] 8004954: 8edb ldrh r3, [r3, #54] ; 0x36 8004956: b29b uxth r3, r3 8004958: 3b01 subs r3, #1 800495a: b29a uxth r2, r3 800495c: 68fb ldr r3, [r7, #12] 800495e: 86da strh r2, [r3, #54] ; 0x36 } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004960: e053 b.n 8004a0a <HAL_SPI_TransmitReceive+0x1d8> { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 8004962: 68fb ldr r3, [r7, #12] 8004964: 681b ldr r3, [r3, #0] 8004966: 689b ldr r3, [r3, #8] 8004968: f003 0302 and.w r3, r3, #2 800496c: 2b02 cmp r3, #2 800496e: d11b bne.n 80049a8 <HAL_SPI_TransmitReceive+0x176> 8004970: 68fb ldr r3, [r7, #12] 8004972: 8edb ldrh r3, [r3, #54] ; 0x36 8004974: b29b uxth r3, r3 8004976: 2b00 cmp r3, #0 8004978: d016 beq.n 80049a8 <HAL_SPI_TransmitReceive+0x176> 800497a: 6afb ldr r3, [r7, #44] ; 0x2c 800497c: 2b01 cmp r3, #1 800497e: d113 bne.n 80049a8 <HAL_SPI_TransmitReceive+0x176> { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8004980: 68fb ldr r3, [r7, #12] 8004982: 6b1b ldr r3, [r3, #48] ; 0x30 8004984: 881a ldrh r2, [r3, #0] 8004986: 68fb ldr r3, [r7, #12] 8004988: 681b ldr r3, [r3, #0] 800498a: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800498c: 68fb ldr r3, [r7, #12] 800498e: 6b1b ldr r3, [r3, #48] ; 0x30 8004990: 1c9a adds r2, r3, #2 8004992: 68fb ldr r3, [r7, #12] 8004994: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004996: 68fb ldr r3, [r7, #12] 8004998: 8edb ldrh r3, [r3, #54] ; 0x36 800499a: b29b uxth r3, r3 800499c: 3b01 subs r3, #1 800499e: b29a uxth r2, r3 80049a0: 68fb ldr r3, [r7, #12] 80049a2: 86da strh r2, [r3, #54] ; 0x36 /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 80049a4: 2300 movs r3, #0 80049a6: 62fb str r3, [r7, #44] ; 0x2c } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 80049a8: 68fb ldr r3, [r7, #12] 80049aa: 681b ldr r3, [r3, #0] 80049ac: 689b ldr r3, [r3, #8] 80049ae: f003 0301 and.w r3, r3, #1 80049b2: 2b01 cmp r3, #1 80049b4: d119 bne.n 80049ea <HAL_SPI_TransmitReceive+0x1b8> 80049b6: 68fb ldr r3, [r7, #12] 80049b8: 8fdb ldrh r3, [r3, #62] ; 0x3e 80049ba: b29b uxth r3, r3 80049bc: 2b00 cmp r3, #0 80049be: d014 beq.n 80049ea <HAL_SPI_TransmitReceive+0x1b8> { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 80049c0: 68fb ldr r3, [r7, #12] 80049c2: 681b ldr r3, [r3, #0] 80049c4: 68da ldr r2, [r3, #12] 80049c6: 68fb ldr r3, [r7, #12] 80049c8: 6b9b ldr r3, [r3, #56] ; 0x38 80049ca: b292 uxth r2, r2 80049cc: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 80049ce: 68fb ldr r3, [r7, #12] 80049d0: 6b9b ldr r3, [r3, #56] ; 0x38 80049d2: 1c9a adds r2, r3, #2 80049d4: 68fb ldr r3, [r7, #12] 80049d6: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 80049d8: 68fb ldr r3, [r7, #12] 80049da: 8fdb ldrh r3, [r3, #62] ; 0x3e 80049dc: b29b uxth r3, r3 80049de: 3b01 subs r3, #1 80049e0: b29a uxth r2, r3 80049e2: 68fb ldr r3, [r7, #12] 80049e4: 87da strh r2, [r3, #62] ; 0x3e /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 80049e6: 2301 movs r3, #1 80049e8: 62fb str r3, [r7, #44] ; 0x2c } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 80049ea: f7fd fe19 bl 8002620 <HAL_GetTick> 80049ee: 4602 mov r2, r0 80049f0: 6a7b ldr r3, [r7, #36] ; 0x24 80049f2: 1ad3 subs r3, r2, r3 80049f4: 6bba ldr r2, [r7, #56] ; 0x38 80049f6: 429a cmp r2, r3 80049f8: d807 bhi.n 8004a0a <HAL_SPI_TransmitReceive+0x1d8> 80049fa: 6bbb ldr r3, [r7, #56] ; 0x38 80049fc: f1b3 3fff cmp.w r3, #4294967295 8004a00: d003 beq.n 8004a0a <HAL_SPI_TransmitReceive+0x1d8> { errorcode = HAL_TIMEOUT; 8004a02: 2303 movs r3, #3 8004a04: f887 302b strb.w r3, [r7, #43] ; 0x2b goto error; 8004a08: e0a7 b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004a0a: 68fb ldr r3, [r7, #12] 8004a0c: 8edb ldrh r3, [r3, #54] ; 0x36 8004a0e: b29b uxth r3, r3 8004a10: 2b00 cmp r3, #0 8004a12: d1a6 bne.n 8004962 <HAL_SPI_TransmitReceive+0x130> 8004a14: 68fb ldr r3, [r7, #12] 8004a16: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004a18: b29b uxth r3, r3 8004a1a: 2b00 cmp r3, #0 8004a1c: d1a1 bne.n 8004962 <HAL_SPI_TransmitReceive+0x130> 8004a1e: e07c b.n 8004b1a <HAL_SPI_TransmitReceive+0x2e8> } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004a20: 68fb ldr r3, [r7, #12] 8004a22: 685b ldr r3, [r3, #4] 8004a24: 2b00 cmp r3, #0 8004a26: d002 beq.n 8004a2e <HAL_SPI_TransmitReceive+0x1fc> 8004a28: 8b7b ldrh r3, [r7, #26] 8004a2a: 2b01 cmp r3, #1 8004a2c: d16b bne.n 8004b06 <HAL_SPI_TransmitReceive+0x2d4> { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 8004a2e: 68fb ldr r3, [r7, #12] 8004a30: 6b1a ldr r2, [r3, #48] ; 0x30 8004a32: 68fb ldr r3, [r7, #12] 8004a34: 681b ldr r3, [r3, #0] 8004a36: 330c adds r3, #12 8004a38: 7812 ldrb r2, [r2, #0] 8004a3a: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8004a3c: 68fb ldr r3, [r7, #12] 8004a3e: 6b1b ldr r3, [r3, #48] ; 0x30 8004a40: 1c5a adds r2, r3, #1 8004a42: 68fb ldr r3, [r7, #12] 8004a44: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004a46: 68fb ldr r3, [r7, #12] 8004a48: 8edb ldrh r3, [r3, #54] ; 0x36 8004a4a: b29b uxth r3, r3 8004a4c: 3b01 subs r3, #1 8004a4e: b29a uxth r2, r3 8004a50: 68fb ldr r3, [r7, #12] 8004a52: 86da strh r2, [r3, #54] ; 0x36 } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004a54: e057 b.n 8004b06 <HAL_SPI_TransmitReceive+0x2d4> { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 8004a56: 68fb ldr r3, [r7, #12] 8004a58: 681b ldr r3, [r3, #0] 8004a5a: 689b ldr r3, [r3, #8] 8004a5c: f003 0302 and.w r3, r3, #2 8004a60: 2b02 cmp r3, #2 8004a62: d11c bne.n 8004a9e <HAL_SPI_TransmitReceive+0x26c> 8004a64: 68fb ldr r3, [r7, #12] 8004a66: 8edb ldrh r3, [r3, #54] ; 0x36 8004a68: b29b uxth r3, r3 8004a6a: 2b00 cmp r3, #0 8004a6c: d017 beq.n 8004a9e <HAL_SPI_TransmitReceive+0x26c> 8004a6e: 6afb ldr r3, [r7, #44] ; 0x2c 8004a70: 2b01 cmp r3, #1 8004a72: d114 bne.n 8004a9e <HAL_SPI_TransmitReceive+0x26c> { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); 8004a74: 68fb ldr r3, [r7, #12] 8004a76: 6b1a ldr r2, [r3, #48] ; 0x30 8004a78: 68fb ldr r3, [r7, #12] 8004a7a: 681b ldr r3, [r3, #0] 8004a7c: 330c adds r3, #12 8004a7e: 7812 ldrb r2, [r2, #0] 8004a80: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8004a82: 68fb ldr r3, [r7, #12] 8004a84: 6b1b ldr r3, [r3, #48] ; 0x30 8004a86: 1c5a adds r2, r3, #1 8004a88: 68fb ldr r3, [r7, #12] 8004a8a: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004a8c: 68fb ldr r3, [r7, #12] 8004a8e: 8edb ldrh r3, [r3, #54] ; 0x36 8004a90: b29b uxth r3, r3 8004a92: 3b01 subs r3, #1 8004a94: b29a uxth r2, r3 8004a96: 68fb ldr r3, [r7, #12] 8004a98: 86da strh r2, [r3, #54] ; 0x36 /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 8004a9a: 2300 movs r3, #0 8004a9c: 62fb str r3, [r7, #44] ; 0x2c } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 8004a9e: 68fb ldr r3, [r7, #12] 8004aa0: 681b ldr r3, [r3, #0] 8004aa2: 689b ldr r3, [r3, #8] 8004aa4: f003 0301 and.w r3, r3, #1 8004aa8: 2b01 cmp r3, #1 8004aaa: d119 bne.n 8004ae0 <HAL_SPI_TransmitReceive+0x2ae> 8004aac: 68fb ldr r3, [r7, #12] 8004aae: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004ab0: b29b uxth r3, r3 8004ab2: 2b00 cmp r3, #0 8004ab4: d014 beq.n 8004ae0 <HAL_SPI_TransmitReceive+0x2ae> { (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; 8004ab6: 68fb ldr r3, [r7, #12] 8004ab8: 681b ldr r3, [r3, #0] 8004aba: 68da ldr r2, [r3, #12] 8004abc: 68fb ldr r3, [r7, #12] 8004abe: 6b9b ldr r3, [r3, #56] ; 0x38 8004ac0: b2d2 uxtb r2, r2 8004ac2: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 8004ac4: 68fb ldr r3, [r7, #12] 8004ac6: 6b9b ldr r3, [r3, #56] ; 0x38 8004ac8: 1c5a adds r2, r3, #1 8004aca: 68fb ldr r3, [r7, #12] 8004acc: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8004ace: 68fb ldr r3, [r7, #12] 8004ad0: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004ad2: b29b uxth r3, r3 8004ad4: 3b01 subs r3, #1 8004ad6: b29a uxth r2, r3 8004ad8: 68fb ldr r3, [r7, #12] 8004ada: 87da strh r2, [r3, #62] ; 0x3e /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 8004adc: 2301 movs r3, #1 8004ade: 62fb str r3, [r7, #44] ; 0x2c } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 8004ae0: f7fd fd9e bl 8002620 <HAL_GetTick> 8004ae4: 4602 mov r2, r0 8004ae6: 6a7b ldr r3, [r7, #36] ; 0x24 8004ae8: 1ad3 subs r3, r2, r3 8004aea: 6bba ldr r2, [r7, #56] ; 0x38 8004aec: 429a cmp r2, r3 8004aee: d803 bhi.n 8004af8 <HAL_SPI_TransmitReceive+0x2c6> 8004af0: 6bbb ldr r3, [r7, #56] ; 0x38 8004af2: f1b3 3fff cmp.w r3, #4294967295 8004af6: d102 bne.n 8004afe <HAL_SPI_TransmitReceive+0x2cc> 8004af8: 6bbb ldr r3, [r7, #56] ; 0x38 8004afa: 2b00 cmp r3, #0 8004afc: d103 bne.n 8004b06 <HAL_SPI_TransmitReceive+0x2d4> { errorcode = HAL_TIMEOUT; 8004afe: 2303 movs r3, #3 8004b00: f887 302b strb.w r3, [r7, #43] ; 0x2b goto error; 8004b04: e029 b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004b06: 68fb ldr r3, [r7, #12] 8004b08: 8edb ldrh r3, [r3, #54] ; 0x36 8004b0a: b29b uxth r3, r3 8004b0c: 2b00 cmp r3, #0 8004b0e: d1a2 bne.n 8004a56 <HAL_SPI_TransmitReceive+0x224> 8004b10: 68fb ldr r3, [r7, #12] 8004b12: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004b14: b29b uxth r3, r3 8004b16: 2b00 cmp r3, #0 8004b18: d19d bne.n 8004a56 <HAL_SPI_TransmitReceive+0x224> } } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 8004b1a: 6a7a ldr r2, [r7, #36] ; 0x24 8004b1c: 6bb9 ldr r1, [r7, #56] ; 0x38 8004b1e: 68f8 ldr r0, [r7, #12] 8004b20: f000 fb66 bl 80051f0 <SPI_EndRxTxTransaction> 8004b24: 4603 mov r3, r0 8004b26: 2b00 cmp r3, #0 8004b28: d006 beq.n 8004b38 <HAL_SPI_TransmitReceive+0x306> { errorcode = HAL_ERROR; 8004b2a: 2301 movs r3, #1 8004b2c: f887 302b strb.w r3, [r7, #43] ; 0x2b hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8004b30: 68fb ldr r3, [r7, #12] 8004b32: 2220 movs r2, #32 8004b34: 655a str r2, [r3, #84] ; 0x54 goto error; 8004b36: e010 b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 8004b38: 68fb ldr r3, [r7, #12] 8004b3a: 689b ldr r3, [r3, #8] 8004b3c: 2b00 cmp r3, #0 8004b3e: d10b bne.n 8004b58 <HAL_SPI_TransmitReceive+0x326> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8004b40: 2300 movs r3, #0 8004b42: 617b str r3, [r7, #20] 8004b44: 68fb ldr r3, [r7, #12] 8004b46: 681b ldr r3, [r3, #0] 8004b48: 68db ldr r3, [r3, #12] 8004b4a: 617b str r3, [r7, #20] 8004b4c: 68fb ldr r3, [r7, #12] 8004b4e: 681b ldr r3, [r3, #0] 8004b50: 689b ldr r3, [r3, #8] 8004b52: 617b str r3, [r7, #20] 8004b54: 697b ldr r3, [r7, #20] 8004b56: e000 b.n 8004b5a <HAL_SPI_TransmitReceive+0x328> } error : 8004b58: bf00 nop hspi->State = HAL_SPI_STATE_READY; 8004b5a: 68fb ldr r3, [r7, #12] 8004b5c: 2201 movs r2, #1 8004b5e: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004b62: 68fb ldr r3, [r7, #12] 8004b64: 2200 movs r2, #0 8004b66: f883 2050 strb.w r2, [r3, #80] ; 0x50 return errorcode; 8004b6a: f897 302b ldrb.w r3, [r7, #43] ; 0x2b } 8004b6e: 4618 mov r0, r3 8004b70: 3730 adds r7, #48 ; 0x30 8004b72: 46bd mov sp, r7 8004b74: bd80 pop {r7, pc} ... 08004b78 <HAL_SPI_TransmitReceive_IT>: * @param pRxData pointer to reception data buffer * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { 8004b78: b480 push {r7} 8004b7a: b087 sub sp, #28 8004b7c: af00 add r7, sp, #0 8004b7e: 60f8 str r0, [r7, #12] 8004b80: 60b9 str r1, [r7, #8] 8004b82: 607a str r2, [r7, #4] 8004b84: 807b strh r3, [r7, #2] uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; 8004b86: 2300 movs r3, #0 8004b88: 75fb strb r3, [r7, #23] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process locked */ __HAL_LOCK(hspi); 8004b8a: 68fb ldr r3, [r7, #12] 8004b8c: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 8004b90: 2b01 cmp r3, #1 8004b92: d101 bne.n 8004b98 <HAL_SPI_TransmitReceive_IT+0x20> 8004b94: 2302 movs r3, #2 8004b96: e075 b.n 8004c84 <HAL_SPI_TransmitReceive_IT+0x10c> 8004b98: 68fb ldr r3, [r7, #12] 8004b9a: 2201 movs r2, #1 8004b9c: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init temporary variables */ tmp_state = hspi->State; 8004ba0: 68fb ldr r3, [r7, #12] 8004ba2: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004ba6: 75bb strb r3, [r7, #22] tmp_mode = hspi->Init.Mode; 8004ba8: 68fb ldr r3, [r7, #12] 8004baa: 685b ldr r3, [r3, #4] 8004bac: 613b str r3, [r7, #16] if (!((tmp_state == HAL_SPI_STATE_READY) || \ 8004bae: 7dbb ldrb r3, [r7, #22] 8004bb0: 2b01 cmp r3, #1 8004bb2: d00d beq.n 8004bd0 <HAL_SPI_TransmitReceive_IT+0x58> 8004bb4: 693b ldr r3, [r7, #16] 8004bb6: f5b3 7f82 cmp.w r3, #260 ; 0x104 8004bba: d106 bne.n 8004bca <HAL_SPI_TransmitReceive_IT+0x52> ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) 8004bbc: 68fb ldr r3, [r7, #12] 8004bbe: 689b ldr r3, [r3, #8] 8004bc0: 2b00 cmp r3, #0 8004bc2: d102 bne.n 8004bca <HAL_SPI_TransmitReceive_IT+0x52> 8004bc4: 7dbb ldrb r3, [r7, #22] 8004bc6: 2b04 cmp r3, #4 8004bc8: d002 beq.n 8004bd0 <HAL_SPI_TransmitReceive_IT+0x58> { errorcode = HAL_BUSY; 8004bca: 2302 movs r3, #2 8004bcc: 75fb strb r3, [r7, #23] goto error; 8004bce: e054 b.n 8004c7a <HAL_SPI_TransmitReceive_IT+0x102> } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 8004bd0: 68bb ldr r3, [r7, #8] 8004bd2: 2b00 cmp r3, #0 8004bd4: d005 beq.n 8004be2 <HAL_SPI_TransmitReceive_IT+0x6a> 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 2b00 cmp r3, #0 8004bda: d002 beq.n 8004be2 <HAL_SPI_TransmitReceive_IT+0x6a> 8004bdc: 887b ldrh r3, [r7, #2] 8004bde: 2b00 cmp r3, #0 8004be0: d102 bne.n 8004be8 <HAL_SPI_TransmitReceive_IT+0x70> { errorcode = HAL_ERROR; 8004be2: 2301 movs r3, #1 8004be4: 75fb strb r3, [r7, #23] goto error; 8004be6: e048 b.n 8004c7a <HAL_SPI_TransmitReceive_IT+0x102> } /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 8004be8: 68fb ldr r3, [r7, #12] 8004bea: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004bee: b2db uxtb r3, r3 8004bf0: 2b04 cmp r3, #4 8004bf2: d003 beq.n 8004bfc <HAL_SPI_TransmitReceive_IT+0x84> { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 8004bf4: 68fb ldr r3, [r7, #12] 8004bf6: 2205 movs r2, #5 8004bf8: f883 2051 strb.w r2, [r3, #81] ; 0x51 } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004bfc: 68fb ldr r3, [r7, #12] 8004bfe: 2200 movs r2, #0 8004c00: 655a str r2, [r3, #84] ; 0x54 hspi->pTxBuffPtr = (uint8_t *)pTxData; 8004c02: 68fb ldr r3, [r7, #12] 8004c04: 68ba ldr r2, [r7, #8] 8004c06: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = Size; 8004c08: 68fb ldr r3, [r7, #12] 8004c0a: 887a ldrh r2, [r7, #2] 8004c0c: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = Size; 8004c0e: 68fb ldr r3, [r7, #12] 8004c10: 887a ldrh r2, [r7, #2] 8004c12: 86da strh r2, [r3, #54] ; 0x36 hspi->pRxBuffPtr = (uint8_t *)pRxData; 8004c14: 68fb ldr r3, [r7, #12] 8004c16: 687a ldr r2, [r7, #4] 8004c18: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = Size; 8004c1a: 68fb ldr r3, [r7, #12] 8004c1c: 887a ldrh r2, [r7, #2] 8004c1e: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = Size; 8004c20: 68fb ldr r3, [r7, #12] 8004c22: 887a ldrh r2, [r7, #2] 8004c24: 87da strh r2, [r3, #62] ; 0x3e /* Set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8004c26: 68fb ldr r3, [r7, #12] 8004c28: 68db ldr r3, [r3, #12] 8004c2a: 2b00 cmp r3, #0 8004c2c: d006 beq.n 8004c3c <HAL_SPI_TransmitReceive_IT+0xc4> { hspi->RxISR = SPI_2linesRxISR_16BIT; 8004c2e: 68fb ldr r3, [r7, #12] 8004c30: 4a17 ldr r2, [pc, #92] ; (8004c90 <HAL_SPI_TransmitReceive_IT+0x118>) 8004c32: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = SPI_2linesTxISR_16BIT; 8004c34: 68fb ldr r3, [r7, #12] 8004c36: 4a17 ldr r2, [pc, #92] ; (8004c94 <HAL_SPI_TransmitReceive_IT+0x11c>) 8004c38: 645a str r2, [r3, #68] ; 0x44 8004c3a: e005 b.n 8004c48 <HAL_SPI_TransmitReceive_IT+0xd0> } else { hspi->RxISR = SPI_2linesRxISR_8BIT; 8004c3c: 68fb ldr r3, [r7, #12] 8004c3e: 4a16 ldr r2, [pc, #88] ; (8004c98 <HAL_SPI_TransmitReceive_IT+0x120>) 8004c40: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = SPI_2linesTxISR_8BIT; 8004c42: 68fb ldr r3, [r7, #12] 8004c44: 4a15 ldr r2, [pc, #84] ; (8004c9c <HAL_SPI_TransmitReceive_IT+0x124>) 8004c46: 645a str r2, [r3, #68] ; 0x44 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8004c48: 68fb ldr r3, [r7, #12] 8004c4a: 681b ldr r3, [r3, #0] 8004c4c: 685a ldr r2, [r3, #4] 8004c4e: 68fb ldr r3, [r7, #12] 8004c50: 681b ldr r3, [r3, #0] 8004c52: f042 02e0 orr.w r2, r2, #224 ; 0xe0 8004c56: 605a str r2, [r3, #4] /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004c58: 68fb ldr r3, [r7, #12] 8004c5a: 681b ldr r3, [r3, #0] 8004c5c: 681b ldr r3, [r3, #0] 8004c5e: f003 0340 and.w r3, r3, #64 ; 0x40 8004c62: 2b40 cmp r3, #64 ; 0x40 8004c64: d008 beq.n 8004c78 <HAL_SPI_TransmitReceive_IT+0x100> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004c66: 68fb ldr r3, [r7, #12] 8004c68: 681b ldr r3, [r3, #0] 8004c6a: 681a ldr r2, [r3, #0] 8004c6c: 68fb ldr r3, [r7, #12] 8004c6e: 681b ldr r3, [r3, #0] 8004c70: f042 0240 orr.w r2, r2, #64 ; 0x40 8004c74: 601a str r2, [r3, #0] 8004c76: e000 b.n 8004c7a <HAL_SPI_TransmitReceive_IT+0x102> } error : 8004c78: bf00 nop /* Process Unlocked */ __HAL_UNLOCK(hspi); 8004c7a: 68fb ldr r3, [r7, #12] 8004c7c: 2200 movs r2, #0 8004c7e: f883 2050 strb.w r2, [r3, #80] ; 0x50 return errorcode; 8004c82: 7dfb ldrb r3, [r7, #23] } 8004c84: 4618 mov r0, r3 8004c86: 371c adds r7, #28 8004c88: 46bd mov sp, r7 8004c8a: bc80 pop {r7} 8004c8c: 4770 bx lr 8004c8e: bf00 nop 8004c90: 08004f7d .word 0x08004f7d 8004c94: 08004fdd .word 0x08004fdd 8004c98: 08004eb9 .word 0x08004eb9 8004c9c: 08004f1d .word 0x08004f1d 08004ca0 <HAL_SPI_IRQHandler>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { 8004ca0: b580 push {r7, lr} 8004ca2: b088 sub sp, #32 8004ca4: af00 add r7, sp, #0 8004ca6: 6078 str r0, [r7, #4] uint32_t itsource = hspi->Instance->CR2; 8004ca8: 687b ldr r3, [r7, #4] 8004caa: 681b ldr r3, [r3, #0] 8004cac: 685b ldr r3, [r3, #4] 8004cae: 61fb str r3, [r7, #28] uint32_t itflag = hspi->Instance->SR; 8004cb0: 687b ldr r3, [r7, #4] 8004cb2: 681b ldr r3, [r3, #0] 8004cb4: 689b ldr r3, [r3, #8] 8004cb6: 61bb str r3, [r7, #24] /* SPI in mode Receiver ----------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 8004cb8: 69bb ldr r3, [r7, #24] 8004cba: 099b lsrs r3, r3, #6 8004cbc: f003 0301 and.w r3, r3, #1 8004cc0: 2b00 cmp r3, #0 8004cc2: d10f bne.n 8004ce4 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 8004cc4: 69bb ldr r3, [r7, #24] 8004cc6: f003 0301 and.w r3, r3, #1 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 8004cca: 2b00 cmp r3, #0 8004ccc: d00a beq.n 8004ce4 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 8004cce: 69fb ldr r3, [r7, #28] 8004cd0: 099b lsrs r3, r3, #6 8004cd2: f003 0301 and.w r3, r3, #1 8004cd6: 2b00 cmp r3, #0 8004cd8: d004 beq.n 8004ce4 <HAL_SPI_IRQHandler+0x44> { hspi->RxISR(hspi); 8004cda: 687b ldr r3, [r7, #4] 8004cdc: 6c1b ldr r3, [r3, #64] ; 0x40 8004cde: 6878 ldr r0, [r7, #4] 8004ce0: 4798 blx r3 return; 8004ce2: e0be b.n 8004e62 <HAL_SPI_IRQHandler+0x1c2> } /* SPI in mode Transmitter -------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) 8004ce4: 69bb ldr r3, [r7, #24] 8004ce6: 085b lsrs r3, r3, #1 8004ce8: f003 0301 and.w r3, r3, #1 8004cec: 2b00 cmp r3, #0 8004cee: d00a beq.n 8004d06 <HAL_SPI_IRQHandler+0x66> 8004cf0: 69fb ldr r3, [r7, #28] 8004cf2: 09db lsrs r3, r3, #7 8004cf4: f003 0301 and.w r3, r3, #1 8004cf8: 2b00 cmp r3, #0 8004cfa: d004 beq.n 8004d06 <HAL_SPI_IRQHandler+0x66> { hspi->TxISR(hspi); 8004cfc: 687b ldr r3, [r7, #4] 8004cfe: 6c5b ldr r3, [r3, #68] ; 0x44 8004d00: 6878 ldr r0, [r7, #4] 8004d02: 4798 blx r3 return; 8004d04: e0ad b.n 8004e62 <HAL_SPI_IRQHandler+0x1c2> } /* SPI in Error Treatment --------------------------------------------------*/ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)) 8004d06: 69bb ldr r3, [r7, #24] 8004d08: 095b lsrs r3, r3, #5 8004d0a: f003 0301 and.w r3, r3, #1 8004d0e: 2b00 cmp r3, #0 8004d10: d106 bne.n 8004d20 <HAL_SPI_IRQHandler+0x80> 8004d12: 69bb ldr r3, [r7, #24] 8004d14: 099b lsrs r3, r3, #6 8004d16: f003 0301 and.w r3, r3, #1 8004d1a: 2b00 cmp r3, #0 8004d1c: f000 80a1 beq.w 8004e62 <HAL_SPI_IRQHandler+0x1c2> && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) 8004d20: 69fb ldr r3, [r7, #28] 8004d22: 095b lsrs r3, r3, #5 8004d24: f003 0301 and.w r3, r3, #1 8004d28: 2b00 cmp r3, #0 8004d2a: f000 809a beq.w 8004e62 <HAL_SPI_IRQHandler+0x1c2> { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) 8004d2e: 69bb ldr r3, [r7, #24] 8004d30: 099b lsrs r3, r3, #6 8004d32: f003 0301 and.w r3, r3, #1 8004d36: 2b00 cmp r3, #0 8004d38: d023 beq.n 8004d82 <HAL_SPI_IRQHandler+0xe2> { if (hspi->State != HAL_SPI_STATE_BUSY_TX) 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004d40: b2db uxtb r3, r3 8004d42: 2b03 cmp r3, #3 8004d44: d011 beq.n 8004d6a <HAL_SPI_IRQHandler+0xca> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); 8004d46: 687b ldr r3, [r7, #4] 8004d48: 6d5b ldr r3, [r3, #84] ; 0x54 8004d4a: f043 0204 orr.w r2, r3, #4 8004d4e: 687b ldr r3, [r7, #4] 8004d50: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_OVRFLAG(hspi); 8004d52: 2300 movs r3, #0 8004d54: 617b str r3, [r7, #20] 8004d56: 687b ldr r3, [r7, #4] 8004d58: 681b ldr r3, [r3, #0] 8004d5a: 68db ldr r3, [r3, #12] 8004d5c: 617b str r3, [r7, #20] 8004d5e: 687b ldr r3, [r7, #4] 8004d60: 681b ldr r3, [r3, #0] 8004d62: 689b ldr r3, [r3, #8] 8004d64: 617b str r3, [r7, #20] 8004d66: 697b ldr r3, [r7, #20] 8004d68: e00b b.n 8004d82 <HAL_SPI_IRQHandler+0xe2> } else { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8004d6a: 2300 movs r3, #0 8004d6c: 613b str r3, [r7, #16] 8004d6e: 687b ldr r3, [r7, #4] 8004d70: 681b ldr r3, [r3, #0] 8004d72: 68db ldr r3, [r3, #12] 8004d74: 613b str r3, [r7, #16] 8004d76: 687b ldr r3, [r7, #4] 8004d78: 681b ldr r3, [r3, #0] 8004d7a: 689b ldr r3, [r3, #8] 8004d7c: 613b str r3, [r7, #16] 8004d7e: 693b ldr r3, [r7, #16] return; 8004d80: e06f b.n 8004e62 <HAL_SPI_IRQHandler+0x1c2> } } /* SPI Mode Fault error interrupt occurred -------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) 8004d82: 69bb ldr r3, [r7, #24] 8004d84: 095b lsrs r3, r3, #5 8004d86: f003 0301 and.w r3, r3, #1 8004d8a: 2b00 cmp r3, #0 8004d8c: d014 beq.n 8004db8 <HAL_SPI_IRQHandler+0x118> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); 8004d8e: 687b ldr r3, [r7, #4] 8004d90: 6d5b ldr r3, [r3, #84] ; 0x54 8004d92: f043 0201 orr.w r2, r3, #1 8004d96: 687b ldr r3, [r7, #4] 8004d98: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_MODFFLAG(hspi); 8004d9a: 2300 movs r3, #0 8004d9c: 60fb str r3, [r7, #12] 8004d9e: 687b ldr r3, [r7, #4] 8004da0: 681b ldr r3, [r3, #0] 8004da2: 689b ldr r3, [r3, #8] 8004da4: 60fb str r3, [r7, #12] 8004da6: 687b ldr r3, [r7, #4] 8004da8: 681b ldr r3, [r3, #0] 8004daa: 681a ldr r2, [r3, #0] 8004dac: 687b ldr r3, [r7, #4] 8004dae: 681b ldr r3, [r3, #0] 8004db0: f022 0240 bic.w r2, r2, #64 ; 0x40 8004db4: 601a str r2, [r3, #0] 8004db6: 68fb ldr r3, [r7, #12] } /* SPI Frame error interrupt occurred ------------------------------------*/ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8004db8: 687b ldr r3, [r7, #4] 8004dba: 6d5b ldr r3, [r3, #84] ; 0x54 8004dbc: 2b00 cmp r3, #0 8004dbe: d04f beq.n 8004e60 <HAL_SPI_IRQHandler+0x1c0> { /* Disable all interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); 8004dc0: 687b ldr r3, [r7, #4] 8004dc2: 681b ldr r3, [r3, #0] 8004dc4: 685a ldr r2, [r3, #4] 8004dc6: 687b ldr r3, [r7, #4] 8004dc8: 681b ldr r3, [r3, #0] 8004dca: f022 02e0 bic.w r2, r2, #224 ; 0xe0 8004dce: 605a str r2, [r3, #4] hspi->State = HAL_SPI_STATE_READY; 8004dd0: 687b ldr r3, [r7, #4] 8004dd2: 2201 movs r2, #1 8004dd4: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Disable the SPI DMA requests if enabled */ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) 8004dd8: 69fb ldr r3, [r7, #28] 8004dda: f003 0302 and.w r3, r3, #2 8004dde: 2b00 cmp r3, #0 8004de0: d104 bne.n 8004dec <HAL_SPI_IRQHandler+0x14c> 8004de2: 69fb ldr r3, [r7, #28] 8004de4: f003 0301 and.w r3, r3, #1 8004de8: 2b00 cmp r3, #0 8004dea: d034 beq.n 8004e56 <HAL_SPI_IRQHandler+0x1b6> { CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); 8004dec: 687b ldr r3, [r7, #4] 8004dee: 681b ldr r3, [r3, #0] 8004df0: 685a ldr r2, [r3, #4] 8004df2: 687b ldr r3, [r7, #4] 8004df4: 681b ldr r3, [r3, #0] 8004df6: f022 0203 bic.w r2, r2, #3 8004dfa: 605a str r2, [r3, #4] /* Abort the SPI DMA Rx channel */ if (hspi->hdmarx != NULL) 8004dfc: 687b ldr r3, [r7, #4] 8004dfe: 6cdb ldr r3, [r3, #76] ; 0x4c 8004e00: 2b00 cmp r3, #0 8004e02: d011 beq.n 8004e28 <HAL_SPI_IRQHandler+0x188> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; 8004e04: 687b ldr r3, [r7, #4] 8004e06: 6cdb ldr r3, [r3, #76] ; 0x4c 8004e08: 4a17 ldr r2, [pc, #92] ; (8004e68 <HAL_SPI_IRQHandler+0x1c8>) 8004e0a: 635a str r2, [r3, #52] ; 0x34 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) 8004e0c: 687b ldr r3, [r7, #4] 8004e0e: 6cdb ldr r3, [r3, #76] ; 0x4c 8004e10: 4618 mov r0, r3 8004e12: f7fe fa53 bl 80032bc <HAL_DMA_Abort_IT> 8004e16: 4603 mov r3, r0 8004e18: 2b00 cmp r3, #0 8004e1a: d005 beq.n 8004e28 <HAL_SPI_IRQHandler+0x188> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 8004e1c: 687b ldr r3, [r7, #4] 8004e1e: 6d5b ldr r3, [r3, #84] ; 0x54 8004e20: f043 0240 orr.w r2, r3, #64 ; 0x40 8004e24: 687b ldr r3, [r7, #4] 8004e26: 655a str r2, [r3, #84] ; 0x54 } } /* Abort the SPI DMA Tx channel */ if (hspi->hdmatx != NULL) 8004e28: 687b ldr r3, [r7, #4] 8004e2a: 6c9b ldr r3, [r3, #72] ; 0x48 8004e2c: 2b00 cmp r3, #0 8004e2e: d016 beq.n 8004e5e <HAL_SPI_IRQHandler+0x1be> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; 8004e30: 687b ldr r3, [r7, #4] 8004e32: 6c9b ldr r3, [r3, #72] ; 0x48 8004e34: 4a0c ldr r2, [pc, #48] ; (8004e68 <HAL_SPI_IRQHandler+0x1c8>) 8004e36: 635a str r2, [r3, #52] ; 0x34 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) 8004e38: 687b ldr r3, [r7, #4] 8004e3a: 6c9b ldr r3, [r3, #72] ; 0x48 8004e3c: 4618 mov r0, r3 8004e3e: f7fe fa3d bl 80032bc <HAL_DMA_Abort_IT> 8004e42: 4603 mov r3, r0 8004e44: 2b00 cmp r3, #0 8004e46: d00a beq.n 8004e5e <HAL_SPI_IRQHandler+0x1be> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 8004e48: 687b ldr r3, [r7, #4] 8004e4a: 6d5b ldr r3, [r3, #84] ; 0x54 8004e4c: f043 0240 orr.w r2, r3, #64 ; 0x40 8004e50: 687b ldr r3, [r7, #4] 8004e52: 655a str r2, [r3, #84] ; 0x54 if (hspi->hdmatx != NULL) 8004e54: e003 b.n 8004e5e <HAL_SPI_IRQHandler+0x1be> { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 8004e56: 6878 ldr r0, [r7, #4] 8004e58: f000 f811 bl 8004e7e <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } return; 8004e5c: e000 b.n 8004e60 <HAL_SPI_IRQHandler+0x1c0> if (hspi->hdmatx != NULL) 8004e5e: bf00 nop return; 8004e60: bf00 nop } } 8004e62: 3720 adds r7, #32 8004e64: 46bd mov sp, r7 8004e66: bd80 pop {r7, pc} 8004e68: 08004e91 .word 0x08004e91 08004e6c <HAL_SPI_RxCpltCallback>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { 8004e6c: b480 push {r7} 8004e6e: b083 sub sp, #12 8004e70: af00 add r7, sp, #0 8004e72: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback should be implemented in the user file */ } 8004e74: bf00 nop 8004e76: 370c adds r7, #12 8004e78: 46bd mov sp, r7 8004e7a: bc80 pop {r7} 8004e7c: 4770 bx lr 08004e7e <HAL_SPI_ErrorCallback>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { 8004e7e: b480 push {r7} 8004e80: b083 sub sp, #12 8004e82: af00 add r7, sp, #0 8004e84: 6078 str r0, [r7, #4] the HAL_SPI_ErrorCallback should be implemented in the user file */ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes and user can use HAL_SPI_GetError() API to check the latest error occurred */ } 8004e86: bf00 nop 8004e88: 370c adds r7, #12 8004e8a: 46bd mov sp, r7 8004e8c: bc80 pop {r7} 8004e8e: 4770 bx lr 08004e90 <SPI_DMAAbortOnError>: * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8004e90: b580 push {r7, lr} 8004e92: b084 sub sp, #16 8004e94: af00 add r7, sp, #0 8004e96: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ 8004e98: 687b ldr r3, [r7, #4] 8004e9a: 6a5b ldr r3, [r3, #36] ; 0x24 8004e9c: 60fb str r3, [r7, #12] hspi->RxXferCount = 0U; 8004e9e: 68fb ldr r3, [r7, #12] 8004ea0: 2200 movs r2, #0 8004ea2: 87da strh r2, [r3, #62] ; 0x3e hspi->TxXferCount = 0U; 8004ea4: 68fb ldr r3, [r7, #12] 8004ea6: 2200 movs r2, #0 8004ea8: 86da strh r2, [r3, #54] ; 0x36 /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 8004eaa: 68f8 ldr r0, [r7, #12] 8004eac: f7ff ffe7 bl 8004e7e <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 8004eb0: bf00 nop 8004eb2: 3710 adds r7, #16 8004eb4: 46bd mov sp, r7 8004eb6: bd80 pop {r7, pc} 08004eb8 <SPI_2linesRxISR_8BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { 8004eb8: b580 push {r7, lr} 8004eba: b082 sub sp, #8 8004ebc: af00 add r7, sp, #0 8004ebe: 6078 str r0, [r7, #4] /* Receive data in 8bit mode */ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); 8004ec0: 687b ldr r3, [r7, #4] 8004ec2: 681b ldr r3, [r3, #0] 8004ec4: f103 020c add.w r2, r3, #12 8004ec8: 687b ldr r3, [r7, #4] 8004eca: 6b9b ldr r3, [r3, #56] ; 0x38 8004ecc: 7812 ldrb r2, [r2, #0] 8004ece: b2d2 uxtb r2, r2 8004ed0: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 8004ed2: 687b ldr r3, [r7, #4] 8004ed4: 6b9b ldr r3, [r3, #56] ; 0x38 8004ed6: 1c5a adds r2, r3, #1 8004ed8: 687b ldr r3, [r7, #4] 8004eda: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8004edc: 687b ldr r3, [r7, #4] 8004ede: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004ee0: b29b uxth r3, r3 8004ee2: 3b01 subs r3, #1 8004ee4: b29a uxth r2, r3 8004ee6: 687b ldr r3, [r7, #4] 8004ee8: 87da strh r2, [r3, #62] ; 0x3e /* Check end of the reception */ if (hspi->RxXferCount == 0U) 8004eea: 687b ldr r3, [r7, #4] 8004eec: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004eee: b29b uxth r3, r3 8004ef0: 2b00 cmp r3, #0 8004ef2: d10f bne.n 8004f14 <SPI_2linesRxISR_8BIT+0x5c> return; } #endif /* USE_SPI_CRC */ /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); 8004ef4: 687b ldr r3, [r7, #4] 8004ef6: 681b ldr r3, [r3, #0] 8004ef8: 685a ldr r2, [r3, #4] 8004efa: 687b ldr r3, [r7, #4] 8004efc: 681b ldr r3, [r3, #0] 8004efe: f022 0260 bic.w r2, r2, #96 ; 0x60 8004f02: 605a str r2, [r3, #4] if (hspi->TxXferCount == 0U) 8004f04: 687b ldr r3, [r7, #4] 8004f06: 8edb ldrh r3, [r3, #54] ; 0x36 8004f08: b29b uxth r3, r3 8004f0a: 2b00 cmp r3, #0 8004f0c: d102 bne.n 8004f14 <SPI_2linesRxISR_8BIT+0x5c> { SPI_CloseRxTx_ISR(hspi); 8004f0e: 6878 ldr r0, [r7, #4] 8004f10: f000 f98c bl 800522c <SPI_CloseRxTx_ISR> } } } 8004f14: bf00 nop 8004f16: 3708 adds r7, #8 8004f18: 46bd mov sp, r7 8004f1a: bd80 pop {r7, pc} 08004f1c <SPI_2linesTxISR_8BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { 8004f1c: b580 push {r7, lr} 8004f1e: b082 sub sp, #8 8004f20: af00 add r7, sp, #0 8004f22: 6078 str r0, [r7, #4] *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); 8004f24: 687b ldr r3, [r7, #4] 8004f26: 6b1a ldr r2, [r3, #48] ; 0x30 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 681b ldr r3, [r3, #0] 8004f2c: 330c adds r3, #12 8004f2e: 7812 ldrb r2, [r2, #0] 8004f30: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8004f32: 687b ldr r3, [r7, #4] 8004f34: 6b1b ldr r3, [r3, #48] ; 0x30 8004f36: 1c5a adds r2, r3, #1 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004f3c: 687b ldr r3, [r7, #4] 8004f3e: 8edb ldrh r3, [r3, #54] ; 0x36 8004f40: b29b uxth r3, r3 8004f42: 3b01 subs r3, #1 8004f44: b29a uxth r2, r3 8004f46: 687b ldr r3, [r7, #4] 8004f48: 86da strh r2, [r3, #54] ; 0x36 /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) 8004f4a: 687b ldr r3, [r7, #4] 8004f4c: 8edb ldrh r3, [r3, #54] ; 0x36 8004f4e: b29b uxth r3, r3 8004f50: 2b00 cmp r3, #0 8004f52: d10f bne.n 8004f74 <SPI_2linesTxISR_8BIT+0x58> return; } #endif /* USE_SPI_CRC */ /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); 8004f54: 687b ldr r3, [r7, #4] 8004f56: 681b ldr r3, [r3, #0] 8004f58: 685a ldr r2, [r3, #4] 8004f5a: 687b ldr r3, [r7, #4] 8004f5c: 681b ldr r3, [r3, #0] 8004f5e: f022 0280 bic.w r2, r2, #128 ; 0x80 8004f62: 605a str r2, [r3, #4] if (hspi->RxXferCount == 0U) 8004f64: 687b ldr r3, [r7, #4] 8004f66: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004f68: b29b uxth r3, r3 8004f6a: 2b00 cmp r3, #0 8004f6c: d102 bne.n 8004f74 <SPI_2linesTxISR_8BIT+0x58> { SPI_CloseRxTx_ISR(hspi); 8004f6e: 6878 ldr r0, [r7, #4] 8004f70: f000 f95c bl 800522c <SPI_CloseRxTx_ISR> } } } 8004f74: bf00 nop 8004f76: 3708 adds r7, #8 8004f78: 46bd mov sp, r7 8004f7a: bd80 pop {r7, pc} 08004f7c <SPI_2linesRxISR_16BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { 8004f7c: b580 push {r7, lr} 8004f7e: b082 sub sp, #8 8004f80: af00 add r7, sp, #0 8004f82: 6078 str r0, [r7, #4] /* Receive data in 16 Bit mode */ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); 8004f84: 687b ldr r3, [r7, #4] 8004f86: 681b ldr r3, [r3, #0] 8004f88: 68da ldr r2, [r3, #12] 8004f8a: 687b ldr r3, [r7, #4] 8004f8c: 6b9b ldr r3, [r3, #56] ; 0x38 8004f8e: b292 uxth r2, r2 8004f90: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8004f92: 687b ldr r3, [r7, #4] 8004f94: 6b9b ldr r3, [r3, #56] ; 0x38 8004f96: 1c9a adds r2, r3, #2 8004f98: 687b ldr r3, [r7, #4] 8004f9a: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8004f9c: 687b ldr r3, [r7, #4] 8004f9e: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004fa0: b29b uxth r3, r3 8004fa2: 3b01 subs r3, #1 8004fa4: b29a uxth r2, r3 8004fa6: 687b ldr r3, [r7, #4] 8004fa8: 87da strh r2, [r3, #62] ; 0x3e if (hspi->RxXferCount == 0U) 8004faa: 687b ldr r3, [r7, #4] 8004fac: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004fae: b29b uxth r3, r3 8004fb0: 2b00 cmp r3, #0 8004fb2: d10f bne.n 8004fd4 <SPI_2linesRxISR_16BIT+0x58> return; } #endif /* USE_SPI_CRC */ /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); 8004fb4: 687b ldr r3, [r7, #4] 8004fb6: 681b ldr r3, [r3, #0] 8004fb8: 685a ldr r2, [r3, #4] 8004fba: 687b ldr r3, [r7, #4] 8004fbc: 681b ldr r3, [r3, #0] 8004fbe: f022 0240 bic.w r2, r2, #64 ; 0x40 8004fc2: 605a str r2, [r3, #4] if (hspi->TxXferCount == 0U) 8004fc4: 687b ldr r3, [r7, #4] 8004fc6: 8edb ldrh r3, [r3, #54] ; 0x36 8004fc8: b29b uxth r3, r3 8004fca: 2b00 cmp r3, #0 8004fcc: d102 bne.n 8004fd4 <SPI_2linesRxISR_16BIT+0x58> { SPI_CloseRxTx_ISR(hspi); 8004fce: 6878 ldr r0, [r7, #4] 8004fd0: f000 f92c bl 800522c <SPI_CloseRxTx_ISR> } } } 8004fd4: bf00 nop 8004fd6: 3708 adds r7, #8 8004fd8: 46bd mov sp, r7 8004fda: bd80 pop {r7, pc} 08004fdc <SPI_2linesTxISR_16BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { 8004fdc: b580 push {r7, lr} 8004fde: b082 sub sp, #8 8004fe0: af00 add r7, sp, #0 8004fe2: 6078 str r0, [r7, #4] /* Transmit data in 16 Bit mode */ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 6b1b ldr r3, [r3, #48] ; 0x30 8004fe8: 881a ldrh r2, [r3, #0] 8004fea: 687b ldr r3, [r7, #4] 8004fec: 681b ldr r3, [r3, #0] 8004fee: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8004ff0: 687b ldr r3, [r7, #4] 8004ff2: 6b1b ldr r3, [r3, #48] ; 0x30 8004ff4: 1c9a adds r2, r3, #2 8004ff6: 687b ldr r3, [r7, #4] 8004ff8: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004ffa: 687b ldr r3, [r7, #4] 8004ffc: 8edb ldrh r3, [r3, #54] ; 0x36 8004ffe: b29b uxth r3, r3 8005000: 3b01 subs r3, #1 8005002: b29a uxth r2, r3 8005004: 687b ldr r3, [r7, #4] 8005006: 86da strh r2, [r3, #54] ; 0x36 /* Enable CRC Transmission */ if (hspi->TxXferCount == 0U) 8005008: 687b ldr r3, [r7, #4] 800500a: 8edb ldrh r3, [r3, #54] ; 0x36 800500c: b29b uxth r3, r3 800500e: 2b00 cmp r3, #0 8005010: d10f bne.n 8005032 <SPI_2linesTxISR_16BIT+0x56> return; } #endif /* USE_SPI_CRC */ /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); 8005012: 687b ldr r3, [r7, #4] 8005014: 681b ldr r3, [r3, #0] 8005016: 685a ldr r2, [r3, #4] 8005018: 687b ldr r3, [r7, #4] 800501a: 681b ldr r3, [r3, #0] 800501c: f022 0280 bic.w r2, r2, #128 ; 0x80 8005020: 605a str r2, [r3, #4] if (hspi->RxXferCount == 0U) 8005022: 687b ldr r3, [r7, #4] 8005024: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005026: b29b uxth r3, r3 8005028: 2b00 cmp r3, #0 800502a: d102 bne.n 8005032 <SPI_2linesTxISR_16BIT+0x56> { SPI_CloseRxTx_ISR(hspi); 800502c: 6878 ldr r0, [r7, #4] 800502e: f000 f8fd bl 800522c <SPI_CloseRxTx_ISR> } } } 8005032: bf00 nop 8005034: 3708 adds r7, #8 8005036: 46bd mov sp, r7 8005038: bd80 pop {r7, pc} ... 0800503c <SPI_WaitFlagStateUntilTimeout>: * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 800503c: b580 push {r7, lr} 800503e: b088 sub sp, #32 8005040: af00 add r7, sp, #0 8005042: 60f8 str r0, [r7, #12] 8005044: 60b9 str r1, [r7, #8] 8005046: 603b str r3, [r7, #0] 8005048: 4613 mov r3, r2 800504a: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 800504c: f7fd fae8 bl 8002620 <HAL_GetTick> 8005050: 4602 mov r2, r0 8005052: 6abb ldr r3, [r7, #40] ; 0x28 8005054: 1a9b subs r3, r3, r2 8005056: 683a ldr r2, [r7, #0] 8005058: 4413 add r3, r2 800505a: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 800505c: f7fd fae0 bl 8002620 <HAL_GetTick> 8005060: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 8005062: 4b39 ldr r3, [pc, #228] ; (8005148 <SPI_WaitFlagStateUntilTimeout+0x10c>) 8005064: 681b ldr r3, [r3, #0] 8005066: 015b lsls r3, r3, #5 8005068: 0d1b lsrs r3, r3, #20 800506a: 69fa ldr r2, [r7, #28] 800506c: fb02 f303 mul.w r3, r2, r3 8005070: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 8005072: e054 b.n 800511e <SPI_WaitFlagStateUntilTimeout+0xe2> { if (Timeout != HAL_MAX_DELAY) 8005074: 683b ldr r3, [r7, #0] 8005076: f1b3 3fff cmp.w r3, #4294967295 800507a: d050 beq.n 800511e <SPI_WaitFlagStateUntilTimeout+0xe2> { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800507c: f7fd fad0 bl 8002620 <HAL_GetTick> 8005080: 4602 mov r2, r0 8005082: 69bb ldr r3, [r7, #24] 8005084: 1ad3 subs r3, r2, r3 8005086: 69fa ldr r2, [r7, #28] 8005088: 429a cmp r2, r3 800508a: d902 bls.n 8005092 <SPI_WaitFlagStateUntilTimeout+0x56> 800508c: 69fb ldr r3, [r7, #28] 800508e: 2b00 cmp r3, #0 8005090: d13d bne.n 800510e <SPI_WaitFlagStateUntilTimeout+0xd2> /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8005092: 68fb ldr r3, [r7, #12] 8005094: 681b ldr r3, [r3, #0] 8005096: 685a ldr r2, [r3, #4] 8005098: 68fb ldr r3, [r7, #12] 800509a: 681b ldr r3, [r3, #0] 800509c: f022 02e0 bic.w r2, r2, #224 ; 0xe0 80050a0: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 80050a2: 68fb ldr r3, [r7, #12] 80050a4: 685b ldr r3, [r3, #4] 80050a6: f5b3 7f82 cmp.w r3, #260 ; 0x104 80050aa: d111 bne.n 80050d0 <SPI_WaitFlagStateUntilTimeout+0x94> 80050ac: 68fb ldr r3, [r7, #12] 80050ae: 689b ldr r3, [r3, #8] 80050b0: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 80050b4: d004 beq.n 80050c0 <SPI_WaitFlagStateUntilTimeout+0x84> || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 80050b6: 68fb ldr r3, [r7, #12] 80050b8: 689b ldr r3, [r3, #8] 80050ba: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80050be: d107 bne.n 80050d0 <SPI_WaitFlagStateUntilTimeout+0x94> { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80050c0: 68fb ldr r3, [r7, #12] 80050c2: 681b ldr r3, [r3, #0] 80050c4: 681a ldr r2, [r3, #0] 80050c6: 68fb ldr r3, [r7, #12] 80050c8: 681b ldr r3, [r3, #0] 80050ca: f022 0240 bic.w r2, r2, #64 ; 0x40 80050ce: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 80050d0: 68fb ldr r3, [r7, #12] 80050d2: 6a9b ldr r3, [r3, #40] ; 0x28 80050d4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80050d8: d10f bne.n 80050fa <SPI_WaitFlagStateUntilTimeout+0xbe> { SPI_RESET_CRC(hspi); 80050da: 68fb ldr r3, [r7, #12] 80050dc: 681b ldr r3, [r3, #0] 80050de: 681a ldr r2, [r3, #0] 80050e0: 68fb ldr r3, [r7, #12] 80050e2: 681b ldr r3, [r3, #0] 80050e4: f422 5200 bic.w r2, r2, #8192 ; 0x2000 80050e8: 601a str r2, [r3, #0] 80050ea: 68fb ldr r3, [r7, #12] 80050ec: 681b ldr r3, [r3, #0] 80050ee: 681a ldr r2, [r3, #0] 80050f0: 68fb ldr r3, [r7, #12] 80050f2: 681b ldr r3, [r3, #0] 80050f4: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80050f8: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 80050fa: 68fb ldr r3, [r7, #12] 80050fc: 2201 movs r2, #1 80050fe: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); 8005102: 68fb ldr r3, [r7, #12] 8005104: 2200 movs r2, #0 8005106: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 800510a: 2303 movs r3, #3 800510c: e017 b.n 800513e <SPI_WaitFlagStateUntilTimeout+0x102> } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if(count == 0U) 800510e: 697b ldr r3, [r7, #20] 8005110: 2b00 cmp r3, #0 8005112: d101 bne.n 8005118 <SPI_WaitFlagStateUntilTimeout+0xdc> { tmp_timeout = 0U; 8005114: 2300 movs r3, #0 8005116: 61fb str r3, [r7, #28] } count--; 8005118: 697b ldr r3, [r7, #20] 800511a: 3b01 subs r3, #1 800511c: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800511e: 68fb ldr r3, [r7, #12] 8005120: 681b ldr r3, [r3, #0] 8005122: 689a ldr r2, [r3, #8] 8005124: 68bb ldr r3, [r7, #8] 8005126: 4013 ands r3, r2 8005128: 68ba ldr r2, [r7, #8] 800512a: 429a cmp r2, r3 800512c: bf0c ite eq 800512e: 2301 moveq r3, #1 8005130: 2300 movne r3, #0 8005132: b2db uxtb r3, r3 8005134: 461a mov r2, r3 8005136: 79fb ldrb r3, [r7, #7] 8005138: 429a cmp r2, r3 800513a: d19b bne.n 8005074 <SPI_WaitFlagStateUntilTimeout+0x38> } } return HAL_OK; 800513c: 2300 movs r3, #0 } 800513e: 4618 mov r0, r3 8005140: 3720 adds r7, #32 8005142: 46bd mov sp, r7 8005144: bd80 pop {r7, pc} 8005146: bf00 nop 8005148: 20000058 .word 0x20000058 0800514c <SPI_EndRxTransaction>: * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 800514c: b580 push {r7, lr} 800514e: b086 sub sp, #24 8005150: af02 add r7, sp, #8 8005152: 60f8 str r0, [r7, #12] 8005154: 60b9 str r1, [r7, #8] 8005156: 607a str r2, [r7, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8005158: 68fb ldr r3, [r7, #12] 800515a: 685b ldr r3, [r3, #4] 800515c: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005160: d111 bne.n 8005186 <SPI_EndRxTransaction+0x3a> 8005162: 68fb ldr r3, [r7, #12] 8005164: 689b ldr r3, [r3, #8] 8005166: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800516a: d004 beq.n 8005176 <SPI_EndRxTransaction+0x2a> || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800516c: 68fb ldr r3, [r7, #12] 800516e: 689b ldr r3, [r3, #8] 8005170: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8005174: d107 bne.n 8005186 <SPI_EndRxTransaction+0x3a> { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8005176: 68fb ldr r3, [r7, #12] 8005178: 681b ldr r3, [r3, #0] 800517a: 681a ldr r2, [r3, #0] 800517c: 68fb ldr r3, [r7, #12] 800517e: 681b ldr r3, [r3, #0] 8005180: f022 0240 bic.w r2, r2, #64 ; 0x40 8005184: 601a str r2, [r3, #0] } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)) 8005186: 68fb ldr r3, [r7, #12] 8005188: 685b ldr r3, [r3, #4] 800518a: f5b3 7f82 cmp.w r3, #260 ; 0x104 800518e: d117 bne.n 80051c0 <SPI_EndRxTransaction+0x74> 8005190: 68fb ldr r3, [r7, #12] 8005192: 689b ldr r3, [r3, #8] 8005194: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8005198: d112 bne.n 80051c0 <SPI_EndRxTransaction+0x74> { /* Wait the RXNE reset */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) 800519a: 687b ldr r3, [r7, #4] 800519c: 9300 str r3, [sp, #0] 800519e: 68bb ldr r3, [r7, #8] 80051a0: 2200 movs r2, #0 80051a2: 2101 movs r1, #1 80051a4: 68f8 ldr r0, [r7, #12] 80051a6: f7ff ff49 bl 800503c <SPI_WaitFlagStateUntilTimeout> 80051aa: 4603 mov r3, r0 80051ac: 2b00 cmp r3, #0 80051ae: d01a beq.n 80051e6 <SPI_EndRxTransaction+0x9a> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 80051b0: 68fb ldr r3, [r7, #12] 80051b2: 6d5b ldr r3, [r3, #84] ; 0x54 80051b4: f043 0220 orr.w r2, r3, #32 80051b8: 68fb ldr r3, [r7, #12] 80051ba: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 80051bc: 2303 movs r3, #3 80051be: e013 b.n 80051e8 <SPI_EndRxTransaction+0x9c> } } else { /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 80051c0: 687b ldr r3, [r7, #4] 80051c2: 9300 str r3, [sp, #0] 80051c4: 68bb ldr r3, [r7, #8] 80051c6: 2200 movs r2, #0 80051c8: 2180 movs r1, #128 ; 0x80 80051ca: 68f8 ldr r0, [r7, #12] 80051cc: f7ff ff36 bl 800503c <SPI_WaitFlagStateUntilTimeout> 80051d0: 4603 mov r3, r0 80051d2: 2b00 cmp r3, #0 80051d4: d007 beq.n 80051e6 <SPI_EndRxTransaction+0x9a> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 80051d6: 68fb ldr r3, [r7, #12] 80051d8: 6d5b ldr r3, [r3, #84] ; 0x54 80051da: f043 0220 orr.w r2, r3, #32 80051de: 68fb ldr r3, [r7, #12] 80051e0: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 80051e2: 2303 movs r3, #3 80051e4: e000 b.n 80051e8 <SPI_EndRxTransaction+0x9c> } } return HAL_OK; 80051e6: 2300 movs r3, #0 } 80051e8: 4618 mov r0, r3 80051ea: 3710 adds r7, #16 80051ec: 46bd mov sp, r7 80051ee: bd80 pop {r7, pc} 080051f0 <SPI_EndRxTxTransaction>: * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 80051f0: b580 push {r7, lr} 80051f2: b086 sub sp, #24 80051f4: af02 add r7, sp, #8 80051f6: 60f8 str r0, [r7, #12] 80051f8: 60b9 str r1, [r7, #8] 80051fa: 607a str r2, [r7, #4] /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 80051fc: 687b ldr r3, [r7, #4] 80051fe: 9300 str r3, [sp, #0] 8005200: 68bb ldr r3, [r7, #8] 8005202: 2200 movs r2, #0 8005204: 2180 movs r1, #128 ; 0x80 8005206: 68f8 ldr r0, [r7, #12] 8005208: f7ff ff18 bl 800503c <SPI_WaitFlagStateUntilTimeout> 800520c: 4603 mov r3, r0 800520e: 2b00 cmp r3, #0 8005210: d007 beq.n 8005222 <SPI_EndRxTxTransaction+0x32> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005212: 68fb ldr r3, [r7, #12] 8005214: 6d5b ldr r3, [r3, #84] ; 0x54 8005216: f043 0220 orr.w r2, r3, #32 800521a: 68fb ldr r3, [r7, #12] 800521c: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 800521e: 2303 movs r3, #3 8005220: e000 b.n 8005224 <SPI_EndRxTxTransaction+0x34> } return HAL_OK; 8005222: 2300 movs r3, #0 } 8005224: 4618 mov r0, r3 8005226: 3710 adds r7, #16 8005228: 46bd mov sp, r7 800522a: bd80 pop {r7, pc} 0800522c <SPI_CloseRxTx_ISR>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { 800522c: b580 push {r7, lr} 800522e: b086 sub sp, #24 8005230: af00 add r7, sp, #0 8005232: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); 8005234: 4b35 ldr r3, [pc, #212] ; (800530c <SPI_CloseRxTx_ISR+0xe0>) 8005236: 681b ldr r3, [r3, #0] 8005238: 4a35 ldr r2, [pc, #212] ; (8005310 <SPI_CloseRxTx_ISR+0xe4>) 800523a: fba2 2303 umull r2, r3, r2, r3 800523e: 0a5b lsrs r3, r3, #9 8005240: 2264 movs r2, #100 ; 0x64 8005242: fb02 f303 mul.w r3, r2, r3 8005246: 613b str r3, [r7, #16] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005248: f7fd f9ea bl 8002620 <HAL_GetTick> 800524c: 6178 str r0, [r7, #20] /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800524e: 687b ldr r3, [r7, #4] 8005250: 681b ldr r3, [r3, #0] 8005252: 685a ldr r2, [r3, #4] 8005254: 687b ldr r3, [r7, #4] 8005256: 681b ldr r3, [r3, #0] 8005258: f022 0220 bic.w r2, r2, #32 800525c: 605a str r2, [r3, #4] /* Wait until TXE flag is set */ do { if (count == 0U) 800525e: 693b ldr r3, [r7, #16] 8005260: 2b00 cmp r3, #0 8005262: d106 bne.n 8005272 <SPI_CloseRxTx_ISR+0x46> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005264: 687b ldr r3, [r7, #4] 8005266: 6d5b ldr r3, [r3, #84] ; 0x54 8005268: f043 0220 orr.w r2, r3, #32 800526c: 687b ldr r3, [r7, #4] 800526e: 655a str r2, [r3, #84] ; 0x54 break; 8005270: e009 b.n 8005286 <SPI_CloseRxTx_ISR+0x5a> } count--; 8005272: 693b ldr r3, [r7, #16] 8005274: 3b01 subs r3, #1 8005276: 613b str r3, [r7, #16] } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); 8005278: 687b ldr r3, [r7, #4] 800527a: 681b ldr r3, [r3, #0] 800527c: 689b ldr r3, [r3, #8] 800527e: f003 0302 and.w r3, r3, #2 8005282: 2b00 cmp r3, #0 8005284: d0eb beq.n 800525e <SPI_CloseRxTx_ISR+0x32> /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 8005286: 697a ldr r2, [r7, #20] 8005288: 2164 movs r1, #100 ; 0x64 800528a: 6878 ldr r0, [r7, #4] 800528c: f7ff ffb0 bl 80051f0 <SPI_EndRxTxTransaction> 8005290: 4603 mov r3, r0 8005292: 2b00 cmp r3, #0 8005294: d005 beq.n 80052a2 <SPI_CloseRxTx_ISR+0x76> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005296: 687b ldr r3, [r7, #4] 8005298: 6d5b ldr r3, [r3, #84] ; 0x54 800529a: f043 0220 orr.w r2, r3, #32 800529e: 687b ldr r3, [r7, #4] 80052a0: 655a str r2, [r3, #84] ; 0x54 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 80052a2: 687b ldr r3, [r7, #4] 80052a4: 689b ldr r3, [r3, #8] 80052a6: 2b00 cmp r3, #0 80052a8: d10a bne.n 80052c0 <SPI_CloseRxTx_ISR+0x94> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 80052aa: 2300 movs r3, #0 80052ac: 60fb str r3, [r7, #12] 80052ae: 687b ldr r3, [r7, #4] 80052b0: 681b ldr r3, [r3, #0] 80052b2: 68db ldr r3, [r3, #12] 80052b4: 60fb str r3, [r7, #12] 80052b6: 687b ldr r3, [r7, #4] 80052b8: 681b ldr r3, [r3, #0] 80052ba: 689b ldr r3, [r3, #8] 80052bc: 60fb str r3, [r7, #12] 80052be: 68fb ldr r3, [r7, #12] } } else { #endif /* USE_SPI_CRC */ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) 80052c0: 687b ldr r3, [r7, #4] 80052c2: 6d5b ldr r3, [r3, #84] ; 0x54 80052c4: 2b00 cmp r3, #0 80052c6: d115 bne.n 80052f4 <SPI_CloseRxTx_ISR+0xc8> { if (hspi->State == HAL_SPI_STATE_BUSY_RX) 80052c8: 687b ldr r3, [r7, #4] 80052ca: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80052ce: b2db uxtb r3, r3 80052d0: 2b04 cmp r3, #4 80052d2: d107 bne.n 80052e4 <SPI_CloseRxTx_ISR+0xb8> { hspi->State = HAL_SPI_STATE_READY; 80052d4: 687b ldr r3, [r7, #4] 80052d6: 2201 movs r2, #1 80052d8: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Call user Rx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxCpltCallback(hspi); #else HAL_SPI_RxCpltCallback(hspi); 80052dc: 6878 ldr r0, [r7, #4] 80052de: f7ff fdc5 bl 8004e6c <HAL_SPI_RxCpltCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } #endif /* USE_SPI_CRC */ } 80052e2: e00e b.n 8005302 <SPI_CloseRxTx_ISR+0xd6> hspi->State = HAL_SPI_STATE_READY; 80052e4: 687b ldr r3, [r7, #4] 80052e6: 2201 movs r2, #1 80052e8: f883 2051 strb.w r2, [r3, #81] ; 0x51 HAL_SPI_TxRxCpltCallback(hspi); 80052ec: 6878 ldr r0, [r7, #4] 80052ee: f7fb fddd bl 8000eac <HAL_SPI_TxRxCpltCallback> } 80052f2: e006 b.n 8005302 <SPI_CloseRxTx_ISR+0xd6> hspi->State = HAL_SPI_STATE_READY; 80052f4: 687b ldr r3, [r7, #4] 80052f6: 2201 movs r2, #1 80052f8: f883 2051 strb.w r2, [r3, #81] ; 0x51 HAL_SPI_ErrorCallback(hspi); 80052fc: 6878 ldr r0, [r7, #4] 80052fe: f7ff fdbe bl 8004e7e <HAL_SPI_ErrorCallback> } 8005302: bf00 nop 8005304: 3718 adds r7, #24 8005306: 46bd mov sp, r7 8005308: bd80 pop {r7, pc} 800530a: bf00 nop 800530c: 20000058 .word 0x20000058 8005310: 057619f1 .word 0x057619f1 08005314 <HAL_TIM_Base_Init>: * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8005314: b580 push {r7, lr} 8005316: b082 sub sp, #8 8005318: af00 add r7, sp, #0 800531a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800531c: 687b ldr r3, [r7, #4] 800531e: 2b00 cmp r3, #0 8005320: d101 bne.n 8005326 <HAL_TIM_Base_Init+0x12> { return HAL_ERROR; 8005322: 2301 movs r3, #1 8005324: e041 b.n 80053aa <HAL_TIM_Base_Init+0x96> assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005326: 687b ldr r3, [r7, #4] 8005328: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800532c: b2db uxtb r3, r3 800532e: 2b00 cmp r3, #0 8005330: d106 bne.n 8005340 <HAL_TIM_Base_Init+0x2c> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005332: 687b ldr r3, [r7, #4] 8005334: 2200 movs r2, #0 8005336: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800533a: 6878 ldr r0, [r7, #4] 800533c: f7fc ffa2 bl 8002284 <HAL_TIM_Base_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005340: 687b ldr r3, [r7, #4] 8005342: 2202 movs r2, #2 8005344: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005348: 687b ldr r3, [r7, #4] 800534a: 681a ldr r2, [r3, #0] 800534c: 687b ldr r3, [r7, #4] 800534e: 3304 adds r3, #4 8005350: 4619 mov r1, r3 8005352: 4610 mov r0, r2 8005354: f000 fb02 bl 800595c <TIM_Base_SetConfig> /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005358: 687b ldr r3, [r7, #4] 800535a: 2201 movs r2, #1 800535c: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005360: 687b ldr r3, [r7, #4] 8005362: 2201 movs r2, #1 8005364: f883 203e strb.w r2, [r3, #62] ; 0x3e 8005368: 687b ldr r3, [r7, #4] 800536a: 2201 movs r2, #1 800536c: f883 203f strb.w r2, [r3, #63] ; 0x3f 8005370: 687b ldr r3, [r7, #4] 8005372: 2201 movs r2, #1 8005374: f883 2040 strb.w r2, [r3, #64] ; 0x40 8005378: 687b ldr r3, [r7, #4] 800537a: 2201 movs r2, #1 800537c: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005380: 687b ldr r3, [r7, #4] 8005382: 2201 movs r2, #1 8005384: f883 2042 strb.w r2, [r3, #66] ; 0x42 8005388: 687b ldr r3, [r7, #4] 800538a: 2201 movs r2, #1 800538c: f883 2043 strb.w r2, [r3, #67] ; 0x43 8005390: 687b ldr r3, [r7, #4] 8005392: 2201 movs r2, #1 8005394: f883 2044 strb.w r2, [r3, #68] ; 0x44 8005398: 687b ldr r3, [r7, #4] 800539a: 2201 movs r2, #1 800539c: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80053a0: 687b ldr r3, [r7, #4] 80053a2: 2201 movs r2, #1 80053a4: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 80053a8: 2300 movs r3, #0 } 80053aa: 4618 mov r0, r3 80053ac: 3708 adds r7, #8 80053ae: 46bd mov sp, r7 80053b0: bd80 pop {r7, pc} ... 080053b4 <HAL_TIM_Base_Start>: * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 80053b4: b480 push {r7} 80053b6: b085 sub sp, #20 80053b8: af00 add r7, sp, #0 80053ba: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 80053bc: 687b ldr r3, [r7, #4] 80053be: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80053c2: b2db uxtb r3, r3 80053c4: 2b01 cmp r3, #1 80053c6: d001 beq.n 80053cc <HAL_TIM_Base_Start+0x18> { return HAL_ERROR; 80053c8: 2301 movs r3, #1 80053ca: e032 b.n 8005432 <HAL_TIM_Base_Start+0x7e> } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80053cc: 687b ldr r3, [r7, #4] 80053ce: 2202 movs r2, #2 80053d0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80053d4: 687b ldr r3, [r7, #4] 80053d6: 681b ldr r3, [r3, #0] 80053d8: 4a18 ldr r2, [pc, #96] ; (800543c <HAL_TIM_Base_Start+0x88>) 80053da: 4293 cmp r3, r2 80053dc: d00e beq.n 80053fc <HAL_TIM_Base_Start+0x48> 80053de: 687b ldr r3, [r7, #4] 80053e0: 681b ldr r3, [r3, #0] 80053e2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80053e6: d009 beq.n 80053fc <HAL_TIM_Base_Start+0x48> 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4a14 ldr r2, [pc, #80] ; (8005440 <HAL_TIM_Base_Start+0x8c>) 80053ee: 4293 cmp r3, r2 80053f0: d004 beq.n 80053fc <HAL_TIM_Base_Start+0x48> 80053f2: 687b ldr r3, [r7, #4] 80053f4: 681b ldr r3, [r3, #0] 80053f6: 4a13 ldr r2, [pc, #76] ; (8005444 <HAL_TIM_Base_Start+0x90>) 80053f8: 4293 cmp r3, r2 80053fa: d111 bne.n 8005420 <HAL_TIM_Base_Start+0x6c> { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80053fc: 687b ldr r3, [r7, #4] 80053fe: 681b ldr r3, [r3, #0] 8005400: 689b ldr r3, [r3, #8] 8005402: f003 0307 and.w r3, r3, #7 8005406: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005408: 68fb ldr r3, [r7, #12] 800540a: 2b06 cmp r3, #6 800540c: d010 beq.n 8005430 <HAL_TIM_Base_Start+0x7c> { __HAL_TIM_ENABLE(htim); 800540e: 687b ldr r3, [r7, #4] 8005410: 681b ldr r3, [r3, #0] 8005412: 681a ldr r2, [r3, #0] 8005414: 687b ldr r3, [r7, #4] 8005416: 681b ldr r3, [r3, #0] 8005418: f042 0201 orr.w r2, r2, #1 800541c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800541e: e007 b.n 8005430 <HAL_TIM_Base_Start+0x7c> } } else { __HAL_TIM_ENABLE(htim); 8005420: 687b ldr r3, [r7, #4] 8005422: 681b ldr r3, [r3, #0] 8005424: 681a ldr r2, [r3, #0] 8005426: 687b ldr r3, [r7, #4] 8005428: 681b ldr r3, [r3, #0] 800542a: f042 0201 orr.w r2, r2, #1 800542e: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8005430: 2300 movs r3, #0 } 8005432: 4618 mov r0, r3 8005434: 3714 adds r7, #20 8005436: 46bd mov sp, r7 8005438: bc80 pop {r7} 800543a: 4770 bx lr 800543c: 40012c00 .word 0x40012c00 8005440: 40000400 .word 0x40000400 8005444: 40000800 .word 0x40000800 08005448 <HAL_TIM_PWM_Init>: * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8005448: b580 push {r7, lr} 800544a: b082 sub sp, #8 800544c: af00 add r7, sp, #0 800544e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005450: 687b ldr r3, [r7, #4] 8005452: 2b00 cmp r3, #0 8005454: d101 bne.n 800545a <HAL_TIM_PWM_Init+0x12> { return HAL_ERROR; 8005456: 2301 movs r3, #1 8005458: e041 b.n 80054de <HAL_TIM_PWM_Init+0x96> assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800545a: 687b ldr r3, [r7, #4] 800545c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005460: b2db uxtb r3, r3 8005462: 2b00 cmp r3, #0 8005464: d106 bne.n 8005474 <HAL_TIM_PWM_Init+0x2c> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005466: 687b ldr r3, [r7, #4] 8005468: 2200 movs r2, #0 800546a: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800546e: 6878 ldr r0, [r7, #4] 8005470: f000 f839 bl 80054e6 <HAL_TIM_PWM_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005474: 687b ldr r3, [r7, #4] 8005476: 2202 movs r2, #2 8005478: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800547c: 687b ldr r3, [r7, #4] 800547e: 681a ldr r2, [r3, #0] 8005480: 687b ldr r3, [r7, #4] 8005482: 3304 adds r3, #4 8005484: 4619 mov r1, r3 8005486: 4610 mov r0, r2 8005488: f000 fa68 bl 800595c <TIM_Base_SetConfig> /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800548c: 687b ldr r3, [r7, #4] 800548e: 2201 movs r2, #1 8005490: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005494: 687b ldr r3, [r7, #4] 8005496: 2201 movs r2, #1 8005498: f883 203e strb.w r2, [r3, #62] ; 0x3e 800549c: 687b ldr r3, [r7, #4] 800549e: 2201 movs r2, #1 80054a0: f883 203f strb.w r2, [r3, #63] ; 0x3f 80054a4: 687b ldr r3, [r7, #4] 80054a6: 2201 movs r2, #1 80054a8: f883 2040 strb.w r2, [r3, #64] ; 0x40 80054ac: 687b ldr r3, [r7, #4] 80054ae: 2201 movs r2, #1 80054b0: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80054b4: 687b ldr r3, [r7, #4] 80054b6: 2201 movs r2, #1 80054b8: f883 2042 strb.w r2, [r3, #66] ; 0x42 80054bc: 687b ldr r3, [r7, #4] 80054be: 2201 movs r2, #1 80054c0: f883 2043 strb.w r2, [r3, #67] ; 0x43 80054c4: 687b ldr r3, [r7, #4] 80054c6: 2201 movs r2, #1 80054c8: f883 2044 strb.w r2, [r3, #68] ; 0x44 80054cc: 687b ldr r3, [r7, #4] 80054ce: 2201 movs r2, #1 80054d0: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80054d4: 687b ldr r3, [r7, #4] 80054d6: 2201 movs r2, #1 80054d8: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 80054dc: 2300 movs r3, #0 } 80054de: 4618 mov r0, r3 80054e0: 3708 adds r7, #8 80054e2: 46bd mov sp, r7 80054e4: bd80 pop {r7, pc} 080054e6 <HAL_TIM_PWM_MspInit>: * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80054e6: b480 push {r7} 80054e8: b083 sub sp, #12 80054ea: af00 add r7, sp, #0 80054ec: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80054ee: bf00 nop 80054f0: 370c adds r7, #12 80054f2: 46bd mov sp, r7 80054f4: bc80 pop {r7} 80054f6: 4770 bx lr 080054f8 <HAL_TIM_OnePulse_Init>: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { 80054f8: b580 push {r7, lr} 80054fa: b082 sub sp, #8 80054fc: af00 add r7, sp, #0 80054fe: 6078 str r0, [r7, #4] 8005500: 6039 str r1, [r7, #0] /* Check the TIM handle allocation */ if (htim == NULL) 8005502: 687b ldr r3, [r7, #4] 8005504: 2b00 cmp r3, #0 8005506: d101 bne.n 800550c <HAL_TIM_OnePulse_Init+0x14> { return HAL_ERROR; 8005508: 2301 movs r3, #1 800550a: e041 b.n 8005590 <HAL_TIM_OnePulse_Init+0x98> assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800550c: 687b ldr r3, [r7, #4] 800550e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005512: b2db uxtb r3, r3 8005514: 2b00 cmp r3, #0 8005516: d106 bne.n 8005526 <HAL_TIM_OnePulse_Init+0x2e> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005518: 687b ldr r3, [r7, #4] 800551a: 2200 movs r2, #0 800551c: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); 8005520: 6878 ldr r0, [r7, #4] 8005522: f000 f839 bl 8005598 <HAL_TIM_OnePulse_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005526: 687b ldr r3, [r7, #4] 8005528: 2202 movs r2, #2 800552a: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800552e: 687b ldr r3, [r7, #4] 8005530: 681a ldr r2, [r3, #0] 8005532: 687b ldr r3, [r7, #4] 8005534: 3304 adds r3, #4 8005536: 4619 mov r1, r3 8005538: 4610 mov r0, r2 800553a: f000 fa0f bl 800595c <TIM_Base_SetConfig> /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; 800553e: 687b ldr r3, [r7, #4] 8005540: 681b ldr r3, [r3, #0] 8005542: 681a ldr r2, [r3, #0] 8005544: 687b ldr r3, [r7, #4] 8005546: 681b ldr r3, [r3, #0] 8005548: f022 0208 bic.w r2, r2, #8 800554c: 601a str r2, [r3, #0] /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; 800554e: 687b ldr r3, [r7, #4] 8005550: 681b ldr r3, [r3, #0] 8005552: 6819 ldr r1, [r3, #0] 8005554: 687b ldr r3, [r7, #4] 8005556: 681b ldr r3, [r3, #0] 8005558: 683a ldr r2, [r7, #0] 800555a: 430a orrs r2, r1 800555c: 601a str r2, [r3, #0] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800555e: 687b ldr r3, [r7, #4] 8005560: 2201 movs r2, #1 8005562: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005566: 687b ldr r3, [r7, #4] 8005568: 2201 movs r2, #1 800556a: f883 203e strb.w r2, [r3, #62] ; 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 800556e: 687b ldr r3, [r7, #4] 8005570: 2201 movs r2, #1 8005572: f883 203f strb.w r2, [r3, #63] ; 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005576: 687b ldr r3, [r7, #4] 8005578: 2201 movs r2, #1 800557a: f883 2042 strb.w r2, [r3, #66] ; 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 800557e: 687b ldr r3, [r7, #4] 8005580: 2201 movs r2, #1 8005582: f883 2043 strb.w r2, [r3, #67] ; 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005586: 687b ldr r3, [r7, #4] 8005588: 2201 movs r2, #1 800558a: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 800558e: 2300 movs r3, #0 } 8005590: 4618 mov r0, r3 8005592: 3708 adds r7, #8 8005594: 46bd mov sp, r7 8005596: bd80 pop {r7, pc} 08005598 <HAL_TIM_OnePulse_MspInit>: * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { 8005598: b480 push {r7} 800559a: b083 sub sp, #12 800559c: af00 add r7, sp, #0 800559e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } 80055a0: bf00 nop 80055a2: 370c adds r7, #12 80055a4: 46bd mov sp, r7 80055a6: bc80 pop {r7} 80055a8: 4770 bx lr ... 080055ac <HAL_TIM_OnePulse_Start>: * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { 80055ac: b580 push {r7, lr} 80055ae: b084 sub sp, #16 80055b0: af00 add r7, sp, #0 80055b2: 6078 str r0, [r7, #4] 80055b4: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 80055b6: 687b ldr r3, [r7, #4] 80055b8: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 80055bc: 73fb strb r3, [r7, #15] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 80055be: 687b ldr r3, [r7, #4] 80055c0: f893 303f ldrb.w r3, [r3, #63] ; 0x3f 80055c4: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 80055c6: 687b ldr r3, [r7, #4] 80055c8: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 80055cc: 737b strb r3, [r7, #13] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 80055ce: 687b ldr r3, [r7, #4] 80055d0: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 80055d4: 733b strb r3, [r7, #12] /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 80055d6: 7bfb ldrb r3, [r7, #15] 80055d8: 2b01 cmp r3, #1 80055da: d108 bne.n 80055ee <HAL_TIM_OnePulse_Start+0x42> || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 80055dc: 7bbb ldrb r3, [r7, #14] 80055de: 2b01 cmp r3, #1 80055e0: d105 bne.n 80055ee <HAL_TIM_OnePulse_Start+0x42> || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 80055e2: 7b7b ldrb r3, [r7, #13] 80055e4: 2b01 cmp r3, #1 80055e6: d102 bne.n 80055ee <HAL_TIM_OnePulse_Start+0x42> || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 80055e8: 7b3b ldrb r3, [r7, #12] 80055ea: 2b01 cmp r3, #1 80055ec: d001 beq.n 80055f2 <HAL_TIM_OnePulse_Start+0x46> { return HAL_ERROR; 80055ee: 2301 movs r3, #1 80055f0: e02b b.n 800564a <HAL_TIM_OnePulse_Start+0x9e> } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 80055f2: 687b ldr r3, [r7, #4] 80055f4: 2202 movs r2, #2 80055f6: f883 203e strb.w r2, [r3, #62] ; 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 80055fa: 687b ldr r3, [r7, #4] 80055fc: 2202 movs r2, #2 80055fe: f883 203f strb.w r2, [r3, #63] ; 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005602: 687b ldr r3, [r7, #4] 8005604: 2202 movs r2, #2 8005606: f883 2042 strb.w r2, [r3, #66] ; 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 800560a: 687b ldr r3, [r7, #4] 800560c: 2202 movs r2, #2 800560e: f883 2043 strb.w r2, [r3, #67] ; 0x43 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005612: 687b ldr r3, [r7, #4] 8005614: 681b ldr r3, [r3, #0] 8005616: 2201 movs r2, #1 8005618: 2100 movs r1, #0 800561a: 4618 mov r0, r3 800561c: f000 fc1e bl 8005e5c <TIM_CCxChannelCmd> TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005620: 687b ldr r3, [r7, #4] 8005622: 681b ldr r3, [r3, #0] 8005624: 2201 movs r2, #1 8005626: 2104 movs r1, #4 8005628: 4618 mov r0, r3 800562a: f000 fc17 bl 8005e5c <TIM_CCxChannelCmd> if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800562e: 687b ldr r3, [r7, #4] 8005630: 681b ldr r3, [r3, #0] 8005632: 4a08 ldr r2, [pc, #32] ; (8005654 <HAL_TIM_OnePulse_Start+0xa8>) 8005634: 4293 cmp r3, r2 8005636: d107 bne.n 8005648 <HAL_TIM_OnePulse_Start+0x9c> { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8005638: 687b ldr r3, [r7, #4] 800563a: 681b ldr r3, [r3, #0] 800563c: 6c5a ldr r2, [r3, #68] ; 0x44 800563e: 687b ldr r3, [r7, #4] 8005640: 681b ldr r3, [r3, #0] 8005642: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8005646: 645a str r2, [r3, #68] ; 0x44 } /* Return function status */ return HAL_OK; 8005648: 2300 movs r3, #0 } 800564a: 4618 mov r0, r3 800564c: 3710 adds r7, #16 800564e: 46bd mov sp, r7 8005650: bd80 pop {r7, pc} 8005652: bf00 nop 8005654: 40012c00 .word 0x40012c00 08005658 <HAL_TIM_PWM_ConfigChannel>: * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005658: b580 push {r7, lr} 800565a: b084 sub sp, #16 800565c: af00 add r7, sp, #0 800565e: 60f8 str r0, [r7, #12] 8005660: 60b9 str r1, [r7, #8] 8005662: 607a str r2, [r7, #4] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005664: 68fb ldr r3, [r7, #12] 8005666: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800566a: 2b01 cmp r3, #1 800566c: d101 bne.n 8005672 <HAL_TIM_PWM_ConfigChannel+0x1a> 800566e: 2302 movs r3, #2 8005670: e0ac b.n 80057cc <HAL_TIM_PWM_ConfigChannel+0x174> 8005672: 68fb ldr r3, [r7, #12] 8005674: 2201 movs r2, #1 8005676: f883 203c strb.w r2, [r3, #60] ; 0x3c switch (Channel) 800567a: 687b ldr r3, [r7, #4] 800567c: 2b0c cmp r3, #12 800567e: f200 809f bhi.w 80057c0 <HAL_TIM_PWM_ConfigChannel+0x168> 8005682: a201 add r2, pc, #4 ; (adr r2, 8005688 <HAL_TIM_PWM_ConfigChannel+0x30>) 8005684: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005688: 080056bd .word 0x080056bd 800568c: 080057c1 .word 0x080057c1 8005690: 080057c1 .word 0x080057c1 8005694: 080057c1 .word 0x080057c1 8005698: 080056fd .word 0x080056fd 800569c: 080057c1 .word 0x080057c1 80056a0: 080057c1 .word 0x080057c1 80056a4: 080057c1 .word 0x080057c1 80056a8: 0800573f .word 0x0800573f 80056ac: 080057c1 .word 0x080057c1 80056b0: 080057c1 .word 0x080057c1 80056b4: 080057c1 .word 0x080057c1 80056b8: 0800577f .word 0x0800577f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80056bc: 68fb ldr r3, [r7, #12] 80056be: 681b ldr r3, [r3, #0] 80056c0: 68b9 ldr r1, [r7, #8] 80056c2: 4618 mov r0, r3 80056c4: f000 f9ac bl 8005a20 <TIM_OC1_SetConfig> /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80056c8: 68fb ldr r3, [r7, #12] 80056ca: 681b ldr r3, [r3, #0] 80056cc: 699a ldr r2, [r3, #24] 80056ce: 68fb ldr r3, [r7, #12] 80056d0: 681b ldr r3, [r3, #0] 80056d2: f042 0208 orr.w r2, r2, #8 80056d6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80056d8: 68fb ldr r3, [r7, #12] 80056da: 681b ldr r3, [r3, #0] 80056dc: 699a ldr r2, [r3, #24] 80056de: 68fb ldr r3, [r7, #12] 80056e0: 681b ldr r3, [r3, #0] 80056e2: f022 0204 bic.w r2, r2, #4 80056e6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80056e8: 68fb ldr r3, [r7, #12] 80056ea: 681b ldr r3, [r3, #0] 80056ec: 6999 ldr r1, [r3, #24] 80056ee: 68bb ldr r3, [r7, #8] 80056f0: 691a ldr r2, [r3, #16] 80056f2: 68fb ldr r3, [r7, #12] 80056f4: 681b ldr r3, [r3, #0] 80056f6: 430a orrs r2, r1 80056f8: 619a str r2, [r3, #24] break; 80056fa: e062 b.n 80057c2 <HAL_TIM_PWM_ConfigChannel+0x16a> { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80056fc: 68fb ldr r3, [r7, #12] 80056fe: 681b ldr r3, [r3, #0] 8005700: 68b9 ldr r1, [r7, #8] 8005702: 4618 mov r0, r3 8005704: f000 f9f2 bl 8005aec <TIM_OC2_SetConfig> /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005708: 68fb ldr r3, [r7, #12] 800570a: 681b ldr r3, [r3, #0] 800570c: 699a ldr r2, [r3, #24] 800570e: 68fb ldr r3, [r7, #12] 8005710: 681b ldr r3, [r3, #0] 8005712: f442 6200 orr.w r2, r2, #2048 ; 0x800 8005716: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8005718: 68fb ldr r3, [r7, #12] 800571a: 681b ldr r3, [r3, #0] 800571c: 699a ldr r2, [r3, #24] 800571e: 68fb ldr r3, [r7, #12] 8005720: 681b ldr r3, [r3, #0] 8005722: f422 6280 bic.w r2, r2, #1024 ; 0x400 8005726: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005728: 68fb ldr r3, [r7, #12] 800572a: 681b ldr r3, [r3, #0] 800572c: 6999 ldr r1, [r3, #24] 800572e: 68bb ldr r3, [r7, #8] 8005730: 691b ldr r3, [r3, #16] 8005732: 021a lsls r2, r3, #8 8005734: 68fb ldr r3, [r7, #12] 8005736: 681b ldr r3, [r3, #0] 8005738: 430a orrs r2, r1 800573a: 619a str r2, [r3, #24] break; 800573c: e041 b.n 80057c2 <HAL_TIM_PWM_ConfigChannel+0x16a> { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800573e: 68fb ldr r3, [r7, #12] 8005740: 681b ldr r3, [r3, #0] 8005742: 68b9 ldr r1, [r7, #8] 8005744: 4618 mov r0, r3 8005746: f000 fa3b bl 8005bc0 <TIM_OC3_SetConfig> /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800574a: 68fb ldr r3, [r7, #12] 800574c: 681b ldr r3, [r3, #0] 800574e: 69da ldr r2, [r3, #28] 8005750: 68fb ldr r3, [r7, #12] 8005752: 681b ldr r3, [r3, #0] 8005754: f042 0208 orr.w r2, r2, #8 8005758: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800575a: 68fb ldr r3, [r7, #12] 800575c: 681b ldr r3, [r3, #0] 800575e: 69da ldr r2, [r3, #28] 8005760: 68fb ldr r3, [r7, #12] 8005762: 681b ldr r3, [r3, #0] 8005764: f022 0204 bic.w r2, r2, #4 8005768: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800576a: 68fb ldr r3, [r7, #12] 800576c: 681b ldr r3, [r3, #0] 800576e: 69d9 ldr r1, [r3, #28] 8005770: 68bb ldr r3, [r7, #8] 8005772: 691a ldr r2, [r3, #16] 8005774: 68fb ldr r3, [r7, #12] 8005776: 681b ldr r3, [r3, #0] 8005778: 430a orrs r2, r1 800577a: 61da str r2, [r3, #28] break; 800577c: e021 b.n 80057c2 <HAL_TIM_PWM_ConfigChannel+0x16a> { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800577e: 68fb ldr r3, [r7, #12] 8005780: 681b ldr r3, [r3, #0] 8005782: 68b9 ldr r1, [r7, #8] 8005784: 4618 mov r0, r3 8005786: f000 fa85 bl 8005c94 <TIM_OC4_SetConfig> /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800578a: 68fb ldr r3, [r7, #12] 800578c: 681b ldr r3, [r3, #0] 800578e: 69da ldr r2, [r3, #28] 8005790: 68fb ldr r3, [r7, #12] 8005792: 681b ldr r3, [r3, #0] 8005794: f442 6200 orr.w r2, r2, #2048 ; 0x800 8005798: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800579a: 68fb ldr r3, [r7, #12] 800579c: 681b ldr r3, [r3, #0] 800579e: 69da ldr r2, [r3, #28] 80057a0: 68fb ldr r3, [r7, #12] 80057a2: 681b ldr r3, [r3, #0] 80057a4: f422 6280 bic.w r2, r2, #1024 ; 0x400 80057a8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80057aa: 68fb ldr r3, [r7, #12] 80057ac: 681b ldr r3, [r3, #0] 80057ae: 69d9 ldr r1, [r3, #28] 80057b0: 68bb ldr r3, [r7, #8] 80057b2: 691b ldr r3, [r3, #16] 80057b4: 021a lsls r2, r3, #8 80057b6: 68fb ldr r3, [r7, #12] 80057b8: 681b ldr r3, [r3, #0] 80057ba: 430a orrs r2, r1 80057bc: 61da str r2, [r3, #28] break; 80057be: e000 b.n 80057c2 <HAL_TIM_PWM_ConfigChannel+0x16a> } default: break; 80057c0: bf00 nop } __HAL_UNLOCK(htim); 80057c2: 68fb ldr r3, [r7, #12] 80057c4: 2200 movs r2, #0 80057c6: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80057ca: 2300 movs r3, #0 } 80057cc: 4618 mov r0, r3 80057ce: 3710 adds r7, #16 80057d0: 46bd mov sp, r7 80057d2: bd80 pop {r7, pc} 080057d4 <HAL_TIM_ConfigClockSource>: * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { 80057d4: b580 push {r7, lr} 80057d6: b084 sub sp, #16 80057d8: af00 add r7, sp, #0 80057da: 6078 str r0, [r7, #4] 80057dc: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80057de: 687b ldr r3, [r7, #4] 80057e0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80057e4: 2b01 cmp r3, #1 80057e6: d101 bne.n 80057ec <HAL_TIM_ConfigClockSource+0x18> 80057e8: 2302 movs r3, #2 80057ea: e0b3 b.n 8005954 <HAL_TIM_ConfigClockSource+0x180> 80057ec: 687b ldr r3, [r7, #4] 80057ee: 2201 movs r2, #1 80057f0: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 80057f4: 687b ldr r3, [r7, #4] 80057f6: 2202 movs r2, #2 80057f8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80057fc: 687b ldr r3, [r7, #4] 80057fe: 681b ldr r3, [r3, #0] 8005800: 689b ldr r3, [r3, #8] 8005802: 60fb str r3, [r7, #12] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8005804: 68fb ldr r3, [r7, #12] 8005806: f023 0377 bic.w r3, r3, #119 ; 0x77 800580a: 60fb str r3, [r7, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800580c: 68fb ldr r3, [r7, #12] 800580e: f423 437f bic.w r3, r3, #65280 ; 0xff00 8005812: 60fb str r3, [r7, #12] htim->Instance->SMCR = tmpsmcr; 8005814: 687b ldr r3, [r7, #4] 8005816: 681b ldr r3, [r3, #0] 8005818: 68fa ldr r2, [r7, #12] 800581a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800581c: 683b ldr r3, [r7, #0] 800581e: 681b ldr r3, [r3, #0] 8005820: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8005824: d03e beq.n 80058a4 <HAL_TIM_ConfigClockSource+0xd0> 8005826: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800582a: f200 8087 bhi.w 800593c <HAL_TIM_ConfigClockSource+0x168> 800582e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8005832: f000 8085 beq.w 8005940 <HAL_TIM_ConfigClockSource+0x16c> 8005836: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800583a: d87f bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 800583c: 2b70 cmp r3, #112 ; 0x70 800583e: d01a beq.n 8005876 <HAL_TIM_ConfigClockSource+0xa2> 8005840: 2b70 cmp r3, #112 ; 0x70 8005842: d87b bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 8005844: 2b60 cmp r3, #96 ; 0x60 8005846: d050 beq.n 80058ea <HAL_TIM_ConfigClockSource+0x116> 8005848: 2b60 cmp r3, #96 ; 0x60 800584a: d877 bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 800584c: 2b50 cmp r3, #80 ; 0x50 800584e: d03c beq.n 80058ca <HAL_TIM_ConfigClockSource+0xf6> 8005850: 2b50 cmp r3, #80 ; 0x50 8005852: d873 bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 8005854: 2b40 cmp r3, #64 ; 0x40 8005856: d058 beq.n 800590a <HAL_TIM_ConfigClockSource+0x136> 8005858: 2b40 cmp r3, #64 ; 0x40 800585a: d86f bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 800585c: 2b30 cmp r3, #48 ; 0x30 800585e: d064 beq.n 800592a <HAL_TIM_ConfigClockSource+0x156> 8005860: 2b30 cmp r3, #48 ; 0x30 8005862: d86b bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 8005864: 2b20 cmp r3, #32 8005866: d060 beq.n 800592a <HAL_TIM_ConfigClockSource+0x156> 8005868: 2b20 cmp r3, #32 800586a: d867 bhi.n 800593c <HAL_TIM_ConfigClockSource+0x168> 800586c: 2b00 cmp r3, #0 800586e: d05c beq.n 800592a <HAL_TIM_ConfigClockSource+0x156> 8005870: 2b10 cmp r3, #16 8005872: d05a beq.n 800592a <HAL_TIM_ConfigClockSource+0x156> TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: break; 8005874: e062 b.n 800593c <HAL_TIM_ConfigClockSource+0x168> TIM_ETR_SetConfig(htim->Instance, 8005876: 687b ldr r3, [r7, #4] 8005878: 6818 ldr r0, [r3, #0] 800587a: 683b ldr r3, [r7, #0] 800587c: 6899 ldr r1, [r3, #8] 800587e: 683b ldr r3, [r7, #0] 8005880: 685a ldr r2, [r3, #4] 8005882: 683b ldr r3, [r7, #0] 8005884: 68db ldr r3, [r3, #12] 8005886: f000 faca bl 8005e1e <TIM_ETR_SetConfig> tmpsmcr = htim->Instance->SMCR; 800588a: 687b ldr r3, [r7, #4] 800588c: 681b ldr r3, [r3, #0] 800588e: 689b ldr r3, [r3, #8] 8005890: 60fb str r3, [r7, #12] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8005892: 68fb ldr r3, [r7, #12] 8005894: f043 0377 orr.w r3, r3, #119 ; 0x77 8005898: 60fb str r3, [r7, #12] htim->Instance->SMCR = tmpsmcr; 800589a: 687b ldr r3, [r7, #4] 800589c: 681b ldr r3, [r3, #0] 800589e: 68fa ldr r2, [r7, #12] 80058a0: 609a str r2, [r3, #8] break; 80058a2: e04e b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> TIM_ETR_SetConfig(htim->Instance, 80058a4: 687b ldr r3, [r7, #4] 80058a6: 6818 ldr r0, [r3, #0] 80058a8: 683b ldr r3, [r7, #0] 80058aa: 6899 ldr r1, [r3, #8] 80058ac: 683b ldr r3, [r7, #0] 80058ae: 685a ldr r2, [r3, #4] 80058b0: 683b ldr r3, [r7, #0] 80058b2: 68db ldr r3, [r3, #12] 80058b4: f000 fab3 bl 8005e1e <TIM_ETR_SetConfig> htim->Instance->SMCR |= TIM_SMCR_ECE; 80058b8: 687b ldr r3, [r7, #4] 80058ba: 681b ldr r3, [r3, #0] 80058bc: 689a ldr r2, [r3, #8] 80058be: 687b ldr r3, [r7, #4] 80058c0: 681b ldr r3, [r3, #0] 80058c2: f442 4280 orr.w r2, r2, #16384 ; 0x4000 80058c6: 609a str r2, [r3, #8] break; 80058c8: e03b b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> TIM_TI1_ConfigInputStage(htim->Instance, 80058ca: 687b ldr r3, [r7, #4] 80058cc: 6818 ldr r0, [r3, #0] 80058ce: 683b ldr r3, [r7, #0] 80058d0: 6859 ldr r1, [r3, #4] 80058d2: 683b ldr r3, [r7, #0] 80058d4: 68db ldr r3, [r3, #12] 80058d6: 461a mov r2, r3 80058d8: f000 fa2a bl 8005d30 <TIM_TI1_ConfigInputStage> TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80058dc: 687b ldr r3, [r7, #4] 80058de: 681b ldr r3, [r3, #0] 80058e0: 2150 movs r1, #80 ; 0x50 80058e2: 4618 mov r0, r3 80058e4: f000 fa81 bl 8005dea <TIM_ITRx_SetConfig> break; 80058e8: e02b b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> TIM_TI2_ConfigInputStage(htim->Instance, 80058ea: 687b ldr r3, [r7, #4] 80058ec: 6818 ldr r0, [r3, #0] 80058ee: 683b ldr r3, [r7, #0] 80058f0: 6859 ldr r1, [r3, #4] 80058f2: 683b ldr r3, [r7, #0] 80058f4: 68db ldr r3, [r3, #12] 80058f6: 461a mov r2, r3 80058f8: f000 fa48 bl 8005d8c <TIM_TI2_ConfigInputStage> TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80058fc: 687b ldr r3, [r7, #4] 80058fe: 681b ldr r3, [r3, #0] 8005900: 2160 movs r1, #96 ; 0x60 8005902: 4618 mov r0, r3 8005904: f000 fa71 bl 8005dea <TIM_ITRx_SetConfig> break; 8005908: e01b b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> TIM_TI1_ConfigInputStage(htim->Instance, 800590a: 687b ldr r3, [r7, #4] 800590c: 6818 ldr r0, [r3, #0] 800590e: 683b ldr r3, [r7, #0] 8005910: 6859 ldr r1, [r3, #4] 8005912: 683b ldr r3, [r7, #0] 8005914: 68db ldr r3, [r3, #12] 8005916: 461a mov r2, r3 8005918: f000 fa0a bl 8005d30 <TIM_TI1_ConfigInputStage> TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800591c: 687b ldr r3, [r7, #4] 800591e: 681b ldr r3, [r3, #0] 8005920: 2140 movs r1, #64 ; 0x40 8005922: 4618 mov r0, r3 8005924: f000 fa61 bl 8005dea <TIM_ITRx_SetConfig> break; 8005928: e00b b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800592a: 687b ldr r3, [r7, #4] 800592c: 681a ldr r2, [r3, #0] 800592e: 683b ldr r3, [r7, #0] 8005930: 681b ldr r3, [r3, #0] 8005932: 4619 mov r1, r3 8005934: 4610 mov r0, r2 8005936: f000 fa58 bl 8005dea <TIM_ITRx_SetConfig> break; 800593a: e002 b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> break; 800593c: bf00 nop 800593e: e000 b.n 8005942 <HAL_TIM_ConfigClockSource+0x16e> break; 8005940: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8005942: 687b ldr r3, [r7, #4] 8005944: 2201 movs r2, #1 8005946: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 800594a: 687b ldr r3, [r7, #4] 800594c: 2200 movs r2, #0 800594e: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8005952: 2300 movs r3, #0 } 8005954: 4618 mov r0, r3 8005956: 3710 adds r7, #16 8005958: 46bd mov sp, r7 800595a: bd80 pop {r7, pc} 0800595c <TIM_Base_SetConfig>: * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 800595c: b480 push {r7} 800595e: b085 sub sp, #20 8005960: af00 add r7, sp, #0 8005962: 6078 str r0, [r7, #4] 8005964: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005966: 687b ldr r3, [r7, #4] 8005968: 681b ldr r3, [r3, #0] 800596a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800596c: 687b ldr r3, [r7, #4] 800596e: 4a29 ldr r2, [pc, #164] ; (8005a14 <TIM_Base_SetConfig+0xb8>) 8005970: 4293 cmp r3, r2 8005972: d00b beq.n 800598c <TIM_Base_SetConfig+0x30> 8005974: 687b ldr r3, [r7, #4] 8005976: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800597a: d007 beq.n 800598c <TIM_Base_SetConfig+0x30> 800597c: 687b ldr r3, [r7, #4] 800597e: 4a26 ldr r2, [pc, #152] ; (8005a18 <TIM_Base_SetConfig+0xbc>) 8005980: 4293 cmp r3, r2 8005982: d003 beq.n 800598c <TIM_Base_SetConfig+0x30> 8005984: 687b ldr r3, [r7, #4] 8005986: 4a25 ldr r2, [pc, #148] ; (8005a1c <TIM_Base_SetConfig+0xc0>) 8005988: 4293 cmp r3, r2 800598a: d108 bne.n 800599e <TIM_Base_SetConfig+0x42> { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800598c: 68fb ldr r3, [r7, #12] 800598e: f023 0370 bic.w r3, r3, #112 ; 0x70 8005992: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005994: 683b ldr r3, [r7, #0] 8005996: 685b ldr r3, [r3, #4] 8005998: 68fa ldr r2, [r7, #12] 800599a: 4313 orrs r3, r2 800599c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800599e: 687b ldr r3, [r7, #4] 80059a0: 4a1c ldr r2, [pc, #112] ; (8005a14 <TIM_Base_SetConfig+0xb8>) 80059a2: 4293 cmp r3, r2 80059a4: d00b beq.n 80059be <TIM_Base_SetConfig+0x62> 80059a6: 687b ldr r3, [r7, #4] 80059a8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80059ac: d007 beq.n 80059be <TIM_Base_SetConfig+0x62> 80059ae: 687b ldr r3, [r7, #4] 80059b0: 4a19 ldr r2, [pc, #100] ; (8005a18 <TIM_Base_SetConfig+0xbc>) 80059b2: 4293 cmp r3, r2 80059b4: d003 beq.n 80059be <TIM_Base_SetConfig+0x62> 80059b6: 687b ldr r3, [r7, #4] 80059b8: 4a18 ldr r2, [pc, #96] ; (8005a1c <TIM_Base_SetConfig+0xc0>) 80059ba: 4293 cmp r3, r2 80059bc: d108 bne.n 80059d0 <TIM_Base_SetConfig+0x74> { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80059be: 68fb ldr r3, [r7, #12] 80059c0: f423 7340 bic.w r3, r3, #768 ; 0x300 80059c4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80059c6: 683b ldr r3, [r7, #0] 80059c8: 68db ldr r3, [r3, #12] 80059ca: 68fa ldr r2, [r7, #12] 80059cc: 4313 orrs r3, r2 80059ce: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80059d0: 68fb ldr r3, [r7, #12] 80059d2: f023 0280 bic.w r2, r3, #128 ; 0x80 80059d6: 683b ldr r3, [r7, #0] 80059d8: 695b ldr r3, [r3, #20] 80059da: 4313 orrs r3, r2 80059dc: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80059de: 687b ldr r3, [r7, #4] 80059e0: 68fa ldr r2, [r7, #12] 80059e2: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80059e4: 683b ldr r3, [r7, #0] 80059e6: 689a ldr r2, [r3, #8] 80059e8: 687b ldr r3, [r7, #4] 80059ea: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80059ec: 683b ldr r3, [r7, #0] 80059ee: 681a ldr r2, [r3, #0] 80059f0: 687b ldr r3, [r7, #4] 80059f2: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80059f4: 687b ldr r3, [r7, #4] 80059f6: 4a07 ldr r2, [pc, #28] ; (8005a14 <TIM_Base_SetConfig+0xb8>) 80059f8: 4293 cmp r3, r2 80059fa: d103 bne.n 8005a04 <TIM_Base_SetConfig+0xa8> { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80059fc: 683b ldr r3, [r7, #0] 80059fe: 691a ldr r2, [r3, #16] 8005a00: 687b ldr r3, [r7, #4] 8005a02: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8005a04: 687b ldr r3, [r7, #4] 8005a06: 2201 movs r2, #1 8005a08: 615a str r2, [r3, #20] } 8005a0a: bf00 nop 8005a0c: 3714 adds r7, #20 8005a0e: 46bd mov sp, r7 8005a10: bc80 pop {r7} 8005a12: 4770 bx lr 8005a14: 40012c00 .word 0x40012c00 8005a18: 40000400 .word 0x40000400 8005a1c: 40000800 .word 0x40000800 08005a20 <TIM_OC1_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8005a20: b480 push {r7} 8005a22: b087 sub sp, #28 8005a24: af00 add r7, sp, #0 8005a26: 6078 str r0, [r7, #4] 8005a28: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8005a2a: 687b ldr r3, [r7, #4] 8005a2c: 6a1b ldr r3, [r3, #32] 8005a2e: f023 0201 bic.w r2, r3, #1 8005a32: 687b ldr r3, [r7, #4] 8005a34: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005a36: 687b ldr r3, [r7, #4] 8005a38: 6a1b ldr r3, [r3, #32] 8005a3a: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 685b ldr r3, [r3, #4] 8005a40: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8005a42: 687b ldr r3, [r7, #4] 8005a44: 699b ldr r3, [r3, #24] 8005a46: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8005a48: 68fb ldr r3, [r7, #12] 8005a4a: f023 0370 bic.w r3, r3, #112 ; 0x70 8005a4e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8005a50: 68fb ldr r3, [r7, #12] 8005a52: f023 0303 bic.w r3, r3, #3 8005a56: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005a58: 683b ldr r3, [r7, #0] 8005a5a: 681b ldr r3, [r3, #0] 8005a5c: 68fa ldr r2, [r7, #12] 8005a5e: 4313 orrs r3, r2 8005a60: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8005a62: 697b ldr r3, [r7, #20] 8005a64: f023 0302 bic.w r3, r3, #2 8005a68: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8005a6a: 683b ldr r3, [r7, #0] 8005a6c: 689b ldr r3, [r3, #8] 8005a6e: 697a ldr r2, [r7, #20] 8005a70: 4313 orrs r3, r2 8005a72: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8005a74: 687b ldr r3, [r7, #4] 8005a76: 4a1c ldr r2, [pc, #112] ; (8005ae8 <TIM_OC1_SetConfig+0xc8>) 8005a78: 4293 cmp r3, r2 8005a7a: d10c bne.n 8005a96 <TIM_OC1_SetConfig+0x76> { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005a7c: 697b ldr r3, [r7, #20] 8005a7e: f023 0308 bic.w r3, r3, #8 8005a82: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8005a84: 683b ldr r3, [r7, #0] 8005a86: 68db ldr r3, [r3, #12] 8005a88: 697a ldr r2, [r7, #20] 8005a8a: 4313 orrs r3, r2 8005a8c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8005a8e: 697b ldr r3, [r7, #20] 8005a90: f023 0304 bic.w r3, r3, #4 8005a94: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005a96: 687b ldr r3, [r7, #4] 8005a98: 4a13 ldr r2, [pc, #76] ; (8005ae8 <TIM_OC1_SetConfig+0xc8>) 8005a9a: 4293 cmp r3, r2 8005a9c: d111 bne.n 8005ac2 <TIM_OC1_SetConfig+0xa2> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8005a9e: 693b ldr r3, [r7, #16] 8005aa0: f423 7380 bic.w r3, r3, #256 ; 0x100 8005aa4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8005aa6: 693b ldr r3, [r7, #16] 8005aa8: f423 7300 bic.w r3, r3, #512 ; 0x200 8005aac: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005aae: 683b ldr r3, [r7, #0] 8005ab0: 695b ldr r3, [r3, #20] 8005ab2: 693a ldr r2, [r7, #16] 8005ab4: 4313 orrs r3, r2 8005ab6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8005ab8: 683b ldr r3, [r7, #0] 8005aba: 699b ldr r3, [r3, #24] 8005abc: 693a ldr r2, [r7, #16] 8005abe: 4313 orrs r3, r2 8005ac0: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005ac2: 687b ldr r3, [r7, #4] 8005ac4: 693a ldr r2, [r7, #16] 8005ac6: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005ac8: 687b ldr r3, [r7, #4] 8005aca: 68fa ldr r2, [r7, #12] 8005acc: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8005ace: 683b ldr r3, [r7, #0] 8005ad0: 685a ldr r2, [r3, #4] 8005ad2: 687b ldr r3, [r7, #4] 8005ad4: 635a str r2, [r3, #52] ; 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005ad6: 687b ldr r3, [r7, #4] 8005ad8: 697a ldr r2, [r7, #20] 8005ada: 621a str r2, [r3, #32] } 8005adc: bf00 nop 8005ade: 371c adds r7, #28 8005ae0: 46bd mov sp, r7 8005ae2: bc80 pop {r7} 8005ae4: 4770 bx lr 8005ae6: bf00 nop 8005ae8: 40012c00 .word 0x40012c00 08005aec <TIM_OC2_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8005aec: b480 push {r7} 8005aee: b087 sub sp, #28 8005af0: af00 add r7, sp, #0 8005af2: 6078 str r0, [r7, #4] 8005af4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8005af6: 687b ldr r3, [r7, #4] 8005af8: 6a1b ldr r3, [r3, #32] 8005afa: f023 0210 bic.w r2, r3, #16 8005afe: 687b ldr r3, [r7, #4] 8005b00: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005b02: 687b ldr r3, [r7, #4] 8005b04: 6a1b ldr r3, [r3, #32] 8005b06: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005b08: 687b ldr r3, [r7, #4] 8005b0a: 685b ldr r3, [r3, #4] 8005b0c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8005b0e: 687b ldr r3, [r7, #4] 8005b10: 699b ldr r3, [r3, #24] 8005b12: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8005b14: 68fb ldr r3, [r7, #12] 8005b16: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 8005b1a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8005b1c: 68fb ldr r3, [r7, #12] 8005b1e: f423 7340 bic.w r3, r3, #768 ; 0x300 8005b22: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005b24: 683b ldr r3, [r7, #0] 8005b26: 681b ldr r3, [r3, #0] 8005b28: 021b lsls r3, r3, #8 8005b2a: 68fa ldr r2, [r7, #12] 8005b2c: 4313 orrs r3, r2 8005b2e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8005b30: 697b ldr r3, [r7, #20] 8005b32: f023 0320 bic.w r3, r3, #32 8005b36: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8005b38: 683b ldr r3, [r7, #0] 8005b3a: 689b ldr r3, [r3, #8] 8005b3c: 011b lsls r3, r3, #4 8005b3e: 697a ldr r2, [r7, #20] 8005b40: 4313 orrs r3, r2 8005b42: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8005b44: 687b ldr r3, [r7, #4] 8005b46: 4a1d ldr r2, [pc, #116] ; (8005bbc <TIM_OC2_SetConfig+0xd0>) 8005b48: 4293 cmp r3, r2 8005b4a: d10d bne.n 8005b68 <TIM_OC2_SetConfig+0x7c> { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8005b4c: 697b ldr r3, [r7, #20] 8005b4e: f023 0380 bic.w r3, r3, #128 ; 0x80 8005b52: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005b54: 683b ldr r3, [r7, #0] 8005b56: 68db ldr r3, [r3, #12] 8005b58: 011b lsls r3, r3, #4 8005b5a: 697a ldr r2, [r7, #20] 8005b5c: 4313 orrs r3, r2 8005b5e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8005b60: 697b ldr r3, [r7, #20] 8005b62: f023 0340 bic.w r3, r3, #64 ; 0x40 8005b66: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005b68: 687b ldr r3, [r7, #4] 8005b6a: 4a14 ldr r2, [pc, #80] ; (8005bbc <TIM_OC2_SetConfig+0xd0>) 8005b6c: 4293 cmp r3, r2 8005b6e: d113 bne.n 8005b98 <TIM_OC2_SetConfig+0xac> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8005b70: 693b ldr r3, [r7, #16] 8005b72: f423 6380 bic.w r3, r3, #1024 ; 0x400 8005b76: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8005b78: 693b ldr r3, [r7, #16] 8005b7a: f423 6300 bic.w r3, r3, #2048 ; 0x800 8005b7e: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005b80: 683b ldr r3, [r7, #0] 8005b82: 695b ldr r3, [r3, #20] 8005b84: 009b lsls r3, r3, #2 8005b86: 693a ldr r2, [r7, #16] 8005b88: 4313 orrs r3, r2 8005b8a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005b8c: 683b ldr r3, [r7, #0] 8005b8e: 699b ldr r3, [r3, #24] 8005b90: 009b lsls r3, r3, #2 8005b92: 693a ldr r2, [r7, #16] 8005b94: 4313 orrs r3, r2 8005b96: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 693a ldr r2, [r7, #16] 8005b9c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005b9e: 687b ldr r3, [r7, #4] 8005ba0: 68fa ldr r2, [r7, #12] 8005ba2: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8005ba4: 683b ldr r3, [r7, #0] 8005ba6: 685a ldr r2, [r3, #4] 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 639a str r2, [r3, #56] ; 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005bac: 687b ldr r3, [r7, #4] 8005bae: 697a ldr r2, [r7, #20] 8005bb0: 621a str r2, [r3, #32] } 8005bb2: bf00 nop 8005bb4: 371c adds r7, #28 8005bb6: 46bd mov sp, r7 8005bb8: bc80 pop {r7} 8005bba: 4770 bx lr 8005bbc: 40012c00 .word 0x40012c00 08005bc0 <TIM_OC3_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8005bc0: b480 push {r7} 8005bc2: b087 sub sp, #28 8005bc4: af00 add r7, sp, #0 8005bc6: 6078 str r0, [r7, #4] 8005bc8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8005bca: 687b ldr r3, [r7, #4] 8005bcc: 6a1b ldr r3, [r3, #32] 8005bce: f423 7280 bic.w r2, r3, #256 ; 0x100 8005bd2: 687b ldr r3, [r7, #4] 8005bd4: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005bd6: 687b ldr r3, [r7, #4] 8005bd8: 6a1b ldr r3, [r3, #32] 8005bda: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 685b ldr r3, [r3, #4] 8005be0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005be2: 687b ldr r3, [r7, #4] 8005be4: 69db ldr r3, [r3, #28] 8005be6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8005be8: 68fb ldr r3, [r7, #12] 8005bea: f023 0370 bic.w r3, r3, #112 ; 0x70 8005bee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8005bf0: 68fb ldr r3, [r7, #12] 8005bf2: f023 0303 bic.w r3, r3, #3 8005bf6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005bf8: 683b ldr r3, [r7, #0] 8005bfa: 681b ldr r3, [r3, #0] 8005bfc: 68fa ldr r2, [r7, #12] 8005bfe: 4313 orrs r3, r2 8005c00: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8005c02: 697b ldr r3, [r7, #20] 8005c04: f423 7300 bic.w r3, r3, #512 ; 0x200 8005c08: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8005c0a: 683b ldr r3, [r7, #0] 8005c0c: 689b ldr r3, [r3, #8] 8005c0e: 021b lsls r3, r3, #8 8005c10: 697a ldr r2, [r7, #20] 8005c12: 4313 orrs r3, r2 8005c14: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8005c16: 687b ldr r3, [r7, #4] 8005c18: 4a1d ldr r2, [pc, #116] ; (8005c90 <TIM_OC3_SetConfig+0xd0>) 8005c1a: 4293 cmp r3, r2 8005c1c: d10d bne.n 8005c3a <TIM_OC3_SetConfig+0x7a> { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8005c1e: 697b ldr r3, [r7, #20] 8005c20: f423 6300 bic.w r3, r3, #2048 ; 0x800 8005c24: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8005c26: 683b ldr r3, [r7, #0] 8005c28: 68db ldr r3, [r3, #12] 8005c2a: 021b lsls r3, r3, #8 8005c2c: 697a ldr r2, [r7, #20] 8005c2e: 4313 orrs r3, r2 8005c30: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8005c32: 697b ldr r3, [r7, #20] 8005c34: f423 6380 bic.w r3, r3, #1024 ; 0x400 8005c38: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 4a14 ldr r2, [pc, #80] ; (8005c90 <TIM_OC3_SetConfig+0xd0>) 8005c3e: 4293 cmp r3, r2 8005c40: d113 bne.n 8005c6a <TIM_OC3_SetConfig+0xaa> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8005c42: 693b ldr r3, [r7, #16] 8005c44: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8005c48: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8005c4a: 693b ldr r3, [r7, #16] 8005c4c: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8005c50: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8005c52: 683b ldr r3, [r7, #0] 8005c54: 695b ldr r3, [r3, #20] 8005c56: 011b lsls r3, r3, #4 8005c58: 693a ldr r2, [r7, #16] 8005c5a: 4313 orrs r3, r2 8005c5c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8005c5e: 683b ldr r3, [r7, #0] 8005c60: 699b ldr r3, [r3, #24] 8005c62: 011b lsls r3, r3, #4 8005c64: 693a ldr r2, [r7, #16] 8005c66: 4313 orrs r3, r2 8005c68: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005c6a: 687b ldr r3, [r7, #4] 8005c6c: 693a ldr r2, [r7, #16] 8005c6e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005c70: 687b ldr r3, [r7, #4] 8005c72: 68fa ldr r2, [r7, #12] 8005c74: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005c76: 683b ldr r3, [r7, #0] 8005c78: 685a ldr r2, [r3, #4] 8005c7a: 687b ldr r3, [r7, #4] 8005c7c: 63da str r2, [r3, #60] ; 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005c7e: 687b ldr r3, [r7, #4] 8005c80: 697a ldr r2, [r7, #20] 8005c82: 621a str r2, [r3, #32] } 8005c84: bf00 nop 8005c86: 371c adds r7, #28 8005c88: 46bd mov sp, r7 8005c8a: bc80 pop {r7} 8005c8c: 4770 bx lr 8005c8e: bf00 nop 8005c90: 40012c00 .word 0x40012c00 08005c94 <TIM_OC4_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8005c94: b480 push {r7} 8005c96: b087 sub sp, #28 8005c98: af00 add r7, sp, #0 8005c9a: 6078 str r0, [r7, #4] 8005c9c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8005c9e: 687b ldr r3, [r7, #4] 8005ca0: 6a1b ldr r3, [r3, #32] 8005ca2: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8005ca6: 687b ldr r3, [r7, #4] 8005ca8: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005caa: 687b ldr r3, [r7, #4] 8005cac: 6a1b ldr r3, [r3, #32] 8005cae: 613b str r3, [r7, #16] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005cb0: 687b ldr r3, [r7, #4] 8005cb2: 685b ldr r3, [r3, #4] 8005cb4: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005cb6: 687b ldr r3, [r7, #4] 8005cb8: 69db ldr r3, [r3, #28] 8005cba: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8005cbc: 68fb ldr r3, [r7, #12] 8005cbe: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 8005cc2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8005cc4: 68fb ldr r3, [r7, #12] 8005cc6: f423 7340 bic.w r3, r3, #768 ; 0x300 8005cca: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005ccc: 683b ldr r3, [r7, #0] 8005cce: 681b ldr r3, [r3, #0] 8005cd0: 021b lsls r3, r3, #8 8005cd2: 68fa ldr r2, [r7, #12] 8005cd4: 4313 orrs r3, r2 8005cd6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8005cd8: 693b ldr r3, [r7, #16] 8005cda: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8005cde: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8005ce0: 683b ldr r3, [r7, #0] 8005ce2: 689b ldr r3, [r3, #8] 8005ce4: 031b lsls r3, r3, #12 8005ce6: 693a ldr r2, [r7, #16] 8005ce8: 4313 orrs r3, r2 8005cea: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005cec: 687b ldr r3, [r7, #4] 8005cee: 4a0f ldr r2, [pc, #60] ; (8005d2c <TIM_OC4_SetConfig+0x98>) 8005cf0: 4293 cmp r3, r2 8005cf2: d109 bne.n 8005d08 <TIM_OC4_SetConfig+0x74> { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005cf4: 697b ldr r3, [r7, #20] 8005cf6: f423 4380 bic.w r3, r3, #16384 ; 0x4000 8005cfa: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005cfc: 683b ldr r3, [r7, #0] 8005cfe: 695b ldr r3, [r3, #20] 8005d00: 019b lsls r3, r3, #6 8005d02: 697a ldr r2, [r7, #20] 8005d04: 4313 orrs r3, r2 8005d06: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005d08: 687b ldr r3, [r7, #4] 8005d0a: 697a ldr r2, [r7, #20] 8005d0c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005d0e: 687b ldr r3, [r7, #4] 8005d10: 68fa ldr r2, [r7, #12] 8005d12: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005d14: 683b ldr r3, [r7, #0] 8005d16: 685a ldr r2, [r3, #4] 8005d18: 687b ldr r3, [r7, #4] 8005d1a: 641a str r2, [r3, #64] ; 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005d1c: 687b ldr r3, [r7, #4] 8005d1e: 693a ldr r2, [r7, #16] 8005d20: 621a str r2, [r3, #32] } 8005d22: bf00 nop 8005d24: 371c adds r7, #28 8005d26: 46bd mov sp, r7 8005d28: bc80 pop {r7} 8005d2a: 4770 bx lr 8005d2c: 40012c00 .word 0x40012c00 08005d30 <TIM_TI1_ConfigInputStage>: * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005d30: b480 push {r7} 8005d32: b087 sub sp, #28 8005d34: af00 add r7, sp, #0 8005d36: 60f8 str r0, [r7, #12] 8005d38: 60b9 str r1, [r7, #8] 8005d3a: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005d3c: 68fb ldr r3, [r7, #12] 8005d3e: 6a1b ldr r3, [r3, #32] 8005d40: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8005d42: 68fb ldr r3, [r7, #12] 8005d44: 6a1b ldr r3, [r3, #32] 8005d46: f023 0201 bic.w r2, r3, #1 8005d4a: 68fb ldr r3, [r7, #12] 8005d4c: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005d4e: 68fb ldr r3, [r7, #12] 8005d50: 699b ldr r3, [r3, #24] 8005d52: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005d54: 693b ldr r3, [r7, #16] 8005d56: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8005d5a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8005d5c: 687b ldr r3, [r7, #4] 8005d5e: 011b lsls r3, r3, #4 8005d60: 693a ldr r2, [r7, #16] 8005d62: 4313 orrs r3, r2 8005d64: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005d66: 697b ldr r3, [r7, #20] 8005d68: f023 030a bic.w r3, r3, #10 8005d6c: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8005d6e: 697a ldr r2, [r7, #20] 8005d70: 68bb ldr r3, [r7, #8] 8005d72: 4313 orrs r3, r2 8005d74: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8005d76: 68fb ldr r3, [r7, #12] 8005d78: 693a ldr r2, [r7, #16] 8005d7a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005d7c: 68fb ldr r3, [r7, #12] 8005d7e: 697a ldr r2, [r7, #20] 8005d80: 621a str r2, [r3, #32] } 8005d82: bf00 nop 8005d84: 371c adds r7, #28 8005d86: 46bd mov sp, r7 8005d88: bc80 pop {r7} 8005d8a: 4770 bx lr 08005d8c <TIM_TI2_ConfigInputStage>: * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005d8c: b480 push {r7} 8005d8e: b087 sub sp, #28 8005d90: af00 add r7, sp, #0 8005d92: 60f8 str r0, [r7, #12] 8005d94: 60b9 str r1, [r7, #8] 8005d96: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8005d98: 68fb ldr r3, [r7, #12] 8005d9a: 6a1b ldr r3, [r3, #32] 8005d9c: f023 0210 bic.w r2, r3, #16 8005da0: 68fb ldr r3, [r7, #12] 8005da2: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005da4: 68fb ldr r3, [r7, #12] 8005da6: 699b ldr r3, [r3, #24] 8005da8: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 8005daa: 68fb ldr r3, [r7, #12] 8005dac: 6a1b ldr r3, [r3, #32] 8005dae: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8005db0: 697b ldr r3, [r7, #20] 8005db2: f423 4370 bic.w r3, r3, #61440 ; 0xf000 8005db6: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 8005db8: 687b ldr r3, [r7, #4] 8005dba: 031b lsls r3, r3, #12 8005dbc: 697a ldr r2, [r7, #20] 8005dbe: 4313 orrs r3, r2 8005dc0: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8005dc2: 693b ldr r3, [r7, #16] 8005dc4: f023 03a0 bic.w r3, r3, #160 ; 0xa0 8005dc8: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 8005dca: 68bb ldr r3, [r7, #8] 8005dcc: 011b lsls r3, r3, #4 8005dce: 693a ldr r2, [r7, #16] 8005dd0: 4313 orrs r3, r2 8005dd2: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8005dd4: 68fb ldr r3, [r7, #12] 8005dd6: 697a ldr r2, [r7, #20] 8005dd8: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005dda: 68fb ldr r3, [r7, #12] 8005ddc: 693a ldr r2, [r7, #16] 8005dde: 621a str r2, [r3, #32] } 8005de0: bf00 nop 8005de2: 371c adds r7, #28 8005de4: 46bd mov sp, r7 8005de6: bc80 pop {r7} 8005de8: 4770 bx lr 08005dea <TIM_ITRx_SetConfig>: * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8005dea: b480 push {r7} 8005dec: b085 sub sp, #20 8005dee: af00 add r7, sp, #0 8005df0: 6078 str r0, [r7, #4] 8005df2: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8005df4: 687b ldr r3, [r7, #4] 8005df6: 689b ldr r3, [r3, #8] 8005df8: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8005dfa: 68fb ldr r3, [r7, #12] 8005dfc: f023 0370 bic.w r3, r3, #112 ; 0x70 8005e00: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8005e02: 683a ldr r2, [r7, #0] 8005e04: 68fb ldr r3, [r7, #12] 8005e06: 4313 orrs r3, r2 8005e08: f043 0307 orr.w r3, r3, #7 8005e0c: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005e0e: 687b ldr r3, [r7, #4] 8005e10: 68fa ldr r2, [r7, #12] 8005e12: 609a str r2, [r3, #8] } 8005e14: bf00 nop 8005e16: 3714 adds r7, #20 8005e18: 46bd mov sp, r7 8005e1a: bc80 pop {r7} 8005e1c: 4770 bx lr 08005e1e <TIM_ETR_SetConfig>: * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005e1e: b480 push {r7} 8005e20: b087 sub sp, #28 8005e22: af00 add r7, sp, #0 8005e24: 60f8 str r0, [r7, #12] 8005e26: 60b9 str r1, [r7, #8] 8005e28: 607a str r2, [r7, #4] 8005e2a: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8005e2c: 68fb ldr r3, [r7, #12] 8005e2e: 689b ldr r3, [r3, #8] 8005e30: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005e32: 697b ldr r3, [r7, #20] 8005e34: f423 437f bic.w r3, r3, #65280 ; 0xff00 8005e38: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8005e3a: 683b ldr r3, [r7, #0] 8005e3c: 021a lsls r2, r3, #8 8005e3e: 687b ldr r3, [r7, #4] 8005e40: 431a orrs r2, r3 8005e42: 68bb ldr r3, [r7, #8] 8005e44: 4313 orrs r3, r2 8005e46: 697a ldr r2, [r7, #20] 8005e48: 4313 orrs r3, r2 8005e4a: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005e4c: 68fb ldr r3, [r7, #12] 8005e4e: 697a ldr r2, [r7, #20] 8005e50: 609a str r2, [r3, #8] } 8005e52: bf00 nop 8005e54: 371c adds r7, #28 8005e56: 46bd mov sp, r7 8005e58: bc80 pop {r7} 8005e5a: 4770 bx lr 08005e5c <TIM_CCxChannelCmd>: * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8005e5c: b480 push {r7} 8005e5e: b087 sub sp, #28 8005e60: af00 add r7, sp, #0 8005e62: 60f8 str r0, [r7, #12] 8005e64: 60b9 str r1, [r7, #8] 8005e66: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8005e68: 68bb ldr r3, [r7, #8] 8005e6a: f003 031f and.w r3, r3, #31 8005e6e: 2201 movs r2, #1 8005e70: fa02 f303 lsl.w r3, r2, r3 8005e74: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8005e76: 68fb ldr r3, [r7, #12] 8005e78: 6a1a ldr r2, [r3, #32] 8005e7a: 697b ldr r3, [r7, #20] 8005e7c: 43db mvns r3, r3 8005e7e: 401a ands r2, r3 8005e80: 68fb ldr r3, [r7, #12] 8005e82: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8005e84: 68fb ldr r3, [r7, #12] 8005e86: 6a1a ldr r2, [r3, #32] 8005e88: 68bb ldr r3, [r7, #8] 8005e8a: f003 031f and.w r3, r3, #31 8005e8e: 6879 ldr r1, [r7, #4] 8005e90: fa01 f303 lsl.w r3, r1, r3 8005e94: 431a orrs r2, r3 8005e96: 68fb ldr r3, [r7, #12] 8005e98: 621a str r2, [r3, #32] } 8005e9a: bf00 nop 8005e9c: 371c adds r7, #28 8005e9e: 46bd mov sp, r7 8005ea0: bc80 pop {r7} 8005ea2: 4770 bx lr 08005ea4 <HAL_TIMEx_MasterConfigSynchronization>: * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8005ea4: b480 push {r7} 8005ea6: b085 sub sp, #20 8005ea8: af00 add r7, sp, #0 8005eaa: 6078 str r0, [r7, #4] 8005eac: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005eae: 687b ldr r3, [r7, #4] 8005eb0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8005eb4: 2b01 cmp r3, #1 8005eb6: d101 bne.n 8005ebc <HAL_TIMEx_MasterConfigSynchronization+0x18> 8005eb8: 2302 movs r3, #2 8005eba: e046 b.n 8005f4a <HAL_TIMEx_MasterConfigSynchronization+0xa6> 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: 2201 movs r2, #1 8005ec0: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005ec4: 687b ldr r3, [r7, #4] 8005ec6: 2202 movs r2, #2 8005ec8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005ecc: 687b ldr r3, [r7, #4] 8005ece: 681b ldr r3, [r3, #0] 8005ed0: 685b ldr r3, [r3, #4] 8005ed2: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005ed4: 687b ldr r3, [r7, #4] 8005ed6: 681b ldr r3, [r3, #0] 8005ed8: 689b ldr r3, [r3, #8] 8005eda: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005edc: 68fb ldr r3, [r7, #12] 8005ede: f023 0370 bic.w r3, r3, #112 ; 0x70 8005ee2: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005ee4: 683b ldr r3, [r7, #0] 8005ee6: 681b ldr r3, [r3, #0] 8005ee8: 68fa ldr r2, [r7, #12] 8005eea: 4313 orrs r3, r2 8005eec: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005eee: 687b ldr r3, [r7, #4] 8005ef0: 681b ldr r3, [r3, #0] 8005ef2: 68fa ldr r2, [r7, #12] 8005ef4: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 681b ldr r3, [r3, #0] 8005efa: 4a16 ldr r2, [pc, #88] ; (8005f54 <HAL_TIMEx_MasterConfigSynchronization+0xb0>) 8005efc: 4293 cmp r3, r2 8005efe: d00e beq.n 8005f1e <HAL_TIMEx_MasterConfigSynchronization+0x7a> 8005f00: 687b ldr r3, [r7, #4] 8005f02: 681b ldr r3, [r3, #0] 8005f04: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005f08: d009 beq.n 8005f1e <HAL_TIMEx_MasterConfigSynchronization+0x7a> 8005f0a: 687b ldr r3, [r7, #4] 8005f0c: 681b ldr r3, [r3, #0] 8005f0e: 4a12 ldr r2, [pc, #72] ; (8005f58 <HAL_TIMEx_MasterConfigSynchronization+0xb4>) 8005f10: 4293 cmp r3, r2 8005f12: d004 beq.n 8005f1e <HAL_TIMEx_MasterConfigSynchronization+0x7a> 8005f14: 687b ldr r3, [r7, #4] 8005f16: 681b ldr r3, [r3, #0] 8005f18: 4a10 ldr r2, [pc, #64] ; (8005f5c <HAL_TIMEx_MasterConfigSynchronization+0xb8>) 8005f1a: 4293 cmp r3, r2 8005f1c: d10c bne.n 8005f38 <HAL_TIMEx_MasterConfigSynchronization+0x94> { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005f1e: 68bb ldr r3, [r7, #8] 8005f20: f023 0380 bic.w r3, r3, #128 ; 0x80 8005f24: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005f26: 683b ldr r3, [r7, #0] 8005f28: 685b ldr r3, [r3, #4] 8005f2a: 68ba ldr r2, [r7, #8] 8005f2c: 4313 orrs r3, r2 8005f2e: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005f30: 687b ldr r3, [r7, #4] 8005f32: 681b ldr r3, [r3, #0] 8005f34: 68ba ldr r2, [r7, #8] 8005f36: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005f38: 687b ldr r3, [r7, #4] 8005f3a: 2201 movs r2, #1 8005f3c: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8005f40: 687b ldr r3, [r7, #4] 8005f42: 2200 movs r2, #0 8005f44: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8005f48: 2300 movs r3, #0 } 8005f4a: 4618 mov r0, r3 8005f4c: 3714 adds r7, #20 8005f4e: 46bd mov sp, r7 8005f50: bc80 pop {r7} 8005f52: 4770 bx lr 8005f54: 40012c00 .word 0x40012c00 8005f58: 40000400 .word 0x40000400 8005f5c: 40000800 .word 0x40000800 08005f60 <HAL_UART_Init>: * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005f60: b580 push {r7, lr} 8005f62: b082 sub sp, #8 8005f64: af00 add r7, sp, #0 8005f66: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005f68: 687b ldr r3, [r7, #4] 8005f6a: 2b00 cmp r3, #0 8005f6c: d101 bne.n 8005f72 <HAL_UART_Init+0x12> { return HAL_ERROR; 8005f6e: 2301 movs r3, #1 8005f70: e03f b.n 8005ff2 <HAL_UART_Init+0x92> assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8005f72: 687b ldr r3, [r7, #4] 8005f74: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005f78: b2db uxtb r3, r3 8005f7a: 2b00 cmp r3, #0 8005f7c: d106 bne.n 8005f8c <HAL_UART_Init+0x2c> { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005f7e: 687b ldr r3, [r7, #4] 8005f80: 2200 movs r2, #0 8005f82: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005f86: 6878 ldr r0, [r7, #4] 8005f88: f7fc f9dc bl 8002344 <HAL_UART_MspInit> #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005f8c: 687b ldr r3, [r7, #4] 8005f8e: 2224 movs r2, #36 ; 0x24 8005f90: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005f94: 687b ldr r3, [r7, #4] 8005f96: 681b ldr r3, [r3, #0] 8005f98: 68da ldr r2, [r3, #12] 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: f422 5200 bic.w r2, r2, #8192 ; 0x2000 8005fa2: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005fa4: 6878 ldr r0, [r7, #4] 8005fa6: f000 f905 bl 80061b4 <UART_SetConfig> /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005faa: 687b ldr r3, [r7, #4] 8005fac: 681b ldr r3, [r3, #0] 8005fae: 691a ldr r2, [r3, #16] 8005fb0: 687b ldr r3, [r7, #4] 8005fb2: 681b ldr r3, [r3, #0] 8005fb4: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8005fb8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005fba: 687b ldr r3, [r7, #4] 8005fbc: 681b ldr r3, [r3, #0] 8005fbe: 695a ldr r2, [r3, #20] 8005fc0: 687b ldr r3, [r7, #4] 8005fc2: 681b ldr r3, [r3, #0] 8005fc4: f022 022a bic.w r2, r2, #42 ; 0x2a 8005fc8: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005fca: 687b ldr r3, [r7, #4] 8005fcc: 681b ldr r3, [r3, #0] 8005fce: 68da ldr r2, [r3, #12] 8005fd0: 687b ldr r3, [r7, #4] 8005fd2: 681b ldr r3, [r3, #0] 8005fd4: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8005fd8: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005fda: 687b ldr r3, [r7, #4] 8005fdc: 2200 movs r2, #0 8005fde: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 8005fe0: 687b ldr r3, [r7, #4] 8005fe2: 2220 movs r2, #32 8005fe4: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8005fe8: 687b ldr r3, [r7, #4] 8005fea: 2220 movs r2, #32 8005fec: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 8005ff0: 2300 movs r3, #0 } 8005ff2: 4618 mov r0, r3 8005ff4: 3708 adds r7, #8 8005ff6: 46bd mov sp, r7 8005ff8: bd80 pop {r7, pc} 08005ffa <HAL_UART_Transmit>: * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8005ffa: b580 push {r7, lr} 8005ffc: b08a sub sp, #40 ; 0x28 8005ffe: af02 add r7, sp, #8 8006000: 60f8 str r0, [r7, #12] 8006002: 60b9 str r1, [r7, #8] 8006004: 603b str r3, [r7, #0] 8006006: 4613 mov r3, r2 8006008: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 800600a: 2300 movs r3, #0 800600c: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800600e: 68fb ldr r3, [r7, #12] 8006010: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8006014: b2db uxtb r3, r3 8006016: 2b20 cmp r3, #32 8006018: d17c bne.n 8006114 <HAL_UART_Transmit+0x11a> { if ((pData == NULL) || (Size == 0U)) 800601a: 68bb ldr r3, [r7, #8] 800601c: 2b00 cmp r3, #0 800601e: d002 beq.n 8006026 <HAL_UART_Transmit+0x2c> 8006020: 88fb ldrh r3, [r7, #6] 8006022: 2b00 cmp r3, #0 8006024: d101 bne.n 800602a <HAL_UART_Transmit+0x30> { return HAL_ERROR; 8006026: 2301 movs r3, #1 8006028: e075 b.n 8006116 <HAL_UART_Transmit+0x11c> } /* Process Locked */ __HAL_LOCK(huart); 800602a: 68fb ldr r3, [r7, #12] 800602c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8006030: 2b01 cmp r3, #1 8006032: d101 bne.n 8006038 <HAL_UART_Transmit+0x3e> 8006034: 2302 movs r3, #2 8006036: e06e b.n 8006116 <HAL_UART_Transmit+0x11c> 8006038: 68fb ldr r3, [r7, #12] 800603a: 2201 movs r2, #1 800603c: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 8006040: 68fb ldr r3, [r7, #12] 8006042: 2200 movs r2, #0 8006044: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8006046: 68fb ldr r3, [r7, #12] 8006048: 2221 movs r2, #33 ; 0x21 800604a: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800604e: f7fc fae7 bl 8002620 <HAL_GetTick> 8006052: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8006054: 68fb ldr r3, [r7, #12] 8006056: 88fa ldrh r2, [r7, #6] 8006058: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 800605a: 68fb ldr r3, [r7, #12] 800605c: 88fa ldrh r2, [r7, #6] 800605e: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006060: 68fb ldr r3, [r7, #12] 8006062: 689b ldr r3, [r3, #8] 8006064: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8006068: d108 bne.n 800607c <HAL_UART_Transmit+0x82> 800606a: 68fb ldr r3, [r7, #12] 800606c: 691b ldr r3, [r3, #16] 800606e: 2b00 cmp r3, #0 8006070: d104 bne.n 800607c <HAL_UART_Transmit+0x82> { pdata8bits = NULL; 8006072: 2300 movs r3, #0 8006074: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8006076: 68bb ldr r3, [r7, #8] 8006078: 61bb str r3, [r7, #24] 800607a: e003 b.n 8006084 <HAL_UART_Transmit+0x8a> } else { pdata8bits = pData; 800607c: 68bb ldr r3, [r7, #8] 800607e: 61fb str r3, [r7, #28] pdata16bits = NULL; 8006080: 2300 movs r3, #0 8006082: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 8006084: 68fb ldr r3, [r7, #12] 8006086: 2200 movs r2, #0 8006088: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) 800608c: e02a b.n 80060e4 <HAL_UART_Transmit+0xea> { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800608e: 683b ldr r3, [r7, #0] 8006090: 9300 str r3, [sp, #0] 8006092: 697b ldr r3, [r7, #20] 8006094: 2200 movs r2, #0 8006096: 2180 movs r1, #128 ; 0x80 8006098: 68f8 ldr r0, [r7, #12] 800609a: f000 f840 bl 800611e <UART_WaitOnFlagUntilTimeout> 800609e: 4603 mov r3, r0 80060a0: 2b00 cmp r3, #0 80060a2: d001 beq.n 80060a8 <HAL_UART_Transmit+0xae> { return HAL_TIMEOUT; 80060a4: 2303 movs r3, #3 80060a6: e036 b.n 8006116 <HAL_UART_Transmit+0x11c> } if (pdata8bits == NULL) 80060a8: 69fb ldr r3, [r7, #28] 80060aa: 2b00 cmp r3, #0 80060ac: d10b bne.n 80060c6 <HAL_UART_Transmit+0xcc> { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 80060ae: 69bb ldr r3, [r7, #24] 80060b0: 881b ldrh r3, [r3, #0] 80060b2: 461a mov r2, r3 80060b4: 68fb ldr r3, [r7, #12] 80060b6: 681b ldr r3, [r3, #0] 80060b8: f3c2 0208 ubfx r2, r2, #0, #9 80060bc: 605a str r2, [r3, #4] pdata16bits++; 80060be: 69bb ldr r3, [r7, #24] 80060c0: 3302 adds r3, #2 80060c2: 61bb str r3, [r7, #24] 80060c4: e007 b.n 80060d6 <HAL_UART_Transmit+0xdc> } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 80060c6: 69fb ldr r3, [r7, #28] 80060c8: 781a ldrb r2, [r3, #0] 80060ca: 68fb ldr r3, [r7, #12] 80060cc: 681b ldr r3, [r3, #0] 80060ce: 605a str r2, [r3, #4] pdata8bits++; 80060d0: 69fb ldr r3, [r7, #28] 80060d2: 3301 adds r3, #1 80060d4: 61fb str r3, [r7, #28] } huart->TxXferCount--; 80060d6: 68fb ldr r3, [r7, #12] 80060d8: 8cdb ldrh r3, [r3, #38] ; 0x26 80060da: b29b uxth r3, r3 80060dc: 3b01 subs r3, #1 80060de: b29a uxth r2, r3 80060e0: 68fb ldr r3, [r7, #12] 80060e2: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 80060e4: 68fb ldr r3, [r7, #12] 80060e6: 8cdb ldrh r3, [r3, #38] ; 0x26 80060e8: b29b uxth r3, r3 80060ea: 2b00 cmp r3, #0 80060ec: d1cf bne.n 800608e <HAL_UART_Transmit+0x94> } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80060ee: 683b ldr r3, [r7, #0] 80060f0: 9300 str r3, [sp, #0] 80060f2: 697b ldr r3, [r7, #20] 80060f4: 2200 movs r2, #0 80060f6: 2140 movs r1, #64 ; 0x40 80060f8: 68f8 ldr r0, [r7, #12] 80060fa: f000 f810 bl 800611e <UART_WaitOnFlagUntilTimeout> 80060fe: 4603 mov r3, r0 8006100: 2b00 cmp r3, #0 8006102: d001 beq.n 8006108 <HAL_UART_Transmit+0x10e> { return HAL_TIMEOUT; 8006104: 2303 movs r3, #3 8006106: e006 b.n 8006116 <HAL_UART_Transmit+0x11c> } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006108: 68fb ldr r3, [r7, #12] 800610a: 2220 movs r2, #32 800610c: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8006110: 2300 movs r3, #0 8006112: e000 b.n 8006116 <HAL_UART_Transmit+0x11c> } else { return HAL_BUSY; 8006114: 2302 movs r3, #2 } } 8006116: 4618 mov r0, r3 8006118: 3720 adds r7, #32 800611a: 46bd mov sp, r7 800611c: bd80 pop {r7, pc} 0800611e <UART_WaitOnFlagUntilTimeout>: * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800611e: b580 push {r7, lr} 8006120: b084 sub sp, #16 8006122: af00 add r7, sp, #0 8006124: 60f8 str r0, [r7, #12] 8006126: 60b9 str r1, [r7, #8] 8006128: 603b str r3, [r7, #0] 800612a: 4613 mov r3, r2 800612c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800612e: e02c b.n 800618a <UART_WaitOnFlagUntilTimeout+0x6c> { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006130: 69bb ldr r3, [r7, #24] 8006132: f1b3 3fff cmp.w r3, #4294967295 8006136: d028 beq.n 800618a <UART_WaitOnFlagUntilTimeout+0x6c> { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8006138: 69bb ldr r3, [r7, #24] 800613a: 2b00 cmp r3, #0 800613c: d007 beq.n 800614e <UART_WaitOnFlagUntilTimeout+0x30> 800613e: f7fc fa6f bl 8002620 <HAL_GetTick> 8006142: 4602 mov r2, r0 8006144: 683b ldr r3, [r7, #0] 8006146: 1ad3 subs r3, r2, r3 8006148: 69ba ldr r2, [r7, #24] 800614a: 429a cmp r2, r3 800614c: d21d bcs.n 800618a <UART_WaitOnFlagUntilTimeout+0x6c> { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 800614e: 68fb ldr r3, [r7, #12] 8006150: 681b ldr r3, [r3, #0] 8006152: 68da ldr r2, [r3, #12] 8006154: 68fb ldr r3, [r7, #12] 8006156: 681b ldr r3, [r3, #0] 8006158: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 800615c: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800615e: 68fb ldr r3, [r7, #12] 8006160: 681b ldr r3, [r3, #0] 8006162: 695a ldr r2, [r3, #20] 8006164: 68fb ldr r3, [r7, #12] 8006166: 681b ldr r3, [r3, #0] 8006168: f022 0201 bic.w r2, r2, #1 800616c: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 800616e: 68fb ldr r3, [r7, #12] 8006170: 2220 movs r2, #32 8006172: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8006176: 68fb ldr r3, [r7, #12] 8006178: 2220 movs r2, #32 800617a: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 800617e: 68fb ldr r3, [r7, #12] 8006180: 2200 movs r2, #0 8006182: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; 8006186: 2303 movs r3, #3 8006188: e00f b.n 80061aa <UART_WaitOnFlagUntilTimeout+0x8c> while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800618a: 68fb ldr r3, [r7, #12] 800618c: 681b ldr r3, [r3, #0] 800618e: 681a ldr r2, [r3, #0] 8006190: 68bb ldr r3, [r7, #8] 8006192: 4013 ands r3, r2 8006194: 68ba ldr r2, [r7, #8] 8006196: 429a cmp r2, r3 8006198: bf0c ite eq 800619a: 2301 moveq r3, #1 800619c: 2300 movne r3, #0 800619e: b2db uxtb r3, r3 80061a0: 461a mov r2, r3 80061a2: 79fb ldrb r3, [r7, #7] 80061a4: 429a cmp r2, r3 80061a6: d0c3 beq.n 8006130 <UART_WaitOnFlagUntilTimeout+0x12> } } } return HAL_OK; 80061a8: 2300 movs r3, #0 } 80061aa: 4618 mov r0, r3 80061ac: 3710 adds r7, #16 80061ae: 46bd mov sp, r7 80061b0: bd80 pop {r7, pc} ... 080061b4 <UART_SetConfig>: * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 80061b4: b580 push {r7, lr} 80061b6: b084 sub sp, #16 80061b8: af00 add r7, sp, #0 80061ba: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80061bc: 687b ldr r3, [r7, #4] 80061be: 681b ldr r3, [r3, #0] 80061c0: 691b ldr r3, [r3, #16] 80061c2: f423 5140 bic.w r1, r3, #12288 ; 0x3000 80061c6: 687b ldr r3, [r7, #4] 80061c8: 68da ldr r2, [r3, #12] 80061ca: 687b ldr r3, [r7, #4] 80061cc: 681b ldr r3, [r3, #0] 80061ce: 430a orrs r2, r1 80061d0: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 80061d2: 687b ldr r3, [r7, #4] 80061d4: 689a ldr r2, [r3, #8] 80061d6: 687b ldr r3, [r7, #4] 80061d8: 691b ldr r3, [r3, #16] 80061da: 431a orrs r2, r3 80061dc: 687b ldr r3, [r7, #4] 80061de: 695b ldr r3, [r3, #20] 80061e0: 4313 orrs r3, r2 80061e2: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 80061e4: 687b ldr r3, [r7, #4] 80061e6: 681b ldr r3, [r3, #0] 80061e8: 68db ldr r3, [r3, #12] 80061ea: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 80061ee: f023 030c bic.w r3, r3, #12 80061f2: 687a ldr r2, [r7, #4] 80061f4: 6812 ldr r2, [r2, #0] 80061f6: 68b9 ldr r1, [r7, #8] 80061f8: 430b orrs r3, r1 80061fa: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80061fc: 687b ldr r3, [r7, #4] 80061fe: 681b ldr r3, [r3, #0] 8006200: 695b ldr r3, [r3, #20] 8006202: f423 7140 bic.w r1, r3, #768 ; 0x300 8006206: 687b ldr r3, [r7, #4] 8006208: 699a ldr r2, [r3, #24] 800620a: 687b ldr r3, [r7, #4] 800620c: 681b ldr r3, [r3, #0] 800620e: 430a orrs r2, r1 8006210: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8006212: 687b ldr r3, [r7, #4] 8006214: 681b ldr r3, [r3, #0] 8006216: 4a2c ldr r2, [pc, #176] ; (80062c8 <UART_SetConfig+0x114>) 8006218: 4293 cmp r3, r2 800621a: d103 bne.n 8006224 <UART_SetConfig+0x70> { pclk = HAL_RCC_GetPCLK2Freq(); 800621c: f7fd fe90 bl 8003f40 <HAL_RCC_GetPCLK2Freq> 8006220: 60f8 str r0, [r7, #12] 8006222: e002 b.n 800622a <UART_SetConfig+0x76> } else { pclk = HAL_RCC_GetPCLK1Freq(); 8006224: f7fd fe78 bl 8003f18 <HAL_RCC_GetPCLK1Freq> 8006228: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 800622a: 68fa ldr r2, [r7, #12] 800622c: 4613 mov r3, r2 800622e: 009b lsls r3, r3, #2 8006230: 4413 add r3, r2 8006232: 009a lsls r2, r3, #2 8006234: 441a add r2, r3 8006236: 687b ldr r3, [r7, #4] 8006238: 685b ldr r3, [r3, #4] 800623a: 009b lsls r3, r3, #2 800623c: fbb2 f3f3 udiv r3, r2, r3 8006240: 4a22 ldr r2, [pc, #136] ; (80062cc <UART_SetConfig+0x118>) 8006242: fba2 2303 umull r2, r3, r2, r3 8006246: 095b lsrs r3, r3, #5 8006248: 0119 lsls r1, r3, #4 800624a: 68fa ldr r2, [r7, #12] 800624c: 4613 mov r3, r2 800624e: 009b lsls r3, r3, #2 8006250: 4413 add r3, r2 8006252: 009a lsls r2, r3, #2 8006254: 441a add r2, r3 8006256: 687b ldr r3, [r7, #4] 8006258: 685b ldr r3, [r3, #4] 800625a: 009b lsls r3, r3, #2 800625c: fbb2 f2f3 udiv r2, r2, r3 8006260: 4b1a ldr r3, [pc, #104] ; (80062cc <UART_SetConfig+0x118>) 8006262: fba3 0302 umull r0, r3, r3, r2 8006266: 095b lsrs r3, r3, #5 8006268: 2064 movs r0, #100 ; 0x64 800626a: fb00 f303 mul.w r3, r0, r3 800626e: 1ad3 subs r3, r2, r3 8006270: 011b lsls r3, r3, #4 8006272: 3332 adds r3, #50 ; 0x32 8006274: 4a15 ldr r2, [pc, #84] ; (80062cc <UART_SetConfig+0x118>) 8006276: fba2 2303 umull r2, r3, r2, r3 800627a: 095b lsrs r3, r3, #5 800627c: f003 03f0 and.w r3, r3, #240 ; 0xf0 8006280: 4419 add r1, r3 8006282: 68fa ldr r2, [r7, #12] 8006284: 4613 mov r3, r2 8006286: 009b lsls r3, r3, #2 8006288: 4413 add r3, r2 800628a: 009a lsls r2, r3, #2 800628c: 441a add r2, r3 800628e: 687b ldr r3, [r7, #4] 8006290: 685b ldr r3, [r3, #4] 8006292: 009b lsls r3, r3, #2 8006294: fbb2 f2f3 udiv r2, r2, r3 8006298: 4b0c ldr r3, [pc, #48] ; (80062cc <UART_SetConfig+0x118>) 800629a: fba3 0302 umull r0, r3, r3, r2 800629e: 095b lsrs r3, r3, #5 80062a0: 2064 movs r0, #100 ; 0x64 80062a2: fb00 f303 mul.w r3, r0, r3 80062a6: 1ad3 subs r3, r2, r3 80062a8: 011b lsls r3, r3, #4 80062aa: 3332 adds r3, #50 ; 0x32 80062ac: 4a07 ldr r2, [pc, #28] ; (80062cc <UART_SetConfig+0x118>) 80062ae: fba2 2303 umull r2, r3, r2, r3 80062b2: 095b lsrs r3, r3, #5 80062b4: f003 020f and.w r2, r3, #15 80062b8: 687b ldr r3, [r7, #4] 80062ba: 681b ldr r3, [r3, #0] 80062bc: 440a add r2, r1 80062be: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 80062c0: bf00 nop 80062c2: 3710 adds r7, #16 80062c4: 46bd mov sp, r7 80062c6: bd80 pop {r7, pc} 80062c8: 40013800 .word 0x40013800 80062cc: 51eb851f .word 0x51eb851f 080062d0 <SPI1_Send>: //------------------------------------------------------------- void SPI1_Send (uint8_t *dt, uint16_t cnt) { 80062d0: b580 push {r7, lr} 80062d2: b082 sub sp, #8 80062d4: af00 add r7, sp, #0 80062d6: 6078 str r0, [r7, #4] 80062d8: 460b mov r3, r1 80062da: 807b strh r3, [r7, #2] HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); 80062dc: 887a ldrh r2, [r7, #2] 80062de: f241 3388 movw r3, #5000 ; 0x1388 80062e2: 6879 ldr r1, [r7, #4] 80062e4: 4803 ldr r0, [pc, #12] ; (80062f4 <SPI1_Send+0x24>) 80062e6: f7fe f857 bl 8004398 <HAL_SPI_Transmit> } 80062ea: bf00 nop 80062ec: 3708 adds r7, #8 80062ee: 46bd mov sp, r7 80062f0: bd80 pop {r7, pc} 80062f2: bf00 nop 80062f4: 2000064c .word 0x2000064c 080062f8 <SPI1_Recv>: //------------------------------------------------------------- void SPI1_Recv (uint8_t *dt, uint16_t cnt) { 80062f8: b580 push {r7, lr} 80062fa: b082 sub sp, #8 80062fc: af00 add r7, sp, #0 80062fe: 6078 str r0, [r7, #4] 8006300: 460b mov r3, r1 8006302: 807b strh r3, [r7, #2] HAL_SPI_Receive (&hspi1, dt, cnt, 5000); 8006304: 887a ldrh r2, [r7, #2] 8006306: f241 3388 movw r3, #5000 ; 0x1388 800630a: 6879 ldr r1, [r7, #4] 800630c: 4803 ldr r0, [pc, #12] ; (800631c <SPI1_Recv+0x24>) 800630e: f7fe f97f bl 8004610 <HAL_SPI_Receive> } 8006312: bf00 nop 8006314: 3708 adds r7, #8 8006316: 46bd mov sp, r7 8006318: bd80 pop {r7, pc} 800631a: bf00 nop 800631c: 2000064c .word 0x2000064c 08006320 <W25_Reset>: //------------------------------------------------------------- void W25_Reset (void) { 8006320: b580 push {r7, lr} 8006322: af00 add r7, sp, #0 cs_set(); 8006324: 2200 movs r2, #0 8006326: 2110 movs r1, #16 8006328: 4809 ldr r0, [pc, #36] ; (8006350 <W25_Reset+0x30>) 800632a: f7fd f9d8 bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_ENABLE_RESET; 800632e: 4b09 ldr r3, [pc, #36] ; (8006354 <W25_Reset+0x34>) 8006330: 2266 movs r2, #102 ; 0x66 8006332: 701a strb r2, [r3, #0] buf[1] = W25_RESET; 8006334: 4b07 ldr r3, [pc, #28] ; (8006354 <W25_Reset+0x34>) 8006336: 2299 movs r2, #153 ; 0x99 8006338: 705a strb r2, [r3, #1] SPI1_Send(buf, 2); 800633a: 2102 movs r1, #2 800633c: 4805 ldr r0, [pc, #20] ; (8006354 <W25_Reset+0x34>) 800633e: f7ff ffc7 bl 80062d0 <SPI1_Send> cs_reset(); 8006342: 2201 movs r2, #1 8006344: 2110 movs r1, #16 8006346: 4802 ldr r0, [pc, #8] ; (8006350 <W25_Reset+0x30>) 8006348: f7fd f9c9 bl 80036de <HAL_GPIO_WritePin> } 800634c: bf00 nop 800634e: bd80 pop {r7, pc} 8006350: 40010800 .word 0x40010800 8006354: 20000a50 .word 0x20000a50 08006358 <W25_Write_Enable>: strcat(str_info,str1); sprintf(str1,"Capacity: %u KB\n",(unsigned int)w25_info.NumKB); strcat(str_info,str1); }//------------------------------------------------------------- void W25_Write_Enable(void) { 8006358: b580 push {r7, lr} 800635a: af00 add r7, sp, #0 cs_set(); 800635c: 2200 movs r2, #0 800635e: 2110 movs r1, #16 8006360: 4808 ldr r0, [pc, #32] ; (8006384 <W25_Write_Enable+0x2c>) 8006362: f7fd f9bc bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_WRITE_ENABLE; 8006366: 4b08 ldr r3, [pc, #32] ; (8006388 <W25_Write_Enable+0x30>) 8006368: 2206 movs r2, #6 800636a: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 800636c: 2101 movs r1, #1 800636e: 4806 ldr r0, [pc, #24] ; (8006388 <W25_Write_Enable+0x30>) 8006370: f7ff ffae bl 80062d0 <SPI1_Send> cs_reset(); 8006374: 2201 movs r2, #1 8006376: 2110 movs r1, #16 8006378: 4802 ldr r0, [pc, #8] ; (8006384 <W25_Write_Enable+0x2c>) 800637a: f7fd f9b0 bl 80036de <HAL_GPIO_WritePin> } 800637e: bf00 nop 8006380: bd80 pop {r7, pc} 8006382: bf00 nop 8006384: 40010800 .word 0x40010800 8006388: 20000a50 .word 0x20000a50 0800638c <W25_Write_Disable>: //------------------------------------------------------------- void W25_Write_Disable(void) { 800638c: b580 push {r7, lr} 800638e: af00 add r7, sp, #0 cs_set(); 8006390: 2200 movs r2, #0 8006392: 2110 movs r1, #16 8006394: 4808 ldr r0, [pc, #32] ; (80063b8 <W25_Write_Disable+0x2c>) 8006396: f7fd f9a2 bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_WRITE_DISABLE; 800639a: 4b08 ldr r3, [pc, #32] ; (80063bc <W25_Write_Disable+0x30>) 800639c: 2204 movs r2, #4 800639e: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 80063a0: 2101 movs r1, #1 80063a2: 4806 ldr r0, [pc, #24] ; (80063bc <W25_Write_Disable+0x30>) 80063a4: f7ff ff94 bl 80062d0 <SPI1_Send> cs_reset(); 80063a8: 2201 movs r2, #1 80063aa: 2110 movs r1, #16 80063ac: 4802 ldr r0, [pc, #8] ; (80063b8 <W25_Write_Disable+0x2c>) 80063ae: f7fd f996 bl 80036de <HAL_GPIO_WritePin> } 80063b2: bf00 nop 80063b4: bd80 pop {r7, pc} 80063b6: bf00 nop 80063b8: 40010800 .word 0x40010800 80063bc: 20000a50 .word 0x20000a50 080063c0 <W25_Set_Block_Protect>: //------------------------------------------------------------- void W25_Set_Block_Protect(uint8_t val) { 80063c0: b480 push {r7} 80063c2: b083 sub sp, #12 80063c4: af00 add r7, sp, #0 80063c6: 4603 mov r3, r0 80063c8: 71fb strb r3, [r7, #7] buf[0] = W25_WRITE_STATUS_1; buf[1] = ((val & 0x0F) << 2); cs_set(); SPI1_Send(buf, 2); cs_reset();*/ } 80063ca: bf00 nop 80063cc: 370c adds r7, #12 80063ce: 46bd mov sp, r7 80063d0: bc80 pop {r7} 80063d2: 4770 bx lr 080063d4 <W25_Wait_Write_End>: //------------------------------------------------------------- void W25_Wait_Write_End(void) { 80063d4: b580 push {r7, lr} 80063d6: af00 add r7, sp, #0 HAL_Delay(1); 80063d8: 2001 movs r0, #1 80063da: f7fc f92b bl 8002634 <HAL_Delay> cs_set(); 80063de: 2200 movs r2, #0 80063e0: 2110 movs r1, #16 80063e2: 4812 ldr r0, [pc, #72] ; (800642c <W25_Wait_Write_End+0x58>) 80063e4: f7fd f97b bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_READ_STATUS_1; 80063e8: 4b11 ldr r3, [pc, #68] ; (8006430 <W25_Wait_Write_End+0x5c>) 80063ea: 2205 movs r2, #5 80063ec: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 80063ee: 2101 movs r1, #1 80063f0: 480f ldr r0, [pc, #60] ; (8006430 <W25_Wait_Write_End+0x5c>) 80063f2: f7ff ff6d bl 80062d0 <SPI1_Send> do{ SPI1_Recv(buf,1); 80063f6: 2101 movs r1, #1 80063f8: 480d ldr r0, [pc, #52] ; (8006430 <W25_Wait_Write_End+0x5c>) 80063fa: f7ff ff7d bl 80062f8 <SPI1_Recv> w25_info.StatusRegister1 = buf[0]; 80063fe: 4b0c ldr r3, [pc, #48] ; (8006430 <W25_Wait_Write_End+0x5c>) 8006400: 781a ldrb r2, [r3, #0] 8006402: 4b0c ldr r3, [pc, #48] ; (8006434 <W25_Wait_Write_End+0x60>) 8006404: f883 2020 strb.w r2, [r3, #32] HAL_Delay(1); 8006408: 2001 movs r0, #1 800640a: f7fc f913 bl 8002634 <HAL_Delay> } while((w25_info.StatusRegister1 & 0x01) == 0x01); 800640e: 4b09 ldr r3, [pc, #36] ; (8006434 <W25_Wait_Write_End+0x60>) 8006410: f893 3020 ldrb.w r3, [r3, #32] 8006414: f003 0301 and.w r3, r3, #1 8006418: 2b00 cmp r3, #0 800641a: d1ec bne.n 80063f6 <W25_Wait_Write_End+0x22> cs_reset(); 800641c: 2201 movs r2, #1 800641e: 2110 movs r1, #16 8006420: 4802 ldr r0, [pc, #8] ; (800642c <W25_Wait_Write_End+0x58>) 8006422: f7fd f95c bl 80036de <HAL_GPIO_WritePin> } 8006426: bf00 nop 8006428: bd80 pop {r7, pc} 800642a: bf00 nop 800642c: 40010800 .word 0x40010800 8006430: 20000a50 .word 0x20000a50 8006434: 20000a0c .word 0x20000a0c 08006438 <W25_Erase_Chip>: W25_Write_Disable(); W25_Set_Block_Protect(0x0F); } //------------------------------------------------------------- void W25_Erase_Chip(void) { 8006438: b580 push {r7, lr} 800643a: af00 add r7, sp, #0 W25_Wait_Write_End(); 800643c: f7ff ffca bl 80063d4 <W25_Wait_Write_End> W25_Write_Enable(); 8006440: f7ff ff8a bl 8006358 <W25_Write_Enable> cs_set(); 8006444: 2200 movs r2, #0 8006446: 2110 movs r1, #16 8006448: 480b ldr r0, [pc, #44] ; (8006478 <W25_Erase_Chip+0x40>) 800644a: f7fd f948 bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_CHIP_ERASE; 800644e: 4b0b ldr r3, [pc, #44] ; (800647c <W25_Erase_Chip+0x44>) 8006450: 22c7 movs r2, #199 ; 0xc7 8006452: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 8006454: 2101 movs r1, #1 8006456: 4809 ldr r0, [pc, #36] ; (800647c <W25_Erase_Chip+0x44>) 8006458: f7ff ff3a bl 80062d0 <SPI1_Send> cs_reset(); 800645c: 2201 movs r2, #1 800645e: 2110 movs r1, #16 8006460: 4805 ldr r0, [pc, #20] ; (8006478 <W25_Erase_Chip+0x40>) 8006462: f7fd f93c bl 80036de <HAL_GPIO_WritePin> W25_Wait_Write_End(); 8006466: f7ff ffb5 bl 80063d4 <W25_Wait_Write_End> W25_Write_Disable(); 800646a: f7ff ff8f bl 800638c <W25_Write_Disable> W25_Set_Block_Protect(0x0F); 800646e: 200f movs r0, #15 8006470: f7ff ffa6 bl 80063c0 <W25_Set_Block_Protect> } 8006474: bf00 nop 8006476: bd80 pop {r7, pc} 8006478: 40010800 .word 0x40010800 800647c: 20000a50 .word 0x20000a50 08006480 <W25_Write_Page>: W25_Write_Disable(); W25_Set_Block_Protect(0x0F); } //------------------------------------------------------------- void W25_Write_Page(uint8_t* data, uint32_t page_addr, uint32_t offset, uint32_t sz) { 8006480: b580 push {r7, lr} 8006482: b084 sub sp, #16 8006484: af00 add r7, sp, #0 8006486: 60f8 str r0, [r7, #12] 8006488: 60b9 str r1, [r7, #8] 800648a: 607a str r2, [r7, #4] 800648c: 603b str r3, [r7, #0] if(sz > w25_info.PageSize) 800648e: 4b39 ldr r3, [pc, #228] ; (8006574 <W25_Write_Page+0xf4>) 8006490: 881b ldrh r3, [r3, #0] 8006492: 461a mov r2, r3 8006494: 683b ldr r3, [r7, #0] 8006496: 4293 cmp r3, r2 8006498: d902 bls.n 80064a0 <W25_Write_Page+0x20> sz=w25_info.PageSize; 800649a: 4b36 ldr r3, [pc, #216] ; (8006574 <W25_Write_Page+0xf4>) 800649c: 881b ldrh r3, [r3, #0] 800649e: 603b str r3, [r7, #0] if((offset+sz) > w25_info.PageSize) 80064a0: 687a ldr r2, [r7, #4] 80064a2: 683b ldr r3, [r7, #0] 80064a4: 4413 add r3, r2 80064a6: 4a33 ldr r2, [pc, #204] ; (8006574 <W25_Write_Page+0xf4>) 80064a8: 8812 ldrh r2, [r2, #0] 80064aa: 4293 cmp r3, r2 80064ac: d905 bls.n 80064ba <W25_Write_Page+0x3a> sz = w25_info.PageSize - offset; 80064ae: 4b31 ldr r3, [pc, #196] ; (8006574 <W25_Write_Page+0xf4>) 80064b0: 881b ldrh r3, [r3, #0] 80064b2: 461a mov r2, r3 80064b4: 687b ldr r3, [r7, #4] 80064b6: 1ad3 subs r3, r2, r3 80064b8: 603b str r3, [r7, #0] page_addr = page_addr * w25_info.PageSize + offset; 80064ba: 4b2e ldr r3, [pc, #184] ; (8006574 <W25_Write_Page+0xf4>) 80064bc: 881b ldrh r3, [r3, #0] 80064be: 461a mov r2, r3 80064c0: 68bb ldr r3, [r7, #8] 80064c2: fb02 f303 mul.w r3, r2, r3 80064c6: 687a ldr r2, [r7, #4] 80064c8: 4413 add r3, r2 80064ca: 60bb str r3, [r7, #8] W25_Wait_Write_End(); 80064cc: f7ff ff82 bl 80063d4 <W25_Wait_Write_End> W25_Set_Block_Protect(0x00); 80064d0: 2000 movs r0, #0 80064d2: f7ff ff75 bl 80063c0 <W25_Set_Block_Protect> W25_Write_Enable(); 80064d6: f7ff ff3f bl 8006358 <W25_Write_Enable> cs_set(); 80064da: 2200 movs r2, #0 80064dc: 2110 movs r1, #16 80064de: 4826 ldr r0, [pc, #152] ; (8006578 <W25_Write_Page+0xf8>) 80064e0: f7fd f8fd bl 80036de <HAL_GPIO_WritePin> buf[0] = W25_PAGE_PROGRAMM; 80064e4: 4b25 ldr r3, [pc, #148] ; (800657c <W25_Write_Page+0xfc>) 80064e6: 2202 movs r2, #2 80064e8: 701a strb r2, [r3, #0] if(w25_info.high_cap) 80064ea: 4b22 ldr r3, [pc, #136] ; (8006574 <W25_Write_Page+0xf4>) 80064ec: 7fdb ldrb r3, [r3, #31] 80064ee: 2b00 cmp r3, #0 80064f0: d017 beq.n 8006522 <W25_Write_Page+0xa2> { buf[1] = (page_addr >> 24) & 0xFF; 80064f2: 68bb ldr r3, [r7, #8] 80064f4: 0e1b lsrs r3, r3, #24 80064f6: b2da uxtb r2, r3 80064f8: 4b20 ldr r3, [pc, #128] ; (800657c <W25_Write_Page+0xfc>) 80064fa: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 16) & 0xFF; 80064fc: 68bb ldr r3, [r7, #8] 80064fe: 0c1b lsrs r3, r3, #16 8006500: b2da uxtb r2, r3 8006502: 4b1e ldr r3, [pc, #120] ; (800657c <W25_Write_Page+0xfc>) 8006504: 709a strb r2, [r3, #2] buf[3] = (page_addr >> 8) & 0xFF; 8006506: 68bb ldr r3, [r7, #8] 8006508: 0a1b lsrs r3, r3, #8 800650a: b2da uxtb r2, r3 800650c: 4b1b ldr r3, [pc, #108] ; (800657c <W25_Write_Page+0xfc>) 800650e: 70da strb r2, [r3, #3] buf[4] = page_addr & 0xFF; 8006510: 68bb ldr r3, [r7, #8] 8006512: b2da uxtb r2, r3 8006514: 4b19 ldr r3, [pc, #100] ; (800657c <W25_Write_Page+0xfc>) 8006516: 711a strb r2, [r3, #4] SPI1_Send(buf, 5); 8006518: 2105 movs r1, #5 800651a: 4818 ldr r0, [pc, #96] ; (800657c <W25_Write_Page+0xfc>) 800651c: f7ff fed8 bl 80062d0 <SPI1_Send> 8006520: e011 b.n 8006546 <W25_Write_Page+0xc6> } else { buf[1] = (page_addr >> 16) & 0xFF; 8006522: 68bb ldr r3, [r7, #8] 8006524: 0c1b lsrs r3, r3, #16 8006526: b2da uxtb r2, r3 8006528: 4b14 ldr r3, [pc, #80] ; (800657c <W25_Write_Page+0xfc>) 800652a: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 8) & 0xFF; 800652c: 68bb ldr r3, [r7, #8] 800652e: 0a1b lsrs r3, r3, #8 8006530: b2da uxtb r2, r3 8006532: 4b12 ldr r3, [pc, #72] ; (800657c <W25_Write_Page+0xfc>) 8006534: 709a strb r2, [r3, #2] buf[3] = page_addr & 0xFF; 8006536: 68bb ldr r3, [r7, #8] 8006538: b2da uxtb r2, r3 800653a: 4b10 ldr r3, [pc, #64] ; (800657c <W25_Write_Page+0xfc>) 800653c: 70da strb r2, [r3, #3] SPI1_Send(buf, 4); 800653e: 2104 movs r1, #4 8006540: 480e ldr r0, [pc, #56] ; (800657c <W25_Write_Page+0xfc>) 8006542: f7ff fec5 bl 80062d0 <SPI1_Send> } SPI1_Send(data, sz); 8006546: 683b ldr r3, [r7, #0] 8006548: b29b uxth r3, r3 800654a: 4619 mov r1, r3 800654c: 68f8 ldr r0, [r7, #12] 800654e: f7ff febf bl 80062d0 <SPI1_Send> cs_reset(); 8006552: 2201 movs r2, #1 8006554: 2110 movs r1, #16 8006556: 4808 ldr r0, [pc, #32] ; (8006578 <W25_Write_Page+0xf8>) 8006558: f7fd f8c1 bl 80036de <HAL_GPIO_WritePin> W25_Wait_Write_End(); 800655c: f7ff ff3a bl 80063d4 <W25_Wait_Write_End> W25_Write_Disable(); 8006560: f7ff ff14 bl 800638c <W25_Write_Disable> W25_Set_Block_Protect(0x0F); 8006564: 200f movs r0, #15 8006566: f7ff ff2b bl 80063c0 <W25_Set_Block_Protect> } 800656a: bf00 nop 800656c: 3710 adds r7, #16 800656e: 46bd mov sp, r7 8006570: bd80 pop {r7, pc} 8006572: bf00 nop 8006574: 20000a0c .word 0x20000a0c 8006578: 40010800 .word 0x40010800 800657c: 20000a50 .word 0x20000a50 08006580 <W25_Read_ID>: SPI1_Recv(data, sz); cs_reset(); } //------------------------------------------------------------- uint32_t W25_Read_ID(void) { 8006580: b580 push {r7, lr} 8006582: b082 sub sp, #8 8006584: af00 add r7, sp, #0 uint8_t dt[4]; buf[0] = W25_GET_JEDEC_ID; 8006586: 4b10 ldr r3, [pc, #64] ; (80065c8 <W25_Read_ID+0x48>) 8006588: 229f movs r2, #159 ; 0x9f 800658a: 701a strb r2, [r3, #0] cs_set(); 800658c: 2200 movs r2, #0 800658e: 2110 movs r1, #16 8006590: 480e ldr r0, [pc, #56] ; (80065cc <W25_Read_ID+0x4c>) 8006592: f7fd f8a4 bl 80036de <HAL_GPIO_WritePin> SPI1_Send(buf, 1); 8006596: 2101 movs r1, #1 8006598: 480b ldr r0, [pc, #44] ; (80065c8 <W25_Read_ID+0x48>) 800659a: f7ff fe99 bl 80062d0 <SPI1_Send> SPI1_Recv(dt,3); 800659e: 1d3b adds r3, r7, #4 80065a0: 2103 movs r1, #3 80065a2: 4618 mov r0, r3 80065a4: f7ff fea8 bl 80062f8 <SPI1_Recv> cs_reset(); 80065a8: 2201 movs r2, #1 80065aa: 2110 movs r1, #16 80065ac: 4807 ldr r0, [pc, #28] ; (80065cc <W25_Read_ID+0x4c>) 80065ae: f7fd f896 bl 80036de <HAL_GPIO_WritePin> return (dt[0] << 16) | (dt[1] << 8) | dt[2]; 80065b2: 793b ldrb r3, [r7, #4] 80065b4: 041a lsls r2, r3, #16 80065b6: 797b ldrb r3, [r7, #5] 80065b8: 021b lsls r3, r3, #8 80065ba: 4313 orrs r3, r2 80065bc: 79ba ldrb r2, [r7, #6] 80065be: 4313 orrs r3, r2 } 80065c0: 4618 mov r0, r3 80065c2: 3708 adds r7, #8 80065c4: 46bd mov sp, r7 80065c6: bd80 pop {r7, pc} 80065c8: 20000a50 .word 0x20000a50 80065cc: 40010800 .word 0x40010800 080065d0 <W25_Ini>: //------------------------------------------------------------- void W25_Ini(char need_report) { 80065d0: b580 push {r7, lr} 80065d2: b084 sub sp, #16 80065d4: af00 add r7, sp, #0 80065d6: 4603 mov r3, r0 80065d8: 71fb strb r3, [r7, #7] unsigned int id = W25_Read_ID(); 80065da: f7ff ffd1 bl 8006580 <W25_Read_ID> 80065de: 60f8 str r0, [r7, #12] HAL_Delay(100); 80065e0: 2064 movs r0, #100 ; 0x64 80065e2: f7fc f827 bl 8002634 <HAL_Delay> W25_Reset(); 80065e6: f7ff fe9b bl 8006320 <W25_Reset> HAL_Delay(100); 80065ea: 2064 movs r0, #100 ; 0x64 80065ec: f7fc f822 bl 8002634 <HAL_Delay> if (need_report) 80065f0: 79fb ldrb r3, [r7, #7] 80065f2: 2b00 cmp r3, #0 80065f4: d016 beq.n 8006624 <W25_Ini+0x54> { HAL_UART_Transmit(&huart1,(uint8_t*)"\r\n",2,0x1000); 80065f6: f44f 5380 mov.w r3, #4096 ; 0x1000 80065fa: 2202 movs r2, #2 80065fc: 4950 ldr r1, [pc, #320] ; (8006740 <W25_Ini+0x170>) 80065fe: 4851 ldr r0, [pc, #324] ; (8006744 <W25_Ini+0x174>) 8006600: f7ff fcfb bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"ID:0x%X\r\n",id); 8006604: 68fa ldr r2, [r7, #12] 8006606: 4950 ldr r1, [pc, #320] ; (8006748 <W25_Ini+0x178>) 8006608: 4850 ldr r0, [pc, #320] ; (800674c <W25_Ini+0x17c>) 800660a: f000 fa43 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 800660e: 484f ldr r0, [pc, #316] ; (800674c <W25_Ini+0x17c>) 8006610: f7f9 fd9c bl 800014c <strlen> 8006614: 4603 mov r3, r0 8006616: b29a uxth r2, r3 8006618: f44f 5380 mov.w r3, #4096 ; 0x1000 800661c: 494b ldr r1, [pc, #300] ; (800674c <W25_Ini+0x17c>) 800661e: 4849 ldr r0, [pc, #292] ; (8006744 <W25_Ini+0x174>) 8006620: f7ff fceb bl 8005ffa <HAL_UART_Transmit> } id &= 0x0000ffff; 8006624: 68fb ldr r3, [r7, #12] 8006626: b29b uxth r3, r3 8006628: 60fb str r3, [r7, #12] w25_info.high_cap = 0; 800662a: 4b49 ldr r3, [pc, #292] ; (8006750 <W25_Ini+0x180>) 800662c: 2200 movs r2, #0 800662e: 77da strb r2, [r3, #31] switch(id) 8006630: 68fb ldr r3, [r7, #12] 8006632: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 8006636: 3b11 subs r3, #17 8006638: 2b09 cmp r3, #9 800663a: d870 bhi.n 800671e <W25_Ini+0x14e> 800663c: a201 add r2, pc, #4 ; (adr r2, 8006644 <W25_Ini+0x74>) 800663e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006642: bf00 nop 8006644: 0800670f .word 0x0800670f 8006648: 080066ff .word 0x080066ff 800664c: 080066ef .word 0x080066ef 8006650: 080066df .word 0x080066df 8006654: 080066cf .word 0x080066cf 8006658: 080066bf .word 0x080066bf 800665c: 080066af .word 0x080066af 8006660: 0800669d .word 0x0800669d 8006664: 08006685 .word 0x08006685 8006668: 0800666d .word 0x0800666d { case 0x401A: w25_info.high_cap=1; 800666c: 4b38 ldr r3, [pc, #224] ; (8006750 <W25_Ini+0x180>) 800666e: 2201 movs r2, #1 8006670: 77da strb r2, [r3, #31] w25_info.BlockCount=1024; 8006672: 4b37 ldr r3, [pc, #220] ; (8006750 <W25_Ini+0x180>) 8006674: f44f 6280 mov.w r2, #1024 ; 0x400 8006678: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q512\r\n"); 800667a: 4936 ldr r1, [pc, #216] ; (8006754 <W25_Ini+0x184>) 800667c: 4833 ldr r0, [pc, #204] ; (800674c <W25_Ini+0x17c>) 800667e: f000 fa09 bl 8006a94 <siprintf> break; 8006682: e07d b.n 8006780 <W25_Ini+0x1b0> case 0x4019: w25_info.high_cap=1; 8006684: 4b32 ldr r3, [pc, #200] ; (8006750 <W25_Ini+0x180>) 8006686: 2201 movs r2, #1 8006688: 77da strb r2, [r3, #31] w25_info.BlockCount=512; 800668a: 4b31 ldr r3, [pc, #196] ; (8006750 <W25_Ini+0x180>) 800668c: f44f 7200 mov.w r2, #512 ; 0x200 8006690: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q256\r\n"); 8006692: 4931 ldr r1, [pc, #196] ; (8006758 <W25_Ini+0x188>) 8006694: 482d ldr r0, [pc, #180] ; (800674c <W25_Ini+0x17c>) 8006696: f000 f9fd bl 8006a94 <siprintf> break; 800669a: e071 b.n 8006780 <W25_Ini+0x1b0> case 0x4018: w25_info.BlockCount=256; 800669c: 4b2c ldr r3, [pc, #176] ; (8006750 <W25_Ini+0x180>) 800669e: f44f 7280 mov.w r2, #256 ; 0x100 80066a2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q128\r\n"); 80066a4: 492d ldr r1, [pc, #180] ; (800675c <W25_Ini+0x18c>) 80066a6: 4829 ldr r0, [pc, #164] ; (800674c <W25_Ini+0x17c>) 80066a8: f000 f9f4 bl 8006a94 <siprintf> break; 80066ac: e068 b.n 8006780 <W25_Ini+0x1b0> case 0x4017: w25_info.BlockCount=128; 80066ae: 4b28 ldr r3, [pc, #160] ; (8006750 <W25_Ini+0x180>) 80066b0: 2280 movs r2, #128 ; 0x80 80066b2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q64\r\n"); 80066b4: 492a ldr r1, [pc, #168] ; (8006760 <W25_Ini+0x190>) 80066b6: 4825 ldr r0, [pc, #148] ; (800674c <W25_Ini+0x17c>) 80066b8: f000 f9ec bl 8006a94 <siprintf> break; 80066bc: e060 b.n 8006780 <W25_Ini+0x1b0> case 0x4016: w25_info.BlockCount=64; 80066be: 4b24 ldr r3, [pc, #144] ; (8006750 <W25_Ini+0x180>) 80066c0: 2240 movs r2, #64 ; 0x40 80066c2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q32\r\n"); 80066c4: 4927 ldr r1, [pc, #156] ; (8006764 <W25_Ini+0x194>) 80066c6: 4821 ldr r0, [pc, #132] ; (800674c <W25_Ini+0x17c>) 80066c8: f000 f9e4 bl 8006a94 <siprintf> break; 80066cc: e058 b.n 8006780 <W25_Ini+0x1b0> case 0x4015: w25_info.BlockCount=32; 80066ce: 4b20 ldr r3, [pc, #128] ; (8006750 <W25_Ini+0x180>) 80066d0: 2220 movs r2, #32 80066d2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q16\r\n"); 80066d4: 4924 ldr r1, [pc, #144] ; (8006768 <W25_Ini+0x198>) 80066d6: 481d ldr r0, [pc, #116] ; (800674c <W25_Ini+0x17c>) 80066d8: f000 f9dc bl 8006a94 <siprintf> break; 80066dc: e050 b.n 8006780 <W25_Ini+0x1b0> case 0x4014: w25_info.BlockCount=16; 80066de: 4b1c ldr r3, [pc, #112] ; (8006750 <W25_Ini+0x180>) 80066e0: 2210 movs r2, #16 80066e2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q80\r\n"); 80066e4: 4921 ldr r1, [pc, #132] ; (800676c <W25_Ini+0x19c>) 80066e6: 4819 ldr r0, [pc, #100] ; (800674c <W25_Ini+0x17c>) 80066e8: f000 f9d4 bl 8006a94 <siprintf> break; 80066ec: e048 b.n 8006780 <W25_Ini+0x1b0> case 0x4013: w25_info.BlockCount=8; 80066ee: 4b18 ldr r3, [pc, #96] ; (8006750 <W25_Ini+0x180>) 80066f0: 2208 movs r2, #8 80066f2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q40\r\n"); 80066f4: 491e ldr r1, [pc, #120] ; (8006770 <W25_Ini+0x1a0>) 80066f6: 4815 ldr r0, [pc, #84] ; (800674c <W25_Ini+0x17c>) 80066f8: f000 f9cc bl 8006a94 <siprintf> break; 80066fc: e040 b.n 8006780 <W25_Ini+0x1b0> case 0x4012: w25_info.BlockCount=4; 80066fe: 4b14 ldr r3, [pc, #80] ; (8006750 <W25_Ini+0x180>) 8006700: 2204 movs r2, #4 8006702: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q20\r\n"); 8006704: 491b ldr r1, [pc, #108] ; (8006774 <W25_Ini+0x1a4>) 8006706: 4811 ldr r0, [pc, #68] ; (800674c <W25_Ini+0x17c>) 8006708: f000 f9c4 bl 8006a94 <siprintf> break; 800670c: e038 b.n 8006780 <W25_Ini+0x1b0> case 0x4011: w25_info.BlockCount=2; 800670e: 4b10 ldr r3, [pc, #64] ; (8006750 <W25_Ini+0x180>) 8006710: 2202 movs r2, #2 8006712: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q10\r\n"); 8006714: 4918 ldr r1, [pc, #96] ; (8006778 <W25_Ini+0x1a8>) 8006716: 480d ldr r0, [pc, #52] ; (800674c <W25_Ini+0x17c>) 8006718: f000 f9bc bl 8006a94 <siprintf> break; 800671c: e030 b.n 8006780 <W25_Ini+0x1b0> default: sprintf(str1,"w25qxx Unknown ID\r\n"); 800671e: 4917 ldr r1, [pc, #92] ; (800677c <W25_Ini+0x1ac>) 8006720: 480a ldr r0, [pc, #40] ; (800674c <W25_Ini+0x17c>) 8006722: f000 f9b7 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8006726: 4809 ldr r0, [pc, #36] ; (800674c <W25_Ini+0x17c>) 8006728: f7f9 fd10 bl 800014c <strlen> 800672c: 4603 mov r3, r0 800672e: b29a uxth r2, r3 8006730: f44f 5380 mov.w r3, #4096 ; 0x1000 8006734: 4905 ldr r1, [pc, #20] ; (800674c <W25_Ini+0x17c>) 8006736: 4803 ldr r0, [pc, #12] ; (8006744 <W25_Ini+0x174>) 8006738: f7ff fc5f bl 8005ffa <HAL_UART_Transmit> return; 800673c: e0d6 b.n 80068ec <W25_Ini+0x31c> 800673e: bf00 nop 8006740: 08007548 .word 0x08007548 8006744: 2000078c .word 0x2000078c 8006748: 0800754c .word 0x0800754c 800674c: 20000a30 .word 0x20000a30 8006750: 20000a0c .word 0x20000a0c 8006754: 08007558 .word 0x08007558 8006758: 08007570 .word 0x08007570 800675c: 08007588 .word 0x08007588 8006760: 080075a0 .word 0x080075a0 8006764: 080075b8 .word 0x080075b8 8006768: 080075d0 .word 0x080075d0 800676c: 080075e8 .word 0x080075e8 8006770: 08007600 .word 0x08007600 8006774: 08007618 .word 0x08007618 8006778: 08007630 .word 0x08007630 800677c: 08007648 .word 0x08007648 } if (need_report) 8006780: 79fb ldrb r3, [r7, #7] 8006782: 2b00 cmp r3, #0 8006784: d00a beq.n 800679c <W25_Ini+0x1cc> { HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8006786: 485b ldr r0, [pc, #364] ; (80068f4 <W25_Ini+0x324>) 8006788: f7f9 fce0 bl 800014c <strlen> 800678c: 4603 mov r3, r0 800678e: b29a uxth r2, r3 8006790: f44f 5380 mov.w r3, #4096 ; 0x1000 8006794: 4957 ldr r1, [pc, #348] ; (80068f4 <W25_Ini+0x324>) 8006796: 4858 ldr r0, [pc, #352] ; (80068f8 <W25_Ini+0x328>) 8006798: f7ff fc2f bl 8005ffa <HAL_UART_Transmit> } w25_info.PageSize=256; 800679c: 4b57 ldr r3, [pc, #348] ; (80068fc <W25_Ini+0x32c>) 800679e: f44f 7280 mov.w r2, #256 ; 0x100 80067a2: 801a strh r2, [r3, #0] w25_info.SectorSize=0x1000; 80067a4: 4b55 ldr r3, [pc, #340] ; (80068fc <W25_Ini+0x32c>) 80067a6: f44f 5280 mov.w r2, #4096 ; 0x1000 80067aa: 609a str r2, [r3, #8] w25_info.SectorCount=w25_info.BlockCount*16; 80067ac: 4b53 ldr r3, [pc, #332] ; (80068fc <W25_Ini+0x32c>) 80067ae: 695b ldr r3, [r3, #20] 80067b0: 011b lsls r3, r3, #4 80067b2: 4a52 ldr r2, [pc, #328] ; (80068fc <W25_Ini+0x32c>) 80067b4: 60d3 str r3, [r2, #12] w25_info.PageCount=(w25_info.SectorCount*w25_info.SectorSize)/w25_info.PageSize; 80067b6: 4b51 ldr r3, [pc, #324] ; (80068fc <W25_Ini+0x32c>) 80067b8: 68db ldr r3, [r3, #12] 80067ba: 4a50 ldr r2, [pc, #320] ; (80068fc <W25_Ini+0x32c>) 80067bc: 6892 ldr r2, [r2, #8] 80067be: fb02 f303 mul.w r3, r2, r3 80067c2: 4a4e ldr r2, [pc, #312] ; (80068fc <W25_Ini+0x32c>) 80067c4: 8812 ldrh r2, [r2, #0] 80067c6: fbb3 f3f2 udiv r3, r3, r2 80067ca: 4a4c ldr r2, [pc, #304] ; (80068fc <W25_Ini+0x32c>) 80067cc: 6053 str r3, [r2, #4] w25_info.BlockSize=w25_info.SectorSize*16; 80067ce: 4b4b ldr r3, [pc, #300] ; (80068fc <W25_Ini+0x32c>) 80067d0: 689b ldr r3, [r3, #8] 80067d2: 011b lsls r3, r3, #4 80067d4: 4a49 ldr r2, [pc, #292] ; (80068fc <W25_Ini+0x32c>) 80067d6: 6113 str r3, [r2, #16] w25_info.NumKB=(w25_info.SectorCount*w25_info.SectorSize)/1024; 80067d8: 4b48 ldr r3, [pc, #288] ; (80068fc <W25_Ini+0x32c>) 80067da: 68db ldr r3, [r3, #12] 80067dc: 4a47 ldr r2, [pc, #284] ; (80068fc <W25_Ini+0x32c>) 80067de: 6892 ldr r2, [r2, #8] 80067e0: fb02 f303 mul.w r3, r2, r3 80067e4: 0a9b lsrs r3, r3, #10 80067e6: 4a45 ldr r2, [pc, #276] ; (80068fc <W25_Ini+0x32c>) 80067e8: 6193 str r3, [r2, #24] if (need_report) 80067ea: 79fb ldrb r3, [r7, #7] 80067ec: 2b00 cmp r3, #0 80067ee: d07d beq.n 80068ec <W25_Ini+0x31c> { sprintf(str1,"Page Size: %d Bytes\r\n",(unsigned int)w25_info.PageSize);HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80067f0: 4b42 ldr r3, [pc, #264] ; (80068fc <W25_Ini+0x32c>) 80067f2: 881b ldrh r3, [r3, #0] 80067f4: 461a mov r2, r3 80067f6: 4942 ldr r1, [pc, #264] ; (8006900 <W25_Ini+0x330>) 80067f8: 483e ldr r0, [pc, #248] ; (80068f4 <W25_Ini+0x324>) 80067fa: f000 f94b bl 8006a94 <siprintf> 80067fe: 483d ldr r0, [pc, #244] ; (80068f4 <W25_Ini+0x324>) 8006800: f7f9 fca4 bl 800014c <strlen> 8006804: 4603 mov r3, r0 8006806: b29a uxth r2, r3 8006808: f44f 5380 mov.w r3, #4096 ; 0x1000 800680c: 4939 ldr r1, [pc, #228] ; (80068f4 <W25_Ini+0x324>) 800680e: 483a ldr r0, [pc, #232] ; (80068f8 <W25_Ini+0x328>) 8006810: f7ff fbf3 bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Page Count: %u\r\n",(unsigned int)w25_info.PageCount); 8006814: 4b39 ldr r3, [pc, #228] ; (80068fc <W25_Ini+0x32c>) 8006816: 685b ldr r3, [r3, #4] 8006818: 461a mov r2, r3 800681a: 493a ldr r1, [pc, #232] ; (8006904 <W25_Ini+0x334>) 800681c: 4835 ldr r0, [pc, #212] ; (80068f4 <W25_Ini+0x324>) 800681e: f000 f939 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8006822: 4834 ldr r0, [pc, #208] ; (80068f4 <W25_Ini+0x324>) 8006824: f7f9 fc92 bl 800014c <strlen> 8006828: 4603 mov r3, r0 800682a: b29a uxth r2, r3 800682c: f44f 5380 mov.w r3, #4096 ; 0x1000 8006830: 4930 ldr r1, [pc, #192] ; (80068f4 <W25_Ini+0x324>) 8006832: 4831 ldr r0, [pc, #196] ; (80068f8 <W25_Ini+0x328>) 8006834: f7ff fbe1 bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Sector Size: %u Bytes\r\n",(unsigned int)w25_info.SectorSize); 8006838: 4b30 ldr r3, [pc, #192] ; (80068fc <W25_Ini+0x32c>) 800683a: 689b ldr r3, [r3, #8] 800683c: 461a mov r2, r3 800683e: 4932 ldr r1, [pc, #200] ; (8006908 <W25_Ini+0x338>) 8006840: 482c ldr r0, [pc, #176] ; (80068f4 <W25_Ini+0x324>) 8006842: f000 f927 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8006846: 482b ldr r0, [pc, #172] ; (80068f4 <W25_Ini+0x324>) 8006848: f7f9 fc80 bl 800014c <strlen> 800684c: 4603 mov r3, r0 800684e: b29a uxth r2, r3 8006850: f44f 5380 mov.w r3, #4096 ; 0x1000 8006854: 4927 ldr r1, [pc, #156] ; (80068f4 <W25_Ini+0x324>) 8006856: 4828 ldr r0, [pc, #160] ; (80068f8 <W25_Ini+0x328>) 8006858: f7ff fbcf bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Sector Count: %u\r\n",(unsigned int)w25_info.SectorCount); 800685c: 4b27 ldr r3, [pc, #156] ; (80068fc <W25_Ini+0x32c>) 800685e: 68db ldr r3, [r3, #12] 8006860: 461a mov r2, r3 8006862: 492a ldr r1, [pc, #168] ; (800690c <W25_Ini+0x33c>) 8006864: 4823 ldr r0, [pc, #140] ; (80068f4 <W25_Ini+0x324>) 8006866: f000 f915 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 800686a: 4822 ldr r0, [pc, #136] ; (80068f4 <W25_Ini+0x324>) 800686c: f7f9 fc6e bl 800014c <strlen> 8006870: 4603 mov r3, r0 8006872: b29a uxth r2, r3 8006874: f44f 5380 mov.w r3, #4096 ; 0x1000 8006878: 491e ldr r1, [pc, #120] ; (80068f4 <W25_Ini+0x324>) 800687a: 481f ldr r0, [pc, #124] ; (80068f8 <W25_Ini+0x328>) 800687c: f7ff fbbd bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Block Size: %u Bytes\r\n",(unsigned int)w25_info.BlockSize); 8006880: 4b1e ldr r3, [pc, #120] ; (80068fc <W25_Ini+0x32c>) 8006882: 691b ldr r3, [r3, #16] 8006884: 461a mov r2, r3 8006886: 4922 ldr r1, [pc, #136] ; (8006910 <W25_Ini+0x340>) 8006888: 481a ldr r0, [pc, #104] ; (80068f4 <W25_Ini+0x324>) 800688a: f000 f903 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 800688e: 4819 ldr r0, [pc, #100] ; (80068f4 <W25_Ini+0x324>) 8006890: f7f9 fc5c bl 800014c <strlen> 8006894: 4603 mov r3, r0 8006896: b29a uxth r2, r3 8006898: f44f 5380 mov.w r3, #4096 ; 0x1000 800689c: 4915 ldr r1, [pc, #84] ; (80068f4 <W25_Ini+0x324>) 800689e: 4816 ldr r0, [pc, #88] ; (80068f8 <W25_Ini+0x328>) 80068a0: f7ff fbab bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Block Count: %u\r\n",(unsigned int)w25_info.BlockCount); 80068a4: 4b15 ldr r3, [pc, #84] ; (80068fc <W25_Ini+0x32c>) 80068a6: 695b ldr r3, [r3, #20] 80068a8: 461a mov r2, r3 80068aa: 491a ldr r1, [pc, #104] ; (8006914 <W25_Ini+0x344>) 80068ac: 4811 ldr r0, [pc, #68] ; (80068f4 <W25_Ini+0x324>) 80068ae: f000 f8f1 bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80068b2: 4810 ldr r0, [pc, #64] ; (80068f4 <W25_Ini+0x324>) 80068b4: f7f9 fc4a bl 800014c <strlen> 80068b8: 4603 mov r3, r0 80068ba: b29a uxth r2, r3 80068bc: f44f 5380 mov.w r3, #4096 ; 0x1000 80068c0: 490c ldr r1, [pc, #48] ; (80068f4 <W25_Ini+0x324>) 80068c2: 480d ldr r0, [pc, #52] ; (80068f8 <W25_Ini+0x328>) 80068c4: f7ff fb99 bl 8005ffa <HAL_UART_Transmit> sprintf(str1,"Capacity: %u KB\r\n",(unsigned int)w25_info.NumKB); 80068c8: 4b0c ldr r3, [pc, #48] ; (80068fc <W25_Ini+0x32c>) 80068ca: 699b ldr r3, [r3, #24] 80068cc: 461a mov r2, r3 80068ce: 4912 ldr r1, [pc, #72] ; (8006918 <W25_Ini+0x348>) 80068d0: 4808 ldr r0, [pc, #32] ; (80068f4 <W25_Ini+0x324>) 80068d2: f000 f8df bl 8006a94 <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80068d6: 4807 ldr r0, [pc, #28] ; (80068f4 <W25_Ini+0x324>) 80068d8: f7f9 fc38 bl 800014c <strlen> 80068dc: 4603 mov r3, r0 80068de: b29a uxth r2, r3 80068e0: f44f 5380 mov.w r3, #4096 ; 0x1000 80068e4: 4903 ldr r1, [pc, #12] ; (80068f4 <W25_Ini+0x324>) 80068e6: 4804 ldr r0, [pc, #16] ; (80068f8 <W25_Ini+0x328>) 80068e8: f7ff fb87 bl 8005ffa <HAL_UART_Transmit> } } 80068ec: 3710 adds r7, #16 80068ee: 46bd mov sp, r7 80068f0: bd80 pop {r7, pc} 80068f2: bf00 nop 80068f4: 20000a30 .word 0x20000a30 80068f8: 2000078c .word 0x2000078c 80068fc: 20000a0c .word 0x20000a0c 8006900: 0800765c .word 0x0800765c 8006904: 08007674 .word 0x08007674 8006908: 08007688 .word 0x08007688 800690c: 080074f4 .word 0x080074f4 8006910: 080076a0 .word 0x080076a0 8006914: 080076b8 .word 0x080076b8 8006918: 080076cc .word 0x080076cc 0800691c <W25_Read_Page>: //------------------------------------------------------------- void W25_Read_Page(uint8_t* data, uint32_t page_addr, uint32_t offset, uint32_t sz) { 800691c: b580 push {r7, lr} 800691e: b084 sub sp, #16 8006920: af00 add r7, sp, #0 8006922: 60f8 str r0, [r7, #12] 8006924: 60b9 str r1, [r7, #8] 8006926: 607a str r2, [r7, #4] 8006928: 603b str r3, [r7, #0] if(sz > w25_info.PageSize) 800692a: 4b37 ldr r3, [pc, #220] ; (8006a08 <W25_Read_Page+0xec>) 800692c: 881b ldrh r3, [r3, #0] 800692e: 461a mov r2, r3 8006930: 683b ldr r3, [r7, #0] 8006932: 4293 cmp r3, r2 8006934: d902 bls.n 800693c <W25_Read_Page+0x20> sz=w25_info.PageSize; 8006936: 4b34 ldr r3, [pc, #208] ; (8006a08 <W25_Read_Page+0xec>) 8006938: 881b ldrh r3, [r3, #0] 800693a: 603b str r3, [r7, #0] if((offset+sz) > w25_info.PageSize) 800693c: 687a ldr r2, [r7, #4] 800693e: 683b ldr r3, [r7, #0] 8006940: 4413 add r3, r2 8006942: 4a31 ldr r2, [pc, #196] ; (8006a08 <W25_Read_Page+0xec>) 8006944: 8812 ldrh r2, [r2, #0] 8006946: 4293 cmp r3, r2 8006948: d905 bls.n 8006956 <W25_Read_Page+0x3a> sz = w25_info.PageSize - offset; 800694a: 4b2f ldr r3, [pc, #188] ; (8006a08 <W25_Read_Page+0xec>) 800694c: 881b ldrh r3, [r3, #0] 800694e: 461a mov r2, r3 8006950: 687b ldr r3, [r7, #4] 8006952: 1ad3 subs r3, r2, r3 8006954: 603b str r3, [r7, #0] page_addr = page_addr * w25_info.PageSize + offset; 8006956: 4b2c ldr r3, [pc, #176] ; (8006a08 <W25_Read_Page+0xec>) 8006958: 881b ldrh r3, [r3, #0] 800695a: 461a mov r2, r3 800695c: 68bb ldr r3, [r7, #8] 800695e: fb02 f303 mul.w r3, r2, r3 8006962: 687a ldr r2, [r7, #4] 8006964: 4413 add r3, r2 8006966: 60bb str r3, [r7, #8] buf[0] = W25_FAST_READ; 8006968: 4b28 ldr r3, [pc, #160] ; (8006a0c <W25_Read_Page+0xf0>) 800696a: 220b movs r2, #11 800696c: 701a strb r2, [r3, #0] if(w25_info.high_cap) 800696e: 4b26 ldr r3, [pc, #152] ; (8006a08 <W25_Read_Page+0xec>) 8006970: 7fdb ldrb r3, [r3, #31] 8006972: 2b00 cmp r3, #0 8006974: d01f beq.n 80069b6 <W25_Read_Page+0x9a> { buf[1] = (page_addr >> 24) & 0xFF; 8006976: 68bb ldr r3, [r7, #8] 8006978: 0e1b lsrs r3, r3, #24 800697a: b2da uxtb r2, r3 800697c: 4b23 ldr r3, [pc, #140] ; (8006a0c <W25_Read_Page+0xf0>) 800697e: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 16) & 0xFF; 8006980: 68bb ldr r3, [r7, #8] 8006982: 0c1b lsrs r3, r3, #16 8006984: b2da uxtb r2, r3 8006986: 4b21 ldr r3, [pc, #132] ; (8006a0c <W25_Read_Page+0xf0>) 8006988: 709a strb r2, [r3, #2] buf[3] = (page_addr >> 8) & 0xFF; 800698a: 68bb ldr r3, [r7, #8] 800698c: 0a1b lsrs r3, r3, #8 800698e: b2da uxtb r2, r3 8006990: 4b1e ldr r3, [pc, #120] ; (8006a0c <W25_Read_Page+0xf0>) 8006992: 70da strb r2, [r3, #3] buf[4] = page_addr & 0xFF; 8006994: 68bb ldr r3, [r7, #8] 8006996: b2da uxtb r2, r3 8006998: 4b1c ldr r3, [pc, #112] ; (8006a0c <W25_Read_Page+0xf0>) 800699a: 711a strb r2, [r3, #4] buf[5] = 0; 800699c: 4b1b ldr r3, [pc, #108] ; (8006a0c <W25_Read_Page+0xf0>) 800699e: 2200 movs r2, #0 80069a0: 715a strb r2, [r3, #5] cs_set(); 80069a2: 2200 movs r2, #0 80069a4: 2110 movs r1, #16 80069a6: 481a ldr r0, [pc, #104] ; (8006a10 <W25_Read_Page+0xf4>) 80069a8: f7fc fe99 bl 80036de <HAL_GPIO_WritePin> SPI1_Send(buf, 6); 80069ac: 2106 movs r1, #6 80069ae: 4817 ldr r0, [pc, #92] ; (8006a0c <W25_Read_Page+0xf0>) 80069b0: f7ff fc8e bl 80062d0 <SPI1_Send> 80069b4: e019 b.n 80069ea <W25_Read_Page+0xce> } else { buf[1] = (page_addr >> 16) & 0xFF; 80069b6: 68bb ldr r3, [r7, #8] 80069b8: 0c1b lsrs r3, r3, #16 80069ba: b2da uxtb r2, r3 80069bc: 4b13 ldr r3, [pc, #76] ; (8006a0c <W25_Read_Page+0xf0>) 80069be: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 8) & 0xFF; 80069c0: 68bb ldr r3, [r7, #8] 80069c2: 0a1b lsrs r3, r3, #8 80069c4: b2da uxtb r2, r3 80069c6: 4b11 ldr r3, [pc, #68] ; (8006a0c <W25_Read_Page+0xf0>) 80069c8: 709a strb r2, [r3, #2] buf[3] = page_addr & 0xFF; 80069ca: 68bb ldr r3, [r7, #8] 80069cc: b2da uxtb r2, r3 80069ce: 4b0f ldr r3, [pc, #60] ; (8006a0c <W25_Read_Page+0xf0>) 80069d0: 70da strb r2, [r3, #3] buf[4] = 0; 80069d2: 4b0e ldr r3, [pc, #56] ; (8006a0c <W25_Read_Page+0xf0>) 80069d4: 2200 movs r2, #0 80069d6: 711a strb r2, [r3, #4] cs_set(); 80069d8: 2200 movs r2, #0 80069da: 2110 movs r1, #16 80069dc: 480c ldr r0, [pc, #48] ; (8006a10 <W25_Read_Page+0xf4>) 80069de: f7fc fe7e bl 80036de <HAL_GPIO_WritePin> SPI1_Send(buf, 5); 80069e2: 2105 movs r1, #5 80069e4: 4809 ldr r0, [pc, #36] ; (8006a0c <W25_Read_Page+0xf0>) 80069e6: f7ff fc73 bl 80062d0 <SPI1_Send> } SPI1_Recv(data, sz); 80069ea: 683b ldr r3, [r7, #0] 80069ec: b29b uxth r3, r3 80069ee: 4619 mov r1, r3 80069f0: 68f8 ldr r0, [r7, #12] 80069f2: f7ff fc81 bl 80062f8 <SPI1_Recv> cs_reset(); 80069f6: 2201 movs r2, #1 80069f8: 2110 movs r1, #16 80069fa: 4805 ldr r0, [pc, #20] ; (8006a10 <W25_Read_Page+0xf4>) 80069fc: f7fc fe6f bl 80036de <HAL_GPIO_WritePin> } 8006a00: bf00 nop 8006a02: 3710 adds r7, #16 8006a04: 46bd mov sp, r7 8006a06: bd80 pop {r7, pc} 8006a08: 20000a0c .word 0x20000a0c 8006a0c: 20000a50 .word 0x20000a50 8006a10: 40010800 .word 0x40010800 08006a14 <__errno>: 8006a14: 4b01 ldr r3, [pc, #4] ; (8006a1c <__errno+0x8>) 8006a16: 6818 ldr r0, [r3, #0] 8006a18: 4770 bx lr 8006a1a: bf00 nop 8006a1c: 20000064 .word 0x20000064 08006a20 <__libc_init_array>: 8006a20: b570 push {r4, r5, r6, lr} 8006a22: 2600 movs r6, #0 8006a24: 4d0c ldr r5, [pc, #48] ; (8006a58 <__libc_init_array+0x38>) 8006a26: 4c0d ldr r4, [pc, #52] ; (8006a5c <__libc_init_array+0x3c>) 8006a28: 1b64 subs r4, r4, r5 8006a2a: 10a4 asrs r4, r4, #2 8006a2c: 42a6 cmp r6, r4 8006a2e: d109 bne.n 8006a44 <__libc_init_array+0x24> 8006a30: f000 fc9c bl 800736c <_init> 8006a34: 2600 movs r6, #0 8006a36: 4d0a ldr r5, [pc, #40] ; (8006a60 <__libc_init_array+0x40>) 8006a38: 4c0a ldr r4, [pc, #40] ; (8006a64 <__libc_init_array+0x44>) 8006a3a: 1b64 subs r4, r4, r5 8006a3c: 10a4 asrs r4, r4, #2 8006a3e: 42a6 cmp r6, r4 8006a40: d105 bne.n 8006a4e <__libc_init_array+0x2e> 8006a42: bd70 pop {r4, r5, r6, pc} 8006a44: f855 3b04 ldr.w r3, [r5], #4 8006a48: 4798 blx r3 8006a4a: 3601 adds r6, #1 8006a4c: e7ee b.n 8006a2c <__libc_init_array+0xc> 8006a4e: f855 3b04 ldr.w r3, [r5], #4 8006a52: 4798 blx r3 8006a54: 3601 adds r6, #1 8006a56: e7f2 b.n 8006a3e <__libc_init_array+0x1e> 8006a58: 08007b2c .word 0x08007b2c 8006a5c: 08007b2c .word 0x08007b2c 8006a60: 08007b2c .word 0x08007b2c 8006a64: 08007b30 .word 0x08007b30 08006a68 <memcpy>: 8006a68: 440a add r2, r1 8006a6a: 4291 cmp r1, r2 8006a6c: f100 33ff add.w r3, r0, #4294967295 8006a70: d100 bne.n 8006a74 <memcpy+0xc> 8006a72: 4770 bx lr 8006a74: b510 push {r4, lr} 8006a76: f811 4b01 ldrb.w r4, [r1], #1 8006a7a: 4291 cmp r1, r2 8006a7c: f803 4f01 strb.w r4, [r3, #1]! 8006a80: d1f9 bne.n 8006a76 <memcpy+0xe> 8006a82: bd10 pop {r4, pc} 08006a84 <memset>: 8006a84: 4603 mov r3, r0 8006a86: 4402 add r2, r0 8006a88: 4293 cmp r3, r2 8006a8a: d100 bne.n 8006a8e <memset+0xa> 8006a8c: 4770 bx lr 8006a8e: f803 1b01 strb.w r1, [r3], #1 8006a92: e7f9 b.n 8006a88 <memset+0x4> 08006a94 <siprintf>: 8006a94: b40e push {r1, r2, r3} 8006a96: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 8006a9a: b500 push {lr} 8006a9c: b09c sub sp, #112 ; 0x70 8006a9e: ab1d add r3, sp, #116 ; 0x74 8006aa0: 9002 str r0, [sp, #8] 8006aa2: 9006 str r0, [sp, #24] 8006aa4: 9107 str r1, [sp, #28] 8006aa6: 9104 str r1, [sp, #16] 8006aa8: 4808 ldr r0, [pc, #32] ; (8006acc <siprintf+0x38>) 8006aaa: 4909 ldr r1, [pc, #36] ; (8006ad0 <siprintf+0x3c>) 8006aac: f853 2b04 ldr.w r2, [r3], #4 8006ab0: 9105 str r1, [sp, #20] 8006ab2: 6800 ldr r0, [r0, #0] 8006ab4: a902 add r1, sp, #8 8006ab6: 9301 str r3, [sp, #4] 8006ab8: f000 f868 bl 8006b8c <_svfiprintf_r> 8006abc: 2200 movs r2, #0 8006abe: 9b02 ldr r3, [sp, #8] 8006ac0: 701a strb r2, [r3, #0] 8006ac2: b01c add sp, #112 ; 0x70 8006ac4: f85d eb04 ldr.w lr, [sp], #4 8006ac8: b003 add sp, #12 8006aca: 4770 bx lr 8006acc: 20000064 .word 0x20000064 8006ad0: ffff0208 .word 0xffff0208 08006ad4 <__ssputs_r>: 8006ad4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006ad8: 688e ldr r6, [r1, #8] 8006ada: 4682 mov sl, r0 8006adc: 429e cmp r6, r3 8006ade: 460c mov r4, r1 8006ae0: 4690 mov r8, r2 8006ae2: 461f mov r7, r3 8006ae4: d838 bhi.n 8006b58 <__ssputs_r+0x84> 8006ae6: 898a ldrh r2, [r1, #12] 8006ae8: f412 6f90 tst.w r2, #1152 ; 0x480 8006aec: d032 beq.n 8006b54 <__ssputs_r+0x80> 8006aee: 6825 ldr r5, [r4, #0] 8006af0: 6909 ldr r1, [r1, #16] 8006af2: 3301 adds r3, #1 8006af4: eba5 0901 sub.w r9, r5, r1 8006af8: 6965 ldr r5, [r4, #20] 8006afa: 444b add r3, r9 8006afc: eb05 0545 add.w r5, r5, r5, lsl #1 8006b00: eb05 75d5 add.w r5, r5, r5, lsr #31 8006b04: 106d asrs r5, r5, #1 8006b06: 429d cmp r5, r3 8006b08: bf38 it cc 8006b0a: 461d movcc r5, r3 8006b0c: 0553 lsls r3, r2, #21 8006b0e: d531 bpl.n 8006b74 <__ssputs_r+0xa0> 8006b10: 4629 mov r1, r5 8006b12: f000 fb61 bl 80071d8 <_malloc_r> 8006b16: 4606 mov r6, r0 8006b18: b950 cbnz r0, 8006b30 <__ssputs_r+0x5c> 8006b1a: 230c movs r3, #12 8006b1c: f04f 30ff mov.w r0, #4294967295 8006b20: f8ca 3000 str.w r3, [sl] 8006b24: 89a3 ldrh r3, [r4, #12] 8006b26: f043 0340 orr.w r3, r3, #64 ; 0x40 8006b2a: 81a3 strh r3, [r4, #12] 8006b2c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006b30: 464a mov r2, r9 8006b32: 6921 ldr r1, [r4, #16] 8006b34: f7ff ff98 bl 8006a68 <memcpy> 8006b38: 89a3 ldrh r3, [r4, #12] 8006b3a: f423 6390 bic.w r3, r3, #1152 ; 0x480 8006b3e: f043 0380 orr.w r3, r3, #128 ; 0x80 8006b42: 81a3 strh r3, [r4, #12] 8006b44: 6126 str r6, [r4, #16] 8006b46: 444e add r6, r9 8006b48: 6026 str r6, [r4, #0] 8006b4a: 463e mov r6, r7 8006b4c: 6165 str r5, [r4, #20] 8006b4e: eba5 0509 sub.w r5, r5, r9 8006b52: 60a5 str r5, [r4, #8] 8006b54: 42be cmp r6, r7 8006b56: d900 bls.n 8006b5a <__ssputs_r+0x86> 8006b58: 463e mov r6, r7 8006b5a: 4632 mov r2, r6 8006b5c: 4641 mov r1, r8 8006b5e: 6820 ldr r0, [r4, #0] 8006b60: f000 fab8 bl 80070d4 <memmove> 8006b64: 68a3 ldr r3, [r4, #8] 8006b66: 2000 movs r0, #0 8006b68: 1b9b subs r3, r3, r6 8006b6a: 60a3 str r3, [r4, #8] 8006b6c: 6823 ldr r3, [r4, #0] 8006b6e: 4433 add r3, r6 8006b70: 6023 str r3, [r4, #0] 8006b72: e7db b.n 8006b2c <__ssputs_r+0x58> 8006b74: 462a mov r2, r5 8006b76: f000 fba3 bl 80072c0 <_realloc_r> 8006b7a: 4606 mov r6, r0 8006b7c: 2800 cmp r0, #0 8006b7e: d1e1 bne.n 8006b44 <__ssputs_r+0x70> 8006b80: 4650 mov r0, sl 8006b82: 6921 ldr r1, [r4, #16] 8006b84: f000 fac0 bl 8007108 <_free_r> 8006b88: e7c7 b.n 8006b1a <__ssputs_r+0x46> ... 08006b8c <_svfiprintf_r>: 8006b8c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006b90: 4698 mov r8, r3 8006b92: 898b ldrh r3, [r1, #12] 8006b94: 4607 mov r7, r0 8006b96: 061b lsls r3, r3, #24 8006b98: 460d mov r5, r1 8006b9a: 4614 mov r4, r2 8006b9c: b09d sub sp, #116 ; 0x74 8006b9e: d50e bpl.n 8006bbe <_svfiprintf_r+0x32> 8006ba0: 690b ldr r3, [r1, #16] 8006ba2: b963 cbnz r3, 8006bbe <_svfiprintf_r+0x32> 8006ba4: 2140 movs r1, #64 ; 0x40 8006ba6: f000 fb17 bl 80071d8 <_malloc_r> 8006baa: 6028 str r0, [r5, #0] 8006bac: 6128 str r0, [r5, #16] 8006bae: b920 cbnz r0, 8006bba <_svfiprintf_r+0x2e> 8006bb0: 230c movs r3, #12 8006bb2: 603b str r3, [r7, #0] 8006bb4: f04f 30ff mov.w r0, #4294967295 8006bb8: e0d1 b.n 8006d5e <_svfiprintf_r+0x1d2> 8006bba: 2340 movs r3, #64 ; 0x40 8006bbc: 616b str r3, [r5, #20] 8006bbe: 2300 movs r3, #0 8006bc0: 9309 str r3, [sp, #36] ; 0x24 8006bc2: 2320 movs r3, #32 8006bc4: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8006bc8: 2330 movs r3, #48 ; 0x30 8006bca: f04f 0901 mov.w r9, #1 8006bce: f8cd 800c str.w r8, [sp, #12] 8006bd2: f8df 81a4 ldr.w r8, [pc, #420] ; 8006d78 <_svfiprintf_r+0x1ec> 8006bd6: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8006bda: 4623 mov r3, r4 8006bdc: 469a mov sl, r3 8006bde: f813 2b01 ldrb.w r2, [r3], #1 8006be2: b10a cbz r2, 8006be8 <_svfiprintf_r+0x5c> 8006be4: 2a25 cmp r2, #37 ; 0x25 8006be6: d1f9 bne.n 8006bdc <_svfiprintf_r+0x50> 8006be8: ebba 0b04 subs.w fp, sl, r4 8006bec: d00b beq.n 8006c06 <_svfiprintf_r+0x7a> 8006bee: 465b mov r3, fp 8006bf0: 4622 mov r2, r4 8006bf2: 4629 mov r1, r5 8006bf4: 4638 mov r0, r7 8006bf6: f7ff ff6d bl 8006ad4 <__ssputs_r> 8006bfa: 3001 adds r0, #1 8006bfc: f000 80aa beq.w 8006d54 <_svfiprintf_r+0x1c8> 8006c00: 9a09 ldr r2, [sp, #36] ; 0x24 8006c02: 445a add r2, fp 8006c04: 9209 str r2, [sp, #36] ; 0x24 8006c06: f89a 3000 ldrb.w r3, [sl] 8006c0a: 2b00 cmp r3, #0 8006c0c: f000 80a2 beq.w 8006d54 <_svfiprintf_r+0x1c8> 8006c10: 2300 movs r3, #0 8006c12: f04f 32ff mov.w r2, #4294967295 8006c16: e9cd 2305 strd r2, r3, [sp, #20] 8006c1a: f10a 0a01 add.w sl, sl, #1 8006c1e: 9304 str r3, [sp, #16] 8006c20: 9307 str r3, [sp, #28] 8006c22: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8006c26: 931a str r3, [sp, #104] ; 0x68 8006c28: 4654 mov r4, sl 8006c2a: 2205 movs r2, #5 8006c2c: f814 1b01 ldrb.w r1, [r4], #1 8006c30: 4851 ldr r0, [pc, #324] ; (8006d78 <_svfiprintf_r+0x1ec>) 8006c32: f000 fa41 bl 80070b8 <memchr> 8006c36: 9a04 ldr r2, [sp, #16] 8006c38: b9d8 cbnz r0, 8006c72 <_svfiprintf_r+0xe6> 8006c3a: 06d0 lsls r0, r2, #27 8006c3c: bf44 itt mi 8006c3e: 2320 movmi r3, #32 8006c40: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8006c44: 0711 lsls r1, r2, #28 8006c46: bf44 itt mi 8006c48: 232b movmi r3, #43 ; 0x2b 8006c4a: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8006c4e: f89a 3000 ldrb.w r3, [sl] 8006c52: 2b2a cmp r3, #42 ; 0x2a 8006c54: d015 beq.n 8006c82 <_svfiprintf_r+0xf6> 8006c56: 4654 mov r4, sl 8006c58: 2000 movs r0, #0 8006c5a: f04f 0c0a mov.w ip, #10 8006c5e: 9a07 ldr r2, [sp, #28] 8006c60: 4621 mov r1, r4 8006c62: f811 3b01 ldrb.w r3, [r1], #1 8006c66: 3b30 subs r3, #48 ; 0x30 8006c68: 2b09 cmp r3, #9 8006c6a: d94e bls.n 8006d0a <_svfiprintf_r+0x17e> 8006c6c: b1b0 cbz r0, 8006c9c <_svfiprintf_r+0x110> 8006c6e: 9207 str r2, [sp, #28] 8006c70: e014 b.n 8006c9c <_svfiprintf_r+0x110> 8006c72: eba0 0308 sub.w r3, r0, r8 8006c76: fa09 f303 lsl.w r3, r9, r3 8006c7a: 4313 orrs r3, r2 8006c7c: 46a2 mov sl, r4 8006c7e: 9304 str r3, [sp, #16] 8006c80: e7d2 b.n 8006c28 <_svfiprintf_r+0x9c> 8006c82: 9b03 ldr r3, [sp, #12] 8006c84: 1d19 adds r1, r3, #4 8006c86: 681b ldr r3, [r3, #0] 8006c88: 9103 str r1, [sp, #12] 8006c8a: 2b00 cmp r3, #0 8006c8c: bfbb ittet lt 8006c8e: 425b neglt r3, r3 8006c90: f042 0202 orrlt.w r2, r2, #2 8006c94: 9307 strge r3, [sp, #28] 8006c96: 9307 strlt r3, [sp, #28] 8006c98: bfb8 it lt 8006c9a: 9204 strlt r2, [sp, #16] 8006c9c: 7823 ldrb r3, [r4, #0] 8006c9e: 2b2e cmp r3, #46 ; 0x2e 8006ca0: d10c bne.n 8006cbc <_svfiprintf_r+0x130> 8006ca2: 7863 ldrb r3, [r4, #1] 8006ca4: 2b2a cmp r3, #42 ; 0x2a 8006ca6: d135 bne.n 8006d14 <_svfiprintf_r+0x188> 8006ca8: 9b03 ldr r3, [sp, #12] 8006caa: 3402 adds r4, #2 8006cac: 1d1a adds r2, r3, #4 8006cae: 681b ldr r3, [r3, #0] 8006cb0: 9203 str r2, [sp, #12] 8006cb2: 2b00 cmp r3, #0 8006cb4: bfb8 it lt 8006cb6: f04f 33ff movlt.w r3, #4294967295 8006cba: 9305 str r3, [sp, #20] 8006cbc: f8df a0bc ldr.w sl, [pc, #188] ; 8006d7c <_svfiprintf_r+0x1f0> 8006cc0: 2203 movs r2, #3 8006cc2: 4650 mov r0, sl 8006cc4: 7821 ldrb r1, [r4, #0] 8006cc6: f000 f9f7 bl 80070b8 <memchr> 8006cca: b140 cbz r0, 8006cde <_svfiprintf_r+0x152> 8006ccc: 2340 movs r3, #64 ; 0x40 8006cce: eba0 000a sub.w r0, r0, sl 8006cd2: fa03 f000 lsl.w r0, r3, r0 8006cd6: 9b04 ldr r3, [sp, #16] 8006cd8: 3401 adds r4, #1 8006cda: 4303 orrs r3, r0 8006cdc: 9304 str r3, [sp, #16] 8006cde: f814 1b01 ldrb.w r1, [r4], #1 8006ce2: 2206 movs r2, #6 8006ce4: 4826 ldr r0, [pc, #152] ; (8006d80 <_svfiprintf_r+0x1f4>) 8006ce6: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8006cea: f000 f9e5 bl 80070b8 <memchr> 8006cee: 2800 cmp r0, #0 8006cf0: d038 beq.n 8006d64 <_svfiprintf_r+0x1d8> 8006cf2: 4b24 ldr r3, [pc, #144] ; (8006d84 <_svfiprintf_r+0x1f8>) 8006cf4: bb1b cbnz r3, 8006d3e <_svfiprintf_r+0x1b2> 8006cf6: 9b03 ldr r3, [sp, #12] 8006cf8: 3307 adds r3, #7 8006cfa: f023 0307 bic.w r3, r3, #7 8006cfe: 3308 adds r3, #8 8006d00: 9303 str r3, [sp, #12] 8006d02: 9b09 ldr r3, [sp, #36] ; 0x24 8006d04: 4433 add r3, r6 8006d06: 9309 str r3, [sp, #36] ; 0x24 8006d08: e767 b.n 8006bda <_svfiprintf_r+0x4e> 8006d0a: 460c mov r4, r1 8006d0c: 2001 movs r0, #1 8006d0e: fb0c 3202 mla r2, ip, r2, r3 8006d12: e7a5 b.n 8006c60 <_svfiprintf_r+0xd4> 8006d14: 2300 movs r3, #0 8006d16: f04f 0c0a mov.w ip, #10 8006d1a: 4619 mov r1, r3 8006d1c: 3401 adds r4, #1 8006d1e: 9305 str r3, [sp, #20] 8006d20: 4620 mov r0, r4 8006d22: f810 2b01 ldrb.w r2, [r0], #1 8006d26: 3a30 subs r2, #48 ; 0x30 8006d28: 2a09 cmp r2, #9 8006d2a: d903 bls.n 8006d34 <_svfiprintf_r+0x1a8> 8006d2c: 2b00 cmp r3, #0 8006d2e: d0c5 beq.n 8006cbc <_svfiprintf_r+0x130> 8006d30: 9105 str r1, [sp, #20] 8006d32: e7c3 b.n 8006cbc <_svfiprintf_r+0x130> 8006d34: 4604 mov r4, r0 8006d36: 2301 movs r3, #1 8006d38: fb0c 2101 mla r1, ip, r1, r2 8006d3c: e7f0 b.n 8006d20 <_svfiprintf_r+0x194> 8006d3e: ab03 add r3, sp, #12 8006d40: 9300 str r3, [sp, #0] 8006d42: 462a mov r2, r5 8006d44: 4638 mov r0, r7 8006d46: 4b10 ldr r3, [pc, #64] ; (8006d88 <_svfiprintf_r+0x1fc>) 8006d48: a904 add r1, sp, #16 8006d4a: f3af 8000 nop.w 8006d4e: 1c42 adds r2, r0, #1 8006d50: 4606 mov r6, r0 8006d52: d1d6 bne.n 8006d02 <_svfiprintf_r+0x176> 8006d54: 89ab ldrh r3, [r5, #12] 8006d56: 065b lsls r3, r3, #25 8006d58: f53f af2c bmi.w 8006bb4 <_svfiprintf_r+0x28> 8006d5c: 9809 ldr r0, [sp, #36] ; 0x24 8006d5e: b01d add sp, #116 ; 0x74 8006d60: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006d64: ab03 add r3, sp, #12 8006d66: 9300 str r3, [sp, #0] 8006d68: 462a mov r2, r5 8006d6a: 4638 mov r0, r7 8006d6c: 4b06 ldr r3, [pc, #24] ; (8006d88 <_svfiprintf_r+0x1fc>) 8006d6e: a904 add r1, sp, #16 8006d70: f000 f87c bl 8006e6c <_printf_i> 8006d74: e7eb b.n 8006d4e <_svfiprintf_r+0x1c2> 8006d76: bf00 nop 8006d78: 08007af8 .word 0x08007af8 8006d7c: 08007afe .word 0x08007afe 8006d80: 08007b02 .word 0x08007b02 8006d84: 00000000 .word 0x00000000 8006d88: 08006ad5 .word 0x08006ad5 08006d8c <_printf_common>: 8006d8c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006d90: 4616 mov r6, r2 8006d92: 4699 mov r9, r3 8006d94: 688a ldr r2, [r1, #8] 8006d96: 690b ldr r3, [r1, #16] 8006d98: 4607 mov r7, r0 8006d9a: 4293 cmp r3, r2 8006d9c: bfb8 it lt 8006d9e: 4613 movlt r3, r2 8006da0: 6033 str r3, [r6, #0] 8006da2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8006da6: 460c mov r4, r1 8006da8: f8dd 8020 ldr.w r8, [sp, #32] 8006dac: b10a cbz r2, 8006db2 <_printf_common+0x26> 8006dae: 3301 adds r3, #1 8006db0: 6033 str r3, [r6, #0] 8006db2: 6823 ldr r3, [r4, #0] 8006db4: 0699 lsls r1, r3, #26 8006db6: bf42 ittt mi 8006db8: 6833 ldrmi r3, [r6, #0] 8006dba: 3302 addmi r3, #2 8006dbc: 6033 strmi r3, [r6, #0] 8006dbe: 6825 ldr r5, [r4, #0] 8006dc0: f015 0506 ands.w r5, r5, #6 8006dc4: d106 bne.n 8006dd4 <_printf_common+0x48> 8006dc6: f104 0a19 add.w sl, r4, #25 8006dca: 68e3 ldr r3, [r4, #12] 8006dcc: 6832 ldr r2, [r6, #0] 8006dce: 1a9b subs r3, r3, r2 8006dd0: 42ab cmp r3, r5 8006dd2: dc28 bgt.n 8006e26 <_printf_common+0x9a> 8006dd4: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8006dd8: 1e13 subs r3, r2, #0 8006dda: 6822 ldr r2, [r4, #0] 8006ddc: bf18 it ne 8006dde: 2301 movne r3, #1 8006de0: 0692 lsls r2, r2, #26 8006de2: d42d bmi.n 8006e40 <_printf_common+0xb4> 8006de4: 4649 mov r1, r9 8006de6: 4638 mov r0, r7 8006de8: f104 0243 add.w r2, r4, #67 ; 0x43 8006dec: 47c0 blx r8 8006dee: 3001 adds r0, #1 8006df0: d020 beq.n 8006e34 <_printf_common+0xa8> 8006df2: 6823 ldr r3, [r4, #0] 8006df4: 68e5 ldr r5, [r4, #12] 8006df6: f003 0306 and.w r3, r3, #6 8006dfa: 2b04 cmp r3, #4 8006dfc: bf18 it ne 8006dfe: 2500 movne r5, #0 8006e00: 6832 ldr r2, [r6, #0] 8006e02: f04f 0600 mov.w r6, #0 8006e06: 68a3 ldr r3, [r4, #8] 8006e08: bf08 it eq 8006e0a: 1aad subeq r5, r5, r2 8006e0c: 6922 ldr r2, [r4, #16] 8006e0e: bf08 it eq 8006e10: ea25 75e5 biceq.w r5, r5, r5, asr #31 8006e14: 4293 cmp r3, r2 8006e16: bfc4 itt gt 8006e18: 1a9b subgt r3, r3, r2 8006e1a: 18ed addgt r5, r5, r3 8006e1c: 341a adds r4, #26 8006e1e: 42b5 cmp r5, r6 8006e20: d11a bne.n 8006e58 <_printf_common+0xcc> 8006e22: 2000 movs r0, #0 8006e24: e008 b.n 8006e38 <_printf_common+0xac> 8006e26: 2301 movs r3, #1 8006e28: 4652 mov r2, sl 8006e2a: 4649 mov r1, r9 8006e2c: 4638 mov r0, r7 8006e2e: 47c0 blx r8 8006e30: 3001 adds r0, #1 8006e32: d103 bne.n 8006e3c <_printf_common+0xb0> 8006e34: f04f 30ff mov.w r0, #4294967295 8006e38: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006e3c: 3501 adds r5, #1 8006e3e: e7c4 b.n 8006dca <_printf_common+0x3e> 8006e40: 2030 movs r0, #48 ; 0x30 8006e42: 18e1 adds r1, r4, r3 8006e44: f881 0043 strb.w r0, [r1, #67] ; 0x43 8006e48: 1c5a adds r2, r3, #1 8006e4a: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8006e4e: 4422 add r2, r4 8006e50: 3302 adds r3, #2 8006e52: f882 1043 strb.w r1, [r2, #67] ; 0x43 8006e56: e7c5 b.n 8006de4 <_printf_common+0x58> 8006e58: 2301 movs r3, #1 8006e5a: 4622 mov r2, r4 8006e5c: 4649 mov r1, r9 8006e5e: 4638 mov r0, r7 8006e60: 47c0 blx r8 8006e62: 3001 adds r0, #1 8006e64: d0e6 beq.n 8006e34 <_printf_common+0xa8> 8006e66: 3601 adds r6, #1 8006e68: e7d9 b.n 8006e1e <_printf_common+0x92> ... 08006e6c <_printf_i>: 8006e6c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8006e70: 7e0f ldrb r7, [r1, #24] 8006e72: 4691 mov r9, r2 8006e74: 2f78 cmp r7, #120 ; 0x78 8006e76: 4680 mov r8, r0 8006e78: 460c mov r4, r1 8006e7a: 469a mov sl, r3 8006e7c: 9d0c ldr r5, [sp, #48] ; 0x30 8006e7e: f101 0243 add.w r2, r1, #67 ; 0x43 8006e82: d807 bhi.n 8006e94 <_printf_i+0x28> 8006e84: 2f62 cmp r7, #98 ; 0x62 8006e86: d80a bhi.n 8006e9e <_printf_i+0x32> 8006e88: 2f00 cmp r7, #0 8006e8a: f000 80d9 beq.w 8007040 <_printf_i+0x1d4> 8006e8e: 2f58 cmp r7, #88 ; 0x58 8006e90: f000 80a4 beq.w 8006fdc <_printf_i+0x170> 8006e94: f104 0542 add.w r5, r4, #66 ; 0x42 8006e98: f884 7042 strb.w r7, [r4, #66] ; 0x42 8006e9c: e03a b.n 8006f14 <_printf_i+0xa8> 8006e9e: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8006ea2: 2b15 cmp r3, #21 8006ea4: d8f6 bhi.n 8006e94 <_printf_i+0x28> 8006ea6: a101 add r1, pc, #4 ; (adr r1, 8006eac <_printf_i+0x40>) 8006ea8: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8006eac: 08006f05 .word 0x08006f05 8006eb0: 08006f19 .word 0x08006f19 8006eb4: 08006e95 .word 0x08006e95 8006eb8: 08006e95 .word 0x08006e95 8006ebc: 08006e95 .word 0x08006e95 8006ec0: 08006e95 .word 0x08006e95 8006ec4: 08006f19 .word 0x08006f19 8006ec8: 08006e95 .word 0x08006e95 8006ecc: 08006e95 .word 0x08006e95 8006ed0: 08006e95 .word 0x08006e95 8006ed4: 08006e95 .word 0x08006e95 8006ed8: 08007027 .word 0x08007027 8006edc: 08006f49 .word 0x08006f49 8006ee0: 08007009 .word 0x08007009 8006ee4: 08006e95 .word 0x08006e95 8006ee8: 08006e95 .word 0x08006e95 8006eec: 08007049 .word 0x08007049 8006ef0: 08006e95 .word 0x08006e95 8006ef4: 08006f49 .word 0x08006f49 8006ef8: 08006e95 .word 0x08006e95 8006efc: 08006e95 .word 0x08006e95 8006f00: 08007011 .word 0x08007011 8006f04: 682b ldr r3, [r5, #0] 8006f06: 1d1a adds r2, r3, #4 8006f08: 681b ldr r3, [r3, #0] 8006f0a: 602a str r2, [r5, #0] 8006f0c: f104 0542 add.w r5, r4, #66 ; 0x42 8006f10: f884 3042 strb.w r3, [r4, #66] ; 0x42 8006f14: 2301 movs r3, #1 8006f16: e0a4 b.n 8007062 <_printf_i+0x1f6> 8006f18: 6820 ldr r0, [r4, #0] 8006f1a: 6829 ldr r1, [r5, #0] 8006f1c: 0606 lsls r6, r0, #24 8006f1e: f101 0304 add.w r3, r1, #4 8006f22: d50a bpl.n 8006f3a <_printf_i+0xce> 8006f24: 680e ldr r6, [r1, #0] 8006f26: 602b str r3, [r5, #0] 8006f28: 2e00 cmp r6, #0 8006f2a: da03 bge.n 8006f34 <_printf_i+0xc8> 8006f2c: 232d movs r3, #45 ; 0x2d 8006f2e: 4276 negs r6, r6 8006f30: f884 3043 strb.w r3, [r4, #67] ; 0x43 8006f34: 230a movs r3, #10 8006f36: 485e ldr r0, [pc, #376] ; (80070b0 <_printf_i+0x244>) 8006f38: e019 b.n 8006f6e <_printf_i+0x102> 8006f3a: 680e ldr r6, [r1, #0] 8006f3c: f010 0f40 tst.w r0, #64 ; 0x40 8006f40: 602b str r3, [r5, #0] 8006f42: bf18 it ne 8006f44: b236 sxthne r6, r6 8006f46: e7ef b.n 8006f28 <_printf_i+0xbc> 8006f48: 682b ldr r3, [r5, #0] 8006f4a: 6820 ldr r0, [r4, #0] 8006f4c: 1d19 adds r1, r3, #4 8006f4e: 6029 str r1, [r5, #0] 8006f50: 0601 lsls r1, r0, #24 8006f52: d501 bpl.n 8006f58 <_printf_i+0xec> 8006f54: 681e ldr r6, [r3, #0] 8006f56: e002 b.n 8006f5e <_printf_i+0xf2> 8006f58: 0646 lsls r6, r0, #25 8006f5a: d5fb bpl.n 8006f54 <_printf_i+0xe8> 8006f5c: 881e ldrh r6, [r3, #0] 8006f5e: 2f6f cmp r7, #111 ; 0x6f 8006f60: bf0c ite eq 8006f62: 2308 moveq r3, #8 8006f64: 230a movne r3, #10 8006f66: 4852 ldr r0, [pc, #328] ; (80070b0 <_printf_i+0x244>) 8006f68: 2100 movs r1, #0 8006f6a: f884 1043 strb.w r1, [r4, #67] ; 0x43 8006f6e: 6865 ldr r5, [r4, #4] 8006f70: 2d00 cmp r5, #0 8006f72: bfa8 it ge 8006f74: 6821 ldrge r1, [r4, #0] 8006f76: 60a5 str r5, [r4, #8] 8006f78: bfa4 itt ge 8006f7a: f021 0104 bicge.w r1, r1, #4 8006f7e: 6021 strge r1, [r4, #0] 8006f80: b90e cbnz r6, 8006f86 <_printf_i+0x11a> 8006f82: 2d00 cmp r5, #0 8006f84: d04d beq.n 8007022 <_printf_i+0x1b6> 8006f86: 4615 mov r5, r2 8006f88: fbb6 f1f3 udiv r1, r6, r3 8006f8c: fb03 6711 mls r7, r3, r1, r6 8006f90: 5dc7 ldrb r7, [r0, r7] 8006f92: f805 7d01 strb.w r7, [r5, #-1]! 8006f96: 4637 mov r7, r6 8006f98: 42bb cmp r3, r7 8006f9a: 460e mov r6, r1 8006f9c: d9f4 bls.n 8006f88 <_printf_i+0x11c> 8006f9e: 2b08 cmp r3, #8 8006fa0: d10b bne.n 8006fba <_printf_i+0x14e> 8006fa2: 6823 ldr r3, [r4, #0] 8006fa4: 07de lsls r6, r3, #31 8006fa6: d508 bpl.n 8006fba <_printf_i+0x14e> 8006fa8: 6923 ldr r3, [r4, #16] 8006faa: 6861 ldr r1, [r4, #4] 8006fac: 4299 cmp r1, r3 8006fae: bfde ittt le 8006fb0: 2330 movle r3, #48 ; 0x30 8006fb2: f805 3c01 strble.w r3, [r5, #-1] 8006fb6: f105 35ff addle.w r5, r5, #4294967295 8006fba: 1b52 subs r2, r2, r5 8006fbc: 6122 str r2, [r4, #16] 8006fbe: 464b mov r3, r9 8006fc0: 4621 mov r1, r4 8006fc2: 4640 mov r0, r8 8006fc4: f8cd a000 str.w sl, [sp] 8006fc8: aa03 add r2, sp, #12 8006fca: f7ff fedf bl 8006d8c <_printf_common> 8006fce: 3001 adds r0, #1 8006fd0: d14c bne.n 800706c <_printf_i+0x200> 8006fd2: f04f 30ff mov.w r0, #4294967295 8006fd6: b004 add sp, #16 8006fd8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006fdc: 4834 ldr r0, [pc, #208] ; (80070b0 <_printf_i+0x244>) 8006fde: f881 7045 strb.w r7, [r1, #69] ; 0x45 8006fe2: 6829 ldr r1, [r5, #0] 8006fe4: 6823 ldr r3, [r4, #0] 8006fe6: f851 6b04 ldr.w r6, [r1], #4 8006fea: 6029 str r1, [r5, #0] 8006fec: 061d lsls r5, r3, #24 8006fee: d514 bpl.n 800701a <_printf_i+0x1ae> 8006ff0: 07df lsls r7, r3, #31 8006ff2: bf44 itt mi 8006ff4: f043 0320 orrmi.w r3, r3, #32 8006ff8: 6023 strmi r3, [r4, #0] 8006ffa: b91e cbnz r6, 8007004 <_printf_i+0x198> 8006ffc: 6823 ldr r3, [r4, #0] 8006ffe: f023 0320 bic.w r3, r3, #32 8007002: 6023 str r3, [r4, #0] 8007004: 2310 movs r3, #16 8007006: e7af b.n 8006f68 <_printf_i+0xfc> 8007008: 6823 ldr r3, [r4, #0] 800700a: f043 0320 orr.w r3, r3, #32 800700e: 6023 str r3, [r4, #0] 8007010: 2378 movs r3, #120 ; 0x78 8007012: 4828 ldr r0, [pc, #160] ; (80070b4 <_printf_i+0x248>) 8007014: f884 3045 strb.w r3, [r4, #69] ; 0x45 8007018: e7e3 b.n 8006fe2 <_printf_i+0x176> 800701a: 0659 lsls r1, r3, #25 800701c: bf48 it mi 800701e: b2b6 uxthmi r6, r6 8007020: e7e6 b.n 8006ff0 <_printf_i+0x184> 8007022: 4615 mov r5, r2 8007024: e7bb b.n 8006f9e <_printf_i+0x132> 8007026: 682b ldr r3, [r5, #0] 8007028: 6826 ldr r6, [r4, #0] 800702a: 1d18 adds r0, r3, #4 800702c: 6961 ldr r1, [r4, #20] 800702e: 6028 str r0, [r5, #0] 8007030: 0635 lsls r5, r6, #24 8007032: 681b ldr r3, [r3, #0] 8007034: d501 bpl.n 800703a <_printf_i+0x1ce> 8007036: 6019 str r1, [r3, #0] 8007038: e002 b.n 8007040 <_printf_i+0x1d4> 800703a: 0670 lsls r0, r6, #25 800703c: d5fb bpl.n 8007036 <_printf_i+0x1ca> 800703e: 8019 strh r1, [r3, #0] 8007040: 2300 movs r3, #0 8007042: 4615 mov r5, r2 8007044: 6123 str r3, [r4, #16] 8007046: e7ba b.n 8006fbe <_printf_i+0x152> 8007048: 682b ldr r3, [r5, #0] 800704a: 2100 movs r1, #0 800704c: 1d1a adds r2, r3, #4 800704e: 602a str r2, [r5, #0] 8007050: 681d ldr r5, [r3, #0] 8007052: 6862 ldr r2, [r4, #4] 8007054: 4628 mov r0, r5 8007056: f000 f82f bl 80070b8 <memchr> 800705a: b108 cbz r0, 8007060 <_printf_i+0x1f4> 800705c: 1b40 subs r0, r0, r5 800705e: 6060 str r0, [r4, #4] 8007060: 6863 ldr r3, [r4, #4] 8007062: 6123 str r3, [r4, #16] 8007064: 2300 movs r3, #0 8007066: f884 3043 strb.w r3, [r4, #67] ; 0x43 800706a: e7a8 b.n 8006fbe <_printf_i+0x152> 800706c: 462a mov r2, r5 800706e: 4649 mov r1, r9 8007070: 4640 mov r0, r8 8007072: 6923 ldr r3, [r4, #16] 8007074: 47d0 blx sl 8007076: 3001 adds r0, #1 8007078: d0ab beq.n 8006fd2 <_printf_i+0x166> 800707a: 6823 ldr r3, [r4, #0] 800707c: 079b lsls r3, r3, #30 800707e: d413 bmi.n 80070a8 <_printf_i+0x23c> 8007080: 68e0 ldr r0, [r4, #12] 8007082: 9b03 ldr r3, [sp, #12] 8007084: 4298 cmp r0, r3 8007086: bfb8 it lt 8007088: 4618 movlt r0, r3 800708a: e7a4 b.n 8006fd6 <_printf_i+0x16a> 800708c: 2301 movs r3, #1 800708e: 4632 mov r2, r6 8007090: 4649 mov r1, r9 8007092: 4640 mov r0, r8 8007094: 47d0 blx sl 8007096: 3001 adds r0, #1 8007098: d09b beq.n 8006fd2 <_printf_i+0x166> 800709a: 3501 adds r5, #1 800709c: 68e3 ldr r3, [r4, #12] 800709e: 9903 ldr r1, [sp, #12] 80070a0: 1a5b subs r3, r3, r1 80070a2: 42ab cmp r3, r5 80070a4: dcf2 bgt.n 800708c <_printf_i+0x220> 80070a6: e7eb b.n 8007080 <_printf_i+0x214> 80070a8: 2500 movs r5, #0 80070aa: f104 0619 add.w r6, r4, #25 80070ae: e7f5 b.n 800709c <_printf_i+0x230> 80070b0: 08007b09 .word 0x08007b09 80070b4: 08007b1a .word 0x08007b1a 080070b8 <memchr>: 80070b8: 4603 mov r3, r0 80070ba: b510 push {r4, lr} 80070bc: b2c9 uxtb r1, r1 80070be: 4402 add r2, r0 80070c0: 4293 cmp r3, r2 80070c2: 4618 mov r0, r3 80070c4: d101 bne.n 80070ca <memchr+0x12> 80070c6: 2000 movs r0, #0 80070c8: e003 b.n 80070d2 <memchr+0x1a> 80070ca: 7804 ldrb r4, [r0, #0] 80070cc: 3301 adds r3, #1 80070ce: 428c cmp r4, r1 80070d0: d1f6 bne.n 80070c0 <memchr+0x8> 80070d2: bd10 pop {r4, pc} 080070d4 <memmove>: 80070d4: 4288 cmp r0, r1 80070d6: b510 push {r4, lr} 80070d8: eb01 0402 add.w r4, r1, r2 80070dc: d902 bls.n 80070e4 <memmove+0x10> 80070de: 4284 cmp r4, r0 80070e0: 4623 mov r3, r4 80070e2: d807 bhi.n 80070f4 <memmove+0x20> 80070e4: 1e43 subs r3, r0, #1 80070e6: 42a1 cmp r1, r4 80070e8: d008 beq.n 80070fc <memmove+0x28> 80070ea: f811 2b01 ldrb.w r2, [r1], #1 80070ee: f803 2f01 strb.w r2, [r3, #1]! 80070f2: e7f8 b.n 80070e6 <memmove+0x12> 80070f4: 4601 mov r1, r0 80070f6: 4402 add r2, r0 80070f8: 428a cmp r2, r1 80070fa: d100 bne.n 80070fe <memmove+0x2a> 80070fc: bd10 pop {r4, pc} 80070fe: f813 4d01 ldrb.w r4, [r3, #-1]! 8007102: f802 4d01 strb.w r4, [r2, #-1]! 8007106: e7f7 b.n 80070f8 <memmove+0x24> 08007108 <_free_r>: 8007108: b538 push {r3, r4, r5, lr} 800710a: 4605 mov r5, r0 800710c: 2900 cmp r1, #0 800710e: d040 beq.n 8007192 <_free_r+0x8a> 8007110: f851 3c04 ldr.w r3, [r1, #-4] 8007114: 1f0c subs r4, r1, #4 8007116: 2b00 cmp r3, #0 8007118: bfb8 it lt 800711a: 18e4 addlt r4, r4, r3 800711c: f000 f910 bl 8007340 <__malloc_lock> 8007120: 4a1c ldr r2, [pc, #112] ; (8007194 <_free_r+0x8c>) 8007122: 6813 ldr r3, [r2, #0] 8007124: b933 cbnz r3, 8007134 <_free_r+0x2c> 8007126: 6063 str r3, [r4, #4] 8007128: 6014 str r4, [r2, #0] 800712a: 4628 mov r0, r5 800712c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8007130: f000 b90c b.w 800734c <__malloc_unlock> 8007134: 42a3 cmp r3, r4 8007136: d908 bls.n 800714a <_free_r+0x42> 8007138: 6820 ldr r0, [r4, #0] 800713a: 1821 adds r1, r4, r0 800713c: 428b cmp r3, r1 800713e: bf01 itttt eq 8007140: 6819 ldreq r1, [r3, #0] 8007142: 685b ldreq r3, [r3, #4] 8007144: 1809 addeq r1, r1, r0 8007146: 6021 streq r1, [r4, #0] 8007148: e7ed b.n 8007126 <_free_r+0x1e> 800714a: 461a mov r2, r3 800714c: 685b ldr r3, [r3, #4] 800714e: b10b cbz r3, 8007154 <_free_r+0x4c> 8007150: 42a3 cmp r3, r4 8007152: d9fa bls.n 800714a <_free_r+0x42> 8007154: 6811 ldr r1, [r2, #0] 8007156: 1850 adds r0, r2, r1 8007158: 42a0 cmp r0, r4 800715a: d10b bne.n 8007174 <_free_r+0x6c> 800715c: 6820 ldr r0, [r4, #0] 800715e: 4401 add r1, r0 8007160: 1850 adds r0, r2, r1 8007162: 4283 cmp r3, r0 8007164: 6011 str r1, [r2, #0] 8007166: d1e0 bne.n 800712a <_free_r+0x22> 8007168: 6818 ldr r0, [r3, #0] 800716a: 685b ldr r3, [r3, #4] 800716c: 4401 add r1, r0 800716e: 6011 str r1, [r2, #0] 8007170: 6053 str r3, [r2, #4] 8007172: e7da b.n 800712a <_free_r+0x22> 8007174: d902 bls.n 800717c <_free_r+0x74> 8007176: 230c movs r3, #12 8007178: 602b str r3, [r5, #0] 800717a: e7d6 b.n 800712a <_free_r+0x22> 800717c: 6820 ldr r0, [r4, #0] 800717e: 1821 adds r1, r4, r0 8007180: 428b cmp r3, r1 8007182: bf01 itttt eq 8007184: 6819 ldreq r1, [r3, #0] 8007186: 685b ldreq r3, [r3, #4] 8007188: 1809 addeq r1, r1, r0 800718a: 6021 streq r1, [r4, #0] 800718c: 6063 str r3, [r4, #4] 800718e: 6054 str r4, [r2, #4] 8007190: e7cb b.n 800712a <_free_r+0x22> 8007192: bd38 pop {r3, r4, r5, pc} 8007194: 20000a5c .word 0x20000a5c 08007198 <sbrk_aligned>: 8007198: b570 push {r4, r5, r6, lr} 800719a: 4e0e ldr r6, [pc, #56] ; (80071d4 <sbrk_aligned+0x3c>) 800719c: 460c mov r4, r1 800719e: 6831 ldr r1, [r6, #0] 80071a0: 4605 mov r5, r0 80071a2: b911 cbnz r1, 80071aa <sbrk_aligned+0x12> 80071a4: f000 f8bc bl 8007320 <_sbrk_r> 80071a8: 6030 str r0, [r6, #0] 80071aa: 4621 mov r1, r4 80071ac: 4628 mov r0, r5 80071ae: f000 f8b7 bl 8007320 <_sbrk_r> 80071b2: 1c43 adds r3, r0, #1 80071b4: d00a beq.n 80071cc <sbrk_aligned+0x34> 80071b6: 1cc4 adds r4, r0, #3 80071b8: f024 0403 bic.w r4, r4, #3 80071bc: 42a0 cmp r0, r4 80071be: d007 beq.n 80071d0 <sbrk_aligned+0x38> 80071c0: 1a21 subs r1, r4, r0 80071c2: 4628 mov r0, r5 80071c4: f000 f8ac bl 8007320 <_sbrk_r> 80071c8: 3001 adds r0, #1 80071ca: d101 bne.n 80071d0 <sbrk_aligned+0x38> 80071cc: f04f 34ff mov.w r4, #4294967295 80071d0: 4620 mov r0, r4 80071d2: bd70 pop {r4, r5, r6, pc} 80071d4: 20000a60 .word 0x20000a60 080071d8 <_malloc_r>: 80071d8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80071dc: 1ccd adds r5, r1, #3 80071de: f025 0503 bic.w r5, r5, #3 80071e2: 3508 adds r5, #8 80071e4: 2d0c cmp r5, #12 80071e6: bf38 it cc 80071e8: 250c movcc r5, #12 80071ea: 2d00 cmp r5, #0 80071ec: 4607 mov r7, r0 80071ee: db01 blt.n 80071f4 <_malloc_r+0x1c> 80071f0: 42a9 cmp r1, r5 80071f2: d905 bls.n 8007200 <_malloc_r+0x28> 80071f4: 230c movs r3, #12 80071f6: 2600 movs r6, #0 80071f8: 603b str r3, [r7, #0] 80071fa: 4630 mov r0, r6 80071fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8007200: 4e2e ldr r6, [pc, #184] ; (80072bc <_malloc_r+0xe4>) 8007202: f000 f89d bl 8007340 <__malloc_lock> 8007206: 6833 ldr r3, [r6, #0] 8007208: 461c mov r4, r3 800720a: bb34 cbnz r4, 800725a <_malloc_r+0x82> 800720c: 4629 mov r1, r5 800720e: 4638 mov r0, r7 8007210: f7ff ffc2 bl 8007198 <sbrk_aligned> 8007214: 1c43 adds r3, r0, #1 8007216: 4604 mov r4, r0 8007218: d14d bne.n 80072b6 <_malloc_r+0xde> 800721a: 6834 ldr r4, [r6, #0] 800721c: 4626 mov r6, r4 800721e: 2e00 cmp r6, #0 8007220: d140 bne.n 80072a4 <_malloc_r+0xcc> 8007222: 6823 ldr r3, [r4, #0] 8007224: 4631 mov r1, r6 8007226: 4638 mov r0, r7 8007228: eb04 0803 add.w r8, r4, r3 800722c: f000 f878 bl 8007320 <_sbrk_r> 8007230: 4580 cmp r8, r0 8007232: d13a bne.n 80072aa <_malloc_r+0xd2> 8007234: 6821 ldr r1, [r4, #0] 8007236: 3503 adds r5, #3 8007238: 1a6d subs r5, r5, r1 800723a: f025 0503 bic.w r5, r5, #3 800723e: 3508 adds r5, #8 8007240: 2d0c cmp r5, #12 8007242: bf38 it cc 8007244: 250c movcc r5, #12 8007246: 4638 mov r0, r7 8007248: 4629 mov r1, r5 800724a: f7ff ffa5 bl 8007198 <sbrk_aligned> 800724e: 3001 adds r0, #1 8007250: d02b beq.n 80072aa <_malloc_r+0xd2> 8007252: 6823 ldr r3, [r4, #0] 8007254: 442b add r3, r5 8007256: 6023 str r3, [r4, #0] 8007258: e00e b.n 8007278 <_malloc_r+0xa0> 800725a: 6822 ldr r2, [r4, #0] 800725c: 1b52 subs r2, r2, r5 800725e: d41e bmi.n 800729e <_malloc_r+0xc6> 8007260: 2a0b cmp r2, #11 8007262: d916 bls.n 8007292 <_malloc_r+0xba> 8007264: 1961 adds r1, r4, r5 8007266: 42a3 cmp r3, r4 8007268: 6025 str r5, [r4, #0] 800726a: bf18 it ne 800726c: 6059 strne r1, [r3, #4] 800726e: 6863 ldr r3, [r4, #4] 8007270: bf08 it eq 8007272: 6031 streq r1, [r6, #0] 8007274: 5162 str r2, [r4, r5] 8007276: 604b str r3, [r1, #4] 8007278: 4638 mov r0, r7 800727a: f104 060b add.w r6, r4, #11 800727e: f000 f865 bl 800734c <__malloc_unlock> 8007282: f026 0607 bic.w r6, r6, #7 8007286: 1d23 adds r3, r4, #4 8007288: 1af2 subs r2, r6, r3 800728a: d0b6 beq.n 80071fa <_malloc_r+0x22> 800728c: 1b9b subs r3, r3, r6 800728e: 50a3 str r3, [r4, r2] 8007290: e7b3 b.n 80071fa <_malloc_r+0x22> 8007292: 6862 ldr r2, [r4, #4] 8007294: 42a3 cmp r3, r4 8007296: bf0c ite eq 8007298: 6032 streq r2, [r6, #0] 800729a: 605a strne r2, [r3, #4] 800729c: e7ec b.n 8007278 <_malloc_r+0xa0> 800729e: 4623 mov r3, r4 80072a0: 6864 ldr r4, [r4, #4] 80072a2: e7b2 b.n 800720a <_malloc_r+0x32> 80072a4: 4634 mov r4, r6 80072a6: 6876 ldr r6, [r6, #4] 80072a8: e7b9 b.n 800721e <_malloc_r+0x46> 80072aa: 230c movs r3, #12 80072ac: 4638 mov r0, r7 80072ae: 603b str r3, [r7, #0] 80072b0: f000 f84c bl 800734c <__malloc_unlock> 80072b4: e7a1 b.n 80071fa <_malloc_r+0x22> 80072b6: 6025 str r5, [r4, #0] 80072b8: e7de b.n 8007278 <_malloc_r+0xa0> 80072ba: bf00 nop 80072bc: 20000a5c .word 0x20000a5c 080072c0 <_realloc_r>: 80072c0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80072c4: 4680 mov r8, r0 80072c6: 4614 mov r4, r2 80072c8: 460e mov r6, r1 80072ca: b921 cbnz r1, 80072d6 <_realloc_r+0x16> 80072cc: 4611 mov r1, r2 80072ce: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80072d2: f7ff bf81 b.w 80071d8 <_malloc_r> 80072d6: b92a cbnz r2, 80072e4 <_realloc_r+0x24> 80072d8: f7ff ff16 bl 8007108 <_free_r> 80072dc: 4625 mov r5, r4 80072de: 4628 mov r0, r5 80072e0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80072e4: f000 f838 bl 8007358 <_malloc_usable_size_r> 80072e8: 4284 cmp r4, r0 80072ea: 4607 mov r7, r0 80072ec: d802 bhi.n 80072f4 <_realloc_r+0x34> 80072ee: ebb4 0f50 cmp.w r4, r0, lsr #1 80072f2: d812 bhi.n 800731a <_realloc_r+0x5a> 80072f4: 4621 mov r1, r4 80072f6: 4640 mov r0, r8 80072f8: f7ff ff6e bl 80071d8 <_malloc_r> 80072fc: 4605 mov r5, r0 80072fe: 2800 cmp r0, #0 8007300: d0ed beq.n 80072de <_realloc_r+0x1e> 8007302: 42bc cmp r4, r7 8007304: 4622 mov r2, r4 8007306: 4631 mov r1, r6 8007308: bf28 it cs 800730a: 463a movcs r2, r7 800730c: f7ff fbac bl 8006a68 <memcpy> 8007310: 4631 mov r1, r6 8007312: 4640 mov r0, r8 8007314: f7ff fef8 bl 8007108 <_free_r> 8007318: e7e1 b.n 80072de <_realloc_r+0x1e> 800731a: 4635 mov r5, r6 800731c: e7df b.n 80072de <_realloc_r+0x1e> ... 08007320 <_sbrk_r>: 8007320: b538 push {r3, r4, r5, lr} 8007322: 2300 movs r3, #0 8007324: 4d05 ldr r5, [pc, #20] ; (800733c <_sbrk_r+0x1c>) 8007326: 4604 mov r4, r0 8007328: 4608 mov r0, r1 800732a: 602b str r3, [r5, #0] 800732c: f7fb f8be bl 80024ac <_sbrk> 8007330: 1c43 adds r3, r0, #1 8007332: d102 bne.n 800733a <_sbrk_r+0x1a> 8007334: 682b ldr r3, [r5, #0] 8007336: b103 cbz r3, 800733a <_sbrk_r+0x1a> 8007338: 6023 str r3, [r4, #0] 800733a: bd38 pop {r3, r4, r5, pc} 800733c: 20000a64 .word 0x20000a64 08007340 <__malloc_lock>: 8007340: 4801 ldr r0, [pc, #4] ; (8007348 <__malloc_lock+0x8>) 8007342: f000 b811 b.w 8007368 <__retarget_lock_acquire_recursive> 8007346: bf00 nop 8007348: 20000a68 .word 0x20000a68 0800734c <__malloc_unlock>: 800734c: 4801 ldr r0, [pc, #4] ; (8007354 <__malloc_unlock+0x8>) 800734e: f000 b80c b.w 800736a <__retarget_lock_release_recursive> 8007352: bf00 nop 8007354: 20000a68 .word 0x20000a68 08007358 <_malloc_usable_size_r>: 8007358: f851 3c04 ldr.w r3, [r1, #-4] 800735c: 1f18 subs r0, r3, #4 800735e: 2b00 cmp r3, #0 8007360: bfbc itt lt 8007362: 580b ldrlt r3, [r1, r0] 8007364: 18c0 addlt r0, r0, r3 8007366: 4770 bx lr 08007368 <__retarget_lock_acquire_recursive>: 8007368: 4770 bx lr 0800736a <__retarget_lock_release_recursive>: 800736a: 4770 bx lr 0800736c <_init>: 800736c: b5f8 push {r3, r4, r5, r6, r7, lr} 800736e: bf00 nop 8007370: bcf8 pop {r3, r4, r5, r6, r7} 8007372: bc08 pop {r3} 8007374: 469e mov lr, r3 8007376: 4770 bx lr 08007378 <_fini>: 8007378: b5f8 push {r3, r4, r5, r6, r7, lr} 800737a: bf00 nop 800737c: bcf8 pop {r3, r4, r5, r6, r7} 800737e: bc08 pop {r3} 8007380: 469e mov lr, r3 8007382: 4770 bx lr