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Tonometer
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Tonometer
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main
Debug/Tonometer.list
21 223 строки
795 KB
Andrianooo
Исправлена логика парсера, расчет CRC
28 апр 2026, 10:11
28 апр 2026, 10:11
845050b
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Tonometer.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000081cc 08000110 08000110 00010110 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000007b0 080082dc 080082dc 000182dc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008a8c 08008a8c 00020080 2**0 CONTENTS 4 .ARM 00000000 08008a8c 08008a8c 00020080 2**0 CONTENTS 5 .preinit_array 00000000 08008a8c 08008a8c 00020080 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008a8c 08008a8c 00018a8c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008a90 08008a90 00018a90 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000080 20000000 08008a94 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000d74 20000080 08008b14 00020080 2**2 ALLOC 10 ._user_heap_stack 00000604 20000df4 08008b14 00020df4 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00020080 2**0 CONTENTS, READONLY 12 .debug_info 00013c72 00000000 00000000 000200a9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002f7b 00000000 00000000 00033d1b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001228 00000000 00000000 00036c98 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00001100 00000000 00000000 00037ec0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00019f68 00000000 00000000 00038fc0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000158c4 00000000 00000000 00052f28 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000927f0 00000000 00000000 000687ec 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000fafdc 2**0 CONTENTS, READONLY 20 .debug_frame 00004ff0 00000000 00000000 000fb02c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000110 <__do_global_dtors_aux>: 8000110: b510 push {r4, lr} 8000112: 4c05 ldr r4, [pc, #20] ; (8000128 <__do_global_dtors_aux+0x18>) 8000114: 7823 ldrb r3, [r4, #0] 8000116: b933 cbnz r3, 8000126 <__do_global_dtors_aux+0x16> 8000118: 4b04 ldr r3, [pc, #16] ; (800012c <__do_global_dtors_aux+0x1c>) 800011a: b113 cbz r3, 8000122 <__do_global_dtors_aux+0x12> 800011c: 4804 ldr r0, [pc, #16] ; (8000130 <__do_global_dtors_aux+0x20>) 800011e: f3af 8000 nop.w 8000122: 2301 movs r3, #1 8000124: 7023 strb r3, [r4, #0] 8000126: bd10 pop {r4, pc} 8000128: 20000080 .word 0x20000080 800012c: 00000000 .word 0x00000000 8000130: 080082c4 .word 0x080082c4 08000134 <frame_dummy>: 8000134: b508 push {r3, lr} 8000136: 4b03 ldr r3, [pc, #12] ; (8000144 <frame_dummy+0x10>) 8000138: b11b cbz r3, 8000142 <frame_dummy+0xe> 800013a: 4903 ldr r1, [pc, #12] ; (8000148 <frame_dummy+0x14>) 800013c: 4803 ldr r0, [pc, #12] ; (800014c <frame_dummy+0x18>) 800013e: f3af 8000 nop.w 8000142: bd08 pop {r3, pc} 8000144: 00000000 .word 0x00000000 8000148: 20000084 .word 0x20000084 800014c: 080082c4 .word 0x080082c4 08000150 <strlen>: 8000150: 4603 mov r3, r0 8000152: f813 2b01 ldrb.w r2, [r3], #1 8000156: 2a00 cmp r2, #0 8000158: d1fb bne.n 8000152 <strlen+0x2> 800015a: 1a18 subs r0, r3, r0 800015c: 3801 subs r0, #1 800015e: 4770 bx lr 08000160 <__aeabi_drsub>: 8000160: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000164: e002 b.n 800016c <__adddf3> 8000166: bf00 nop 08000168 <__aeabi_dsub>: 8000168: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800016c <__adddf3>: 800016c: b530 push {r4, r5, lr} 800016e: ea4f 0441 mov.w r4, r1, lsl #1 8000172: ea4f 0543 mov.w r5, r3, lsl #1 8000176: ea94 0f05 teq r4, r5 800017a: bf08 it eq 800017c: ea90 0f02 teqeq r0, r2 8000180: bf1f itttt ne 8000182: ea54 0c00 orrsne.w ip, r4, r0 8000186: ea55 0c02 orrsne.w ip, r5, r2 800018a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800018e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000192: f000 80e2 beq.w 800035a <__adddf3+0x1ee> 8000196: ea4f 5454 mov.w r4, r4, lsr #21 800019a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800019e: bfb8 it lt 80001a0: 426d neglt r5, r5 80001a2: dd0c ble.n 80001be <__adddf3+0x52> 80001a4: 442c add r4, r5 80001a6: ea80 0202 eor.w r2, r0, r2 80001aa: ea81 0303 eor.w r3, r1, r3 80001ae: ea82 0000 eor.w r0, r2, r0 80001b2: ea83 0101 eor.w r1, r3, r1 80001b6: ea80 0202 eor.w r2, r0, r2 80001ba: ea81 0303 eor.w r3, r1, r3 80001be: 2d36 cmp r5, #54 ; 0x36 80001c0: bf88 it hi 80001c2: bd30 pophi {r4, r5, pc} 80001c4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80001c8: ea4f 3101 mov.w r1, r1, lsl #12 80001cc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 80001d0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80001d4: d002 beq.n 80001dc <__adddf3+0x70> 80001d6: 4240 negs r0, r0 80001d8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80001dc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80001e0: ea4f 3303 mov.w r3, r3, lsl #12 80001e4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80001e8: d002 beq.n 80001f0 <__adddf3+0x84> 80001ea: 4252 negs r2, r2 80001ec: eb63 0343 sbc.w r3, r3, r3, lsl #1 80001f0: ea94 0f05 teq r4, r5 80001f4: f000 80a7 beq.w 8000346 <__adddf3+0x1da> 80001f8: f1a4 0401 sub.w r4, r4, #1 80001fc: f1d5 0e20 rsbs lr, r5, #32 8000200: db0d blt.n 800021e <__adddf3+0xb2> 8000202: fa02 fc0e lsl.w ip, r2, lr 8000206: fa22 f205 lsr.w r2, r2, r5 800020a: 1880 adds r0, r0, r2 800020c: f141 0100 adc.w r1, r1, #0 8000210: fa03 f20e lsl.w r2, r3, lr 8000214: 1880 adds r0, r0, r2 8000216: fa43 f305 asr.w r3, r3, r5 800021a: 4159 adcs r1, r3 800021c: e00e b.n 800023c <__adddf3+0xd0> 800021e: f1a5 0520 sub.w r5, r5, #32 8000222: f10e 0e20 add.w lr, lr, #32 8000226: 2a01 cmp r2, #1 8000228: fa03 fc0e lsl.w ip, r3, lr 800022c: bf28 it cs 800022e: f04c 0c02 orrcs.w ip, ip, #2 8000232: fa43 f305 asr.w r3, r3, r5 8000236: 18c0 adds r0, r0, r3 8000238: eb51 71e3 adcs.w r1, r1, r3, asr #31 800023c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000240: d507 bpl.n 8000252 <__adddf3+0xe6> 8000242: f04f 0e00 mov.w lr, #0 8000246: f1dc 0c00 rsbs ip, ip, #0 800024a: eb7e 0000 sbcs.w r0, lr, r0 800024e: eb6e 0101 sbc.w r1, lr, r1 8000252: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000256: d31b bcc.n 8000290 <__adddf3+0x124> 8000258: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800025c: d30c bcc.n 8000278 <__adddf3+0x10c> 800025e: 0849 lsrs r1, r1, #1 8000260: ea5f 0030 movs.w r0, r0, rrx 8000264: ea4f 0c3c mov.w ip, ip, rrx 8000268: f104 0401 add.w r4, r4, #1 800026c: ea4f 5244 mov.w r2, r4, lsl #21 8000270: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000274: f080 809a bcs.w 80003ac <__adddf3+0x240> 8000278: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800027c: bf08 it eq 800027e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000282: f150 0000 adcs.w r0, r0, #0 8000286: eb41 5104 adc.w r1, r1, r4, lsl #20 800028a: ea41 0105 orr.w r1, r1, r5 800028e: bd30 pop {r4, r5, pc} 8000290: ea5f 0c4c movs.w ip, ip, lsl #1 8000294: 4140 adcs r0, r0 8000296: eb41 0101 adc.w r1, r1, r1 800029a: 3c01 subs r4, #1 800029c: bf28 it cs 800029e: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 80002a2: d2e9 bcs.n 8000278 <__adddf3+0x10c> 80002a4: f091 0f00 teq r1, #0 80002a8: bf04 itt eq 80002aa: 4601 moveq r1, r0 80002ac: 2000 moveq r0, #0 80002ae: fab1 f381 clz r3, r1 80002b2: bf08 it eq 80002b4: 3320 addeq r3, #32 80002b6: f1a3 030b sub.w r3, r3, #11 80002ba: f1b3 0220 subs.w r2, r3, #32 80002be: da0c bge.n 80002da <__adddf3+0x16e> 80002c0: 320c adds r2, #12 80002c2: dd08 ble.n 80002d6 <__adddf3+0x16a> 80002c4: f102 0c14 add.w ip, r2, #20 80002c8: f1c2 020c rsb r2, r2, #12 80002cc: fa01 f00c lsl.w r0, r1, ip 80002d0: fa21 f102 lsr.w r1, r1, r2 80002d4: e00c b.n 80002f0 <__adddf3+0x184> 80002d6: f102 0214 add.w r2, r2, #20 80002da: bfd8 it le 80002dc: f1c2 0c20 rsble ip, r2, #32 80002e0: fa01 f102 lsl.w r1, r1, r2 80002e4: fa20 fc0c lsr.w ip, r0, ip 80002e8: bfdc itt le 80002ea: ea41 010c orrle.w r1, r1, ip 80002ee: 4090 lslle r0, r2 80002f0: 1ae4 subs r4, r4, r3 80002f2: bfa2 ittt ge 80002f4: eb01 5104 addge.w r1, r1, r4, lsl #20 80002f8: 4329 orrge r1, r5 80002fa: bd30 popge {r4, r5, pc} 80002fc: ea6f 0404 mvn.w r4, r4 8000300: 3c1f subs r4, #31 8000302: da1c bge.n 800033e <__adddf3+0x1d2> 8000304: 340c adds r4, #12 8000306: dc0e bgt.n 8000326 <__adddf3+0x1ba> 8000308: f104 0414 add.w r4, r4, #20 800030c: f1c4 0220 rsb r2, r4, #32 8000310: fa20 f004 lsr.w r0, r0, r4 8000314: fa01 f302 lsl.w r3, r1, r2 8000318: ea40 0003 orr.w r0, r0, r3 800031c: fa21 f304 lsr.w r3, r1, r4 8000320: ea45 0103 orr.w r1, r5, r3 8000324: bd30 pop {r4, r5, pc} 8000326: f1c4 040c rsb r4, r4, #12 800032a: f1c4 0220 rsb r2, r4, #32 800032e: fa20 f002 lsr.w r0, r0, r2 8000332: fa01 f304 lsl.w r3, r1, r4 8000336: ea40 0003 orr.w r0, r0, r3 800033a: 4629 mov r1, r5 800033c: bd30 pop {r4, r5, pc} 800033e: fa21 f004 lsr.w r0, r1, r4 8000342: 4629 mov r1, r5 8000344: bd30 pop {r4, r5, pc} 8000346: f094 0f00 teq r4, #0 800034a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800034e: bf06 itte eq 8000350: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000354: 3401 addeq r4, #1 8000356: 3d01 subne r5, #1 8000358: e74e b.n 80001f8 <__adddf3+0x8c> 800035a: ea7f 5c64 mvns.w ip, r4, asr #21 800035e: bf18 it ne 8000360: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000364: d029 beq.n 80003ba <__adddf3+0x24e> 8000366: ea94 0f05 teq r4, r5 800036a: bf08 it eq 800036c: ea90 0f02 teqeq r0, r2 8000370: d005 beq.n 800037e <__adddf3+0x212> 8000372: ea54 0c00 orrs.w ip, r4, r0 8000376: bf04 itt eq 8000378: 4619 moveq r1, r3 800037a: 4610 moveq r0, r2 800037c: bd30 pop {r4, r5, pc} 800037e: ea91 0f03 teq r1, r3 8000382: bf1e ittt ne 8000384: 2100 movne r1, #0 8000386: 2000 movne r0, #0 8000388: bd30 popne {r4, r5, pc} 800038a: ea5f 5c54 movs.w ip, r4, lsr #21 800038e: d105 bne.n 800039c <__adddf3+0x230> 8000390: 0040 lsls r0, r0, #1 8000392: 4149 adcs r1, r1 8000394: bf28 it cs 8000396: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800039a: bd30 pop {r4, r5, pc} 800039c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 80003a0: bf3c itt cc 80003a2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 80003a6: bd30 popcc {r4, r5, pc} 80003a8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80003ac: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 80003b0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80003b4: f04f 0000 mov.w r0, #0 80003b8: bd30 pop {r4, r5, pc} 80003ba: ea7f 5c64 mvns.w ip, r4, asr #21 80003be: bf1a itte ne 80003c0: 4619 movne r1, r3 80003c2: 4610 movne r0, r2 80003c4: ea7f 5c65 mvnseq.w ip, r5, asr #21 80003c8: bf1c itt ne 80003ca: 460b movne r3, r1 80003cc: 4602 movne r2, r0 80003ce: ea50 3401 orrs.w r4, r0, r1, lsl #12 80003d2: bf06 itte eq 80003d4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80003d8: ea91 0f03 teqeq r1, r3 80003dc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80003e0: bd30 pop {r4, r5, pc} 80003e2: bf00 nop 080003e4 <__aeabi_ui2d>: 80003e4: f090 0f00 teq r0, #0 80003e8: bf04 itt eq 80003ea: 2100 moveq r1, #0 80003ec: 4770 bxeq lr 80003ee: b530 push {r4, r5, lr} 80003f0: f44f 6480 mov.w r4, #1024 ; 0x400 80003f4: f104 0432 add.w r4, r4, #50 ; 0x32 80003f8: f04f 0500 mov.w r5, #0 80003fc: f04f 0100 mov.w r1, #0 8000400: e750 b.n 80002a4 <__adddf3+0x138> 8000402: bf00 nop 08000404 <__aeabi_i2d>: 8000404: f090 0f00 teq r0, #0 8000408: bf04 itt eq 800040a: 2100 moveq r1, #0 800040c: 4770 bxeq lr 800040e: b530 push {r4, r5, lr} 8000410: f44f 6480 mov.w r4, #1024 ; 0x400 8000414: f104 0432 add.w r4, r4, #50 ; 0x32 8000418: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 800041c: bf48 it mi 800041e: 4240 negmi r0, r0 8000420: f04f 0100 mov.w r1, #0 8000424: e73e b.n 80002a4 <__adddf3+0x138> 8000426: bf00 nop 08000428 <__aeabi_f2d>: 8000428: 0042 lsls r2, r0, #1 800042a: ea4f 01e2 mov.w r1, r2, asr #3 800042e: ea4f 0131 mov.w r1, r1, rrx 8000432: ea4f 7002 mov.w r0, r2, lsl #28 8000436: bf1f itttt ne 8000438: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 800043c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000440: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000444: 4770 bxne lr 8000446: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800044a: bf08 it eq 800044c: 4770 bxeq lr 800044e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000452: bf04 itt eq 8000454: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000458: 4770 bxeq lr 800045a: b530 push {r4, r5, lr} 800045c: f44f 7460 mov.w r4, #896 ; 0x380 8000460: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000464: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000468: e71c b.n 80002a4 <__adddf3+0x138> 800046a: bf00 nop 0800046c <__aeabi_ul2d>: 800046c: ea50 0201 orrs.w r2, r0, r1 8000470: bf08 it eq 8000472: 4770 bxeq lr 8000474: b530 push {r4, r5, lr} 8000476: f04f 0500 mov.w r5, #0 800047a: e00a b.n 8000492 <__aeabi_l2d+0x16> 0800047c <__aeabi_l2d>: 800047c: ea50 0201 orrs.w r2, r0, r1 8000480: bf08 it eq 8000482: 4770 bxeq lr 8000484: b530 push {r4, r5, lr} 8000486: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800048a: d502 bpl.n 8000492 <__aeabi_l2d+0x16> 800048c: 4240 negs r0, r0 800048e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000492: f44f 6480 mov.w r4, #1024 ; 0x400 8000496: f104 0432 add.w r4, r4, #50 ; 0x32 800049a: ea5f 5c91 movs.w ip, r1, lsr #22 800049e: f43f aed8 beq.w 8000252 <__adddf3+0xe6> 80004a2: f04f 0203 mov.w r2, #3 80004a6: ea5f 0cdc movs.w ip, ip, lsr #3 80004aa: bf18 it ne 80004ac: 3203 addne r2, #3 80004ae: ea5f 0cdc movs.w ip, ip, lsr #3 80004b2: bf18 it ne 80004b4: 3203 addne r2, #3 80004b6: eb02 02dc add.w r2, r2, ip, lsr #3 80004ba: f1c2 0320 rsb r3, r2, #32 80004be: fa00 fc03 lsl.w ip, r0, r3 80004c2: fa20 f002 lsr.w r0, r0, r2 80004c6: fa01 fe03 lsl.w lr, r1, r3 80004ca: ea40 000e orr.w r0, r0, lr 80004ce: fa21 f102 lsr.w r1, r1, r2 80004d2: 4414 add r4, r2 80004d4: e6bd b.n 8000252 <__adddf3+0xe6> 80004d6: bf00 nop 080004d8 <__aeabi_dmul>: 80004d8: b570 push {r4, r5, r6, lr} 80004da: f04f 0cff mov.w ip, #255 ; 0xff 80004de: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80004e2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80004e6: bf1d ittte ne 80004e8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80004ec: ea94 0f0c teqne r4, ip 80004f0: ea95 0f0c teqne r5, ip 80004f4: f000 f8de bleq 80006b4 <__aeabi_dmul+0x1dc> 80004f8: 442c add r4, r5 80004fa: ea81 0603 eor.w r6, r1, r3 80004fe: ea21 514c bic.w r1, r1, ip, lsl #21 8000502: ea23 534c bic.w r3, r3, ip, lsl #21 8000506: ea50 3501 orrs.w r5, r0, r1, lsl #12 800050a: bf18 it ne 800050c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000510: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000514: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8000518: d038 beq.n 800058c <__aeabi_dmul+0xb4> 800051a: fba0 ce02 umull ip, lr, r0, r2 800051e: f04f 0500 mov.w r5, #0 8000522: fbe1 e502 umlal lr, r5, r1, r2 8000526: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 800052a: fbe0 e503 umlal lr, r5, r0, r3 800052e: f04f 0600 mov.w r6, #0 8000532: fbe1 5603 umlal r5, r6, r1, r3 8000536: f09c 0f00 teq ip, #0 800053a: bf18 it ne 800053c: f04e 0e01 orrne.w lr, lr, #1 8000540: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000544: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000548: f564 7440 sbc.w r4, r4, #768 ; 0x300 800054c: d204 bcs.n 8000558 <__aeabi_dmul+0x80> 800054e: ea5f 0e4e movs.w lr, lr, lsl #1 8000552: 416d adcs r5, r5 8000554: eb46 0606 adc.w r6, r6, r6 8000558: ea42 21c6 orr.w r1, r2, r6, lsl #11 800055c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000560: ea4f 20c5 mov.w r0, r5, lsl #11 8000564: ea40 505e orr.w r0, r0, lr, lsr #21 8000568: ea4f 2ece mov.w lr, lr, lsl #11 800056c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000570: bf88 it hi 8000572: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000576: d81e bhi.n 80005b6 <__aeabi_dmul+0xde> 8000578: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800057c: bf08 it eq 800057e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000582: f150 0000 adcs.w r0, r0, #0 8000586: eb41 5104 adc.w r1, r1, r4, lsl #20 800058a: bd70 pop {r4, r5, r6, pc} 800058c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000590: ea46 0101 orr.w r1, r6, r1 8000594: ea40 0002 orr.w r0, r0, r2 8000598: ea81 0103 eor.w r1, r1, r3 800059c: ebb4 045c subs.w r4, r4, ip, lsr #1 80005a0: bfc2 ittt gt 80005a2: ebd4 050c rsbsgt r5, r4, ip 80005a6: ea41 5104 orrgt.w r1, r1, r4, lsl #20 80005aa: bd70 popgt {r4, r5, r6, pc} 80005ac: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005b0: f04f 0e00 mov.w lr, #0 80005b4: 3c01 subs r4, #1 80005b6: f300 80ab bgt.w 8000710 <__aeabi_dmul+0x238> 80005ba: f114 0f36 cmn.w r4, #54 ; 0x36 80005be: bfde ittt le 80005c0: 2000 movle r0, #0 80005c2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 80005c6: bd70 pople {r4, r5, r6, pc} 80005c8: f1c4 0400 rsb r4, r4, #0 80005cc: 3c20 subs r4, #32 80005ce: da35 bge.n 800063c <__aeabi_dmul+0x164> 80005d0: 340c adds r4, #12 80005d2: dc1b bgt.n 800060c <__aeabi_dmul+0x134> 80005d4: f104 0414 add.w r4, r4, #20 80005d8: f1c4 0520 rsb r5, r4, #32 80005dc: fa00 f305 lsl.w r3, r0, r5 80005e0: fa20 f004 lsr.w r0, r0, r4 80005e4: fa01 f205 lsl.w r2, r1, r5 80005e8: ea40 0002 orr.w r0, r0, r2 80005ec: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80005f0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80005f4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80005f8: fa21 f604 lsr.w r6, r1, r4 80005fc: eb42 0106 adc.w r1, r2, r6 8000600: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000604: bf08 it eq 8000606: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800060a: bd70 pop {r4, r5, r6, pc} 800060c: f1c4 040c rsb r4, r4, #12 8000610: f1c4 0520 rsb r5, r4, #32 8000614: fa00 f304 lsl.w r3, r0, r4 8000618: fa20 f005 lsr.w r0, r0, r5 800061c: fa01 f204 lsl.w r2, r1, r4 8000620: ea40 0002 orr.w r0, r0, r2 8000624: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000628: eb10 70d3 adds.w r0, r0, r3, lsr #31 800062c: f141 0100 adc.w r1, r1, #0 8000630: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000634: bf08 it eq 8000636: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800063a: bd70 pop {r4, r5, r6, pc} 800063c: f1c4 0520 rsb r5, r4, #32 8000640: fa00 f205 lsl.w r2, r0, r5 8000644: ea4e 0e02 orr.w lr, lr, r2 8000648: fa20 f304 lsr.w r3, r0, r4 800064c: fa01 f205 lsl.w r2, r1, r5 8000650: ea43 0302 orr.w r3, r3, r2 8000654: fa21 f004 lsr.w r0, r1, r4 8000658: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800065c: fa21 f204 lsr.w r2, r1, r4 8000660: ea20 0002 bic.w r0, r0, r2 8000664: eb00 70d3 add.w r0, r0, r3, lsr #31 8000668: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800066c: bf08 it eq 800066e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000672: bd70 pop {r4, r5, r6, pc} 8000674: f094 0f00 teq r4, #0 8000678: d10f bne.n 800069a <__aeabi_dmul+0x1c2> 800067a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800067e: 0040 lsls r0, r0, #1 8000680: eb41 0101 adc.w r1, r1, r1 8000684: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000688: bf08 it eq 800068a: 3c01 subeq r4, #1 800068c: d0f7 beq.n 800067e <__aeabi_dmul+0x1a6> 800068e: ea41 0106 orr.w r1, r1, r6 8000692: f095 0f00 teq r5, #0 8000696: bf18 it ne 8000698: 4770 bxne lr 800069a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800069e: 0052 lsls r2, r2, #1 80006a0: eb43 0303 adc.w r3, r3, r3 80006a4: f413 1f80 tst.w r3, #1048576 ; 0x100000 80006a8: bf08 it eq 80006aa: 3d01 subeq r5, #1 80006ac: d0f7 beq.n 800069e <__aeabi_dmul+0x1c6> 80006ae: ea43 0306 orr.w r3, r3, r6 80006b2: 4770 bx lr 80006b4: ea94 0f0c teq r4, ip 80006b8: ea0c 5513 and.w r5, ip, r3, lsr #20 80006bc: bf18 it ne 80006be: ea95 0f0c teqne r5, ip 80006c2: d00c beq.n 80006de <__aeabi_dmul+0x206> 80006c4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006c8: bf18 it ne 80006ca: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006ce: d1d1 bne.n 8000674 <__aeabi_dmul+0x19c> 80006d0: ea81 0103 eor.w r1, r1, r3 80006d4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006d8: f04f 0000 mov.w r0, #0 80006dc: bd70 pop {r4, r5, r6, pc} 80006de: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006e2: bf06 itte eq 80006e4: 4610 moveq r0, r2 80006e6: 4619 moveq r1, r3 80006e8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006ec: d019 beq.n 8000722 <__aeabi_dmul+0x24a> 80006ee: ea94 0f0c teq r4, ip 80006f2: d102 bne.n 80006fa <__aeabi_dmul+0x222> 80006f4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80006f8: d113 bne.n 8000722 <__aeabi_dmul+0x24a> 80006fa: ea95 0f0c teq r5, ip 80006fe: d105 bne.n 800070c <__aeabi_dmul+0x234> 8000700: ea52 3603 orrs.w r6, r2, r3, lsl #12 8000704: bf1c itt ne 8000706: 4610 movne r0, r2 8000708: 4619 movne r1, r3 800070a: d10a bne.n 8000722 <__aeabi_dmul+0x24a> 800070c: ea81 0103 eor.w r1, r1, r3 8000710: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000714: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000718: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 800071c: f04f 0000 mov.w r0, #0 8000720: bd70 pop {r4, r5, r6, pc} 8000722: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000726: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 800072a: bd70 pop {r4, r5, r6, pc} 0800072c <__aeabi_ddiv>: 800072c: b570 push {r4, r5, r6, lr} 800072e: f04f 0cff mov.w ip, #255 ; 0xff 8000732: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8000736: ea1c 5411 ands.w r4, ip, r1, lsr #20 800073a: bf1d ittte ne 800073c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000740: ea94 0f0c teqne r4, ip 8000744: ea95 0f0c teqne r5, ip 8000748: f000 f8a7 bleq 800089a <__aeabi_ddiv+0x16e> 800074c: eba4 0405 sub.w r4, r4, r5 8000750: ea81 0e03 eor.w lr, r1, r3 8000754: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000758: ea4f 3101 mov.w r1, r1, lsl #12 800075c: f000 8088 beq.w 8000870 <__aeabi_ddiv+0x144> 8000760: ea4f 3303 mov.w r3, r3, lsl #12 8000764: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000768: ea45 1313 orr.w r3, r5, r3, lsr #4 800076c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000770: ea4f 2202 mov.w r2, r2, lsl #8 8000774: ea45 1511 orr.w r5, r5, r1, lsr #4 8000778: ea45 6510 orr.w r5, r5, r0, lsr #24 800077c: ea4f 2600 mov.w r6, r0, lsl #8 8000780: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000784: 429d cmp r5, r3 8000786: bf08 it eq 8000788: 4296 cmpeq r6, r2 800078a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800078e: f504 7440 add.w r4, r4, #768 ; 0x300 8000792: d202 bcs.n 800079a <__aeabi_ddiv+0x6e> 8000794: 085b lsrs r3, r3, #1 8000796: ea4f 0232 mov.w r2, r2, rrx 800079a: 1ab6 subs r6, r6, r2 800079c: eb65 0503 sbc.w r5, r5, r3 80007a0: 085b lsrs r3, r3, #1 80007a2: ea4f 0232 mov.w r2, r2, rrx 80007a6: f44f 1080 mov.w r0, #1048576 ; 0x100000 80007aa: f44f 2c00 mov.w ip, #524288 ; 0x80000 80007ae: ebb6 0e02 subs.w lr, r6, r2 80007b2: eb75 0e03 sbcs.w lr, r5, r3 80007b6: bf22 ittt cs 80007b8: 1ab6 subcs r6, r6, r2 80007ba: 4675 movcs r5, lr 80007bc: ea40 000c orrcs.w r0, r0, ip 80007c0: 085b lsrs r3, r3, #1 80007c2: ea4f 0232 mov.w r2, r2, rrx 80007c6: ebb6 0e02 subs.w lr, r6, r2 80007ca: eb75 0e03 sbcs.w lr, r5, r3 80007ce: bf22 ittt cs 80007d0: 1ab6 subcs r6, r6, r2 80007d2: 4675 movcs r5, lr 80007d4: ea40 005c orrcs.w r0, r0, ip, lsr #1 80007d8: 085b lsrs r3, r3, #1 80007da: ea4f 0232 mov.w r2, r2, rrx 80007de: ebb6 0e02 subs.w lr, r6, r2 80007e2: eb75 0e03 sbcs.w lr, r5, r3 80007e6: bf22 ittt cs 80007e8: 1ab6 subcs r6, r6, r2 80007ea: 4675 movcs r5, lr 80007ec: ea40 009c orrcs.w r0, r0, ip, lsr #2 80007f0: 085b lsrs r3, r3, #1 80007f2: ea4f 0232 mov.w r2, r2, rrx 80007f6: ebb6 0e02 subs.w lr, r6, r2 80007fa: eb75 0e03 sbcs.w lr, r5, r3 80007fe: bf22 ittt cs 8000800: 1ab6 subcs r6, r6, r2 8000802: 4675 movcs r5, lr 8000804: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000808: ea55 0e06 orrs.w lr, r5, r6 800080c: d018 beq.n 8000840 <__aeabi_ddiv+0x114> 800080e: ea4f 1505 mov.w r5, r5, lsl #4 8000812: ea45 7516 orr.w r5, r5, r6, lsr #28 8000816: ea4f 1606 mov.w r6, r6, lsl #4 800081a: ea4f 03c3 mov.w r3, r3, lsl #3 800081e: ea43 7352 orr.w r3, r3, r2, lsr #29 8000822: ea4f 02c2 mov.w r2, r2, lsl #3 8000826: ea5f 1c1c movs.w ip, ip, lsr #4 800082a: d1c0 bne.n 80007ae <__aeabi_ddiv+0x82> 800082c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000830: d10b bne.n 800084a <__aeabi_ddiv+0x11e> 8000832: ea41 0100 orr.w r1, r1, r0 8000836: f04f 0000 mov.w r0, #0 800083a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 800083e: e7b6 b.n 80007ae <__aeabi_ddiv+0x82> 8000840: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000844: bf04 itt eq 8000846: 4301 orreq r1, r0 8000848: 2000 moveq r0, #0 800084a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800084e: bf88 it hi 8000850: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000854: f63f aeaf bhi.w 80005b6 <__aeabi_dmul+0xde> 8000858: ebb5 0c03 subs.w ip, r5, r3 800085c: bf04 itt eq 800085e: ebb6 0c02 subseq.w ip, r6, r2 8000862: ea5f 0c50 movseq.w ip, r0, lsr #1 8000866: f150 0000 adcs.w r0, r0, #0 800086a: eb41 5104 adc.w r1, r1, r4, lsl #20 800086e: bd70 pop {r4, r5, r6, pc} 8000870: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000874: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000878: eb14 045c adds.w r4, r4, ip, lsr #1 800087c: bfc2 ittt gt 800087e: ebd4 050c rsbsgt r5, r4, ip 8000882: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000886: bd70 popgt {r4, r5, r6, pc} 8000888: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800088c: f04f 0e00 mov.w lr, #0 8000890: 3c01 subs r4, #1 8000892: e690 b.n 80005b6 <__aeabi_dmul+0xde> 8000894: ea45 0e06 orr.w lr, r5, r6 8000898: e68d b.n 80005b6 <__aeabi_dmul+0xde> 800089a: ea0c 5513 and.w r5, ip, r3, lsr #20 800089e: ea94 0f0c teq r4, ip 80008a2: bf08 it eq 80008a4: ea95 0f0c teqeq r5, ip 80008a8: f43f af3b beq.w 8000722 <__aeabi_dmul+0x24a> 80008ac: ea94 0f0c teq r4, ip 80008b0: d10a bne.n 80008c8 <__aeabi_ddiv+0x19c> 80008b2: ea50 3401 orrs.w r4, r0, r1, lsl #12 80008b6: f47f af34 bne.w 8000722 <__aeabi_dmul+0x24a> 80008ba: ea95 0f0c teq r5, ip 80008be: f47f af25 bne.w 800070c <__aeabi_dmul+0x234> 80008c2: 4610 mov r0, r2 80008c4: 4619 mov r1, r3 80008c6: e72c b.n 8000722 <__aeabi_dmul+0x24a> 80008c8: ea95 0f0c teq r5, ip 80008cc: d106 bne.n 80008dc <__aeabi_ddiv+0x1b0> 80008ce: ea52 3503 orrs.w r5, r2, r3, lsl #12 80008d2: f43f aefd beq.w 80006d0 <__aeabi_dmul+0x1f8> 80008d6: 4610 mov r0, r2 80008d8: 4619 mov r1, r3 80008da: e722 b.n 8000722 <__aeabi_dmul+0x24a> 80008dc: ea50 0641 orrs.w r6, r0, r1, lsl #1 80008e0: bf18 it ne 80008e2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80008e6: f47f aec5 bne.w 8000674 <__aeabi_dmul+0x19c> 80008ea: ea50 0441 orrs.w r4, r0, r1, lsl #1 80008ee: f47f af0d bne.w 800070c <__aeabi_dmul+0x234> 80008f2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80008f6: f47f aeeb bne.w 80006d0 <__aeabi_dmul+0x1f8> 80008fa: e712 b.n 8000722 <__aeabi_dmul+0x24a> 080008fc <__aeabi_d2iz>: 80008fc: ea4f 0241 mov.w r2, r1, lsl #1 8000900: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000904: d215 bcs.n 8000932 <__aeabi_d2iz+0x36> 8000906: d511 bpl.n 800092c <__aeabi_d2iz+0x30> 8000908: f46f 7378 mvn.w r3, #992 ; 0x3e0 800090c: ebb3 5262 subs.w r2, r3, r2, asr #21 8000910: d912 bls.n 8000938 <__aeabi_d2iz+0x3c> 8000912: ea4f 23c1 mov.w r3, r1, lsl #11 8000916: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 800091a: ea43 5350 orr.w r3, r3, r0, lsr #21 800091e: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000922: fa23 f002 lsr.w r0, r3, r2 8000926: bf18 it ne 8000928: 4240 negne r0, r0 800092a: 4770 bx lr 800092c: f04f 0000 mov.w r0, #0 8000930: 4770 bx lr 8000932: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000936: d105 bne.n 8000944 <__aeabi_d2iz+0x48> 8000938: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 800093c: bf08 it eq 800093e: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000942: 4770 bx lr 8000944: f04f 0000 mov.w r0, #0 8000948: 4770 bx lr 800094a: bf00 nop 0800094c <initM>: int16_t prevPeak = -1; int8_t overCtr = 0; void initM() { 800094c: b480 push {r7} 800094e: af00 add r7, sp, #0 absoluteCounter = 0; 8000950: 4b14 ldr r3, [pc, #80] ; (80009a4 <initM+0x58>) 8000952: 2200 movs r2, #0 8000954: 801a strh r2, [r3, #0] valuesCounter = 0; 8000956: 4b14 ldr r3, [pc, #80] ; (80009a8 <initM+0x5c>) 8000958: 2200 movs r2, #0 800095a: 801a strh r2, [r3, #0] prevValue = -1; 800095c: 4b13 ldr r3, [pc, #76] ; (80009ac <initM+0x60>) 800095e: f64f 72ff movw r2, #65535 ; 0xffff 8000962: 801a strh r2, [r3, #0] risingSequenceEnd = 0; 8000964: 4b12 ldr r3, [pc, #72] ; (80009b0 <initM+0x64>) 8000966: 2200 movs r2, #0 8000968: 801a strh r2, [r3, #0] medianCounter = 0; 800096a: 4b12 ldr r3, [pc, #72] ; (80009b4 <initM+0x68>) 800096c: 2200 movs r2, #0 800096e: 701a strb r2, [r3, #0] rising = 0; 8000970: 4b11 ldr r3, [pc, #68] ; (80009b8 <initM+0x6c>) 8000972: 2200 movs r2, #0 8000974: 701a strb r2, [r3, #0] bigRise = 0; 8000976: 4b11 ldr r3, [pc, #68] ; (80009bc <initM+0x70>) 8000978: 2200 movs r2, #0 800097a: 701a strb r2, [r3, #0] prevPeak = -1; 800097c: 4b10 ldr r3, [pc, #64] ; (80009c0 <initM+0x74>) 800097e: f64f 72ff movw r2, #65535 ; 0xffff 8000982: 801a strh r2, [r3, #0] overCtr = 0; 8000984: 4b0f ldr r3, [pc, #60] ; (80009c4 <initM+0x78>) 8000986: 2200 movs r2, #0 8000988: 701a strb r2, [r3, #0] jPrev = 255; 800098a: 4b0f ldr r3, [pc, #60] ; (80009c8 <initM+0x7c>) 800098c: 22ff movs r2, #255 ; 0xff 800098e: 701a strb r2, [r3, #0] uppers = 0, equals = 0; 8000990: 4b0e ldr r3, [pc, #56] ; (80009cc <initM+0x80>) 8000992: 2200 movs r2, #0 8000994: 701a strb r2, [r3, #0] 8000996: 4b0e ldr r3, [pc, #56] ; (80009d0 <initM+0x84>) 8000998: 2200 movs r2, #0 800099a: 701a strb r2, [r3, #0] } 800099c: bf00 nop 800099e: 46bd mov sp, r7 80009a0: bc80 pop {r7} 80009a2: 4770 bx lr 80009a4: 200003bc .word 0x200003bc 80009a8: 200003be .word 0x200003be 80009ac: 20000000 .word 0x20000000 80009b0: 200003c0 .word 0x200003c0 80009b4: 200003e8 .word 0x200003e8 80009b8: 200003e9 .word 0x200003e9 80009bc: 200003ea .word 0x200003ea 80009c0: 20000004 .word 0x20000004 80009c4: 200003ef .word 0x200003ef 80009c8: 20000002 .word 0x20000002 80009cc: 200003ed .word 0x200003ed 80009d0: 200003ee .word 0x200003ee 80009d4: 00000000 .word 0x00000000 080009d8 <ADCToPressure>: int16_t ADCToPressure(int16_t value) { 80009d8: b580 push {r7, lr} 80009da: b082 sub sp, #8 80009dc: af00 add r7, sp, #0 80009de: 4603 mov r3, r0 80009e0: 80fb strh r3, [r7, #6] return value * 0.1675; 80009e2: f9b7 3006 ldrsh.w r3, [r7, #6] 80009e6: 4618 mov r0, r3 80009e8: f7ff fd0c bl 8000404 <__aeabi_i2d> 80009ec: a308 add r3, pc, #32 ; (adr r3, 8000a10 <ADCToPressure+0x38>) 80009ee: e9d3 2300 ldrd r2, r3, [r3] 80009f2: f7ff fd71 bl 80004d8 <__aeabi_dmul> 80009f6: 4602 mov r2, r0 80009f8: 460b mov r3, r1 80009fa: 4610 mov r0, r2 80009fc: 4619 mov r1, r3 80009fe: f7ff ff7d bl 80008fc <__aeabi_d2iz> 8000a02: 4603 mov r3, r0 8000a04: b21b sxth r3, r3 } 8000a06: 4618 mov r0, r3 8000a08: 3708 adds r7, #8 8000a0a: 46bd mov sp, r7 8000a0c: bd80 pop {r7, pc} 8000a0e: bf00 nop 8000a10: d70a3d71 .word 0xd70a3d71 8000a14: 3fc570a3 .word 0x3fc570a3 08000a18 <setData>: int16_t setData(int16_t value, int16_t pressure) { 8000a18: b480 push {r7} 8000a1a: b083 sub sp, #12 8000a1c: af00 add r7, sp, #0 8000a1e: 4603 mov r3, r0 8000a20: 460a mov r2, r1 8000a22: 80fb strh r3, [r7, #6] 8000a24: 4613 mov r3, r2 8000a26: 80bb strh r3, [r7, #4] if (value >= 730) 8000a28: f9b7 3006 ldrsh.w r3, [r7, #6] 8000a2c: f240 22d9 movw r2, #729 ; 0x2d9 8000a30: 4293 cmp r3, r2 8000a32: dd05 ble.n 8000a40 <setData+0x28> value -= 730; 8000a34: 88fb ldrh r3, [r7, #6] 8000a36: f2a3 23da subw r3, r3, #730 ; 0x2da 8000a3a: b29b uxth r3, r3 8000a3c: 80fb strh r3, [r7, #6] 8000a3e: e001 b.n 8000a44 <setData+0x2c> else value = 0; 8000a40: 2300 movs r3, #0 8000a42: 80fb strh r3, [r7, #6] pressure -= 31; 8000a44: 88bb ldrh r3, [r7, #4] 8000a46: 3b1f subs r3, #31 8000a48: b29b uxth r3, r3 8000a4a: 80bb strh r3, [r7, #4] absoluteCounter++; 8000a4c: 4b7a ldr r3, [pc, #488] ; (8000c38 <setData+0x220>) 8000a4e: f9b3 3000 ldrsh.w r3, [r3] 8000a52: b29b uxth r3, r3 8000a54: 3301 adds r3, #1 8000a56: b29b uxth r3, r3 8000a58: b21a sxth r2, r3 8000a5a: 4b77 ldr r3, [pc, #476] ; (8000c38 <setData+0x220>) 8000a5c: 801a strh r2, [r3, #0] //Console.WriteLine(peaksM[1]); if (prevValue < value) 8000a5e: 4b77 ldr r3, [pc, #476] ; (8000c3c <setData+0x224>) 8000a60: f9b3 3000 ldrsh.w r3, [r3] 8000a64: f9b7 2006 ldrsh.w r2, [r7, #6] 8000a68: 429a cmp r2, r3 8000a6a: dd1b ble.n 8000aa4 <setData+0x8c> { //Console.WriteLine(ADCToPressure(value)); bigRise |= ((value - prevValue) >= 10 / 0.1675 ? 1 : 0); 8000a6c: f9b7 3006 ldrsh.w r3, [r7, #6] 8000a70: 4a72 ldr r2, [pc, #456] ; (8000c3c <setData+0x224>) 8000a72: f9b2 2000 ldrsh.w r2, [r2] 8000a76: 1a9b subs r3, r3, r2 8000a78: 2b3b cmp r3, #59 ; 0x3b 8000a7a: bfcc ite gt 8000a7c: 2301 movgt r3, #1 8000a7e: 2300 movle r3, #0 8000a80: b2db uxtb r3, r3 8000a82: b25a sxtb r2, r3 8000a84: 4b6e ldr r3, [pc, #440] ; (8000c40 <setData+0x228>) 8000a86: f993 3000 ldrsb.w r3, [r3] 8000a8a: 4313 orrs r3, r2 8000a8c: b25a sxtb r2, r3 8000a8e: 4b6c ldr r3, [pc, #432] ; (8000c40 <setData+0x228>) 8000a90: 701a strb r2, [r3, #0] if (bigRise == 1) ; rising++; 8000a92: 4b6c ldr r3, [pc, #432] ; (8000c44 <setData+0x22c>) 8000a94: f993 3000 ldrsb.w r3, [r3] 8000a98: b2db uxtb r3, r3 8000a9a: 3301 adds r3, #1 8000a9c: b2db uxtb r3, r3 8000a9e: b25a sxtb r2, r3 8000aa0: 4b68 ldr r3, [pc, #416] ; (8000c44 <setData+0x22c>) 8000aa2: 701a strb r2, [r3, #0] } if (absoluteCounter > 100 && rising >= 3 && prevValue > value && bigRise == 1) 8000aa4: 4b64 ldr r3, [pc, #400] ; (8000c38 <setData+0x220>) 8000aa6: f9b3 3000 ldrsh.w r3, [r3] 8000aaa: 2b64 cmp r3, #100 ; 0x64 8000aac: f340 8210 ble.w 8000ed0 <setData+0x4b8> 8000ab0: 4b64 ldr r3, [pc, #400] ; (8000c44 <setData+0x22c>) 8000ab2: f993 3000 ldrsb.w r3, [r3] 8000ab6: 2b02 cmp r3, #2 8000ab8: f340 820a ble.w 8000ed0 <setData+0x4b8> 8000abc: 4b5f ldr r3, [pc, #380] ; (8000c3c <setData+0x224>) 8000abe: f9b3 3000 ldrsh.w r3, [r3] 8000ac2: f9b7 2006 ldrsh.w r2, [r7, #6] 8000ac6: 429a cmp r2, r3 8000ac8: f280 8202 bge.w 8000ed0 <setData+0x4b8> 8000acc: 4b5c ldr r3, [pc, #368] ; (8000c40 <setData+0x228>) 8000ace: f993 3000 ldrsb.w r3, [r3] 8000ad2: 2b01 cmp r3, #1 8000ad4: f040 81fc bne.w 8000ed0 <setData+0x4b8> { //if (prevValue < 50 / 0.1675) // ; rising = 0; 8000ad8: 4b5a ldr r3, [pc, #360] ; (8000c44 <setData+0x22c>) 8000ada: 2200 movs r2, #0 8000adc: 701a strb r2, [r3, #0] bigRise = 0; 8000ade: 4b58 ldr r3, [pc, #352] ; (8000c40 <setData+0x228>) 8000ae0: 2200 movs r2, #0 8000ae2: 701a strb r2, [r3, #0] if (medianCounter < MEDIAN_SIZE) 8000ae4: 4b58 ldr r3, [pc, #352] ; (8000c48 <setData+0x230>) 8000ae6: f993 3000 ldrsb.w r3, [r3] 8000aea: 2b05 cmp r3, #5 8000aec: dc08 bgt.n 8000b00 <setData+0xe8> medianCounter++; 8000aee: 4b56 ldr r3, [pc, #344] ; (8000c48 <setData+0x230>) 8000af0: f993 3000 ldrsb.w r3, [r3] 8000af4: b2db uxtb r3, r3 8000af6: 3301 adds r3, #1 8000af8: b2db uxtb r3, r3 8000afa: b25a sxtb r2, r3 8000afc: 4b52 ldr r3, [pc, #328] ; (8000c48 <setData+0x230>) 8000afe: 701a strb r2, [r3, #0] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000b00: 4b52 ldr r3, [pc, #328] ; (8000c4c <setData+0x234>) 8000b02: 2200 movs r2, #0 8000b04: 701a strb r2, [r3, #0] 8000b06: e016 b.n 8000b36 <setData+0x11e> medianBuffer[j] = medianBuffer[j+1]; 8000b08: 4b50 ldr r3, [pc, #320] ; (8000c4c <setData+0x234>) 8000b0a: f993 3000 ldrsb.w r3, [r3] 8000b0e: 3301 adds r3, #1 8000b10: 4a4e ldr r2, [pc, #312] ; (8000c4c <setData+0x234>) 8000b12: f992 2000 ldrsb.w r2, [r2] 8000b16: 4611 mov r1, r2 8000b18: 4a4d ldr r2, [pc, #308] ; (8000c50 <setData+0x238>) 8000b1a: f932 2013 ldrsh.w r2, [r2, r3, lsl #1] 8000b1e: 4b4c ldr r3, [pc, #304] ; (8000c50 <setData+0x238>) 8000b20: f823 2011 strh.w r2, [r3, r1, lsl #1] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000b24: 4b49 ldr r3, [pc, #292] ; (8000c4c <setData+0x234>) 8000b26: f993 3000 ldrsb.w r3, [r3] 8000b2a: b2db uxtb r3, r3 8000b2c: 3301 adds r3, #1 8000b2e: b2db uxtb r3, r3 8000b30: b25a sxtb r2, r3 8000b32: 4b46 ldr r3, [pc, #280] ; (8000c4c <setData+0x234>) 8000b34: 701a strb r2, [r3, #0] 8000b36: 4b45 ldr r3, [pc, #276] ; (8000c4c <setData+0x234>) 8000b38: f993 3000 ldrsb.w r3, [r3] 8000b3c: 2b04 cmp r3, #4 8000b3e: dde3 ble.n 8000b08 <setData+0xf0> medianBuffer[MEDIAN_SIZE-1] = prevValue; 8000b40: 4b3e ldr r3, [pc, #248] ; (8000c3c <setData+0x224>) 8000b42: f9b3 2000 ldrsh.w r2, [r3] 8000b46: 4b42 ldr r3, [pc, #264] ; (8000c50 <setData+0x238>) 8000b48: 815a strh r2, [r3, #10] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000b4a: 4b40 ldr r3, [pc, #256] ; (8000c4c <setData+0x234>) 8000b4c: 2200 movs r2, #0 8000b4e: 701a strb r2, [r3, #0] 8000b50: e016 b.n 8000b80 <setData+0x168> pressuresBuffer[j] = pressuresBuffer[j + 1]; 8000b52: 4b3e ldr r3, [pc, #248] ; (8000c4c <setData+0x234>) 8000b54: f993 3000 ldrsb.w r3, [r3] 8000b58: 3301 adds r3, #1 8000b5a: 4a3c ldr r2, [pc, #240] ; (8000c4c <setData+0x234>) 8000b5c: f992 2000 ldrsb.w r2, [r2] 8000b60: 4611 mov r1, r2 8000b62: 4a3c ldr r2, [pc, #240] ; (8000c54 <setData+0x23c>) 8000b64: f932 2013 ldrsh.w r2, [r2, r3, lsl #1] 8000b68: 4b3a ldr r3, [pc, #232] ; (8000c54 <setData+0x23c>) 8000b6a: f823 2011 strh.w r2, [r3, r1, lsl #1] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000b6e: 4b37 ldr r3, [pc, #220] ; (8000c4c <setData+0x234>) 8000b70: f993 3000 ldrsb.w r3, [r3] 8000b74: b2db uxtb r3, r3 8000b76: 3301 adds r3, #1 8000b78: b2db uxtb r3, r3 8000b7a: b25a sxtb r2, r3 8000b7c: 4b33 ldr r3, [pc, #204] ; (8000c4c <setData+0x234>) 8000b7e: 701a strb r2, [r3, #0] 8000b80: 4b32 ldr r3, [pc, #200] ; (8000c4c <setData+0x234>) 8000b82: f993 3000 ldrsb.w r3, [r3] 8000b86: 2b04 cmp r3, #4 8000b88: dde3 ble.n 8000b52 <setData+0x13a> pressuresBuffer[MEDIAN_SIZE - 1] = pressure; 8000b8a: 4a32 ldr r2, [pc, #200] ; (8000c54 <setData+0x23c>) 8000b8c: 88bb ldrh r3, [r7, #4] 8000b8e: 8153 strh r3, [r2, #10] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000b90: 4b2e ldr r3, [pc, #184] ; (8000c4c <setData+0x234>) 8000b92: 2200 movs r2, #0 8000b94: 701a strb r2, [r3, #0] 8000b96: e016 b.n 8000bc6 <setData+0x1ae> countersBuffer[j] = countersBuffer[j + 1]; 8000b98: 4b2c ldr r3, [pc, #176] ; (8000c4c <setData+0x234>) 8000b9a: f993 3000 ldrsb.w r3, [r3] 8000b9e: 3301 adds r3, #1 8000ba0: 4a2a ldr r2, [pc, #168] ; (8000c4c <setData+0x234>) 8000ba2: f992 2000 ldrsb.w r2, [r2] 8000ba6: 4611 mov r1, r2 8000ba8: 4a2b ldr r2, [pc, #172] ; (8000c58 <setData+0x240>) 8000baa: f932 2013 ldrsh.w r2, [r2, r3, lsl #1] 8000bae: 4b2a ldr r3, [pc, #168] ; (8000c58 <setData+0x240>) 8000bb0: f823 2011 strh.w r2, [r3, r1, lsl #1] for (j = 0; j < MEDIAN_SIZE - 1; ++j) 8000bb4: 4b25 ldr r3, [pc, #148] ; (8000c4c <setData+0x234>) 8000bb6: f993 3000 ldrsb.w r3, [r3] 8000bba: b2db uxtb r3, r3 8000bbc: 3301 adds r3, #1 8000bbe: b2db uxtb r3, r3 8000bc0: b25a sxtb r2, r3 8000bc2: 4b22 ldr r3, [pc, #136] ; (8000c4c <setData+0x234>) 8000bc4: 701a strb r2, [r3, #0] 8000bc6: 4b21 ldr r3, [pc, #132] ; (8000c4c <setData+0x234>) 8000bc8: f993 3000 ldrsb.w r3, [r3] 8000bcc: 2b04 cmp r3, #4 8000bce: dde3 ble.n 8000b98 <setData+0x180> countersBuffer[MEDIAN_SIZE - 1] = absoluteCounter; 8000bd0: 4b19 ldr r3, [pc, #100] ; (8000c38 <setData+0x220>) 8000bd2: f9b3 2000 ldrsh.w r2, [r3] 8000bd6: 4b20 ldr r3, [pc, #128] ; (8000c58 <setData+0x240>) 8000bd8: 815a strh r2, [r3, #10] if (medianCounter < MEDIAN_SIZE) 8000bda: 4b1b ldr r3, [pc, #108] ; (8000c48 <setData+0x230>) 8000bdc: f993 3000 ldrsb.w r3, [r3] 8000be0: 2b05 cmp r3, #5 8000be2: dc01 bgt.n 8000be8 <setData+0x1d0> return 0; 8000be4: 2300 movs r3, #0 8000be6: e188 b.n 8000efa <setData+0x4e2> for (j = 0; j != MEDIAN_SIZE; ++j) 8000be8: 4b18 ldr r3, [pc, #96] ; (8000c4c <setData+0x234>) 8000bea: 2200 movs r2, #0 8000bec: 701a strb r2, [r3, #0] 8000bee: e07a b.n 8000ce6 <setData+0x2ce> { uppers = 0; 8000bf0: 4b1a ldr r3, [pc, #104] ; (8000c5c <setData+0x244>) 8000bf2: 2200 movs r2, #0 8000bf4: 701a strb r2, [r3, #0] equals = 0; 8000bf6: 4b1a ldr r3, [pc, #104] ; (8000c60 <setData+0x248>) 8000bf8: 2200 movs r2, #0 8000bfa: 701a strb r2, [r3, #0] for (k = 0; k != MEDIAN_SIZE; ++k) 8000bfc: 4b19 ldr r3, [pc, #100] ; (8000c64 <setData+0x24c>) 8000bfe: 2200 movs r2, #0 8000c00: 701a strb r2, [r3, #0] 8000c02: e053 b.n 8000cac <setData+0x294> if (medianBuffer[j] < medianBuffer[k]) 8000c04: 4b11 ldr r3, [pc, #68] ; (8000c4c <setData+0x234>) 8000c06: f993 3000 ldrsb.w r3, [r3] 8000c0a: 461a mov r2, r3 8000c0c: 4b10 ldr r3, [pc, #64] ; (8000c50 <setData+0x238>) 8000c0e: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000c12: 4b14 ldr r3, [pc, #80] ; (8000c64 <setData+0x24c>) 8000c14: f993 3000 ldrsb.w r3, [r3] 8000c18: 4619 mov r1, r3 8000c1a: 4b0d ldr r3, [pc, #52] ; (8000c50 <setData+0x238>) 8000c1c: f933 3011 ldrsh.w r3, [r3, r1, lsl #1] 8000c20: 429a cmp r2, r3 8000c22: da21 bge.n 8000c68 <setData+0x250> ++uppers; 8000c24: 4b0d ldr r3, [pc, #52] ; (8000c5c <setData+0x244>) 8000c26: f993 3000 ldrsb.w r3, [r3] 8000c2a: b2db uxtb r3, r3 8000c2c: 3301 adds r3, #1 8000c2e: b2db uxtb r3, r3 8000c30: b25a sxtb r2, r3 8000c32: 4b0a ldr r3, [pc, #40] ; (8000c5c <setData+0x244>) 8000c34: 701a strb r2, [r3, #0] 8000c36: e030 b.n 8000c9a <setData+0x282> 8000c38: 200003bc .word 0x200003bc 8000c3c: 20000000 .word 0x20000000 8000c40: 200003ea .word 0x200003ea 8000c44: 200003e9 .word 0x200003e9 8000c48: 200003e8 .word 0x200003e8 8000c4c: 200003eb .word 0x200003eb 8000c50: 200003c4 .word 0x200003c4 8000c54: 200003dc .word 0x200003dc 8000c58: 200003d0 .word 0x200003d0 8000c5c: 200003ed .word 0x200003ed 8000c60: 200003ee .word 0x200003ee 8000c64: 200003ec .word 0x200003ec else if (medianBuffer[j] == medianBuffer[k]) 8000c68: 4ba6 ldr r3, [pc, #664] ; (8000f04 <setData+0x4ec>) 8000c6a: f993 3000 ldrsb.w r3, [r3] 8000c6e: 461a mov r2, r3 8000c70: 4ba5 ldr r3, [pc, #660] ; (8000f08 <setData+0x4f0>) 8000c72: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000c76: 4ba5 ldr r3, [pc, #660] ; (8000f0c <setData+0x4f4>) 8000c78: f993 3000 ldrsb.w r3, [r3] 8000c7c: 4619 mov r1, r3 8000c7e: 4ba2 ldr r3, [pc, #648] ; (8000f08 <setData+0x4f0>) 8000c80: f933 3011 ldrsh.w r3, [r3, r1, lsl #1] 8000c84: 429a cmp r2, r3 8000c86: d108 bne.n 8000c9a <setData+0x282> ++equals; 8000c88: 4ba1 ldr r3, [pc, #644] ; (8000f10 <setData+0x4f8>) 8000c8a: f993 3000 ldrsb.w r3, [r3] 8000c8e: b2db uxtb r3, r3 8000c90: 3301 adds r3, #1 8000c92: b2db uxtb r3, r3 8000c94: b25a sxtb r2, r3 8000c96: 4b9e ldr r3, [pc, #632] ; (8000f10 <setData+0x4f8>) 8000c98: 701a strb r2, [r3, #0] for (k = 0; k != MEDIAN_SIZE; ++k) 8000c9a: 4b9c ldr r3, [pc, #624] ; (8000f0c <setData+0x4f4>) 8000c9c: f993 3000 ldrsb.w r3, [r3] 8000ca0: b2db uxtb r3, r3 8000ca2: 3301 adds r3, #1 8000ca4: b2db uxtb r3, r3 8000ca6: b25a sxtb r2, r3 8000ca8: 4b98 ldr r3, [pc, #608] ; (8000f0c <setData+0x4f4>) 8000caa: 701a strb r2, [r3, #0] 8000cac: 4b97 ldr r3, [pc, #604] ; (8000f0c <setData+0x4f4>) 8000cae: f993 3000 ldrsb.w r3, [r3] 8000cb2: 2b06 cmp r3, #6 8000cb4: d1a6 bne.n 8000c04 <setData+0x1ec> if (uppers == 2 || uppers == 1 && equals > 1) 8000cb6: 4b97 ldr r3, [pc, #604] ; (8000f14 <setData+0x4fc>) 8000cb8: f993 3000 ldrsb.w r3, [r3] 8000cbc: 2b02 cmp r3, #2 8000cbe: d018 beq.n 8000cf2 <setData+0x2da> 8000cc0: 4b94 ldr r3, [pc, #592] ; (8000f14 <setData+0x4fc>) 8000cc2: f993 3000 ldrsb.w r3, [r3] 8000cc6: 2b01 cmp r3, #1 8000cc8: d104 bne.n 8000cd4 <setData+0x2bc> 8000cca: 4b91 ldr r3, [pc, #580] ; (8000f10 <setData+0x4f8>) 8000ccc: f993 3000 ldrsb.w r3, [r3] 8000cd0: 2b01 cmp r3, #1 8000cd2: dc0e bgt.n 8000cf2 <setData+0x2da> for (j = 0; j != MEDIAN_SIZE; ++j) 8000cd4: 4b8b ldr r3, [pc, #556] ; (8000f04 <setData+0x4ec>) 8000cd6: f993 3000 ldrsb.w r3, [r3] 8000cda: b2db uxtb r3, r3 8000cdc: 3301 adds r3, #1 8000cde: b2db uxtb r3, r3 8000ce0: b25a sxtb r2, r3 8000ce2: 4b88 ldr r3, [pc, #544] ; (8000f04 <setData+0x4ec>) 8000ce4: 701a strb r2, [r3, #0] 8000ce6: 4b87 ldr r3, [pc, #540] ; (8000f04 <setData+0x4ec>) 8000ce8: f993 3000 ldrsb.w r3, [r3] 8000cec: 2b06 cmp r3, #6 8000cee: f47f af7f bne.w 8000bf0 <setData+0x1d8> break; } //Console.WriteLine(j); prevValue = medianBuffer[j]; 8000cf2: 4b84 ldr r3, [pc, #528] ; (8000f04 <setData+0x4ec>) 8000cf4: f993 3000 ldrsb.w r3, [r3] 8000cf8: 461a mov r2, r3 8000cfa: 4b83 ldr r3, [pc, #524] ; (8000f08 <setData+0x4f0>) 8000cfc: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000d00: 4b85 ldr r3, [pc, #532] ; (8000f18 <setData+0x500>) 8000d02: 801a strh r2, [r3, #0] if (peaksM[risingSequenceEnd] > 50 && overCtr < 3 && prevPeak != -1 && abs(prevValue - prevPeak) >= 300) 8000d04: 4b85 ldr r3, [pc, #532] ; (8000f1c <setData+0x504>) 8000d06: f9b3 3000 ldrsh.w r3, [r3] 8000d0a: 461a mov r2, r3 8000d0c: 4b84 ldr r3, [pc, #528] ; (8000f20 <setData+0x508>) 8000d0e: f933 3012 ldrsh.w r3, [r3, r2, lsl #1] 8000d12: 2b32 cmp r3, #50 ; 0x32 8000d14: dd2b ble.n 8000d6e <setData+0x356> 8000d16: 4b83 ldr r3, [pc, #524] ; (8000f24 <setData+0x50c>) 8000d18: f993 3000 ldrsb.w r3, [r3] 8000d1c: 2b02 cmp r3, #2 8000d1e: dc26 bgt.n 8000d6e <setData+0x356> 8000d20: 4b81 ldr r3, [pc, #516] ; (8000f28 <setData+0x510>) 8000d22: f9b3 3000 ldrsh.w r3, [r3] 8000d26: f1b3 3fff cmp.w r3, #4294967295 8000d2a: d020 beq.n 8000d6e <setData+0x356> 8000d2c: 4b7a ldr r3, [pc, #488] ; (8000f18 <setData+0x500>) 8000d2e: f9b3 3000 ldrsh.w r3, [r3] 8000d32: 461a mov r2, r3 8000d34: 4b7c ldr r3, [pc, #496] ; (8000f28 <setData+0x510>) 8000d36: f9b3 3000 ldrsh.w r3, [r3] 8000d3a: 1ad3 subs r3, r2, r3 8000d3c: 2b00 cmp r3, #0 8000d3e: bfb8 it lt 8000d40: 425b neglt r3, r3 8000d42: f5b3 7f96 cmp.w r3, #300 ; 0x12c 8000d46: db12 blt.n 8000d6e <setData+0x356> { overCtr++; 8000d48: 4b76 ldr r3, [pc, #472] ; (8000f24 <setData+0x50c>) 8000d4a: f993 3000 ldrsb.w r3, [r3] 8000d4e: b2db uxtb r3, r3 8000d50: 3301 adds r3, #1 8000d52: b2db uxtb r3, r3 8000d54: b25a sxtb r2, r3 8000d56: 4b73 ldr r3, [pc, #460] ; (8000f24 <setData+0x50c>) 8000d58: 701a strb r2, [r3, #0] jPrev--; 8000d5a: 4b74 ldr r3, [pc, #464] ; (8000f2c <setData+0x514>) 8000d5c: f993 3000 ldrsb.w r3, [r3] 8000d60: b2db uxtb r3, r3 8000d62: 3b01 subs r3, #1 8000d64: b2db uxtb r3, r3 8000d66: b25a sxtb r2, r3 8000d68: 4b70 ldr r3, [pc, #448] ; (8000f2c <setData+0x514>) 8000d6a: 701a strb r2, [r3, #0] goto end; 8000d6c: e0c1 b.n 8000ef2 <setData+0x4da> } //if (overCtr == 3) // ; overCtr = 0; 8000d6e: 4b6d ldr r3, [pc, #436] ; (8000f24 <setData+0x50c>) 8000d70: 2200 movs r2, #0 8000d72: 701a strb r2, [r3, #0] if (jPrev < MEDIAN_SIZE && jPrev != 0 && j < jPrev-1) 8000d74: 4b6d ldr r3, [pc, #436] ; (8000f2c <setData+0x514>) 8000d76: f993 3000 ldrsb.w r3, [r3] 8000d7a: 2b05 cmp r3, #5 8000d7c: dc18 bgt.n 8000db0 <setData+0x398> 8000d7e: 4b6b ldr r3, [pc, #428] ; (8000f2c <setData+0x514>) 8000d80: f993 3000 ldrsb.w r3, [r3] 8000d84: 2b00 cmp r3, #0 8000d86: d013 beq.n 8000db0 <setData+0x398> 8000d88: 4b5e ldr r3, [pc, #376] ; (8000f04 <setData+0x4ec>) 8000d8a: f993 3000 ldrsb.w r3, [r3] 8000d8e: 461a mov r2, r3 8000d90: 4b66 ldr r3, [pc, #408] ; (8000f2c <setData+0x514>) 8000d92: f993 3000 ldrsb.w r3, [r3] 8000d96: 3b01 subs r3, #1 8000d98: 429a cmp r2, r3 8000d9a: da09 bge.n 8000db0 <setData+0x398> { jPrev--; 8000d9c: 4b63 ldr r3, [pc, #396] ; (8000f2c <setData+0x514>) 8000d9e: f993 3000 ldrsb.w r3, [r3] 8000da2: b2db uxtb r3, r3 8000da4: 3b01 subs r3, #1 8000da6: b2db uxtb r3, r3 8000da8: b25a sxtb r2, r3 8000daa: 4b60 ldr r3, [pc, #384] ; (8000f2c <setData+0x514>) 8000dac: 701a strb r2, [r3, #0] goto end;// valuesCounter--; 8000dae: e0a0 b.n 8000ef2 <setData+0x4da> } jPrev = j; 8000db0: 4b54 ldr r3, [pc, #336] ; (8000f04 <setData+0x4ec>) 8000db2: f993 2000 ldrsb.w r2, [r3] 8000db6: 4b5d ldr r3, [pc, #372] ; (8000f2c <setData+0x514>) 8000db8: 701a strb r2, [r3, #0] prevPeak = prevValue; 8000dba: 4b57 ldr r3, [pc, #348] ; (8000f18 <setData+0x500>) 8000dbc: f9b3 2000 ldrsh.w r2, [r3] 8000dc0: 4b59 ldr r3, [pc, #356] ; (8000f28 <setData+0x510>) 8000dc2: 801a strh r2, [r3, #0] if (valuesCounter == 0) 8000dc4: 4b5a ldr r3, [pc, #360] ; (8000f30 <setData+0x518>) 8000dc6: f9b3 3000 ldrsh.w r3, [r3] 8000dca: 2b00 cmp r3, #0 8000dcc: d114 bne.n 8000df8 <setData+0x3e0> { peaksM[0] = prevValue; 8000dce: 4b52 ldr r3, [pc, #328] ; (8000f18 <setData+0x500>) 8000dd0: f9b3 2000 ldrsh.w r2, [r3] 8000dd4: 4b52 ldr r3, [pc, #328] ; (8000f20 <setData+0x508>) 8000dd6: 801a strh r2, [r3, #0] pressuresM[0] = pressuresBuffer[j]; 8000dd8: 4b4a ldr r3, [pc, #296] ; (8000f04 <setData+0x4ec>) 8000dda: f993 3000 ldrsb.w r3, [r3] 8000dde: 461a mov r2, r3 8000de0: 4b54 ldr r3, [pc, #336] ; (8000f34 <setData+0x51c>) 8000de2: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000de6: 4b54 ldr r3, [pc, #336] ; (8000f38 <setData+0x520>) 8000de8: 801a strh r2, [r3, #0] valuesCounter = 1; 8000dea: 4b51 ldr r3, [pc, #324] ; (8000f30 <setData+0x518>) 8000dec: 2201 movs r2, #1 8000dee: 801a strh r2, [r3, #0] risingSequenceEnd = 0; 8000df0: 4b4a ldr r3, [pc, #296] ; (8000f1c <setData+0x504>) 8000df2: 2200 movs r2, #0 8000df4: 801a strh r2, [r3, #0] if (valuesCounter == 0) 8000df6: e07c b.n 8000ef2 <setData+0x4da> } else { for (tmp = (valuesCounter - 1); tmp >= risingSequenceEnd; --tmp) 8000df8: 4b4d ldr r3, [pc, #308] ; (8000f30 <setData+0x518>) 8000dfa: f9b3 3000 ldrsh.w r3, [r3] 8000dfe: b29b uxth r3, r3 8000e00: 3b01 subs r3, #1 8000e02: b29b uxth r3, r3 8000e04: b21a sxth r2, r3 8000e06: 4b4d ldr r3, [pc, #308] ; (8000f3c <setData+0x524>) 8000e08: 801a strh r2, [r3, #0] 8000e0a: e020 b.n 8000e4e <setData+0x436> { if (prevValue == peaksM[tmp]) 8000e0c: 4b4b ldr r3, [pc, #300] ; (8000f3c <setData+0x524>) 8000e0e: f9b3 3000 ldrsh.w r3, [r3] 8000e12: 461a mov r2, r3 8000e14: 4b42 ldr r3, [pc, #264] ; (8000f20 <setData+0x508>) 8000e16: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000e1a: 4b3f ldr r3, [pc, #252] ; (8000f18 <setData+0x500>) 8000e1c: f9b3 3000 ldrsh.w r3, [r3] 8000e20: 429a cmp r2, r3 8000e22: d063 beq.n 8000eec <setData+0x4d4> goto end; if (prevValue < peaksM[tmp]) 8000e24: 4b45 ldr r3, [pc, #276] ; (8000f3c <setData+0x524>) 8000e26: f9b3 3000 ldrsh.w r3, [r3] 8000e2a: 461a mov r2, r3 8000e2c: 4b3c ldr r3, [pc, #240] ; (8000f20 <setData+0x508>) 8000e2e: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000e32: 4b39 ldr r3, [pc, #228] ; (8000f18 <setData+0x500>) 8000e34: f9b3 3000 ldrsh.w r3, [r3] 8000e38: 429a cmp r2, r3 8000e3a: dc11 bgt.n 8000e60 <setData+0x448> for (tmp = (valuesCounter - 1); tmp >= risingSequenceEnd; --tmp) 8000e3c: 4b3f ldr r3, [pc, #252] ; (8000f3c <setData+0x524>) 8000e3e: f9b3 3000 ldrsh.w r3, [r3] 8000e42: b29b uxth r3, r3 8000e44: 3b01 subs r3, #1 8000e46: b29b uxth r3, r3 8000e48: b21a sxth r2, r3 8000e4a: 4b3c ldr r3, [pc, #240] ; (8000f3c <setData+0x524>) 8000e4c: 801a strh r2, [r3, #0] 8000e4e: 4b3b ldr r3, [pc, #236] ; (8000f3c <setData+0x524>) 8000e50: f9b3 2000 ldrsh.w r2, [r3] 8000e54: 4b31 ldr r3, [pc, #196] ; (8000f1c <setData+0x504>) 8000e56: f9b3 3000 ldrsh.w r3, [r3] 8000e5a: 429a cmp r2, r3 8000e5c: dad6 bge.n 8000e0c <setData+0x3f4> 8000e5e: e000 b.n 8000e62 <setData+0x44a> { break; 8000e60: bf00 nop } } if (tmp == risingSequenceEnd-1) 8000e62: 4b36 ldr r3, [pc, #216] ; (8000f3c <setData+0x524>) 8000e64: f9b3 3000 ldrsh.w r3, [r3] 8000e68: 461a mov r2, r3 8000e6a: 4b2c ldr r3, [pc, #176] ; (8000f1c <setData+0x504>) 8000e6c: f9b3 3000 ldrsh.w r3, [r3] 8000e70: 3b01 subs r3, #1 8000e72: 429a cmp r2, r3 8000e74: d10a bne.n 8000e8c <setData+0x474> { tmp = risingSequenceEnd++; 8000e76: 4b29 ldr r3, [pc, #164] ; (8000f1c <setData+0x504>) 8000e78: f9b3 2000 ldrsh.w r2, [r3] 8000e7c: b293 uxth r3, r2 8000e7e: 3301 adds r3, #1 8000e80: b29b uxth r3, r3 8000e82: b219 sxth r1, r3 8000e84: 4b25 ldr r3, [pc, #148] ; (8000f1c <setData+0x504>) 8000e86: 8019 strh r1, [r3, #0] 8000e88: 4b2c ldr r3, [pc, #176] ; (8000f3c <setData+0x524>) 8000e8a: 801a strh r2, [r3, #0] } //Console.WriteLine(tmp); peaksM[tmp + 1] = prevValue; 8000e8c: 4b2b ldr r3, [pc, #172] ; (8000f3c <setData+0x524>) 8000e8e: f9b3 3000 ldrsh.w r3, [r3] 8000e92: 3301 adds r3, #1 8000e94: 4a20 ldr r2, [pc, #128] ; (8000f18 <setData+0x500>) 8000e96: f9b2 1000 ldrsh.w r1, [r2] 8000e9a: 4a21 ldr r2, [pc, #132] ; (8000f20 <setData+0x508>) 8000e9c: f822 1013 strh.w r1, [r2, r3, lsl #1] valuesCounter = (tmp + 2); 8000ea0: 4b26 ldr r3, [pc, #152] ; (8000f3c <setData+0x524>) 8000ea2: f9b3 3000 ldrsh.w r3, [r3] 8000ea6: b29b uxth r3, r3 8000ea8: 3302 adds r3, #2 8000eaa: b29b uxth r3, r3 8000eac: b21a sxth r2, r3 8000eae: 4b20 ldr r3, [pc, #128] ; (8000f30 <setData+0x518>) 8000eb0: 801a strh r2, [r3, #0] pressuresM[tmp + 1] = pressuresBuffer[j]; 8000eb2: 4b14 ldr r3, [pc, #80] ; (8000f04 <setData+0x4ec>) 8000eb4: f993 3000 ldrsb.w r3, [r3] 8000eb8: 4619 mov r1, r3 8000eba: 4b20 ldr r3, [pc, #128] ; (8000f3c <setData+0x524>) 8000ebc: f9b3 3000 ldrsh.w r3, [r3] 8000ec0: 3301 adds r3, #1 8000ec2: 4a1c ldr r2, [pc, #112] ; (8000f34 <setData+0x51c>) 8000ec4: f932 1011 ldrsh.w r1, [r2, r1, lsl #1] 8000ec8: 4a1b ldr r2, [pc, #108] ; (8000f38 <setData+0x520>) 8000eca: f822 1013 strh.w r1, [r2, r3, lsl #1] if (valuesCounter == 0) 8000ece: e010 b.n 8000ef2 <setData+0x4da> } } else if (prevValue > value) 8000ed0: 4b11 ldr r3, [pc, #68] ; (8000f18 <setData+0x500>) 8000ed2: f9b3 3000 ldrsh.w r3, [r3] 8000ed6: f9b7 2006 ldrsh.w r2, [r7, #6] 8000eda: 429a cmp r2, r3 8000edc: da08 bge.n 8000ef0 <setData+0x4d8> { bigRise = 0; 8000ede: 4b18 ldr r3, [pc, #96] ; (8000f40 <setData+0x528>) 8000ee0: 2200 movs r2, #0 8000ee2: 701a strb r2, [r3, #0] rising = 0; 8000ee4: 4b17 ldr r3, [pc, #92] ; (8000f44 <setData+0x52c>) 8000ee6: 2200 movs r2, #0 8000ee8: 701a strb r2, [r3, #0] 8000eea: e002 b.n 8000ef2 <setData+0x4da> goto end; 8000eec: bf00 nop 8000eee: e000 b.n 8000ef2 <setData+0x4da> } end: 8000ef0: bf00 nop prevValue = value; 8000ef2: 4a09 ldr r2, [pc, #36] ; (8000f18 <setData+0x500>) 8000ef4: 88fb ldrh r3, [r7, #6] 8000ef6: 8013 strh r3, [r2, #0] return 0; 8000ef8: 2300 movs r3, #0 } 8000efa: 4618 mov r0, r3 8000efc: 370c adds r7, #12 8000efe: 46bd mov sp, r7 8000f00: bc80 pop {r7} 8000f02: 4770 bx lr 8000f04: 200003eb .word 0x200003eb 8000f08: 200003c4 .word 0x200003c4 8000f0c: 200003ec .word 0x200003ec 8000f10: 200003ee .word 0x200003ee 8000f14: 200003ed .word 0x200003ed 8000f18: 20000000 .word 0x20000000 8000f1c: 200003c0 .word 0x200003c0 8000f20: 2000009c .word 0x2000009c 8000f24: 200003ef .word 0x200003ef 8000f28: 20000004 .word 0x20000004 8000f2c: 20000002 .word 0x20000002 8000f30: 200003be .word 0x200003be 8000f34: 200003dc .word 0x200003dc 8000f38: 2000022c .word 0x2000022c 8000f3c: 200003c2 .word 0x200003c2 8000f40: 200003ea .word 0x200003ea 8000f44: 200003e9 .word 0x200003e9 08000f48 <finalize>: const double diastolicMultiplier = 0.85; int16_t awaitedSystolic; int16_t awaitedDiatolic; AP finalize() { 8000f48: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 8000f4c: b082 sub sp, #8 8000f4e: af00 add r7, sp, #0 //valuesCounter -= 10; if (valuesCounter < 5) { 8000f50: 4b8d ldr r3, [pc, #564] ; (8001188 <finalize+0x240>) 8000f52: f9b3 3000 ldrsh.w r3, [r3] 8000f56: 2b04 cmp r3, #4 8000f58: dc09 bgt.n 8000f6e <finalize+0x26> currentAP.systolic = 0; 8000f5a: 4b8c ldr r3, [pc, #560] ; (800118c <finalize+0x244>) 8000f5c: 2200 movs r2, #0 8000f5e: 801a strh r2, [r3, #0] currentAP.diastolic = 0; 8000f60: 4b8a ldr r3, [pc, #552] ; (800118c <finalize+0x244>) 8000f62: 2200 movs r2, #0 8000f64: 805a strh r2, [r3, #2] return currentAP; 8000f66: 4b89 ldr r3, [pc, #548] ; (800118c <finalize+0x244>) 8000f68: 681b ldr r3, [r3, #0] 8000f6a: 607b str r3, [r7, #4] 8000f6c: e1c6 b.n 80012fc <finalize+0x3b4> // if (peaksM[i] > peaksM[i-1]) // { // } maxPeak = 0; 8000f6e: 4b88 ldr r3, [pc, #544] ; (8001190 <finalize+0x248>) 8000f70: 2200 movs r2, #0 8000f72: 801a strh r2, [r3, #0] for (i = 0; i < valuesCounter; ++i) 8000f74: 4b87 ldr r3, [pc, #540] ; (8001194 <finalize+0x24c>) 8000f76: 2200 movs r2, #0 8000f78: 801a strh r2, [r3, #0] 8000f7a: e01d b.n 8000fb8 <finalize+0x70> if (peaksM[i] > maxPeak) 8000f7c: 4b85 ldr r3, [pc, #532] ; (8001194 <finalize+0x24c>) 8000f7e: f9b3 3000 ldrsh.w r3, [r3] 8000f82: 461a mov r2, r3 8000f84: 4b84 ldr r3, [pc, #528] ; (8001198 <finalize+0x250>) 8000f86: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000f8a: 4b81 ldr r3, [pc, #516] ; (8001190 <finalize+0x248>) 8000f8c: f9b3 3000 ldrsh.w r3, [r3] 8000f90: 429a cmp r2, r3 8000f92: dd08 ble.n 8000fa6 <finalize+0x5e> maxPeak = peaksM[i]; 8000f94: 4b7f ldr r3, [pc, #508] ; (8001194 <finalize+0x24c>) 8000f96: f9b3 3000 ldrsh.w r3, [r3] 8000f9a: 461a mov r2, r3 8000f9c: 4b7e ldr r3, [pc, #504] ; (8001198 <finalize+0x250>) 8000f9e: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8000fa2: 4b7b ldr r3, [pc, #492] ; (8001190 <finalize+0x248>) 8000fa4: 801a strh r2, [r3, #0] for (i = 0; i < valuesCounter; ++i) 8000fa6: 4b7b ldr r3, [pc, #492] ; (8001194 <finalize+0x24c>) 8000fa8: f9b3 3000 ldrsh.w r3, [r3] 8000fac: b29b uxth r3, r3 8000fae: 3301 adds r3, #1 8000fb0: b29b uxth r3, r3 8000fb2: b21a sxth r2, r3 8000fb4: 4b77 ldr r3, [pc, #476] ; (8001194 <finalize+0x24c>) 8000fb6: 801a strh r2, [r3, #0] 8000fb8: 4b76 ldr r3, [pc, #472] ; (8001194 <finalize+0x24c>) 8000fba: f9b3 2000 ldrsh.w r2, [r3] 8000fbe: 4b72 ldr r3, [pc, #456] ; (8001188 <finalize+0x240>) 8000fc0: f9b3 3000 ldrsh.w r3, [r3] 8000fc4: 429a cmp r2, r3 8000fc6: dbd9 blt.n 8000f7c <finalize+0x34> awaitedSystolic = (int16_t)(maxPeak * systolicMultiplier); 8000fc8: 4b71 ldr r3, [pc, #452] ; (8001190 <finalize+0x248>) 8000fca: f9b3 3000 ldrsh.w r3, [r3] 8000fce: 4618 mov r0, r3 8000fd0: f7ff fa18 bl 8000404 <__aeabi_i2d> 8000fd4: f04f 0200 mov.w r2, #0 8000fd8: 4b70 ldr r3, [pc, #448] ; (800119c <finalize+0x254>) 8000fda: f7ff fa7d bl 80004d8 <__aeabi_dmul> 8000fde: 4602 mov r2, r0 8000fe0: 460b mov r3, r1 8000fe2: 4610 mov r0, r2 8000fe4: 4619 mov r1, r3 8000fe6: f7ff fc89 bl 80008fc <__aeabi_d2iz> 8000fea: 4603 mov r3, r0 8000fec: b21a sxth r2, r3 8000fee: 4b6c ldr r3, [pc, #432] ; (80011a0 <finalize+0x258>) 8000ff0: 801a strh r2, [r3, #0] awaitedDiatolic = (int16_t)(maxPeak * diastolicMultiplier); 8000ff2: 4b67 ldr r3, [pc, #412] ; (8001190 <finalize+0x248>) 8000ff4: f9b3 3000 ldrsh.w r3, [r3] 8000ff8: 4618 mov r0, r3 8000ffa: f7ff fa03 bl 8000404 <__aeabi_i2d> 8000ffe: a360 add r3, pc, #384 ; (adr r3, 8001180 <finalize+0x238>) 8001000: e9d3 2300 ldrd r2, r3, [r3] 8001004: f7ff fa68 bl 80004d8 <__aeabi_dmul> 8001008: 4602 mov r2, r0 800100a: 460b mov r3, r1 800100c: 4610 mov r0, r2 800100e: 4619 mov r1, r3 8001010: f7ff fc74 bl 80008fc <__aeabi_d2iz> 8001014: 4603 mov r3, r0 8001016: b21a sxth r2, r3 8001018: 4b62 ldr r3, [pc, #392] ; (80011a4 <finalize+0x25c>) 800101a: 801a strh r2, [r3, #0] i = 0; 800101c: 4b5d ldr r3, [pc, #372] ; (8001194 <finalize+0x24c>) 800101e: 2200 movs r2, #0 8001020: 801a strh r2, [r3, #0] while (i < valuesCounter && peaksM[i] < awaitedSystolic) ++i; 8001022: e008 b.n 8001036 <finalize+0xee> 8001024: 4b5b ldr r3, [pc, #364] ; (8001194 <finalize+0x24c>) 8001026: f9b3 3000 ldrsh.w r3, [r3] 800102a: b29b uxth r3, r3 800102c: 3301 adds r3, #1 800102e: b29b uxth r3, r3 8001030: b21a sxth r2, r3 8001032: 4b58 ldr r3, [pc, #352] ; (8001194 <finalize+0x24c>) 8001034: 801a strh r2, [r3, #0] 8001036: 4b57 ldr r3, [pc, #348] ; (8001194 <finalize+0x24c>) 8001038: f9b3 2000 ldrsh.w r2, [r3] 800103c: 4b52 ldr r3, [pc, #328] ; (8001188 <finalize+0x240>) 800103e: f9b3 3000 ldrsh.w r3, [r3] 8001042: 429a cmp r2, r3 8001044: da0b bge.n 800105e <finalize+0x116> 8001046: 4b53 ldr r3, [pc, #332] ; (8001194 <finalize+0x24c>) 8001048: f9b3 3000 ldrsh.w r3, [r3] 800104c: 461a mov r2, r3 800104e: 4b52 ldr r3, [pc, #328] ; (8001198 <finalize+0x250>) 8001050: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8001054: 4b52 ldr r3, [pc, #328] ; (80011a0 <finalize+0x258>) 8001056: f9b3 3000 ldrsh.w r3, [r3] 800105a: 429a cmp r2, r3 800105c: dbe2 blt.n 8001024 <finalize+0xdc> if (i == 0) ++i; 800105e: 4b4d ldr r3, [pc, #308] ; (8001194 <finalize+0x24c>) 8001060: f9b3 3000 ldrsh.w r3, [r3] 8001064: 2b00 cmp r3, #0 8001066: d108 bne.n 800107a <finalize+0x132> 8001068: 4b4a ldr r3, [pc, #296] ; (8001194 <finalize+0x24c>) 800106a: f9b3 3000 ldrsh.w r3, [r3] 800106e: b29b uxth r3, r3 8001070: 3301 adds r3, #1 8001072: b29b uxth r3, r3 8001074: b21a sxth r2, r3 8001076: 4b47 ldr r3, [pc, #284] ; (8001194 <finalize+0x24c>) 8001078: 801a strh r2, [r3, #0] currentAP.systolic = (int16_t)(pressuresM[i - 1] + (double)(pressuresM[i] - pressuresM[i - 1]) * (awaitedSystolic - peaksM[i - 1]) / (peaksM[i] - peaksM[i - 1])); 800107a: 4b46 ldr r3, [pc, #280] ; (8001194 <finalize+0x24c>) 800107c: f9b3 3000 ldrsh.w r3, [r3] 8001080: 3b01 subs r3, #1 8001082: 4a49 ldr r2, [pc, #292] ; (80011a8 <finalize+0x260>) 8001084: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 8001088: 4618 mov r0, r3 800108a: f7ff f9bb bl 8000404 <__aeabi_i2d> 800108e: 4604 mov r4, r0 8001090: 460d mov r5, r1 8001092: 4b40 ldr r3, [pc, #256] ; (8001194 <finalize+0x24c>) 8001094: f9b3 3000 ldrsh.w r3, [r3] 8001098: 461a mov r2, r3 800109a: 4b43 ldr r3, [pc, #268] ; (80011a8 <finalize+0x260>) 800109c: f933 3012 ldrsh.w r3, [r3, r2, lsl #1] 80010a0: 4619 mov r1, r3 80010a2: 4b3c ldr r3, [pc, #240] ; (8001194 <finalize+0x24c>) 80010a4: f9b3 3000 ldrsh.w r3, [r3] 80010a8: 3b01 subs r3, #1 80010aa: 4a3f ldr r2, [pc, #252] ; (80011a8 <finalize+0x260>) 80010ac: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 80010b0: 1acb subs r3, r1, r3 80010b2: 4618 mov r0, r3 80010b4: f7ff f9a6 bl 8000404 <__aeabi_i2d> 80010b8: 4680 mov r8, r0 80010ba: 4689 mov r9, r1 80010bc: 4b38 ldr r3, [pc, #224] ; (80011a0 <finalize+0x258>) 80010be: f9b3 3000 ldrsh.w r3, [r3] 80010c2: 4619 mov r1, r3 80010c4: 4b33 ldr r3, [pc, #204] ; (8001194 <finalize+0x24c>) 80010c6: f9b3 3000 ldrsh.w r3, [r3] 80010ca: 3b01 subs r3, #1 80010cc: 4a32 ldr r2, [pc, #200] ; (8001198 <finalize+0x250>) 80010ce: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 80010d2: 1acb subs r3, r1, r3 80010d4: 4618 mov r0, r3 80010d6: f7ff f995 bl 8000404 <__aeabi_i2d> 80010da: 4602 mov r2, r0 80010dc: 460b mov r3, r1 80010de: 4640 mov r0, r8 80010e0: 4649 mov r1, r9 80010e2: f7ff f9f9 bl 80004d8 <__aeabi_dmul> 80010e6: 4602 mov r2, r0 80010e8: 460b mov r3, r1 80010ea: 4690 mov r8, r2 80010ec: 4699 mov r9, r3 80010ee: 4b29 ldr r3, [pc, #164] ; (8001194 <finalize+0x24c>) 80010f0: f9b3 3000 ldrsh.w r3, [r3] 80010f4: 461a mov r2, r3 80010f6: 4b28 ldr r3, [pc, #160] ; (8001198 <finalize+0x250>) 80010f8: f933 3012 ldrsh.w r3, [r3, r2, lsl #1] 80010fc: 4619 mov r1, r3 80010fe: 4b25 ldr r3, [pc, #148] ; (8001194 <finalize+0x24c>) 8001100: f9b3 3000 ldrsh.w r3, [r3] 8001104: 3b01 subs r3, #1 8001106: 4a24 ldr r2, [pc, #144] ; (8001198 <finalize+0x250>) 8001108: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 800110c: 1acb subs r3, r1, r3 800110e: 4618 mov r0, r3 8001110: f7ff f978 bl 8000404 <__aeabi_i2d> 8001114: 4602 mov r2, r0 8001116: 460b mov r3, r1 8001118: 4640 mov r0, r8 800111a: 4649 mov r1, r9 800111c: f7ff fb06 bl 800072c <__aeabi_ddiv> 8001120: 4602 mov r2, r0 8001122: 460b mov r3, r1 8001124: 4620 mov r0, r4 8001126: 4629 mov r1, r5 8001128: f7ff f820 bl 800016c <__adddf3> 800112c: 4602 mov r2, r0 800112e: 460b mov r3, r1 8001130: 4610 mov r0, r2 8001132: 4619 mov r1, r3 8001134: f7ff fbe2 bl 80008fc <__aeabi_d2iz> 8001138: 4603 mov r3, r0 800113a: b21a sxth r2, r3 800113c: 4b13 ldr r3, [pc, #76] ; (800118c <finalize+0x244>) 800113e: 801a strh r2, [r3, #0] while (i < valuesCounter && peaksM[i] < maxPeak) ++i; 8001140: e008 b.n 8001154 <finalize+0x20c> 8001142: 4b14 ldr r3, [pc, #80] ; (8001194 <finalize+0x24c>) 8001144: f9b3 3000 ldrsh.w r3, [r3] 8001148: b29b uxth r3, r3 800114a: 3301 adds r3, #1 800114c: b29b uxth r3, r3 800114e: b21a sxth r2, r3 8001150: 4b10 ldr r3, [pc, #64] ; (8001194 <finalize+0x24c>) 8001152: 801a strh r2, [r3, #0] 8001154: 4b0f ldr r3, [pc, #60] ; (8001194 <finalize+0x24c>) 8001156: f9b3 2000 ldrsh.w r2, [r3] 800115a: 4b0b ldr r3, [pc, #44] ; (8001188 <finalize+0x240>) 800115c: f9b3 3000 ldrsh.w r3, [r3] 8001160: 429a cmp r2, r3 8001162: da2c bge.n 80011be <finalize+0x276> 8001164: 4b0b ldr r3, [pc, #44] ; (8001194 <finalize+0x24c>) 8001166: f9b3 3000 ldrsh.w r3, [r3] 800116a: 461a mov r2, r3 800116c: 4b0a ldr r3, [pc, #40] ; (8001198 <finalize+0x250>) 800116e: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 8001172: 4b07 ldr r3, [pc, #28] ; (8001190 <finalize+0x248>) 8001174: f9b3 3000 ldrsh.w r3, [r3] 8001178: 429a cmp r2, r3 800117a: dbe2 blt.n 8001142 <finalize+0x1fa> while (i < valuesCounter && peaksM[i] > awaitedDiatolic) ++i; 800117c: e01f b.n 80011be <finalize+0x276> 800117e: bf00 nop 8001180: 33333333 .word 0x33333333 8001184: 3feb3333 .word 0x3feb3333 8001188: 200003be .word 0x200003be 800118c: 200003f4 .word 0x200003f4 8001190: 200003f2 .word 0x200003f2 8001194: 200003f0 .word 0x200003f0 8001198: 2000009c .word 0x2000009c 800119c: 3fe00000 .word 0x3fe00000 80011a0: 200003f8 .word 0x200003f8 80011a4: 200003fa .word 0x200003fa 80011a8: 2000022c .word 0x2000022c 80011ac: 4b59 ldr r3, [pc, #356] ; (8001314 <finalize+0x3cc>) 80011ae: f9b3 3000 ldrsh.w r3, [r3] 80011b2: b29b uxth r3, r3 80011b4: 3301 adds r3, #1 80011b6: b29b uxth r3, r3 80011b8: b21a sxth r2, r3 80011ba: 4b56 ldr r3, [pc, #344] ; (8001314 <finalize+0x3cc>) 80011bc: 801a strh r2, [r3, #0] 80011be: 4b55 ldr r3, [pc, #340] ; (8001314 <finalize+0x3cc>) 80011c0: f9b3 2000 ldrsh.w r2, [r3] 80011c4: 4b54 ldr r3, [pc, #336] ; (8001318 <finalize+0x3d0>) 80011c6: f9b3 3000 ldrsh.w r3, [r3] 80011ca: 429a cmp r2, r3 80011cc: da0b bge.n 80011e6 <finalize+0x29e> 80011ce: 4b51 ldr r3, [pc, #324] ; (8001314 <finalize+0x3cc>) 80011d0: f9b3 3000 ldrsh.w r3, [r3] 80011d4: 461a mov r2, r3 80011d6: 4b51 ldr r3, [pc, #324] ; (800131c <finalize+0x3d4>) 80011d8: f933 2012 ldrsh.w r2, [r3, r2, lsl #1] 80011dc: 4b50 ldr r3, [pc, #320] ; (8001320 <finalize+0x3d8>) 80011de: f9b3 3000 ldrsh.w r3, [r3] 80011e2: 429a cmp r2, r3 80011e4: dce2 bgt.n 80011ac <finalize+0x264> if (i == valuesCounter) --i; 80011e6: 4b4b ldr r3, [pc, #300] ; (8001314 <finalize+0x3cc>) 80011e8: f9b3 2000 ldrsh.w r2, [r3] 80011ec: 4b4a ldr r3, [pc, #296] ; (8001318 <finalize+0x3d0>) 80011ee: f9b3 3000 ldrsh.w r3, [r3] 80011f2: 429a cmp r2, r3 80011f4: d108 bne.n 8001208 <finalize+0x2c0> 80011f6: 4b47 ldr r3, [pc, #284] ; (8001314 <finalize+0x3cc>) 80011f8: f9b3 3000 ldrsh.w r3, [r3] 80011fc: b29b uxth r3, r3 80011fe: 3b01 subs r3, #1 8001200: b29b uxth r3, r3 8001202: b21a sxth r2, r3 8001204: 4b43 ldr r3, [pc, #268] ; (8001314 <finalize+0x3cc>) 8001206: 801a strh r2, [r3, #0] currentAP.diastolic = pressuresM[i - 1] + (double)(pressuresM[i] - pressuresM[i - 1]) * (awaitedDiatolic - peaksM[i - 1]) / (peaksM[i] - peaksM[i - 1]); 8001208: 4b42 ldr r3, [pc, #264] ; (8001314 <finalize+0x3cc>) 800120a: f9b3 3000 ldrsh.w r3, [r3] 800120e: 3b01 subs r3, #1 8001210: 4a44 ldr r2, [pc, #272] ; (8001324 <finalize+0x3dc>) 8001212: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 8001216: 4618 mov r0, r3 8001218: f7ff f8f4 bl 8000404 <__aeabi_i2d> 800121c: 4604 mov r4, r0 800121e: 460d mov r5, r1 8001220: 4b3c ldr r3, [pc, #240] ; (8001314 <finalize+0x3cc>) 8001222: f9b3 3000 ldrsh.w r3, [r3] 8001226: 461a mov r2, r3 8001228: 4b3e ldr r3, [pc, #248] ; (8001324 <finalize+0x3dc>) 800122a: f933 3012 ldrsh.w r3, [r3, r2, lsl #1] 800122e: 4619 mov r1, r3 8001230: 4b38 ldr r3, [pc, #224] ; (8001314 <finalize+0x3cc>) 8001232: f9b3 3000 ldrsh.w r3, [r3] 8001236: 3b01 subs r3, #1 8001238: 4a3a ldr r2, [pc, #232] ; (8001324 <finalize+0x3dc>) 800123a: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 800123e: 1acb subs r3, r1, r3 8001240: 4618 mov r0, r3 8001242: f7ff f8df bl 8000404 <__aeabi_i2d> 8001246: 4680 mov r8, r0 8001248: 4689 mov r9, r1 800124a: 4b35 ldr r3, [pc, #212] ; (8001320 <finalize+0x3d8>) 800124c: f9b3 3000 ldrsh.w r3, [r3] 8001250: 4619 mov r1, r3 8001252: 4b30 ldr r3, [pc, #192] ; (8001314 <finalize+0x3cc>) 8001254: f9b3 3000 ldrsh.w r3, [r3] 8001258: 3b01 subs r3, #1 800125a: 4a30 ldr r2, [pc, #192] ; (800131c <finalize+0x3d4>) 800125c: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 8001260: 1acb subs r3, r1, r3 8001262: 4618 mov r0, r3 8001264: f7ff f8ce bl 8000404 <__aeabi_i2d> 8001268: 4602 mov r2, r0 800126a: 460b mov r3, r1 800126c: 4640 mov r0, r8 800126e: 4649 mov r1, r9 8001270: f7ff f932 bl 80004d8 <__aeabi_dmul> 8001274: 4602 mov r2, r0 8001276: 460b mov r3, r1 8001278: 4690 mov r8, r2 800127a: 4699 mov r9, r3 800127c: 4b25 ldr r3, [pc, #148] ; (8001314 <finalize+0x3cc>) 800127e: f9b3 3000 ldrsh.w r3, [r3] 8001282: 461a mov r2, r3 8001284: 4b25 ldr r3, [pc, #148] ; (800131c <finalize+0x3d4>) 8001286: f933 3012 ldrsh.w r3, [r3, r2, lsl #1] 800128a: 4619 mov r1, r3 800128c: 4b21 ldr r3, [pc, #132] ; (8001314 <finalize+0x3cc>) 800128e: f9b3 3000 ldrsh.w r3, [r3] 8001292: 3b01 subs r3, #1 8001294: 4a21 ldr r2, [pc, #132] ; (800131c <finalize+0x3d4>) 8001296: f932 3013 ldrsh.w r3, [r2, r3, lsl #1] 800129a: 1acb subs r3, r1, r3 800129c: 4618 mov r0, r3 800129e: f7ff f8b1 bl 8000404 <__aeabi_i2d> 80012a2: 4602 mov r2, r0 80012a4: 460b mov r3, r1 80012a6: 4640 mov r0, r8 80012a8: 4649 mov r1, r9 80012aa: f7ff fa3f bl 800072c <__aeabi_ddiv> 80012ae: 4602 mov r2, r0 80012b0: 460b mov r3, r1 80012b2: 4620 mov r0, r4 80012b4: 4629 mov r1, r5 80012b6: f7fe ff59 bl 800016c <__adddf3> 80012ba: 4602 mov r2, r0 80012bc: 460b mov r3, r1 80012be: 4610 mov r0, r2 80012c0: 4619 mov r1, r3 80012c2: f7ff fb1b bl 80008fc <__aeabi_d2iz> 80012c6: 4603 mov r3, r0 80012c8: b21a sxth r2, r3 80012ca: 4b17 ldr r3, [pc, #92] ; (8001328 <finalize+0x3e0>) 80012cc: 805a strh r2, [r3, #2] currentAP.diastolic = (int16_t)(ADCToPressure(currentAP.diastolic) ); 80012ce: 4b16 ldr r3, [pc, #88] ; (8001328 <finalize+0x3e0>) 80012d0: f9b3 3002 ldrsh.w r3, [r3, #2] 80012d4: 4618 mov r0, r3 80012d6: f7ff fb7f bl 80009d8 <ADCToPressure> 80012da: 4603 mov r3, r0 80012dc: 461a mov r2, r3 80012de: 4b12 ldr r3, [pc, #72] ; (8001328 <finalize+0x3e0>) 80012e0: 805a strh r2, [r3, #2] currentAP.systolic = (int16_t)(ADCToPressure(currentAP.systolic) ); 80012e2: 4b11 ldr r3, [pc, #68] ; (8001328 <finalize+0x3e0>) 80012e4: f9b3 3000 ldrsh.w r3, [r3] 80012e8: 4618 mov r0, r3 80012ea: f7ff fb75 bl 80009d8 <ADCToPressure> 80012ee: 4603 mov r3, r0 80012f0: 461a mov r2, r3 80012f2: 4b0d ldr r3, [pc, #52] ; (8001328 <finalize+0x3e0>) 80012f4: 801a strh r2, [r3, #0] // currentAP.diastolic = (int16_t)(currentAP.diastolic * 1.2); return currentAP; 80012f6: 4b0c ldr r3, [pc, #48] ; (8001328 <finalize+0x3e0>) 80012f8: 681b ldr r3, [r3, #0] 80012fa: 607b str r3, [r7, #4] } 80012fc: 2300 movs r3, #0 80012fe: 88ba ldrh r2, [r7, #4] 8001300: f362 030f bfi r3, r2, #0, #16 8001304: 88fa ldrh r2, [r7, #6] 8001306: f362 431f bfi r3, r2, #16, #16 800130a: 4618 mov r0, r3 800130c: 3708 adds r7, #8 800130e: 46bd mov sp, r7 8001310: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 8001314: 200003f0 .word 0x200003f0 8001318: 200003be .word 0x200003be 800131c: 2000009c .word 0x2000009c 8001320: 200003fa .word 0x200003fa 8001324: 2000022c .word 0x2000022c 8001328: 200003f4 .word 0x200003f4 0800132c <TM_init>: bool hasData() { return gotResult; } void TM_init() { 800132c: b580 push {r7, lr} 800132e: af00 add r7, sp, #0 gotResult = false; 8001330: 4b0c ldr r3, [pc, #48] ; (8001364 <TM_init+0x38>) 8001332: 2200 movs r2, #0 8001334: 701a strb r2, [r3, #0] TMS = TMS_NONE; 8001336: 4b0c ldr r3, [pc, #48] ; (8001368 <TM_init+0x3c>) 8001338: 2200 movs r2, #0 800133a: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(GPIOC, GPIO_PIN_PUMP, GPIO_PIN_RESET); 800133c: 2200 movs r2, #0 800133e: f44f 4100 mov.w r1, #32768 ; 0x8000 8001342: 480a ldr r0, [pc, #40] ; (800136c <TM_init+0x40>) 8001344: f002 fd3b bl 8003dbe <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_SOLENOID, GPIO_PIN_RESET); 8001348: 2200 movs r2, #0 800134a: f44f 4180 mov.w r1, #16384 ; 0x4000 800134e: 4807 ldr r0, [pc, #28] ; (800136c <TM_init+0x40>) 8001350: f002 fd35 bl 8003dbe <HAL_GPIO_WritePin> HAL_TIM_Base_Stop_IT(&htim4); 8001354: 4806 ldr r0, [pc, #24] ; (8001370 <TM_init+0x44>) 8001356: f004 fbf7 bl 8005b48 <HAL_TIM_Base_Stop_IT> HAL_TIM_Base_Stop_IT(&htim3); 800135a: 4806 ldr r0, [pc, #24] ; (8001374 <TM_init+0x48>) 800135c: f004 fbf4 bl 8005b48 <HAL_TIM_Base_Stop_IT> } 8001360: bf00 nop 8001362: bd80 pop {r7, pc} 8001364: 20000402 .word 0x20000402 8001368: 200003fc .word 0x200003fc 800136c: 40011000 .word 0x40011000 8001370: 200005ac .word 0x200005ac 8001374: 20000564 .word 0x20000564 08001378 <TM_start>: void TM_start() { 8001378: b580 push {r7, lr} 800137a: af00 add r7, sp, #0 if (TMS == TMS_NONE) { 800137c: 4b06 ldr r3, [pc, #24] ; (8001398 <TM_start+0x20>) 800137e: 781b ldrb r3, [r3, #0] 8001380: 2b00 cmp r3, #0 8001382: d106 bne.n 8001392 <TM_start+0x1a> gotResult = false; 8001384: 4b05 ldr r3, [pc, #20] ; (800139c <TM_start+0x24>) 8001386: 2200 movs r2, #0 8001388: 701a strb r2, [r3, #0] initM(); 800138a: f7ff fadf bl 800094c <initM> beginPumping(); 800138e: f000 f869 bl 8001464 <beginPumping> } } 8001392: bf00 nop 8001394: bd80 pop {r7, pc} 8001396: bf00 nop 8001398: 200003fc .word 0x200003fc 800139c: 20000402 .word 0x20000402 080013a0 <TM_stop>: void TM_stop() { 80013a0: b580 push {r7, lr} 80013a2: af00 add r7, sp, #0 if (TMS != TMS_NONE) 80013a4: 4b03 ldr r3, [pc, #12] ; (80013b4 <TM_stop+0x14>) 80013a6: 781b ldrb r3, [r3, #0] 80013a8: 2b00 cmp r3, #0 80013aa: d001 beq.n 80013b0 <TM_stop+0x10> beginFinishing(); 80013ac: f000 f8b6 bl 800151c <beginFinishing> } 80013b0: bf00 nop 80013b2: bd80 pop {r7, pc} 80013b4: 200003fc .word 0x200003fc 080013b8 <TM_Cycle>: void TM_Cycle() { 80013b8: b580 push {r7, lr} 80013ba: af00 add r7, sp, #0 if (TMS == TMS_NONE) 80013bc: 4b23 ldr r3, [pc, #140] ; (800144c <TM_Cycle+0x94>) 80013be: 781b ldrb r3, [r3, #0] 80013c0: 2b00 cmp r3, #0 80013c2: d040 beq.n 8001446 <TM_Cycle+0x8e> return; if (newValue == 1) { 80013c4: 4b22 ldr r3, [pc, #136] ; (8001450 <TM_Cycle+0x98>) 80013c6: f993 3000 ldrsb.w r3, [r3] 80013ca: 2b01 cmp r3, #1 80013cc: d137 bne.n 800143e <TM_Cycle+0x86> switch(TMS) { 80013ce: 4b1f ldr r3, [pc, #124] ; (800144c <TM_Cycle+0x94>) 80013d0: 781b ldrb r3, [r3, #0] 80013d2: 2b01 cmp r3, #1 80013d4: d002 beq.n 80013dc <TM_Cycle+0x24> 80013d6: 2b02 cmp r3, #2 80013d8: d009 beq.n 80013ee <TM_Cycle+0x36> 80013da: e020 b.n 800141e <TM_Cycle+0x66> case TMS_PUMPING: if (lastMainPressure > PRESSURE_MAX_CODE) 80013dc: 4b1d ldr r3, [pc, #116] ; (8001454 <TM_Cycle+0x9c>) 80013de: 881b ldrh r3, [r3, #0] 80013e0: f240 32f6 movw r2, #1014 ; 0x3f6 80013e4: 4293 cmp r3, r2 80013e6: d917 bls.n 8001418 <TM_Cycle+0x60> beginDeflating(); 80013e8: f000 f874 bl 80014d4 <beginDeflating> break; 80013ec: e014 b.n 8001418 <TM_Cycle+0x60> case TMS_DEFLATING: setData(pulsePressure, lastMainPressure); 80013ee: 4b1a ldr r3, [pc, #104] ; (8001458 <TM_Cycle+0xa0>) 80013f0: 881b ldrh r3, [r3, #0] 80013f2: b21b sxth r3, r3 80013f4: 4a17 ldr r2, [pc, #92] ; (8001454 <TM_Cycle+0x9c>) 80013f6: 8812 ldrh r2, [r2, #0] 80013f8: b212 sxth r2, r2 80013fa: 4611 mov r1, r2 80013fc: 4618 mov r0, r3 80013fe: f7ff fb0b bl 8000a18 <setData> if (lastMainPressure < PRESSURE_MIN_CODE) { 8001402: 4b14 ldr r3, [pc, #80] ; (8001454 <TM_Cycle+0x9c>) 8001404: 881b ldrh r3, [r3, #0] 8001406: f5b3 7f95 cmp.w r3, #298 ; 0x12a 800140a: d807 bhi.n 800141c <TM_Cycle+0x64> gotResult = true; 800140c: 4b13 ldr r3, [pc, #76] ; (800145c <TM_Cycle+0xa4>) 800140e: 2201 movs r2, #1 8001410: 701a strb r2, [r3, #0] beginFinishing(); 8001412: f000 f883 bl 800151c <beginFinishing> } break; 8001416: e001 b.n 800141c <TM_Cycle+0x64> break; 8001418: bf00 nop 800141a: e000 b.n 800141e <TM_Cycle+0x66> break; 800141c: bf00 nop } if (TMS == TMS_DEFLATING) { 800141e: 4b0b ldr r3, [pc, #44] ; (800144c <TM_Cycle+0x94>) 8001420: 781b ldrb r3, [r3, #0] 8001422: 2b02 cmp r3, #2 8001424: d10b bne.n 800143e <TM_Cycle+0x86> HAL_UART_Transmit(&huart1, (uint8_t*)&lastMainPressure, 2, 100); 8001426: 2364 movs r3, #100 ; 0x64 8001428: 2202 movs r2, #2 800142a: 490a ldr r1, [pc, #40] ; (8001454 <TM_Cycle+0x9c>) 800142c: 480c ldr r0, [pc, #48] ; (8001460 <TM_Cycle+0xa8>) 800142e: f005 fae9 bl 8006a04 <HAL_UART_Transmit> HAL_UART_Transmit(&huart1, (uint8_t*)&pulsePressure, 2, 100); 8001432: 2364 movs r3, #100 ; 0x64 8001434: 2202 movs r2, #2 8001436: 4908 ldr r1, [pc, #32] ; (8001458 <TM_Cycle+0xa0>) 8001438: 4809 ldr r0, [pc, #36] ; (8001460 <TM_Cycle+0xa8>) 800143a: f005 fae3 bl 8006a04 <HAL_UART_Transmit> } } newValue = 0; 800143e: 4b04 ldr r3, [pc, #16] ; (8001450 <TM_Cycle+0x98>) 8001440: 2200 movs r2, #0 8001442: 701a strb r2, [r3, #0] 8001444: e000 b.n 8001448 <TM_Cycle+0x90> return; 8001446: bf00 nop } 8001448: bd80 pop {r7, pc} 800144a: bf00 nop 800144c: 200003fc .word 0x200003fc 8001450: 20000403 .word 0x20000403 8001454: 200003fe .word 0x200003fe 8001458: 20000400 .word 0x20000400 800145c: 20000402 .word 0x20000402 8001460: 200005f4 .word 0x200005f4 08001464 <beginPumping>: void beginPumping() { 8001464: b580 push {r7, lr} 8001466: af00 add r7, sp, #0 // Начинает накачку воздуха, запускает сторожевой таймер на полминуты TMS = TMS_PUMPING; 8001468: 4b13 ldr r3, [pc, #76] ; (80014b8 <beginPumping+0x54>) 800146a: 2201 movs r2, #1 800146c: 701a strb r2, [r3, #0] // if (HAL_TIM_Base_Init(&htim4) != HAL_OK) // { // Error_Handler(); // } timerCnt = 0; 800146e: 4b13 ldr r3, [pc, #76] ; (80014bc <beginPumping+0x58>) 8001470: 2200 movs r2, #0 8001472: 801a strh r2, [r3, #0] HAL_TIM_Base_Start_IT(&htim4); 8001474: 4812 ldr r0, [pc, #72] ; (80014c0 <beginPumping+0x5c>) 8001476: f004 fb15 bl 8005aa4 <HAL_TIM_Base_Start_IT> HAL_TIM_Base_Start_IT(&htim3); 800147a: 4812 ldr r0, [pc, #72] ; (80014c4 <beginPumping+0x60>) 800147c: f004 fb12 bl 8005aa4 <HAL_TIM_Base_Start_IT> HAL_ADC_Start_IT(&hadc1); 8001480: 4811 ldr r0, [pc, #68] ; (80014c8 <beginPumping+0x64>) 8001482: f001 fe55 bl 8003130 <HAL_ADC_Start_IT> HAL_ADC_PollForConversion(&hadc1, 100); 8001486: 2164 movs r1, #100 ; 0x64 8001488: 480f ldr r0, [pc, #60] ; (80014c8 <beginPumping+0x64>) 800148a: f001 fd4b bl 8002f24 <HAL_ADC_PollForConversion> HAL_ADC_Start_IT(&hadc2); 800148e: 480f ldr r0, [pc, #60] ; (80014cc <beginPumping+0x68>) 8001490: f001 fe4e bl 8003130 <HAL_ADC_Start_IT> HAL_ADC_PollForConversion(&hadc2, 100); 8001494: 2164 movs r1, #100 ; 0x64 8001496: 480d ldr r0, [pc, #52] ; (80014cc <beginPumping+0x68>) 8001498: f001 fd44 bl 8002f24 <HAL_ADC_PollForConversion> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_PUMP, GPIO_PIN_SET); 800149c: 2201 movs r2, #1 800149e: f44f 4100 mov.w r1, #32768 ; 0x8000 80014a2: 480b ldr r0, [pc, #44] ; (80014d0 <beginPumping+0x6c>) 80014a4: f002 fc8b bl 8003dbe <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_SOLENOID, GPIO_PIN_SET); 80014a8: 2201 movs r2, #1 80014aa: f44f 4180 mov.w r1, #16384 ; 0x4000 80014ae: 4808 ldr r0, [pc, #32] ; (80014d0 <beginPumping+0x6c>) 80014b0: f002 fc85 bl 8003dbe <HAL_GPIO_WritePin> } 80014b4: bf00 nop 80014b6: bd80 pop {r7, pc} 80014b8: 200003fc .word 0x200003fc 80014bc: 20000404 .word 0x20000404 80014c0: 200005ac .word 0x200005ac 80014c4: 20000564 .word 0x20000564 80014c8: 2000040c .word 0x2000040c 80014cc: 2000043c .word 0x2000043c 80014d0: 40011000 .word 0x40011000 080014d4 <beginDeflating>: void beginDeflating() { 80014d4: b580 push {r7, lr} 80014d6: af00 add r7, sp, #0 // Прекращает накачку воздуха, запускает сторожевой таймер на минуту TMS = TMS_DEFLATING; 80014d8: 4b0c ldr r3, [pc, #48] ; (800150c <beginDeflating+0x38>) 80014da: 2202 movs r2, #2 80014dc: 701a strb r2, [r3, #0] HAL_TIM_Base_Stop_IT(&htim4); 80014de: 480c ldr r0, [pc, #48] ; (8001510 <beginDeflating+0x3c>) 80014e0: f004 fb32 bl 8005b48 <HAL_TIM_Base_Stop_IT> // if (HAL_TIM_Base_Init(&htim4) != HAL_OK) // { // Error_Handler(); // } timerCnt = 0; 80014e4: 4b0b ldr r3, [pc, #44] ; (8001514 <beginDeflating+0x40>) 80014e6: 2200 movs r2, #0 80014e8: 801a strh r2, [r3, #0] HAL_TIM_Base_Start_IT(&htim4); 80014ea: 4809 ldr r0, [pc, #36] ; (8001510 <beginDeflating+0x3c>) 80014ec: f004 fada bl 8005aa4 <HAL_TIM_Base_Start_IT> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_PUMP, GPIO_PIN_RESET); 80014f0: 2200 movs r2, #0 80014f2: f44f 4100 mov.w r1, #32768 ; 0x8000 80014f6: 4808 ldr r0, [pc, #32] ; (8001518 <beginDeflating+0x44>) 80014f8: f002 fc61 bl 8003dbe <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_SOLENOID, GPIO_PIN_SET); 80014fc: 2201 movs r2, #1 80014fe: f44f 4180 mov.w r1, #16384 ; 0x4000 8001502: 4805 ldr r0, [pc, #20] ; (8001518 <beginDeflating+0x44>) 8001504: f002 fc5b bl 8003dbe <HAL_GPIO_WritePin> } 8001508: bf00 nop 800150a: bd80 pop {r7, pc} 800150c: 200003fc .word 0x200003fc 8001510: 200005ac .word 0x200005ac 8001514: 20000404 .word 0x20000404 8001518: 40011000 .word 0x40011000 0800151c <beginFinishing>: int32_t APNormalized; void beginFinishing() { 800151c: b580 push {r7, lr} 800151e: af00 add r7, sp, #0 // Начинает спуск воздуха HAL_TIM_Base_Stop_IT(&htim4); 8001520: 4823 ldr r0, [pc, #140] ; (80015b0 <beginFinishing+0x94>) 8001522: f004 fb11 bl 8005b48 <HAL_TIM_Base_Stop_IT> HAL_TIM_Base_Stop_IT(&htim3); 8001526: 4823 ldr r0, [pc, #140] ; (80015b4 <beginFinishing+0x98>) 8001528: f004 fb0e bl 8005b48 <HAL_TIM_Base_Stop_IT> timerCnt = 0; 800152c: 4b22 ldr r3, [pc, #136] ; (80015b8 <beginFinishing+0x9c>) 800152e: 2200 movs r2, #0 8001530: 801a strh r2, [r3, #0] if (TMS == TMS_DEFLATING && gotResult) { 8001532: 4b22 ldr r3, [pc, #136] ; (80015bc <beginFinishing+0xa0>) 8001534: 781b ldrb r3, [r3, #0] 8001536: 2b02 cmp r3, #2 8001538: d125 bne.n 8001586 <beginFinishing+0x6a> 800153a: 4b21 ldr r3, [pc, #132] ; (80015c0 <beginFinishing+0xa4>) 800153c: 781b ldrb r3, [r3, #0] 800153e: 2b00 cmp r3, #0 8001540: d021 beq.n 8001586 <beginFinishing+0x6a> finalize(); 8001542: f7ff fd01 bl 8000f48 <finalize> HAL_UART_Transmit(&huart1, (uint8_t*)¤tAP, 4, 100); 8001546: 2364 movs r3, #100 ; 0x64 8001548: 2204 movs r2, #4 800154a: 491e ldr r1, [pc, #120] ; (80015c4 <beginFinishing+0xa8>) 800154c: 481e ldr r0, [pc, #120] ; (80015c8 <beginFinishing+0xac>) 800154e: f005 fa59 bl 8006a04 <HAL_UART_Transmit> APNormalized = 0; 8001552: 4b1e ldr r3, [pc, #120] ; (80015cc <beginFinishing+0xb0>) 8001554: 2200 movs r2, #0 8001556: 601a str r2, [r3, #0] APNormalized |= (currentAP.systolic); 8001558: 4b1a ldr r3, [pc, #104] ; (80015c4 <beginFinishing+0xa8>) 800155a: f9b3 3000 ldrsh.w r3, [r3] 800155e: 461a mov r2, r3 8001560: 4b1a ldr r3, [pc, #104] ; (80015cc <beginFinishing+0xb0>) 8001562: 681b ldr r3, [r3, #0] 8001564: 4313 orrs r3, r2 8001566: 4a19 ldr r2, [pc, #100] ; (80015cc <beginFinishing+0xb0>) 8001568: 6013 str r3, [r2, #0] APNormalized |= (currentAP.diastolic << 8); 800156a: 4b16 ldr r3, [pc, #88] ; (80015c4 <beginFinishing+0xa8>) 800156c: f9b3 3002 ldrsh.w r3, [r3, #2] 8001570: 021a lsls r2, r3, #8 8001572: 4b16 ldr r3, [pc, #88] ; (80015cc <beginFinishing+0xb0>) 8001574: 681b ldr r3, [r3, #0] 8001576: 4313 orrs r3, r2 8001578: 4a14 ldr r2, [pc, #80] ; (80015cc <beginFinishing+0xb0>) 800157a: 6013 str r3, [r2, #0] writeDataToFlash(APNormalized); 800157c: 4b13 ldr r3, [pc, #76] ; (80015cc <beginFinishing+0xb0>) 800157e: 681b ldr r3, [r3, #0] 8001580: 4618 mov r0, r3 8001582: f000 f88b bl 800169c <writeDataToFlash> } TMS = TMS_NONE; 8001586: 4b0d ldr r3, [pc, #52] ; (80015bc <beginFinishing+0xa0>) 8001588: 2200 movs r2, #0 800158a: 701a strb r2, [r3, #0] gotResult = false; 800158c: 4b0c ldr r3, [pc, #48] ; (80015c0 <beginFinishing+0xa4>) 800158e: 2200 movs r2, #0 8001590: 701a strb r2, [r3, #0] //HAL_ADC_Stop_IT(&hadc2); HAL_GPIO_WritePin(GPIOC, GPIO_PIN_PUMP, GPIO_PIN_RESET); 8001592: 2200 movs r2, #0 8001594: f44f 4100 mov.w r1, #32768 ; 0x8000 8001598: 480d ldr r0, [pc, #52] ; (80015d0 <beginFinishing+0xb4>) 800159a: f002 fc10 bl 8003dbe <HAL_GPIO_WritePin> HAL_GPIO_WritePin(GPIOC, GPIO_PIN_SOLENOID, GPIO_PIN_RESET); 800159e: 2200 movs r2, #0 80015a0: f44f 4180 mov.w r1, #16384 ; 0x4000 80015a4: 480a ldr r0, [pc, #40] ; (80015d0 <beginFinishing+0xb4>) 80015a6: f002 fc0a bl 8003dbe <HAL_GPIO_WritePin> } 80015aa: bf00 nop 80015ac: bd80 pop {r7, pc} 80015ae: bf00 nop 80015b0: 200005ac .word 0x200005ac 80015b4: 20000564 .word 0x20000564 80015b8: 20000404 .word 0x20000404 80015bc: 200003fc .word 0x200003fc 80015c0: 20000402 .word 0x20000402 80015c4: 200003f4 .word 0x200003f4 80015c8: 200005f4 .word 0x200005f4 80015cc: 20000408 .word 0x20000408 80015d0: 40011000 .word 0x40011000 080015d4 <HAL_ADC_ConvCpltCallback>: void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 80015d4: b580 push {r7, lr} 80015d6: b082 sub sp, #8 80015d8: af00 add r7, sp, #0 80015da: 6078 str r0, [r7, #4] if (TMS == TMS_NONE) 80015dc: 4b12 ldr r3, [pc, #72] ; (8001628 <HAL_ADC_ConvCpltCallback+0x54>) 80015de: 781b ldrb r3, [r3, #0] 80015e0: 2b00 cmp r3, #0 80015e2: d01c beq.n 800161e <HAL_ADC_ConvCpltCallback+0x4a> return; if (hadc->Instance == ADC1) { 80015e4: 687b ldr r3, [r7, #4] 80015e6: 681b ldr r3, [r3, #0] 80015e8: 4a10 ldr r2, [pc, #64] ; (800162c <HAL_ADC_ConvCpltCallback+0x58>) 80015ea: 4293 cmp r3, r2 80015ec: d107 bne.n 80015fe <HAL_ADC_ConvCpltCallback+0x2a> lastMainPressure = HAL_ADC_GetValue(hadc); 80015ee: 6878 ldr r0, [r7, #4] 80015f0: f001 fe54 bl 800329c <HAL_ADC_GetValue> 80015f4: 4603 mov r3, r0 80015f6: b29a uxth r2, r3 80015f8: 4b0d ldr r3, [pc, #52] ; (8001630 <HAL_ADC_ConvCpltCallback+0x5c>) 80015fa: 801a strh r2, [r3, #0] 80015fc: e010 b.n 8001620 <HAL_ADC_ConvCpltCallback+0x4c> } else if (hadc->Instance == ADC2) { 80015fe: 687b ldr r3, [r7, #4] 8001600: 681b ldr r3, [r3, #0] 8001602: 4a0c ldr r2, [pc, #48] ; (8001634 <HAL_ADC_ConvCpltCallback+0x60>) 8001604: 4293 cmp r3, r2 8001606: d10b bne.n 8001620 <HAL_ADC_ConvCpltCallback+0x4c> pulsePressure = HAL_ADC_GetValue(hadc); 8001608: 6878 ldr r0, [r7, #4] 800160a: f001 fe47 bl 800329c <HAL_ADC_GetValue> 800160e: 4603 mov r3, r0 8001610: b29a uxth r2, r3 8001612: 4b09 ldr r3, [pc, #36] ; (8001638 <HAL_ADC_ConvCpltCallback+0x64>) 8001614: 801a strh r2, [r3, #0] newValue = 1; 8001616: 4b09 ldr r3, [pc, #36] ; (800163c <HAL_ADC_ConvCpltCallback+0x68>) 8001618: 2201 movs r2, #1 800161a: 701a strb r2, [r3, #0] 800161c: e000 b.n 8001620 <HAL_ADC_ConvCpltCallback+0x4c> return; 800161e: bf00 nop } } 8001620: 3708 adds r7, #8 8001622: 46bd mov sp, r7 8001624: bd80 pop {r7, pc} 8001626: bf00 nop 8001628: 200003fc .word 0x200003fc 800162c: 40012400 .word 0x40012400 8001630: 200003fe .word 0x200003fe 8001634: 40012800 .word 0x40012800 8001638: 20000400 .word 0x20000400 800163c: 20000403 .word 0x20000403 08001640 <HAL_TIM_PeriodElapsedCallback>: void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001640: b580 push {r7, lr} 8001642: b082 sub sp, #8 8001644: af00 add r7, sp, #0 8001646: 6078 str r0, [r7, #4] // if (TMS == TMS_PUMPING) // beginDeflating(); // if (TMS == TMS_DEFLATING) // beginFinishing(); } if (htim->Instance == TIM4) { 8001648: 687b ldr r3, [r7, #4] 800164a: 681b ldr r3, [r3, #0] 800164c: 4a10 ldr r2, [pc, #64] ; (8001690 <HAL_TIM_PeriodElapsedCallback+0x50>) 800164e: 4293 cmp r3, r2 8001650: d119 bne.n 8001686 <HAL_TIM_PeriodElapsedCallback+0x46> timerCnt ++; 8001652: 4b10 ldr r3, [pc, #64] ; (8001694 <HAL_TIM_PeriodElapsedCallback+0x54>) 8001654: 881b ldrh r3, [r3, #0] 8001656: 3301 adds r3, #1 8001658: b29a uxth r2, r3 800165a: 4b0e ldr r3, [pc, #56] ; (8001694 <HAL_TIM_PeriodElapsedCallback+0x54>) 800165c: 801a strh r2, [r3, #0] if (TMS == TMS_PUMPING && timerCnt == 45) 800165e: 4b0e ldr r3, [pc, #56] ; (8001698 <HAL_TIM_PeriodElapsedCallback+0x58>) 8001660: 781b ldrb r3, [r3, #0] 8001662: 2b01 cmp r3, #1 8001664: d105 bne.n 8001672 <HAL_TIM_PeriodElapsedCallback+0x32> 8001666: 4b0b ldr r3, [pc, #44] ; (8001694 <HAL_TIM_PeriodElapsedCallback+0x54>) 8001668: 881b ldrh r3, [r3, #0] 800166a: 2b2d cmp r3, #45 ; 0x2d 800166c: d101 bne.n 8001672 <HAL_TIM_PeriodElapsedCallback+0x32> beginDeflating(); 800166e: f7ff ff31 bl 80014d4 <beginDeflating> if (TMS == TMS_DEFLATING && timerCnt == 90) 8001672: 4b09 ldr r3, [pc, #36] ; (8001698 <HAL_TIM_PeriodElapsedCallback+0x58>) 8001674: 781b ldrb r3, [r3, #0] 8001676: 2b02 cmp r3, #2 8001678: d105 bne.n 8001686 <HAL_TIM_PeriodElapsedCallback+0x46> 800167a: 4b06 ldr r3, [pc, #24] ; (8001694 <HAL_TIM_PeriodElapsedCallback+0x54>) 800167c: 881b ldrh r3, [r3, #0] 800167e: 2b5a cmp r3, #90 ; 0x5a 8001680: d101 bne.n 8001686 <HAL_TIM_PeriodElapsedCallback+0x46> beginFinishing(); 8001682: f7ff ff4b bl 800151c <beginFinishing> // HAL_ADC_Start_IT(&hadc1); // HAL_ADC_Start_IT(&hadc2); } } 8001686: bf00 nop 8001688: 3708 adds r7, #8 800168a: 46bd mov sp, r7 800168c: bd80 pop {r7, pc} 800168e: bf00 nop 8001690: 40000800 .word 0x40000800 8001694: 20000404 .word 0x20000404 8001698: 200003fc .word 0x200003fc 0800169c <writeDataToFlash>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ void writeDataToFlash(int32_t spo2) { 800169c: b580 push {r7, lr} 800169e: b082 sub sp, #8 80016a0: af00 add r7, sp, #0 80016a2: 6078 str r0, [r7, #4] { uint16_t word; uint8_t bytes[2]; } result_data; result_data.word = (uint16_t)(spo2); 80016a4: 687b ldr r3, [r7, #4] 80016a6: b29a uxth r2, r3 80016a8: 4b14 ldr r3, [pc, #80] ; (80016fc <writeDataToFlash+0x60>) 80016aa: 801a strh r2, [r3, #0] W25_Write_Page(result_data.bytes, page_ptr, page_pos_ptr*2, 2); //save 2 bytes to flash 80016ac: 4b14 ldr r3, [pc, #80] ; (8001700 <writeDataToFlash+0x64>) 80016ae: 881b ldrh r3, [r3, #0] 80016b0: b29b uxth r3, r3 80016b2: 4619 mov r1, r3 80016b4: 4b13 ldr r3, [pc, #76] ; (8001704 <writeDataToFlash+0x68>) 80016b6: 781b ldrb r3, [r3, #0] 80016b8: 005b lsls r3, r3, #1 80016ba: 461a mov r2, r3 80016bc: 2302 movs r3, #2 80016be: 480f ldr r0, [pc, #60] ; (80016fc <writeDataToFlash+0x60>) 80016c0: f000 ff2e bl 8002520 <W25_Write_Page> page_pos_ptr++; 80016c4: 4b0f ldr r3, [pc, #60] ; (8001704 <writeDataToFlash+0x68>) 80016c6: 781b ldrb r3, [r3, #0] 80016c8: 3301 adds r3, #1 80016ca: b2da uxtb r2, r3 80016cc: 4b0d ldr r3, [pc, #52] ; (8001704 <writeDataToFlash+0x68>) 80016ce: 701a strb r2, [r3, #0] if (page_pos_ptr == 127) //page is full 80016d0: 4b0c ldr r3, [pc, #48] ; (8001704 <writeDataToFlash+0x68>) 80016d2: 781b ldrb r3, [r3, #0] 80016d4: 2b7f cmp r3, #127 ; 0x7f 80016d6: d109 bne.n 80016ec <writeDataToFlash+0x50> { page_ptr++; 80016d8: 4b09 ldr r3, [pc, #36] ; (8001700 <writeDataToFlash+0x64>) 80016da: 881b ldrh r3, [r3, #0] 80016dc: b29b uxth r3, r3 80016de: 3301 adds r3, #1 80016e0: b29a uxth r2, r3 80016e2: 4b07 ldr r3, [pc, #28] ; (8001700 <writeDataToFlash+0x64>) 80016e4: 801a strh r2, [r3, #0] page_pos_ptr = 0; 80016e6: 4b07 ldr r3, [pc, #28] ; (8001704 <writeDataToFlash+0x68>) 80016e8: 2200 movs r2, #0 80016ea: 701a strb r2, [r3, #0] } HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_2); 80016ec: 2104 movs r1, #4 80016ee: 4806 ldr r0, [pc, #24] ; (8001708 <writeDataToFlash+0x6c>) 80016f0: f002 fb7d bl 8003dee <HAL_GPIO_TogglePin> return; 80016f4: bf00 nop } 80016f6: 3708 adds r7, #8 80016f8: 46bd mov sp, r7 80016fa: bd80 pop {r7, pc} 80016fc: 20000740 .word 0x20000740 8001700: 2000073c .word 0x2000073c 8001704: 2000073e .word 0x2000073e 8001708: 40010800 .word 0x40010800 0800170c <main>: /** * @brief The application entry point. * @retval int */ int main(void) { 800170c: b580 push {r7, lr} 800170e: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001710: f001 f9d0 bl 8002ab4 <HAL_Init> /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001714: f000 f822 bl 800175c <SystemClock_Config> /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001718: f000 faa6 bl 8001c68 <MX_GPIO_Init> MX_SPI2_Init(); 800171c: f000 f92c bl 8001978 <MX_SPI2_Init> MX_USART1_UART_Init(); 8001720: f000 fa78 bl 8001c14 <MX_USART1_UART_Init> MX_SPI1_Init(); 8001724: f000 f8f2 bl 800190c <MX_SPI1_Init> MX_TIM3_Init(); 8001728: f000 f9d6 bl 8001ad8 <MX_TIM3_Init> MX_ADC1_Init(); 800172c: f000 f872 bl 8001814 <MX_ADC1_Init> MX_ADC2_Init(); 8001730: f000 f8ae bl 8001890 <MX_ADC2_Init> MX_TIM2_Init(); 8001734: f000 f952 bl 80019dc <MX_TIM2_Init> MX_TIM4_Init(); 8001738: f000 fa1c bl 8001b74 <MX_TIM4_Init> /* USER CODE BEGIN 2 */ sensorInit(); 800173c: f006 f810 bl 8007760 <sensorInit> /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { if (spi_rx_complete) { 8001740: 4b05 ldr r3, [pc, #20] ; (8001758 <main+0x4c>) 8001742: 781b ldrb r3, [r3, #0] 8001744: 2b00 cmp r3, #0 8001746: d004 beq.n 8001752 <main+0x46> spi_rx_complete = false; 8001748: 4b03 ldr r3, [pc, #12] ; (8001758 <main+0x4c>) 800174a: 2200 movs r2, #0 800174c: 701a strb r2, [r3, #0] parserFSM(); 800174e: f005 fe19 bl 8007384 <parserFSM> } TM_Cycle(); 8001752: f7ff fe31 bl 80013b8 <TM_Cycle> if (spi_rx_complete) { 8001756: e7f3 b.n 8001740 <main+0x34> 8001758: 2000079c .word 0x2000079c 0800175c <SystemClock_Config>: /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800175c: b580 push {r7, lr} 800175e: b094 sub sp, #80 ; 0x50 8001760: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001762: f107 0328 add.w r3, r7, #40 ; 0x28 8001766: 2228 movs r2, #40 ; 0x28 8001768: 2100 movs r1, #0 800176a: 4618 mov r0, r3 800176c: f006 f936 bl 80079dc <memset> RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001770: f107 0314 add.w r3, r7, #20 8001774: 2200 movs r2, #0 8001776: 601a str r2, [r3, #0] 8001778: 605a str r2, [r3, #4] 800177a: 609a str r2, [r3, #8] 800177c: 60da str r2, [r3, #12] 800177e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001780: 1d3b adds r3, r7, #4 8001782: 2200 movs r2, #0 8001784: 601a str r2, [r3, #0] 8001786: 605a str r2, [r3, #4] 8001788: 609a str r2, [r3, #8] 800178a: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800178c: 2301 movs r3, #1 800178e: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001790: f44f 3380 mov.w r3, #65536 ; 0x10000 8001794: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2; 8001796: f44f 3300 mov.w r3, #131072 ; 0x20000 800179a: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800179c: 2301 movs r3, #1 800179e: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80017a0: 2302 movs r3, #2 80017a2: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80017a4: f44f 3380 mov.w r3, #65536 ; 0x10000 80017a8: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 80017aa: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 80017ae: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80017b0: f107 0328 add.w r3, r7, #40 ; 0x28 80017b4: 4618 mov r0, r3 80017b6: f002 fb4b bl 8003e50 <HAL_RCC_OscConfig> 80017ba: 4603 mov r3, r0 80017bc: 2b00 cmp r3, #0 80017be: d001 beq.n 80017c4 <SystemClock_Config+0x68> { Error_Handler(); 80017c0: f000 faf8 bl 8001db4 <Error_Handler> } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80017c4: 230f movs r3, #15 80017c6: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80017c8: 2302 movs r3, #2 80017ca: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80017cc: 2300 movs r3, #0 80017ce: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80017d0: f44f 6380 mov.w r3, #1024 ; 0x400 80017d4: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80017d6: 2300 movs r3, #0 80017d8: 627b str r3, [r7, #36] ; 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80017da: f107 0314 add.w r3, r7, #20 80017de: 2102 movs r1, #2 80017e0: 4618 mov r0, r3 80017e2: f002 fdb7 bl 8004354 <HAL_RCC_ClockConfig> 80017e6: 4603 mov r3, r0 80017e8: 2b00 cmp r3, #0 80017ea: d001 beq.n 80017f0 <SystemClock_Config+0x94> { Error_Handler(); 80017ec: f000 fae2 bl 8001db4 <Error_Handler> } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80017f0: 2302 movs r3, #2 80017f2: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 80017f4: f44f 4300 mov.w r3, #32768 ; 0x8000 80017f8: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80017fa: 1d3b adds r3, r7, #4 80017fc: 4618 mov r0, r3 80017fe: f002 ff39 bl 8004674 <HAL_RCCEx_PeriphCLKConfig> 8001802: 4603 mov r3, r0 8001804: 2b00 cmp r3, #0 8001806: d001 beq.n 800180c <SystemClock_Config+0xb0> { Error_Handler(); 8001808: f000 fad4 bl 8001db4 <Error_Handler> } } 800180c: bf00 nop 800180e: 3750 adds r7, #80 ; 0x50 8001810: 46bd mov sp, r7 8001812: bd80 pop {r7, pc} 08001814 <MX_ADC1_Init>: * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8001814: b580 push {r7, lr} 8001816: b084 sub sp, #16 8001818: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800181a: 1d3b adds r3, r7, #4 800181c: 2200 movs r2, #0 800181e: 601a str r2, [r3, #0] 8001820: 605a str r2, [r3, #4] 8001822: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8001824: 4b18 ldr r3, [pc, #96] ; (8001888 <MX_ADC1_Init+0x74>) 8001826: 4a19 ldr r2, [pc, #100] ; (800188c <MX_ADC1_Init+0x78>) 8001828: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 800182a: 4b17 ldr r3, [pc, #92] ; (8001888 <MX_ADC1_Init+0x74>) 800182c: 2200 movs r2, #0 800182e: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8001830: 4b15 ldr r3, [pc, #84] ; (8001888 <MX_ADC1_Init+0x74>) 8001832: 2200 movs r2, #0 8001834: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8001836: 4b14 ldr r3, [pc, #80] ; (8001888 <MX_ADC1_Init+0x74>) 8001838: 2200 movs r2, #0 800183a: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 800183c: 4b12 ldr r3, [pc, #72] ; (8001888 <MX_ADC1_Init+0x74>) 800183e: f44f 2200 mov.w r2, #524288 ; 0x80000 8001842: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001844: 4b10 ldr r3, [pc, #64] ; (8001888 <MX_ADC1_Init+0x74>) 8001846: 2200 movs r2, #0 8001848: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800184a: 4b0f ldr r3, [pc, #60] ; (8001888 <MX_ADC1_Init+0x74>) 800184c: 2201 movs r2, #1 800184e: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8001850: 480d ldr r0, [pc, #52] ; (8001888 <MX_ADC1_Init+0x74>) 8001852: f001 f9b5 bl 8002bc0 <HAL_ADC_Init> 8001856: 4603 mov r3, r0 8001858: 2b00 cmp r3, #0 800185a: d001 beq.n 8001860 <MX_ADC1_Init+0x4c> { Error_Handler(); 800185c: f000 faaa bl 8001db4 <Error_Handler> } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8001860: 2301 movs r3, #1 8001862: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8001864: 2301 movs r3, #1 8001866: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8001868: 2300 movs r3, #0 800186a: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800186c: 1d3b adds r3, r7, #4 800186e: 4619 mov r1, r3 8001870: 4805 ldr r0, [pc, #20] ; (8001888 <MX_ADC1_Init+0x74>) 8001872: f001 fde7 bl 8003444 <HAL_ADC_ConfigChannel> 8001876: 4603 mov r3, r0 8001878: 2b00 cmp r3, #0 800187a: d001 beq.n 8001880 <MX_ADC1_Init+0x6c> { Error_Handler(); 800187c: f000 fa9a bl 8001db4 <Error_Handler> } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001880: bf00 nop 8001882: 3710 adds r7, #16 8001884: 46bd mov sp, r7 8001886: bd80 pop {r7, pc} 8001888: 2000040c .word 0x2000040c 800188c: 40012400 .word 0x40012400 08001890 <MX_ADC2_Init>: * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8001890: b580 push {r7, lr} 8001892: b084 sub sp, #16 8001894: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8001896: 1d3b adds r3, r7, #4 8001898: 2200 movs r2, #0 800189a: 601a str r2, [r3, #0] 800189c: 605a str r2, [r3, #4] 800189e: 609a str r2, [r3, #8] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 80018a0: 4b18 ldr r3, [pc, #96] ; (8001904 <MX_ADC2_Init+0x74>) 80018a2: 4a19 ldr r2, [pc, #100] ; (8001908 <MX_ADC2_Init+0x78>) 80018a4: 601a str r2, [r3, #0] hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 80018a6: 4b17 ldr r3, [pc, #92] ; (8001904 <MX_ADC2_Init+0x74>) 80018a8: 2200 movs r2, #0 80018aa: 609a str r2, [r3, #8] hadc2.Init.ContinuousConvMode = DISABLE; 80018ac: 4b15 ldr r3, [pc, #84] ; (8001904 <MX_ADC2_Init+0x74>) 80018ae: 2200 movs r2, #0 80018b0: 731a strb r2, [r3, #12] hadc2.Init.DiscontinuousConvMode = DISABLE; 80018b2: 4b14 ldr r3, [pc, #80] ; (8001904 <MX_ADC2_Init+0x74>) 80018b4: 2200 movs r2, #0 80018b6: 751a strb r2, [r3, #20] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80018b8: 4b12 ldr r3, [pc, #72] ; (8001904 <MX_ADC2_Init+0x74>) 80018ba: f44f 2200 mov.w r2, #524288 ; 0x80000 80018be: 61da str r2, [r3, #28] hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80018c0: 4b10 ldr r3, [pc, #64] ; (8001904 <MX_ADC2_Init+0x74>) 80018c2: 2200 movs r2, #0 80018c4: 605a str r2, [r3, #4] hadc2.Init.NbrOfConversion = 1; 80018c6: 4b0f ldr r3, [pc, #60] ; (8001904 <MX_ADC2_Init+0x74>) 80018c8: 2201 movs r2, #1 80018ca: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc2) != HAL_OK) 80018cc: 480d ldr r0, [pc, #52] ; (8001904 <MX_ADC2_Init+0x74>) 80018ce: f001 f977 bl 8002bc0 <HAL_ADC_Init> 80018d2: 4603 mov r3, r0 80018d4: 2b00 cmp r3, #0 80018d6: d001 beq.n 80018dc <MX_ADC2_Init+0x4c> { Error_Handler(); 80018d8: f000 fa6c bl 8001db4 <Error_Handler> } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; 80018dc: 2302 movs r3, #2 80018de: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80018e0: 2301 movs r3, #1 80018e2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80018e4: 2300 movs r3, #0 80018e6: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 80018e8: 1d3b adds r3, r7, #4 80018ea: 4619 mov r1, r3 80018ec: 4805 ldr r0, [pc, #20] ; (8001904 <MX_ADC2_Init+0x74>) 80018ee: f001 fda9 bl 8003444 <HAL_ADC_ConfigChannel> 80018f2: 4603 mov r3, r0 80018f4: 2b00 cmp r3, #0 80018f6: d001 beq.n 80018fc <MX_ADC2_Init+0x6c> { Error_Handler(); 80018f8: f000 fa5c bl 8001db4 <Error_Handler> } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 80018fc: bf00 nop 80018fe: 3710 adds r7, #16 8001900: 46bd mov sp, r7 8001902: bd80 pop {r7, pc} 8001904: 2000043c .word 0x2000043c 8001908: 40012800 .word 0x40012800 0800190c <MX_SPI1_Init>: * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 800190c: b580 push {r7, lr} 800190e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 8001910: 4b17 ldr r3, [pc, #92] ; (8001970 <MX_SPI1_Init+0x64>) 8001912: 4a18 ldr r2, [pc, #96] ; (8001974 <MX_SPI1_Init+0x68>) 8001914: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8001916: 4b16 ldr r3, [pc, #88] ; (8001970 <MX_SPI1_Init+0x64>) 8001918: f44f 7282 mov.w r2, #260 ; 0x104 800191c: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 800191e: 4b14 ldr r3, [pc, #80] ; (8001970 <MX_SPI1_Init+0x64>) 8001920: 2200 movs r2, #0 8001922: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8001924: 4b12 ldr r3, [pc, #72] ; (8001970 <MX_SPI1_Init+0x64>) 8001926: 2200 movs r2, #0 8001928: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 800192a: 4b11 ldr r3, [pc, #68] ; (8001970 <MX_SPI1_Init+0x64>) 800192c: 2200 movs r2, #0 800192e: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8001930: 4b0f ldr r3, [pc, #60] ; (8001970 <MX_SPI1_Init+0x64>) 8001932: 2200 movs r2, #0 8001934: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8001936: 4b0e ldr r3, [pc, #56] ; (8001970 <MX_SPI1_Init+0x64>) 8001938: f44f 7200 mov.w r2, #512 ; 0x200 800193c: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; 800193e: 4b0c ldr r3, [pc, #48] ; (8001970 <MX_SPI1_Init+0x64>) 8001940: 2228 movs r2, #40 ; 0x28 8001942: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8001944: 4b0a ldr r3, [pc, #40] ; (8001970 <MX_SPI1_Init+0x64>) 8001946: 2200 movs r2, #0 8001948: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 800194a: 4b09 ldr r3, [pc, #36] ; (8001970 <MX_SPI1_Init+0x64>) 800194c: 2200 movs r2, #0 800194e: 625a str r2, [r3, #36] ; 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001950: 4b07 ldr r3, [pc, #28] ; (8001970 <MX_SPI1_Init+0x64>) 8001952: 2200 movs r2, #0 8001954: 629a str r2, [r3, #40] ; 0x28 hspi1.Init.CRCPolynomial = 10; 8001956: 4b06 ldr r3, [pc, #24] ; (8001970 <MX_SPI1_Init+0x64>) 8001958: 220a movs r2, #10 800195a: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi1) != HAL_OK) 800195c: 4804 ldr r0, [pc, #16] ; (8001970 <MX_SPI1_Init+0x64>) 800195e: f002 fff5 bl 800494c <HAL_SPI_Init> 8001962: 4603 mov r3, r0 8001964: 2b00 cmp r3, #0 8001966: d001 beq.n 800196c <MX_SPI1_Init+0x60> { Error_Handler(); 8001968: f000 fa24 bl 8001db4 <Error_Handler> } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 800196c: bf00 nop 800196e: bd80 pop {r7, pc} 8001970: 2000046c .word 0x2000046c 8001974: 40013000 .word 0x40013000 08001978 <MX_SPI2_Init>: * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 8001978: b580 push {r7, lr} 800197a: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 800197c: 4b15 ldr r3, [pc, #84] ; (80019d4 <MX_SPI2_Init+0x5c>) 800197e: 4a16 ldr r2, [pc, #88] ; (80019d8 <MX_SPI2_Init+0x60>) 8001980: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_SLAVE; 8001982: 4b14 ldr r3, [pc, #80] ; (80019d4 <MX_SPI2_Init+0x5c>) 8001984: 2200 movs r2, #0 8001986: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 8001988: 4b12 ldr r3, [pc, #72] ; (80019d4 <MX_SPI2_Init+0x5c>) 800198a: 2200 movs r2, #0 800198c: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 800198e: 4b11 ldr r3, [pc, #68] ; (80019d4 <MX_SPI2_Init+0x5c>) 8001990: 2200 movs r2, #0 8001992: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8001994: 4b0f ldr r3, [pc, #60] ; (80019d4 <MX_SPI2_Init+0x5c>) 8001996: 2200 movs r2, #0 8001998: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 800199a: 4b0e ldr r3, [pc, #56] ; (80019d4 <MX_SPI2_Init+0x5c>) 800199c: 2200 movs r2, #0 800199e: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 80019a0: 4b0c ldr r3, [pc, #48] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019a2: f44f 7200 mov.w r2, #512 ; 0x200 80019a6: 619a str r2, [r3, #24] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 80019a8: 4b0a ldr r3, [pc, #40] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019aa: 2200 movs r2, #0 80019ac: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 80019ae: 4b09 ldr r3, [pc, #36] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019b0: 2200 movs r2, #0 80019b2: 625a str r2, [r3, #36] ; 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80019b4: 4b07 ldr r3, [pc, #28] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019b6: 2200 movs r2, #0 80019b8: 629a str r2, [r3, #40] ; 0x28 hspi2.Init.CRCPolynomial = 10; 80019ba: 4b06 ldr r3, [pc, #24] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019bc: 220a movs r2, #10 80019be: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi2) != HAL_OK) 80019c0: 4804 ldr r0, [pc, #16] ; (80019d4 <MX_SPI2_Init+0x5c>) 80019c2: f002 ffc3 bl 800494c <HAL_SPI_Init> 80019c6: 4603 mov r3, r0 80019c8: 2b00 cmp r3, #0 80019ca: d001 beq.n 80019d0 <MX_SPI2_Init+0x58> { Error_Handler(); 80019cc: f000 f9f2 bl 8001db4 <Error_Handler> } /* USER CODE BEGIN SPI2_Init 2 */ //__HAL_SPI_ENABLE_IT(&hspi2, SPI_IT_ERR); /* USER CODE END SPI2_Init 2 */ } 80019d0: bf00 nop 80019d2: bd80 pop {r7, pc} 80019d4: 200004c4 .word 0x200004c4 80019d8: 40003800 .word 0x40003800 080019dc <MX_TIM2_Init>: * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80019dc: b580 push {r7, lr} 80019de: b08e sub sp, #56 ; 0x38 80019e0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80019e2: f107 0328 add.w r3, r7, #40 ; 0x28 80019e6: 2200 movs r2, #0 80019e8: 601a str r2, [r3, #0] 80019ea: 605a str r2, [r3, #4] 80019ec: 609a str r2, [r3, #8] 80019ee: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80019f0: f107 0320 add.w r3, r7, #32 80019f4: 2200 movs r2, #0 80019f6: 601a str r2, [r3, #0] 80019f8: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 80019fa: 1d3b adds r3, r7, #4 80019fc: 2200 movs r2, #0 80019fe: 601a str r2, [r3, #0] 8001a00: 605a str r2, [r3, #4] 8001a02: 609a str r2, [r3, #8] 8001a04: 60da str r2, [r3, #12] 8001a06: 611a str r2, [r3, #16] 8001a08: 615a str r2, [r3, #20] 8001a0a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8001a0c: 4b31 ldr r3, [pc, #196] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a0e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8001a12: 601a str r2, [r3, #0] htim2.Init.Prescaler = 72; 8001a14: 4b2f ldr r3, [pc, #188] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a16: 2248 movs r2, #72 ; 0x48 8001a18: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8001a1a: 4b2e ldr r3, [pc, #184] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a1c: 2200 movs r2, #0 8001a1e: 609a str r2, [r3, #8] htim2.Init.Period = 501; 8001a20: 4b2c ldr r3, [pc, #176] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a22: f240 12f5 movw r2, #501 ; 0x1f5 8001a26: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001a28: 4b2a ldr r3, [pc, #168] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a2a: 2200 movs r2, #0 8001a2c: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001a2e: 4b29 ldr r3, [pc, #164] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a30: 2200 movs r2, #0 8001a32: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001a34: 4827 ldr r0, [pc, #156] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a36: f003 ffe5 bl 8005a04 <HAL_TIM_Base_Init> 8001a3a: 4603 mov r3, r0 8001a3c: 2b00 cmp r3, #0 8001a3e: d001 beq.n 8001a44 <MX_TIM2_Init+0x68> { Error_Handler(); 8001a40: f000 f9b8 bl 8001db4 <Error_Handler> } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001a44: f44f 5380 mov.w r3, #4096 ; 0x1000 8001a48: 62bb str r3, [r7, #40] ; 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8001a4a: f107 0328 add.w r3, r7, #40 ; 0x28 8001a4e: 4619 mov r1, r3 8001a50: 4820 ldr r0, [pc, #128] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a52: f004 fb61 bl 8006118 <HAL_TIM_ConfigClockSource> 8001a56: 4603 mov r3, r0 8001a58: 2b00 cmp r3, #0 8001a5a: d001 beq.n 8001a60 <MX_TIM2_Init+0x84> { Error_Handler(); 8001a5c: f000 f9aa bl 8001db4 <Error_Handler> } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8001a60: 481c ldr r0, [pc, #112] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a62: f004 f89f bl 8005ba4 <HAL_TIM_PWM_Init> 8001a66: 4603 mov r3, r0 8001a68: 2b00 cmp r3, #0 8001a6a: d001 beq.n 8001a70 <MX_TIM2_Init+0x94> { Error_Handler(); 8001a6c: f000 f9a2 bl 8001db4 <Error_Handler> } if (HAL_TIM_OnePulse_Init(&htim2, TIM_OPMODE_SINGLE) != HAL_OK) 8001a70: 2108 movs r1, #8 8001a72: 4818 ldr r0, [pc, #96] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a74: f004 f8ee bl 8005c54 <HAL_TIM_OnePulse_Init> 8001a78: 4603 mov r3, r0 8001a7a: 2b00 cmp r3, #0 8001a7c: d001 beq.n 8001a82 <MX_TIM2_Init+0xa6> { Error_Handler(); 8001a7e: f000 f999 bl 8001db4 <Error_Handler> } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001a82: 2300 movs r3, #0 8001a84: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001a86: 2300 movs r3, #0 8001a88: 627b str r3, [r7, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001a8a: f107 0320 add.w r3, r7, #32 8001a8e: 4619 mov r1, r3 8001a90: 4810 ldr r0, [pc, #64] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001a92: f004 fef7 bl 8006884 <HAL_TIMEx_MasterConfigSynchronization> 8001a96: 4603 mov r3, r0 8001a98: 2b00 cmp r3, #0 8001a9a: d001 beq.n 8001aa0 <MX_TIM2_Init+0xc4> { Error_Handler(); 8001a9c: f000 f98a bl 8001db4 <Error_Handler> } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001aa0: 2360 movs r3, #96 ; 0x60 8001aa2: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 8001aa4: 2301 movs r3, #1 8001aa6: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW; 8001aa8: 2302 movs r3, #2 8001aaa: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001aac: 2300 movs r3, #0 8001aae: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001ab0: 1d3b adds r3, r7, #4 8001ab2: 2200 movs r2, #0 8001ab4: 4619 mov r1, r3 8001ab6: 4807 ldr r0, [pc, #28] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001ab8: f004 fa6c bl 8005f94 <HAL_TIM_PWM_ConfigChannel> 8001abc: 4603 mov r3, r0 8001abe: 2b00 cmp r3, #0 8001ac0: d001 beq.n 8001ac6 <MX_TIM2_Init+0xea> { Error_Handler(); 8001ac2: f000 f977 bl 8001db4 <Error_Handler> } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8001ac6: 4803 ldr r0, [pc, #12] ; (8001ad4 <MX_TIM2_Init+0xf8>) 8001ac8: f000 fb0c bl 80020e4 <HAL_TIM_MspPostInit> } 8001acc: bf00 nop 8001ace: 3738 adds r7, #56 ; 0x38 8001ad0: 46bd mov sp, r7 8001ad2: bd80 pop {r7, pc} 8001ad4: 2000051c .word 0x2000051c 08001ad8 <MX_TIM3_Init>: * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8001ad8: b580 push {r7, lr} 8001ada: b086 sub sp, #24 8001adc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001ade: f107 0308 add.w r3, r7, #8 8001ae2: 2200 movs r2, #0 8001ae4: 601a str r2, [r3, #0] 8001ae6: 605a str r2, [r3, #4] 8001ae8: 609a str r2, [r3, #8] 8001aea: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001aec: 463b mov r3, r7 8001aee: 2200 movs r2, #0 8001af0: 601a str r2, [r3, #0] 8001af2: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001af4: 4b1d ldr r3, [pc, #116] ; (8001b6c <MX_TIM3_Init+0x94>) 8001af6: 4a1e ldr r2, [pc, #120] ; (8001b70 <MX_TIM3_Init+0x98>) 8001af8: 601a str r2, [r3, #0] htim3.Init.Prescaler = 36000; 8001afa: 4b1c ldr r3, [pc, #112] ; (8001b6c <MX_TIM3_Init+0x94>) 8001afc: f648 42a0 movw r2, #36000 ; 0x8ca0 8001b00: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001b02: 4b1a ldr r3, [pc, #104] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b04: 2200 movs r2, #0 8001b06: 609a str r2, [r3, #8] htim3.Init.Period = 10; 8001b08: 4b18 ldr r3, [pc, #96] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b0a: 220a movs r2, #10 8001b0c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 8001b0e: 4b17 ldr r3, [pc, #92] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b10: f44f 7280 mov.w r2, #256 ; 0x100 8001b14: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001b16: 4b15 ldr r3, [pc, #84] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b18: 2200 movs r2, #0 8001b1a: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8001b1c: 4813 ldr r0, [pc, #76] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b1e: f003 ff71 bl 8005a04 <HAL_TIM_Base_Init> 8001b22: 4603 mov r3, r0 8001b24: 2b00 cmp r3, #0 8001b26: d001 beq.n 8001b2c <MX_TIM3_Init+0x54> { Error_Handler(); 8001b28: f000 f944 bl 8001db4 <Error_Handler> } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001b2c: f44f 5380 mov.w r3, #4096 ; 0x1000 8001b30: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8001b32: f107 0308 add.w r3, r7, #8 8001b36: 4619 mov r1, r3 8001b38: 480c ldr r0, [pc, #48] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b3a: f004 faed bl 8006118 <HAL_TIM_ConfigClockSource> 8001b3e: 4603 mov r3, r0 8001b40: 2b00 cmp r3, #0 8001b42: d001 beq.n 8001b48 <MX_TIM3_Init+0x70> { Error_Handler(); 8001b44: f000 f936 bl 8001db4 <Error_Handler> } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 8001b48: 2330 movs r3, #48 ; 0x30 8001b4a: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001b4c: 2300 movs r3, #0 8001b4e: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001b50: 463b mov r3, r7 8001b52: 4619 mov r1, r3 8001b54: 4805 ldr r0, [pc, #20] ; (8001b6c <MX_TIM3_Init+0x94>) 8001b56: f004 fe95 bl 8006884 <HAL_TIMEx_MasterConfigSynchronization> 8001b5a: 4603 mov r3, r0 8001b5c: 2b00 cmp r3, #0 8001b5e: d001 beq.n 8001b64 <MX_TIM3_Init+0x8c> { Error_Handler(); 8001b60: f000 f928 bl 8001db4 <Error_Handler> } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001b64: bf00 nop 8001b66: 3718 adds r7, #24 8001b68: 46bd mov sp, r7 8001b6a: bd80 pop {r7, pc} 8001b6c: 20000564 .word 0x20000564 8001b70: 40000400 .word 0x40000400 08001b74 <MX_TIM4_Init>: * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001b74: b580 push {r7, lr} 8001b76: b086 sub sp, #24 8001b78: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001b7a: f107 0308 add.w r3, r7, #8 8001b7e: 2200 movs r2, #0 8001b80: 601a str r2, [r3, #0] 8001b82: 605a str r2, [r3, #4] 8001b84: 609a str r2, [r3, #8] 8001b86: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001b88: 463b mov r3, r7 8001b8a: 2200 movs r2, #0 8001b8c: 601a str r2, [r3, #0] 8001b8e: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001b90: 4b1e ldr r3, [pc, #120] ; (8001c0c <MX_TIM4_Init+0x98>) 8001b92: 4a1f ldr r2, [pc, #124] ; (8001c10 <MX_TIM4_Init+0x9c>) 8001b94: 601a str r2, [r3, #0] htim4.Init.Prescaler = 7200; 8001b96: 4b1d ldr r3, [pc, #116] ; (8001c0c <MX_TIM4_Init+0x98>) 8001b98: f44f 52e1 mov.w r2, #7200 ; 0x1c20 8001b9c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 8001b9e: 4b1b ldr r3, [pc, #108] ; (8001c0c <MX_TIM4_Init+0x98>) 8001ba0: 2200 movs r2, #0 8001ba2: 609a str r2, [r3, #8] htim4.Init.Period = 10000; 8001ba4: 4b19 ldr r3, [pc, #100] ; (8001c0c <MX_TIM4_Init+0x98>) 8001ba6: f242 7210 movw r2, #10000 ; 0x2710 8001baa: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; 8001bac: 4b17 ldr r3, [pc, #92] ; (8001c0c <MX_TIM4_Init+0x98>) 8001bae: f44f 7200 mov.w r2, #512 ; 0x200 8001bb2: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001bb4: 4b15 ldr r3, [pc, #84] ; (8001c0c <MX_TIM4_Init+0x98>) 8001bb6: 2200 movs r2, #0 8001bb8: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 8001bba: 4814 ldr r0, [pc, #80] ; (8001c0c <MX_TIM4_Init+0x98>) 8001bbc: f003 ff22 bl 8005a04 <HAL_TIM_Base_Init> 8001bc0: 4603 mov r3, r0 8001bc2: 2b00 cmp r3, #0 8001bc4: d001 beq.n 8001bca <MX_TIM4_Init+0x56> { Error_Handler(); 8001bc6: f000 f8f5 bl 8001db4 <Error_Handler> } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001bca: f44f 5380 mov.w r3, #4096 ; 0x1000 8001bce: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8001bd0: f107 0308 add.w r3, r7, #8 8001bd4: 4619 mov r1, r3 8001bd6: 480d ldr r0, [pc, #52] ; (8001c0c <MX_TIM4_Init+0x98>) 8001bd8: f004 fa9e bl 8006118 <HAL_TIM_ConfigClockSource> 8001bdc: 4603 mov r3, r0 8001bde: 2b00 cmp r3, #0 8001be0: d001 beq.n 8001be6 <MX_TIM4_Init+0x72> { Error_Handler(); 8001be2: f000 f8e7 bl 8001db4 <Error_Handler> } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001be6: 2320 movs r3, #32 8001be8: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001bea: 2300 movs r3, #0 8001bec: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 8001bee: 463b mov r3, r7 8001bf0: 4619 mov r1, r3 8001bf2: 4806 ldr r0, [pc, #24] ; (8001c0c <MX_TIM4_Init+0x98>) 8001bf4: f004 fe46 bl 8006884 <HAL_TIMEx_MasterConfigSynchronization> 8001bf8: 4603 mov r3, r0 8001bfa: 2b00 cmp r3, #0 8001bfc: d001 beq.n 8001c02 <MX_TIM4_Init+0x8e> { Error_Handler(); 8001bfe: f000 f8d9 bl 8001db4 <Error_Handler> } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 8001c02: bf00 nop 8001c04: 3718 adds r7, #24 8001c06: 46bd mov sp, r7 8001c08: bd80 pop {r7, pc} 8001c0a: bf00 nop 8001c0c: 200005ac .word 0x200005ac 8001c10: 40000800 .word 0x40000800 08001c14 <MX_USART1_UART_Init>: * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001c14: b580 push {r7, lr} 8001c16: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001c18: 4b11 ldr r3, [pc, #68] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c1a: 4a12 ldr r2, [pc, #72] ; (8001c64 <MX_USART1_UART_Init+0x50>) 8001c1c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001c1e: 4b10 ldr r3, [pc, #64] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c20: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8001c24: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001c26: 4b0e ldr r3, [pc, #56] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c28: 2200 movs r2, #0 8001c2a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001c2c: 4b0c ldr r3, [pc, #48] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c2e: 2200 movs r2, #0 8001c30: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001c32: 4b0b ldr r3, [pc, #44] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c34: 2200 movs r2, #0 8001c36: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001c38: 4b09 ldr r3, [pc, #36] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c3a: 220c movs r2, #12 8001c3c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001c3e: 4b08 ldr r3, [pc, #32] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c40: 2200 movs r2, #0 8001c42: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001c44: 4b06 ldr r3, [pc, #24] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c46: 2200 movs r2, #0 8001c48: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001c4a: 4805 ldr r0, [pc, #20] ; (8001c60 <MX_USART1_UART_Init+0x4c>) 8001c4c: f004 fe8a bl 8006964 <HAL_UART_Init> 8001c50: 4603 mov r3, r0 8001c52: 2b00 cmp r3, #0 8001c54: d001 beq.n 8001c5a <MX_USART1_UART_Init+0x46> { Error_Handler(); 8001c56: f000 f8ad bl 8001db4 <Error_Handler> } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001c5a: bf00 nop 8001c5c: bd80 pop {r7, pc} 8001c5e: bf00 nop 8001c60: 200005f4 .word 0x200005f4 8001c64: 40013800 .word 0x40013800 08001c68 <MX_GPIO_Init>: * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001c68: b580 push {r7, lr} 8001c6a: b088 sub sp, #32 8001c6c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001c6e: f107 0310 add.w r3, r7, #16 8001c72: 2200 movs r2, #0 8001c74: 601a str r2, [r3, #0] 8001c76: 605a str r2, [r3, #4] 8001c78: 609a str r2, [r3, #8] 8001c7a: 60da str r2, [r3, #12] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8001c7c: 4b48 ldr r3, [pc, #288] ; (8001da0 <MX_GPIO_Init+0x138>) 8001c7e: 699b ldr r3, [r3, #24] 8001c80: 4a47 ldr r2, [pc, #284] ; (8001da0 <MX_GPIO_Init+0x138>) 8001c82: f043 0310 orr.w r3, r3, #16 8001c86: 6193 str r3, [r2, #24] 8001c88: 4b45 ldr r3, [pc, #276] ; (8001da0 <MX_GPIO_Init+0x138>) 8001c8a: 699b ldr r3, [r3, #24] 8001c8c: f003 0310 and.w r3, r3, #16 8001c90: 60fb str r3, [r7, #12] 8001c92: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001c94: 4b42 ldr r3, [pc, #264] ; (8001da0 <MX_GPIO_Init+0x138>) 8001c96: 699b ldr r3, [r3, #24] 8001c98: 4a41 ldr r2, [pc, #260] ; (8001da0 <MX_GPIO_Init+0x138>) 8001c9a: f043 0320 orr.w r3, r3, #32 8001c9e: 6193 str r3, [r2, #24] 8001ca0: 4b3f ldr r3, [pc, #252] ; (8001da0 <MX_GPIO_Init+0x138>) 8001ca2: 699b ldr r3, [r3, #24] 8001ca4: f003 0320 and.w r3, r3, #32 8001ca8: 60bb str r3, [r7, #8] 8001caa: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001cac: 4b3c ldr r3, [pc, #240] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cae: 699b ldr r3, [r3, #24] 8001cb0: 4a3b ldr r2, [pc, #236] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cb2: f043 0304 orr.w r3, r3, #4 8001cb6: 6193 str r3, [r2, #24] 8001cb8: 4b39 ldr r3, [pc, #228] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cba: 699b ldr r3, [r3, #24] 8001cbc: f003 0304 and.w r3, r3, #4 8001cc0: 607b str r3, [r7, #4] 8001cc2: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001cc4: 4b36 ldr r3, [pc, #216] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cc6: 699b ldr r3, [r3, #24] 8001cc8: 4a35 ldr r2, [pc, #212] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cca: f043 0308 orr.w r3, r3, #8 8001cce: 6193 str r3, [r2, #24] 8001cd0: 4b33 ldr r3, [pc, #204] ; (8001da0 <MX_GPIO_Init+0x138>) 8001cd2: 699b ldr r3, [r3, #24] 8001cd4: f003 0308 and.w r3, r3, #8 8001cd8: 603b str r3, [r7, #0] 8001cda: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, SW1_Pin|SW2_Pin, GPIO_PIN_RESET); 8001cdc: 2200 movs r2, #0 8001cde: f44f 4140 mov.w r1, #49152 ; 0xc000 8001ce2: 4830 ldr r0, [pc, #192] ; (8001da4 <MX_GPIO_Init+0x13c>) 8001ce4: f002 f86b bl 8003dbe <HAL_GPIO_WritePin> /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, FLASH_nRST_Pin|FLASH_CS_GPIO_Port_Pin|LED_Out_Pin, GPIO_PIN_RESET); 8001ce8: 2200 movs r2, #0 8001cea: f248 0118 movw r1, #32792 ; 0x8018 8001cee: 482e ldr r0, [pc, #184] ; (8001da8 <MX_GPIO_Init+0x140>) 8001cf0: f002 f865 bl 8003dbe <HAL_GPIO_WritePin> /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(ECG_CS_GPIO_Port, ECG_CS_Pin, GPIO_PIN_RESET); 8001cf4: 2200 movs r2, #0 8001cf6: 2101 movs r1, #1 8001cf8: 482c ldr r0, [pc, #176] ; (8001dac <MX_GPIO_Init+0x144>) 8001cfa: f002 f860 bl 8003dbe <HAL_GPIO_WritePin> /*Configure GPIO pins : SW1_Pin SW2_Pin */ GPIO_InitStruct.Pin = SW1_Pin|SW2_Pin; 8001cfe: f44f 4340 mov.w r3, #49152 ; 0xc000 8001d02: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001d04: 2301 movs r3, #1 8001d06: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d08: 2300 movs r3, #0 8001d0a: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d0c: 2302 movs r3, #2 8001d0e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001d10: f107 0310 add.w r3, r7, #16 8001d14: 4619 mov r1, r3 8001d16: 4823 ldr r0, [pc, #140] ; (8001da4 <MX_GPIO_Init+0x13c>) 8001d18: f001 feb6 bl 8003a88 <HAL_GPIO_Init> /*Configure GPIO pins : FLASH_nRST_Pin FLASH_CS_GPIO_Port_Pin LED_Out_Pin */ GPIO_InitStruct.Pin = FLASH_nRST_Pin|FLASH_CS_GPIO_Port_Pin|LED_Out_Pin; 8001d1c: f248 0318 movw r3, #32792 ; 0x8018 8001d20: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001d22: 2301 movs r3, #1 8001d24: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d26: 2300 movs r3, #0 8001d28: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d2a: 2302 movs r3, #2 8001d2c: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001d2e: f107 0310 add.w r3, r7, #16 8001d32: 4619 mov r1, r3 8001d34: 481c ldr r0, [pc, #112] ; (8001da8 <MX_GPIO_Init+0x140>) 8001d36: f001 fea7 bl 8003a88 <HAL_GPIO_Init> /*Configure GPIO pin : ECG_CS_Pin */ GPIO_InitStruct.Pin = ECG_CS_Pin; 8001d3a: 2301 movs r3, #1 8001d3c: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001d3e: 2301 movs r3, #1 8001d40: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d42: 2300 movs r3, #0 8001d44: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d46: 2302 movs r3, #2 8001d48: 61fb str r3, [r7, #28] HAL_GPIO_Init(ECG_CS_GPIO_Port, &GPIO_InitStruct); 8001d4a: f107 0310 add.w r3, r7, #16 8001d4e: 4619 mov r1, r3 8001d50: 4816 ldr r0, [pc, #88] ; (8001dac <MX_GPIO_Init+0x144>) 8001d52: f001 fe99 bl 8003a88 <HAL_GPIO_Init> /*Configure GPIO pin : PB12 */ GPIO_InitStruct.Pin = GPIO_PIN_12; 8001d56: f44f 5380 mov.w r3, #4096 ; 0x1000 8001d5a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8001d5c: 4b14 ldr r3, [pc, #80] ; (8001db0 <MX_GPIO_Init+0x148>) 8001d5e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d60: 2300 movs r3, #0 8001d62: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001d64: f107 0310 add.w r3, r7, #16 8001d68: 4619 mov r1, r3 8001d6a: 4810 ldr r0, [pc, #64] ; (8001dac <MX_GPIO_Init+0x144>) 8001d6c: f001 fe8c bl 8003a88 <HAL_GPIO_Init> /*Configure GPIO pins : ECG_Data_Rdy_Pin ECG_ALARM_Pin */ GPIO_InitStruct.Pin = ECG_Data_Rdy_Pin|ECG_ALARM_Pin; 8001d70: 23c0 movs r3, #192 ; 0xc0 8001d72: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001d74: 2300 movs r3, #0 8001d76: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d78: 2300 movs r3, #0 8001d7a: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001d7c: f107 0310 add.w r3, r7, #16 8001d80: 4619 mov r1, r3 8001d82: 480a ldr r0, [pc, #40] ; (8001dac <MX_GPIO_Init+0x144>) 8001d84: f001 fe80 bl 8003a88 <HAL_GPIO_Init> /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); 8001d88: 2200 movs r2, #0 8001d8a: 2100 movs r1, #0 8001d8c: 2028 movs r0, #40 ; 0x28 8001d8e: f001 fdcc bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8001d92: 2028 movs r0, #40 ; 0x28 8001d94: f001 fde5 bl 8003962 <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001d98: bf00 nop 8001d9a: 3720 adds r7, #32 8001d9c: 46bd mov sp, r7 8001d9e: bd80 pop {r7, pc} 8001da0: 40021000 .word 0x40021000 8001da4: 40011000 .word 0x40011000 8001da8: 40010800 .word 0x40010800 8001dac: 40010c00 .word 0x40010c00 8001db0: 10210000 .word 0x10210000 08001db4 <Error_Handler>: /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001db4: b480 push {r7} 8001db6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001db8: b672 cpsid i } 8001dba: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001dbc: e7fe b.n 8001dbc <Error_Handler+0x8> ... 08001dc0 <HAL_MspInit>: void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001dc0: b480 push {r7} 8001dc2: b085 sub sp, #20 8001dc4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001dc6: 4b15 ldr r3, [pc, #84] ; (8001e1c <HAL_MspInit+0x5c>) 8001dc8: 699b ldr r3, [r3, #24] 8001dca: 4a14 ldr r2, [pc, #80] ; (8001e1c <HAL_MspInit+0x5c>) 8001dcc: f043 0301 orr.w r3, r3, #1 8001dd0: 6193 str r3, [r2, #24] 8001dd2: 4b12 ldr r3, [pc, #72] ; (8001e1c <HAL_MspInit+0x5c>) 8001dd4: 699b ldr r3, [r3, #24] 8001dd6: f003 0301 and.w r3, r3, #1 8001dda: 60bb str r3, [r7, #8] 8001ddc: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8001dde: 4b0f ldr r3, [pc, #60] ; (8001e1c <HAL_MspInit+0x5c>) 8001de0: 69db ldr r3, [r3, #28] 8001de2: 4a0e ldr r2, [pc, #56] ; (8001e1c <HAL_MspInit+0x5c>) 8001de4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001de8: 61d3 str r3, [r2, #28] 8001dea: 4b0c ldr r3, [pc, #48] ; (8001e1c <HAL_MspInit+0x5c>) 8001dec: 69db ldr r3, [r3, #28] 8001dee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001df2: 607b str r3, [r7, #4] 8001df4: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8001df6: 4b0a ldr r3, [pc, #40] ; (8001e20 <HAL_MspInit+0x60>) 8001df8: 685b ldr r3, [r3, #4] 8001dfa: 60fb str r3, [r7, #12] 8001dfc: 68fb ldr r3, [r7, #12] 8001dfe: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8001e02: 60fb str r3, [r7, #12] 8001e04: 68fb ldr r3, [r7, #12] 8001e06: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8001e0a: 60fb str r3, [r7, #12] 8001e0c: 4a04 ldr r2, [pc, #16] ; (8001e20 <HAL_MspInit+0x60>) 8001e0e: 68fb ldr r3, [r7, #12] 8001e10: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001e12: bf00 nop 8001e14: 3714 adds r7, #20 8001e16: 46bd mov sp, r7 8001e18: bc80 pop {r7} 8001e1a: 4770 bx lr 8001e1c: 40021000 .word 0x40021000 8001e20: 40010000 .word 0x40010000 08001e24 <HAL_ADC_MspInit>: * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8001e24: b580 push {r7, lr} 8001e26: b08a sub sp, #40 ; 0x28 8001e28: af00 add r7, sp, #0 8001e2a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001e2c: f107 0318 add.w r3, r7, #24 8001e30: 2200 movs r2, #0 8001e32: 601a str r2, [r3, #0] 8001e34: 605a str r2, [r3, #4] 8001e36: 609a str r2, [r3, #8] 8001e38: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 8001e3a: 687b ldr r3, [r7, #4] 8001e3c: 681b ldr r3, [r3, #0] 8001e3e: 4a30 ldr r2, [pc, #192] ; (8001f00 <HAL_ADC_MspInit+0xdc>) 8001e40: 4293 cmp r3, r2 8001e42: d12a bne.n 8001e9a <HAL_ADC_MspInit+0x76> { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8001e44: 4b2f ldr r3, [pc, #188] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e46: 699b ldr r3, [r3, #24] 8001e48: 4a2e ldr r2, [pc, #184] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e4a: f443 7300 orr.w r3, r3, #512 ; 0x200 8001e4e: 6193 str r3, [r2, #24] 8001e50: 4b2c ldr r3, [pc, #176] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e52: 699b ldr r3, [r3, #24] 8001e54: f403 7300 and.w r3, r3, #512 ; 0x200 8001e58: 617b str r3, [r7, #20] 8001e5a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001e5c: 4b29 ldr r3, [pc, #164] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e5e: 699b ldr r3, [r3, #24] 8001e60: 4a28 ldr r2, [pc, #160] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e62: f043 0304 orr.w r3, r3, #4 8001e66: 6193 str r3, [r2, #24] 8001e68: 4b26 ldr r3, [pc, #152] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001e6a: 699b ldr r3, [r3, #24] 8001e6c: f003 0304 and.w r3, r3, #4 8001e70: 613b str r3, [r7, #16] 8001e72: 693b ldr r3, [r7, #16] /**ADC1 GPIO Configuration PA1 ------> ADC1_IN1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; 8001e74: 2302 movs r3, #2 8001e76: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001e78: 2303 movs r3, #3 8001e7a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e7c: f107 0318 add.w r3, r7, #24 8001e80: 4619 mov r1, r3 8001e82: 4821 ldr r0, [pc, #132] ; (8001f08 <HAL_ADC_MspInit+0xe4>) 8001e84: f001 fe00 bl 8003a88 <HAL_GPIO_Init> /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8001e88: 2200 movs r2, #0 8001e8a: 2100 movs r1, #0 8001e8c: 2012 movs r0, #18 8001e8e: f001 fd4c bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8001e92: 2012 movs r0, #18 8001e94: f001 fd65 bl 8003962 <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8001e98: e02e b.n 8001ef8 <HAL_ADC_MspInit+0xd4> else if(hadc->Instance==ADC2) 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 681b ldr r3, [r3, #0] 8001e9e: 4a1b ldr r2, [pc, #108] ; (8001f0c <HAL_ADC_MspInit+0xe8>) 8001ea0: 4293 cmp r3, r2 8001ea2: d129 bne.n 8001ef8 <HAL_ADC_MspInit+0xd4> __HAL_RCC_ADC2_CLK_ENABLE(); 8001ea4: 4b17 ldr r3, [pc, #92] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001ea6: 699b ldr r3, [r3, #24] 8001ea8: 4a16 ldr r2, [pc, #88] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001eaa: f443 6380 orr.w r3, r3, #1024 ; 0x400 8001eae: 6193 str r3, [r2, #24] 8001eb0: 4b14 ldr r3, [pc, #80] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001eb2: 699b ldr r3, [r3, #24] 8001eb4: f403 6380 and.w r3, r3, #1024 ; 0x400 8001eb8: 60fb str r3, [r7, #12] 8001eba: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001ebc: 4b11 ldr r3, [pc, #68] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001ebe: 699b ldr r3, [r3, #24] 8001ec0: 4a10 ldr r2, [pc, #64] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001ec2: f043 0304 orr.w r3, r3, #4 8001ec6: 6193 str r3, [r2, #24] 8001ec8: 4b0e ldr r3, [pc, #56] ; (8001f04 <HAL_ADC_MspInit+0xe0>) 8001eca: 699b ldr r3, [r3, #24] 8001ecc: f003 0304 and.w r3, r3, #4 8001ed0: 60bb str r3, [r7, #8] 8001ed2: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2; 8001ed4: 2304 movs r3, #4 8001ed6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001ed8: 2303 movs r3, #3 8001eda: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001edc: f107 0318 add.w r3, r7, #24 8001ee0: 4619 mov r1, r3 8001ee2: 4809 ldr r0, [pc, #36] ; (8001f08 <HAL_ADC_MspInit+0xe4>) 8001ee4: f001 fdd0 bl 8003a88 <HAL_GPIO_Init> HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8001ee8: 2200 movs r2, #0 8001eea: 2100 movs r1, #0 8001eec: 2012 movs r0, #18 8001eee: f001 fd1c bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8001ef2: 2012 movs r0, #18 8001ef4: f001 fd35 bl 8003962 <HAL_NVIC_EnableIRQ> } 8001ef8: bf00 nop 8001efa: 3728 adds r7, #40 ; 0x28 8001efc: 46bd mov sp, r7 8001efe: bd80 pop {r7, pc} 8001f00: 40012400 .word 0x40012400 8001f04: 40021000 .word 0x40021000 8001f08: 40010800 .word 0x40010800 8001f0c: 40012800 .word 0x40012800 08001f10 <HAL_SPI_MspInit>: * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8001f10: b580 push {r7, lr} 8001f12: b08a sub sp, #40 ; 0x28 8001f14: af00 add r7, sp, #0 8001f16: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001f18: f107 0318 add.w r3, r7, #24 8001f1c: 2200 movs r2, #0 8001f1e: 601a str r2, [r3, #0] 8001f20: 605a str r2, [r3, #4] 8001f22: 609a str r2, [r3, #8] 8001f24: 60da str r2, [r3, #12] if(hspi->Instance==SPI1) 8001f26: 687b ldr r3, [r7, #4] 8001f28: 681b ldr r3, [r3, #0] 8001f2a: 4a3b ldr r2, [pc, #236] ; (8002018 <HAL_SPI_MspInit+0x108>) 8001f2c: 4293 cmp r3, r2 8001f2e: d130 bne.n 8001f92 <HAL_SPI_MspInit+0x82> { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8001f30: 4b3a ldr r3, [pc, #232] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f32: 699b ldr r3, [r3, #24] 8001f34: 4a39 ldr r2, [pc, #228] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f36: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8001f3a: 6193 str r3, [r2, #24] 8001f3c: 4b37 ldr r3, [pc, #220] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f3e: 699b ldr r3, [r3, #24] 8001f40: f403 5380 and.w r3, r3, #4096 ; 0x1000 8001f44: 617b str r3, [r7, #20] 8001f46: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001f48: 4b34 ldr r3, [pc, #208] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f4a: 699b ldr r3, [r3, #24] 8001f4c: 4a33 ldr r2, [pc, #204] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f4e: f043 0304 orr.w r3, r3, #4 8001f52: 6193 str r3, [r2, #24] 8001f54: 4b31 ldr r3, [pc, #196] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f56: 699b ldr r3, [r3, #24] 8001f58: f003 0304 and.w r3, r3, #4 8001f5c: 613b str r3, [r7, #16] 8001f5e: 693b ldr r3, [r7, #16] /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; 8001f60: 23a0 movs r3, #160 ; 0xa0 8001f62: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001f64: 2302 movs r3, #2 8001f66: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001f68: 2303 movs r3, #3 8001f6a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001f6c: f107 0318 add.w r3, r7, #24 8001f70: 4619 mov r1, r3 8001f72: 482b ldr r0, [pc, #172] ; (8002020 <HAL_SPI_MspInit+0x110>) 8001f74: f001 fd88 bl 8003a88 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_6; 8001f78: 2340 movs r3, #64 ; 0x40 8001f7a: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001f7c: 2300 movs r3, #0 8001f7e: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001f80: 2300 movs r3, #0 8001f82: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001f84: f107 0318 add.w r3, r7, #24 8001f88: 4619 mov r1, r3 8001f8a: 4825 ldr r0, [pc, #148] ; (8002020 <HAL_SPI_MspInit+0x110>) 8001f8c: f001 fd7c bl 8003a88 <HAL_GPIO_Init> /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 8001f90: e03e b.n 8002010 <HAL_SPI_MspInit+0x100> else if(hspi->Instance==SPI2) 8001f92: 687b ldr r3, [r7, #4] 8001f94: 681b ldr r3, [r3, #0] 8001f96: 4a23 ldr r2, [pc, #140] ; (8002024 <HAL_SPI_MspInit+0x114>) 8001f98: 4293 cmp r3, r2 8001f9a: d139 bne.n 8002010 <HAL_SPI_MspInit+0x100> __HAL_RCC_SPI2_CLK_ENABLE(); 8001f9c: 4b1f ldr r3, [pc, #124] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001f9e: 69db ldr r3, [r3, #28] 8001fa0: 4a1e ldr r2, [pc, #120] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001fa2: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001fa6: 61d3 str r3, [r2, #28] 8001fa8: 4b1c ldr r3, [pc, #112] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001faa: 69db ldr r3, [r3, #28] 8001fac: f403 4380 and.w r3, r3, #16384 ; 0x4000 8001fb0: 60fb str r3, [r7, #12] 8001fb2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001fb4: 4b19 ldr r3, [pc, #100] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001fb6: 699b ldr r3, [r3, #24] 8001fb8: 4a18 ldr r2, [pc, #96] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001fba: f043 0308 orr.w r3, r3, #8 8001fbe: 6193 str r3, [r2, #24] 8001fc0: 4b16 ldr r3, [pc, #88] ; (800201c <HAL_SPI_MspInit+0x10c>) 8001fc2: 699b ldr r3, [r3, #24] 8001fc4: f003 0308 and.w r3, r3, #8 8001fc8: 60bb str r3, [r7, #8] 8001fca: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; 8001fcc: f44f 4320 mov.w r3, #40960 ; 0xa000 8001fd0: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001fd2: 2300 movs r3, #0 8001fd4: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001fd6: 2300 movs r3, #0 8001fd8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001fda: f107 0318 add.w r3, r7, #24 8001fde: 4619 mov r1, r3 8001fe0: 4811 ldr r0, [pc, #68] ; (8002028 <HAL_SPI_MspInit+0x118>) 8001fe2: f001 fd51 bl 8003a88 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_14; 8001fe6: f44f 4380 mov.w r3, #16384 ; 0x4000 8001fea: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001fec: 2302 movs r3, #2 8001fee: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001ff0: 2303 movs r3, #3 8001ff2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001ff4: f107 0318 add.w r3, r7, #24 8001ff8: 4619 mov r1, r3 8001ffa: 480b ldr r0, [pc, #44] ; (8002028 <HAL_SPI_MspInit+0x118>) 8001ffc: f001 fd44 bl 8003a88 <HAL_GPIO_Init> HAL_NVIC_SetPriority(SPI2_IRQn, 0, 0); 8002000: 2200 movs r2, #0 8002002: 2100 movs r1, #0 8002004: 2024 movs r0, #36 ; 0x24 8002006: f001 fc90 bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(SPI2_IRQn); 800200a: 2024 movs r0, #36 ; 0x24 800200c: f001 fca9 bl 8003962 <HAL_NVIC_EnableIRQ> } 8002010: bf00 nop 8002012: 3728 adds r7, #40 ; 0x28 8002014: 46bd mov sp, r7 8002016: bd80 pop {r7, pc} 8002018: 40013000 .word 0x40013000 800201c: 40021000 .word 0x40021000 8002020: 40010800 .word 0x40010800 8002024: 40003800 .word 0x40003800 8002028: 40010c00 .word 0x40010c00 0800202c <HAL_TIM_Base_MspInit>: * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 800202c: b580 push {r7, lr} 800202e: b086 sub sp, #24 8002030: af00 add r7, sp, #0 8002032: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800203c: d114 bne.n 8002068 <HAL_TIM_Base_MspInit+0x3c> { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 800203e: 4b26 ldr r3, [pc, #152] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 8002040: 69db ldr r3, [r3, #28] 8002042: 4a25 ldr r2, [pc, #148] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 8002044: f043 0301 orr.w r3, r3, #1 8002048: 61d3 str r3, [r2, #28] 800204a: 4b23 ldr r3, [pc, #140] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 800204c: 69db ldr r3, [r3, #28] 800204e: f003 0301 and.w r3, r3, #1 8002052: 617b str r3, [r7, #20] 8002054: 697b ldr r3, [r7, #20] /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8002056: 2200 movs r2, #0 8002058: 2100 movs r1, #0 800205a: 201c movs r0, #28 800205c: f001 fc65 bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(TIM2_IRQn); 8002060: 201c movs r0, #28 8002062: f001 fc7e bl 8003962 <HAL_NVIC_EnableIRQ> /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 8002066: e032 b.n 80020ce <HAL_TIM_Base_MspInit+0xa2> else if(htim_base->Instance==TIM3) 8002068: 687b ldr r3, [r7, #4] 800206a: 681b ldr r3, [r3, #0] 800206c: 4a1b ldr r2, [pc, #108] ; (80020dc <HAL_TIM_Base_MspInit+0xb0>) 800206e: 4293 cmp r3, r2 8002070: d114 bne.n 800209c <HAL_TIM_Base_MspInit+0x70> __HAL_RCC_TIM3_CLK_ENABLE(); 8002072: 4b19 ldr r3, [pc, #100] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 8002074: 69db ldr r3, [r3, #28] 8002076: 4a18 ldr r2, [pc, #96] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 8002078: f043 0302 orr.w r3, r3, #2 800207c: 61d3 str r3, [r2, #28] 800207e: 4b16 ldr r3, [pc, #88] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 8002080: 69db ldr r3, [r3, #28] 8002082: f003 0302 and.w r3, r3, #2 8002086: 613b str r3, [r7, #16] 8002088: 693b ldr r3, [r7, #16] HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800208a: 2200 movs r2, #0 800208c: 2100 movs r1, #0 800208e: 201d movs r0, #29 8002090: f001 fc4b bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002094: 201d movs r0, #29 8002096: f001 fc64 bl 8003962 <HAL_NVIC_EnableIRQ> } 800209a: e018 b.n 80020ce <HAL_TIM_Base_MspInit+0xa2> else if(htim_base->Instance==TIM4) 800209c: 687b ldr r3, [r7, #4] 800209e: 681b ldr r3, [r3, #0] 80020a0: 4a0f ldr r2, [pc, #60] ; (80020e0 <HAL_TIM_Base_MspInit+0xb4>) 80020a2: 4293 cmp r3, r2 80020a4: d113 bne.n 80020ce <HAL_TIM_Base_MspInit+0xa2> __HAL_RCC_TIM4_CLK_ENABLE(); 80020a6: 4b0c ldr r3, [pc, #48] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 80020a8: 69db ldr r3, [r3, #28] 80020aa: 4a0b ldr r2, [pc, #44] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 80020ac: f043 0304 orr.w r3, r3, #4 80020b0: 61d3 str r3, [r2, #28] 80020b2: 4b09 ldr r3, [pc, #36] ; (80020d8 <HAL_TIM_Base_MspInit+0xac>) 80020b4: 69db ldr r3, [r3, #28] 80020b6: f003 0304 and.w r3, r3, #4 80020ba: 60fb str r3, [r7, #12] 80020bc: 68fb ldr r3, [r7, #12] HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0); 80020be: 2200 movs r2, #0 80020c0: 2100 movs r1, #0 80020c2: 201e movs r0, #30 80020c4: f001 fc31 bl 800392a <HAL_NVIC_SetPriority> HAL_NVIC_EnableIRQ(TIM4_IRQn); 80020c8: 201e movs r0, #30 80020ca: f001 fc4a bl 8003962 <HAL_NVIC_EnableIRQ> } 80020ce: bf00 nop 80020d0: 3718 adds r7, #24 80020d2: 46bd mov sp, r7 80020d4: bd80 pop {r7, pc} 80020d6: bf00 nop 80020d8: 40021000 .word 0x40021000 80020dc: 40000400 .word 0x40000400 80020e0: 40000800 .word 0x40000800 080020e4 <HAL_TIM_MspPostInit>: void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80020e4: b580 push {r7, lr} 80020e6: b088 sub sp, #32 80020e8: af00 add r7, sp, #0 80020ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80020ec: f107 0310 add.w r3, r7, #16 80020f0: 2200 movs r2, #0 80020f2: 601a str r2, [r3, #0] 80020f4: 605a str r2, [r3, #4] 80020f6: 609a str r2, [r3, #8] 80020f8: 60da str r2, [r3, #12] if(htim->Instance==TIM2) 80020fa: 687b ldr r3, [r7, #4] 80020fc: 681b ldr r3, [r3, #0] 80020fe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8002102: d117 bne.n 8002134 <HAL_TIM_MspPostInit+0x50> { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002104: 4b0d ldr r3, [pc, #52] ; (800213c <HAL_TIM_MspPostInit+0x58>) 8002106: 699b ldr r3, [r3, #24] 8002108: 4a0c ldr r2, [pc, #48] ; (800213c <HAL_TIM_MspPostInit+0x58>) 800210a: f043 0304 orr.w r3, r3, #4 800210e: 6193 str r3, [r2, #24] 8002110: 4b0a ldr r3, [pc, #40] ; (800213c <HAL_TIM_MspPostInit+0x58>) 8002112: 699b ldr r3, [r3, #24] 8002114: f003 0304 and.w r3, r3, #4 8002118: 60fb str r3, [r7, #12] 800211a: 68fb ldr r3, [r7, #12] /**TIM2 GPIO Configuration PA0-WKUP ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; 800211c: 2301 movs r3, #1 800211e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002120: 2302 movs r3, #2 8002122: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002124: 2302 movs r3, #2 8002126: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002128: f107 0310 add.w r3, r7, #16 800212c: 4619 mov r1, r3 800212e: 4804 ldr r0, [pc, #16] ; (8002140 <HAL_TIM_MspPostInit+0x5c>) 8002130: f001 fcaa bl 8003a88 <HAL_GPIO_Init> /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8002134: bf00 nop 8002136: 3720 adds r7, #32 8002138: 46bd mov sp, r7 800213a: bd80 pop {r7, pc} 800213c: 40021000 .word 0x40021000 8002140: 40010800 .word 0x40010800 08002144 <HAL_UART_MspInit>: * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8002144: b580 push {r7, lr} 8002146: b088 sub sp, #32 8002148: af00 add r7, sp, #0 800214a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800214c: f107 0310 add.w r3, r7, #16 8002150: 2200 movs r2, #0 8002152: 601a str r2, [r3, #0] 8002154: 605a str r2, [r3, #4] 8002156: 609a str r2, [r3, #8] 8002158: 60da str r2, [r3, #12] if(huart->Instance==USART1) 800215a: 687b ldr r3, [r7, #4] 800215c: 681b ldr r3, [r3, #0] 800215e: 4a1c ldr r2, [pc, #112] ; (80021d0 <HAL_UART_MspInit+0x8c>) 8002160: 4293 cmp r3, r2 8002162: d131 bne.n 80021c8 <HAL_UART_MspInit+0x84> { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8002164: 4b1b ldr r3, [pc, #108] ; (80021d4 <HAL_UART_MspInit+0x90>) 8002166: 699b ldr r3, [r3, #24] 8002168: 4a1a ldr r2, [pc, #104] ; (80021d4 <HAL_UART_MspInit+0x90>) 800216a: f443 4380 orr.w r3, r3, #16384 ; 0x4000 800216e: 6193 str r3, [r2, #24] 8002170: 4b18 ldr r3, [pc, #96] ; (80021d4 <HAL_UART_MspInit+0x90>) 8002172: 699b ldr r3, [r3, #24] 8002174: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002178: 60fb str r3, [r7, #12] 800217a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800217c: 4b15 ldr r3, [pc, #84] ; (80021d4 <HAL_UART_MspInit+0x90>) 800217e: 699b ldr r3, [r3, #24] 8002180: 4a14 ldr r2, [pc, #80] ; (80021d4 <HAL_UART_MspInit+0x90>) 8002182: f043 0304 orr.w r3, r3, #4 8002186: 6193 str r3, [r2, #24] 8002188: 4b12 ldr r3, [pc, #72] ; (80021d4 <HAL_UART_MspInit+0x90>) 800218a: 699b ldr r3, [r3, #24] 800218c: f003 0304 and.w r3, r3, #4 8002190: 60bb str r3, [r7, #8] 8002192: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8002194: f44f 7300 mov.w r3, #512 ; 0x200 8002198: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800219a: 2302 movs r3, #2 800219c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800219e: 2303 movs r3, #3 80021a0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021a2: f107 0310 add.w r3, r7, #16 80021a6: 4619 mov r1, r3 80021a8: 480b ldr r0, [pc, #44] ; (80021d8 <HAL_UART_MspInit+0x94>) 80021aa: f001 fc6d bl 8003a88 <HAL_GPIO_Init> GPIO_InitStruct.Pin = GPIO_PIN_10; 80021ae: f44f 6380 mov.w r3, #1024 ; 0x400 80021b2: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80021b4: 2300 movs r3, #0 80021b6: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021b8: 2300 movs r3, #0 80021ba: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021bc: f107 0310 add.w r3, r7, #16 80021c0: 4619 mov r1, r3 80021c2: 4805 ldr r0, [pc, #20] ; (80021d8 <HAL_UART_MspInit+0x94>) 80021c4: f001 fc60 bl 8003a88 <HAL_GPIO_Init> /* USER CODE END USART1_MspInit 1 */ } } 80021c8: bf00 nop 80021ca: 3720 adds r7, #32 80021cc: 46bd mov sp, r7 80021ce: bd80 pop {r7, pc} 80021d0: 40013800 .word 0x40013800 80021d4: 40021000 .word 0x40021000 80021d8: 40010800 .word 0x40010800 080021dc <NMI_Handler>: /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80021dc: b480 push {r7} 80021de: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80021e0: e7fe b.n 80021e0 <NMI_Handler+0x4> 080021e2 <HardFault_Handler>: /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80021e2: b480 push {r7} 80021e4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80021e6: e7fe b.n 80021e6 <HardFault_Handler+0x4> 080021e8 <MemManage_Handler>: /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80021e8: b480 push {r7} 80021ea: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80021ec: e7fe b.n 80021ec <MemManage_Handler+0x4> 080021ee <BusFault_Handler>: /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80021ee: b480 push {r7} 80021f0: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80021f2: e7fe b.n 80021f2 <BusFault_Handler+0x4> 080021f4 <UsageFault_Handler>: /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80021f4: b480 push {r7} 80021f6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80021f8: e7fe b.n 80021f8 <UsageFault_Handler+0x4> 080021fa <SVC_Handler>: /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80021fa: b480 push {r7} 80021fc: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80021fe: bf00 nop 8002200: 46bd mov sp, r7 8002202: bc80 pop {r7} 8002204: 4770 bx lr 08002206 <DebugMon_Handler>: /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002206: b480 push {r7} 8002208: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800220a: bf00 nop 800220c: 46bd mov sp, r7 800220e: bc80 pop {r7} 8002210: 4770 bx lr 08002212 <PendSV_Handler>: /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002212: b480 push {r7} 8002214: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002216: bf00 nop 8002218: 46bd mov sp, r7 800221a: bc80 pop {r7} 800221c: 4770 bx lr 0800221e <SysTick_Handler>: /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800221e: b580 push {r7, lr} 8002220: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002222: f000 fc8d bl 8002b40 <HAL_IncTick> /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002226: bf00 nop 8002228: bd80 pop {r7, pc} ... 0800222c <ADC1_2_IRQHandler>: /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800222c: b580 push {r7, lr} 800222e: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_2_IRQn 0 */ /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8002230: 4803 ldr r0, [pc, #12] ; (8002240 <ADC1_2_IRQHandler+0x14>) 8002232: f001 f83f bl 80032b4 <HAL_ADC_IRQHandler> HAL_ADC_IRQHandler(&hadc2); 8002236: 4803 ldr r0, [pc, #12] ; (8002244 <ADC1_2_IRQHandler+0x18>) 8002238: f001 f83c bl 80032b4 <HAL_ADC_IRQHandler> /* USER CODE BEGIN ADC1_2_IRQn 1 */ /* USER CODE END ADC1_2_IRQn 1 */ } 800223c: bf00 nop 800223e: bd80 pop {r7, pc} 8002240: 2000040c .word 0x2000040c 8002244: 2000043c .word 0x2000043c 08002248 <TIM2_IRQHandler>: /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8002248: b580 push {r7, lr} 800224a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 800224c: 4802 ldr r0, [pc, #8] ; (8002258 <TIM2_IRQHandler+0x10>) 800224e: f003 fdb1 bl 8005db4 <HAL_TIM_IRQHandler> /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 8002252: bf00 nop 8002254: bd80 pop {r7, pc} 8002256: bf00 nop 8002258: 2000051c .word 0x2000051c 0800225c <TIM3_IRQHandler>: /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800225c: b580 push {r7, lr} 800225e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002260: 4802 ldr r0, [pc, #8] ; (800226c <TIM3_IRQHandler+0x10>) 8002262: f003 fda7 bl 8005db4 <HAL_TIM_IRQHandler> /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 8002266: bf00 nop 8002268: bd80 pop {r7, pc} 800226a: bf00 nop 800226c: 20000564 .word 0x20000564 08002270 <TIM4_IRQHandler>: /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 8002270: b580 push {r7, lr} 8002272: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 8002274: 4802 ldr r0, [pc, #8] ; (8002280 <TIM4_IRQHandler+0x10>) 8002276: f003 fd9d bl 8005db4 <HAL_TIM_IRQHandler> /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 800227a: bf00 nop 800227c: bd80 pop {r7, pc} 800227e: bf00 nop 8002280: 200005ac .word 0x200005ac 08002284 <SPI2_IRQHandler>: /** * @brief This function handles SPI2 global interrupt. */ void SPI2_IRQHandler(void) { 8002284: b580 push {r7, lr} 8002286: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_IRQn 0 */ /* USER CODE END SPI2_IRQn 0 */ HAL_SPI_IRQHandler(&hspi2); 8002288: 4802 ldr r0, [pc, #8] ; (8002294 <SPI2_IRQHandler+0x10>) 800228a: f003 f877 bl 800537c <HAL_SPI_IRQHandler> /* USER CODE BEGIN SPI2_IRQn 1 */ /* USER CODE END SPI2_IRQn 1 */ } 800228e: bf00 nop 8002290: bd80 pop {r7, pc} 8002292: bf00 nop 8002294: 200004c4 .word 0x200004c4 08002298 <EXTI15_10_IRQHandler>: /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8002298: b580 push {r7, lr} 800229a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 800229c: f44f 5080 mov.w r0, #4096 ; 0x1000 80022a0: f001 fdbe bl 8003e20 <HAL_GPIO_EXTI_IRQHandler> /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 80022a4: bf00 nop 80022a6: bd80 pop {r7, pc} 080022a8 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80022a8: b580 push {r7, lr} 80022aa: b086 sub sp, #24 80022ac: af00 add r7, sp, #0 80022ae: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80022b0: 4a14 ldr r2, [pc, #80] ; (8002304 <_sbrk+0x5c>) 80022b2: 4b15 ldr r3, [pc, #84] ; (8002308 <_sbrk+0x60>) 80022b4: 1ad3 subs r3, r2, r3 80022b6: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80022b8: 697b ldr r3, [r7, #20] 80022ba: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80022bc: 4b13 ldr r3, [pc, #76] ; (800230c <_sbrk+0x64>) 80022be: 681b ldr r3, [r3, #0] 80022c0: 2b00 cmp r3, #0 80022c2: d102 bne.n 80022ca <_sbrk+0x22> { __sbrk_heap_end = &_end; 80022c4: 4b11 ldr r3, [pc, #68] ; (800230c <_sbrk+0x64>) 80022c6: 4a12 ldr r2, [pc, #72] ; (8002310 <_sbrk+0x68>) 80022c8: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80022ca: 4b10 ldr r3, [pc, #64] ; (800230c <_sbrk+0x64>) 80022cc: 681a ldr r2, [r3, #0] 80022ce: 687b ldr r3, [r7, #4] 80022d0: 4413 add r3, r2 80022d2: 693a ldr r2, [r7, #16] 80022d4: 429a cmp r2, r3 80022d6: d207 bcs.n 80022e8 <_sbrk+0x40> { errno = ENOMEM; 80022d8: f005 fb48 bl 800796c <__errno> 80022dc: 4603 mov r3, r0 80022de: 220c movs r2, #12 80022e0: 601a str r2, [r3, #0] return (void *)-1; 80022e2: f04f 33ff mov.w r3, #4294967295 80022e6: e009 b.n 80022fc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80022e8: 4b08 ldr r3, [pc, #32] ; (800230c <_sbrk+0x64>) 80022ea: 681b ldr r3, [r3, #0] 80022ec: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80022ee: 4b07 ldr r3, [pc, #28] ; (800230c <_sbrk+0x64>) 80022f0: 681a ldr r2, [r3, #0] 80022f2: 687b ldr r3, [r7, #4] 80022f4: 4413 add r3, r2 80022f6: 4a05 ldr r2, [pc, #20] ; (800230c <_sbrk+0x64>) 80022f8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80022fa: 68fb ldr r3, [r7, #12] } 80022fc: 4618 mov r0, r3 80022fe: 3718 adds r7, #24 8002300: 46bd mov sp, r7 8002302: bd80 pop {r7, pc} 8002304: 20005000 .word 0x20005000 8002308: 00000400 .word 0x00000400 800230c: 20000744 .word 0x20000744 8002310: 20000df8 .word 0x20000df8 08002314 <SystemInit>: * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002314: b480 push {r7} 8002316: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002318: bf00 nop 800231a: 46bd mov sp, r7 800231c: bc80 pop {r7} 800231e: 4770 bx lr 08002320 <Reset_Handler>: .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002320: 480c ldr r0, [pc, #48] ; (8002354 <LoopFillZerobss+0x12>) ldr r1, =_edata 8002322: 490d ldr r1, [pc, #52] ; (8002358 <LoopFillZerobss+0x16>) ldr r2, =_sidata 8002324: 4a0d ldr r2, [pc, #52] ; (800235c <LoopFillZerobss+0x1a>) movs r3, #0 8002326: 2300 movs r3, #0 b LoopCopyDataInit 8002328: e002 b.n 8002330 <LoopCopyDataInit> 0800232a <CopyDataInit>: CopyDataInit: ldr r4, [r2, r3] 800232a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800232c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800232e: 3304 adds r3, #4 08002330 <LoopCopyDataInit>: LoopCopyDataInit: adds r4, r0, r3 8002330: 18c4 adds r4, r0, r3 cmp r4, r1 8002332: 428c cmp r4, r1 bcc CopyDataInit 8002334: d3f9 bcc.n 800232a <CopyDataInit> /* Zero fill the bss segment. */ ldr r2, =_sbss 8002336: 4a0a ldr r2, [pc, #40] ; (8002360 <LoopFillZerobss+0x1e>) ldr r4, =_ebss 8002338: 4c0a ldr r4, [pc, #40] ; (8002364 <LoopFillZerobss+0x22>) movs r3, #0 800233a: 2300 movs r3, #0 b LoopFillZerobss 800233c: e001 b.n 8002342 <LoopFillZerobss> 0800233e <FillZerobss>: FillZerobss: str r3, [r2] 800233e: 6013 str r3, [r2, #0] adds r2, r2, #4 8002340: 3204 adds r2, #4 08002342 <LoopFillZerobss>: LoopFillZerobss: cmp r2, r4 8002342: 42a2 cmp r2, r4 bcc FillZerobss 8002344: d3fb bcc.n 800233e <FillZerobss> /* Call the clock system intitialization function.*/ bl SystemInit 8002346: f7ff ffe5 bl 8002314 <SystemInit> /* Call static constructors */ bl __libc_init_array 800234a: f005 fb15 bl 8007978 <__libc_init_array> /* Call the application's entry point.*/ bl main 800234e: f7ff f9dd bl 800170c <main> bx lr 8002352: 4770 bx lr ldr r0, =_sdata 8002354: 20000000 .word 0x20000000 ldr r1, =_edata 8002358: 20000080 .word 0x20000080 ldr r2, =_sidata 800235c: 08008a94 .word 0x08008a94 ldr r2, =_sbss 8002360: 20000080 .word 0x20000080 ldr r4, =_ebss 8002364: 20000df4 .word 0x20000df4 08002368 <CAN1_RX1_IRQHandler>: * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002368: e7fe b.n 8002368 <CAN1_RX1_IRQHandler> ... 0800236c <SPI1_Send>: //------------------------------------------------------------- void SPI1_Send (uint8_t *dt, uint16_t cnt) { 800236c: b580 push {r7, lr} 800236e: b082 sub sp, #8 8002370: af00 add r7, sp, #0 8002372: 6078 str r0, [r7, #4] 8002374: 460b mov r3, r1 8002376: 807b strh r3, [r7, #2] HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); 8002378: 887a ldrh r2, [r7, #2] 800237a: f241 3388 movw r3, #5000 ; 0x1388 800237e: 6879 ldr r1, [r7, #4] 8002380: 4803 ldr r0, [pc, #12] ; (8002390 <SPI1_Send+0x24>) 8002382: f002 fb67 bl 8004a54 <HAL_SPI_Transmit> } 8002386: bf00 nop 8002388: 3708 adds r7, #8 800238a: 46bd mov sp, r7 800238c: bd80 pop {r7, pc} 800238e: bf00 nop 8002390: 2000046c .word 0x2000046c 08002394 <SPI1_Recv>: //------------------------------------------------------------- void SPI1_Recv (uint8_t *dt, uint16_t cnt) { 8002394: b580 push {r7, lr} 8002396: b082 sub sp, #8 8002398: af00 add r7, sp, #0 800239a: 6078 str r0, [r7, #4] 800239c: 460b mov r3, r1 800239e: 807b strh r3, [r7, #2] HAL_SPI_Receive (&hspi1, dt, cnt, 5000); 80023a0: 887a ldrh r2, [r7, #2] 80023a2: f241 3388 movw r3, #5000 ; 0x1388 80023a6: 6879 ldr r1, [r7, #4] 80023a8: 4803 ldr r0, [pc, #12] ; (80023b8 <SPI1_Recv+0x24>) 80023aa: f002 fc97 bl 8004cdc <HAL_SPI_Receive> } 80023ae: bf00 nop 80023b0: 3708 adds r7, #8 80023b2: 46bd mov sp, r7 80023b4: bd80 pop {r7, pc} 80023b6: bf00 nop 80023b8: 2000046c .word 0x2000046c 080023bc <W25_Reset>: //------------------------------------------------------------- void W25_Reset (void) { 80023bc: b580 push {r7, lr} 80023be: af00 add r7, sp, #0 cs_set(); 80023c0: 2200 movs r2, #0 80023c2: 2110 movs r1, #16 80023c4: 4809 ldr r0, [pc, #36] ; (80023ec <W25_Reset+0x30>) 80023c6: f001 fcfa bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_ENABLE_RESET; 80023ca: 4b09 ldr r3, [pc, #36] ; (80023f0 <W25_Reset+0x34>) 80023cc: 2266 movs r2, #102 ; 0x66 80023ce: 701a strb r2, [r3, #0] buf[1] = W25_RESET; 80023d0: 4b07 ldr r3, [pc, #28] ; (80023f0 <W25_Reset+0x34>) 80023d2: 2299 movs r2, #153 ; 0x99 80023d4: 705a strb r2, [r3, #1] SPI1_Send(buf, 2); 80023d6: 2102 movs r1, #2 80023d8: 4805 ldr r0, [pc, #20] ; (80023f0 <W25_Reset+0x34>) 80023da: f7ff ffc7 bl 800236c <SPI1_Send> cs_reset(); 80023de: 2201 movs r2, #1 80023e0: 2110 movs r1, #16 80023e2: 4802 ldr r0, [pc, #8] ; (80023ec <W25_Reset+0x30>) 80023e4: f001 fceb bl 8003dbe <HAL_GPIO_WritePin> } 80023e8: bf00 nop 80023ea: bd80 pop {r7, pc} 80023ec: 40010800 .word 0x40010800 80023f0: 2000078c .word 0x2000078c 080023f4 <W25_Write_Enable>: strcat(str_info,str1); sprintf(str1,"Capacity: %u KB\n",(unsigned int)w25_info.NumKB); strcat(str_info,str1); }//------------------------------------------------------------- void W25_Write_Enable(void) { 80023f4: b580 push {r7, lr} 80023f6: af00 add r7, sp, #0 cs_set(); 80023f8: 2200 movs r2, #0 80023fa: 2110 movs r1, #16 80023fc: 4808 ldr r0, [pc, #32] ; (8002420 <W25_Write_Enable+0x2c>) 80023fe: f001 fcde bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_WRITE_ENABLE; 8002402: 4b08 ldr r3, [pc, #32] ; (8002424 <W25_Write_Enable+0x30>) 8002404: 2206 movs r2, #6 8002406: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 8002408: 2101 movs r1, #1 800240a: 4806 ldr r0, [pc, #24] ; (8002424 <W25_Write_Enable+0x30>) 800240c: f7ff ffae bl 800236c <SPI1_Send> cs_reset(); 8002410: 2201 movs r2, #1 8002412: 2110 movs r1, #16 8002414: 4802 ldr r0, [pc, #8] ; (8002420 <W25_Write_Enable+0x2c>) 8002416: f001 fcd2 bl 8003dbe <HAL_GPIO_WritePin> } 800241a: bf00 nop 800241c: bd80 pop {r7, pc} 800241e: bf00 nop 8002420: 40010800 .word 0x40010800 8002424: 2000078c .word 0x2000078c 08002428 <W25_Write_Disable>: //------------------------------------------------------------- void W25_Write_Disable(void) { 8002428: b580 push {r7, lr} 800242a: af00 add r7, sp, #0 cs_set(); 800242c: 2200 movs r2, #0 800242e: 2110 movs r1, #16 8002430: 4808 ldr r0, [pc, #32] ; (8002454 <W25_Write_Disable+0x2c>) 8002432: f001 fcc4 bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_WRITE_DISABLE; 8002436: 4b08 ldr r3, [pc, #32] ; (8002458 <W25_Write_Disable+0x30>) 8002438: 2204 movs r2, #4 800243a: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 800243c: 2101 movs r1, #1 800243e: 4806 ldr r0, [pc, #24] ; (8002458 <W25_Write_Disable+0x30>) 8002440: f7ff ff94 bl 800236c <SPI1_Send> cs_reset(); 8002444: 2201 movs r2, #1 8002446: 2110 movs r1, #16 8002448: 4802 ldr r0, [pc, #8] ; (8002454 <W25_Write_Disable+0x2c>) 800244a: f001 fcb8 bl 8003dbe <HAL_GPIO_WritePin> } 800244e: bf00 nop 8002450: bd80 pop {r7, pc} 8002452: bf00 nop 8002454: 40010800 .word 0x40010800 8002458: 2000078c .word 0x2000078c 0800245c <W25_Set_Block_Protect>: //------------------------------------------------------------- void W25_Set_Block_Protect(uint8_t val) { 800245c: b580 push {r7, lr} 800245e: b082 sub sp, #8 8002460: af00 add r7, sp, #0 8002462: 4603 mov r3, r0 8002464: 71fb strb r3, [r7, #7] buf[1] = ((val & 0x0F) << 2); cs_set(); SPI1_Send(buf, 2); cs_reset();*/ W25_Ini(0); 8002466: 2000 movs r0, #0 8002468: f000 f902 bl 8002670 <W25_Ini> } 800246c: bf00 nop 800246e: 3708 adds r7, #8 8002470: 46bd mov sp, r7 8002472: bd80 pop {r7, pc} 08002474 <W25_Wait_Write_End>: //------------------------------------------------------------- void W25_Wait_Write_End(void) { 8002474: b580 push {r7, lr} 8002476: af00 add r7, sp, #0 HAL_Delay(1); 8002478: 2001 movs r0, #1 800247a: f000 fb7d bl 8002b78 <HAL_Delay> cs_set(); 800247e: 2200 movs r2, #0 8002480: 2110 movs r1, #16 8002482: 4812 ldr r0, [pc, #72] ; (80024cc <W25_Wait_Write_End+0x58>) 8002484: f001 fc9b bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_READ_STATUS_1; 8002488: 4b11 ldr r3, [pc, #68] ; (80024d0 <W25_Wait_Write_End+0x5c>) 800248a: 2205 movs r2, #5 800248c: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 800248e: 2101 movs r1, #1 8002490: 480f ldr r0, [pc, #60] ; (80024d0 <W25_Wait_Write_End+0x5c>) 8002492: f7ff ff6b bl 800236c <SPI1_Send> do{ SPI1_Recv(buf,1); 8002496: 2101 movs r1, #1 8002498: 480d ldr r0, [pc, #52] ; (80024d0 <W25_Wait_Write_End+0x5c>) 800249a: f7ff ff7b bl 8002394 <SPI1_Recv> w25_info.StatusRegister1 = buf[0]; 800249e: 4b0c ldr r3, [pc, #48] ; (80024d0 <W25_Wait_Write_End+0x5c>) 80024a0: 781a ldrb r2, [r3, #0] 80024a2: 4b0c ldr r3, [pc, #48] ; (80024d4 <W25_Wait_Write_End+0x60>) 80024a4: f883 2020 strb.w r2, [r3, #32] HAL_Delay(1); 80024a8: 2001 movs r0, #1 80024aa: f000 fb65 bl 8002b78 <HAL_Delay> } while((w25_info.StatusRegister1 & 0x01) == 0x01); 80024ae: 4b09 ldr r3, [pc, #36] ; (80024d4 <W25_Wait_Write_End+0x60>) 80024b0: f893 3020 ldrb.w r3, [r3, #32] 80024b4: f003 0301 and.w r3, r3, #1 80024b8: 2b00 cmp r3, #0 80024ba: d1ec bne.n 8002496 <W25_Wait_Write_End+0x22> cs_reset(); 80024bc: 2201 movs r2, #1 80024be: 2110 movs r1, #16 80024c0: 4802 ldr r0, [pc, #8] ; (80024cc <W25_Wait_Write_End+0x58>) 80024c2: f001 fc7c bl 8003dbe <HAL_GPIO_WritePin> } 80024c6: bf00 nop 80024c8: bd80 pop {r7, pc} 80024ca: bf00 nop 80024cc: 40010800 .word 0x40010800 80024d0: 2000078c .word 0x2000078c 80024d4: 20000748 .word 0x20000748 080024d8 <W25_Erase_Chip>: W25_Write_Disable(); W25_Set_Block_Protect(0x0F); } //------------------------------------------------------------- void W25_Erase_Chip(void) { 80024d8: b580 push {r7, lr} 80024da: af00 add r7, sp, #0 W25_Wait_Write_End(); 80024dc: f7ff ffca bl 8002474 <W25_Wait_Write_End> W25_Write_Enable(); 80024e0: f7ff ff88 bl 80023f4 <W25_Write_Enable> cs_set(); 80024e4: 2200 movs r2, #0 80024e6: 2110 movs r1, #16 80024e8: 480b ldr r0, [pc, #44] ; (8002518 <W25_Erase_Chip+0x40>) 80024ea: f001 fc68 bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_CHIP_ERASE; 80024ee: 4b0b ldr r3, [pc, #44] ; (800251c <W25_Erase_Chip+0x44>) 80024f0: 22c7 movs r2, #199 ; 0xc7 80024f2: 701a strb r2, [r3, #0] SPI1_Send(buf, 1); 80024f4: 2101 movs r1, #1 80024f6: 4809 ldr r0, [pc, #36] ; (800251c <W25_Erase_Chip+0x44>) 80024f8: f7ff ff38 bl 800236c <SPI1_Send> cs_reset(); 80024fc: 2201 movs r2, #1 80024fe: 2110 movs r1, #16 8002500: 4805 ldr r0, [pc, #20] ; (8002518 <W25_Erase_Chip+0x40>) 8002502: f001 fc5c bl 8003dbe <HAL_GPIO_WritePin> W25_Wait_Write_End(); 8002506: f7ff ffb5 bl 8002474 <W25_Wait_Write_End> W25_Write_Disable(); 800250a: f7ff ff8d bl 8002428 <W25_Write_Disable> W25_Set_Block_Protect(0x0F); 800250e: 200f movs r0, #15 8002510: f7ff ffa4 bl 800245c <W25_Set_Block_Protect> } 8002514: bf00 nop 8002516: bd80 pop {r7, pc} 8002518: 40010800 .word 0x40010800 800251c: 2000078c .word 0x2000078c 08002520 <W25_Write_Page>: W25_Write_Disable(); W25_Set_Block_Protect(0x0F); } //------------------------------------------------------------- void W25_Write_Page(uint8_t* data, uint32_t page_addr, uint32_t offset, uint32_t sz) { 8002520: b580 push {r7, lr} 8002522: b084 sub sp, #16 8002524: af00 add r7, sp, #0 8002526: 60f8 str r0, [r7, #12] 8002528: 60b9 str r1, [r7, #8] 800252a: 607a str r2, [r7, #4] 800252c: 603b str r3, [r7, #0] if(sz > w25_info.PageSize) 800252e: 4b39 ldr r3, [pc, #228] ; (8002614 <W25_Write_Page+0xf4>) 8002530: 881b ldrh r3, [r3, #0] 8002532: 461a mov r2, r3 8002534: 683b ldr r3, [r7, #0] 8002536: 4293 cmp r3, r2 8002538: d902 bls.n 8002540 <W25_Write_Page+0x20> sz=w25_info.PageSize; 800253a: 4b36 ldr r3, [pc, #216] ; (8002614 <W25_Write_Page+0xf4>) 800253c: 881b ldrh r3, [r3, #0] 800253e: 603b str r3, [r7, #0] if((offset+sz) > w25_info.PageSize) 8002540: 687a ldr r2, [r7, #4] 8002542: 683b ldr r3, [r7, #0] 8002544: 4413 add r3, r2 8002546: 4a33 ldr r2, [pc, #204] ; (8002614 <W25_Write_Page+0xf4>) 8002548: 8812 ldrh r2, [r2, #0] 800254a: 4293 cmp r3, r2 800254c: d905 bls.n 800255a <W25_Write_Page+0x3a> sz = w25_info.PageSize - offset; 800254e: 4b31 ldr r3, [pc, #196] ; (8002614 <W25_Write_Page+0xf4>) 8002550: 881b ldrh r3, [r3, #0] 8002552: 461a mov r2, r3 8002554: 687b ldr r3, [r7, #4] 8002556: 1ad3 subs r3, r2, r3 8002558: 603b str r3, [r7, #0] page_addr = page_addr * w25_info.PageSize + offset; 800255a: 4b2e ldr r3, [pc, #184] ; (8002614 <W25_Write_Page+0xf4>) 800255c: 881b ldrh r3, [r3, #0] 800255e: 461a mov r2, r3 8002560: 68bb ldr r3, [r7, #8] 8002562: fb02 f303 mul.w r3, r2, r3 8002566: 687a ldr r2, [r7, #4] 8002568: 4413 add r3, r2 800256a: 60bb str r3, [r7, #8] W25_Wait_Write_End(); 800256c: f7ff ff82 bl 8002474 <W25_Wait_Write_End> W25_Set_Block_Protect(0x00); 8002570: 2000 movs r0, #0 8002572: f7ff ff73 bl 800245c <W25_Set_Block_Protect> W25_Write_Enable(); 8002576: f7ff ff3d bl 80023f4 <W25_Write_Enable> cs_set(); 800257a: 2200 movs r2, #0 800257c: 2110 movs r1, #16 800257e: 4826 ldr r0, [pc, #152] ; (8002618 <W25_Write_Page+0xf8>) 8002580: f001 fc1d bl 8003dbe <HAL_GPIO_WritePin> buf[0] = W25_PAGE_PROGRAMM; 8002584: 4b25 ldr r3, [pc, #148] ; (800261c <W25_Write_Page+0xfc>) 8002586: 2202 movs r2, #2 8002588: 701a strb r2, [r3, #0] if(w25_info.high_cap) 800258a: 4b22 ldr r3, [pc, #136] ; (8002614 <W25_Write_Page+0xf4>) 800258c: 7fdb ldrb r3, [r3, #31] 800258e: 2b00 cmp r3, #0 8002590: d017 beq.n 80025c2 <W25_Write_Page+0xa2> { buf[1] = (page_addr >> 24) & 0xFF; 8002592: 68bb ldr r3, [r7, #8] 8002594: 0e1b lsrs r3, r3, #24 8002596: b2da uxtb r2, r3 8002598: 4b20 ldr r3, [pc, #128] ; (800261c <W25_Write_Page+0xfc>) 800259a: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 16) & 0xFF; 800259c: 68bb ldr r3, [r7, #8] 800259e: 0c1b lsrs r3, r3, #16 80025a0: b2da uxtb r2, r3 80025a2: 4b1e ldr r3, [pc, #120] ; (800261c <W25_Write_Page+0xfc>) 80025a4: 709a strb r2, [r3, #2] buf[3] = (page_addr >> 8) & 0xFF; 80025a6: 68bb ldr r3, [r7, #8] 80025a8: 0a1b lsrs r3, r3, #8 80025aa: b2da uxtb r2, r3 80025ac: 4b1b ldr r3, [pc, #108] ; (800261c <W25_Write_Page+0xfc>) 80025ae: 70da strb r2, [r3, #3] buf[4] = page_addr & 0xFF; 80025b0: 68bb ldr r3, [r7, #8] 80025b2: b2da uxtb r2, r3 80025b4: 4b19 ldr r3, [pc, #100] ; (800261c <W25_Write_Page+0xfc>) 80025b6: 711a strb r2, [r3, #4] SPI1_Send(buf, 5); 80025b8: 2105 movs r1, #5 80025ba: 4818 ldr r0, [pc, #96] ; (800261c <W25_Write_Page+0xfc>) 80025bc: f7ff fed6 bl 800236c <SPI1_Send> 80025c0: e011 b.n 80025e6 <W25_Write_Page+0xc6> } else { buf[1] = (page_addr >> 16) & 0xFF; 80025c2: 68bb ldr r3, [r7, #8] 80025c4: 0c1b lsrs r3, r3, #16 80025c6: b2da uxtb r2, r3 80025c8: 4b14 ldr r3, [pc, #80] ; (800261c <W25_Write_Page+0xfc>) 80025ca: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 8) & 0xFF; 80025cc: 68bb ldr r3, [r7, #8] 80025ce: 0a1b lsrs r3, r3, #8 80025d0: b2da uxtb r2, r3 80025d2: 4b12 ldr r3, [pc, #72] ; (800261c <W25_Write_Page+0xfc>) 80025d4: 709a strb r2, [r3, #2] buf[3] = page_addr & 0xFF; 80025d6: 68bb ldr r3, [r7, #8] 80025d8: b2da uxtb r2, r3 80025da: 4b10 ldr r3, [pc, #64] ; (800261c <W25_Write_Page+0xfc>) 80025dc: 70da strb r2, [r3, #3] SPI1_Send(buf, 4); 80025de: 2104 movs r1, #4 80025e0: 480e ldr r0, [pc, #56] ; (800261c <W25_Write_Page+0xfc>) 80025e2: f7ff fec3 bl 800236c <SPI1_Send> } SPI1_Send(data, sz); 80025e6: 683b ldr r3, [r7, #0] 80025e8: b29b uxth r3, r3 80025ea: 4619 mov r1, r3 80025ec: 68f8 ldr r0, [r7, #12] 80025ee: f7ff febd bl 800236c <SPI1_Send> cs_reset(); 80025f2: 2201 movs r2, #1 80025f4: 2110 movs r1, #16 80025f6: 4808 ldr r0, [pc, #32] ; (8002618 <W25_Write_Page+0xf8>) 80025f8: f001 fbe1 bl 8003dbe <HAL_GPIO_WritePin> W25_Wait_Write_End(); 80025fc: f7ff ff3a bl 8002474 <W25_Wait_Write_End> W25_Write_Disable(); 8002600: f7ff ff12 bl 8002428 <W25_Write_Disable> W25_Set_Block_Protect(0x0F); 8002604: 200f movs r0, #15 8002606: f7ff ff29 bl 800245c <W25_Set_Block_Protect> } 800260a: bf00 nop 800260c: 3710 adds r7, #16 800260e: 46bd mov sp, r7 8002610: bd80 pop {r7, pc} 8002612: bf00 nop 8002614: 20000748 .word 0x20000748 8002618: 40010800 .word 0x40010800 800261c: 2000078c .word 0x2000078c 08002620 <W25_Read_ID>: SPI1_Recv(data, sz); cs_reset(); } //------------------------------------------------------------- uint32_t W25_Read_ID(void) { 8002620: b580 push {r7, lr} 8002622: b082 sub sp, #8 8002624: af00 add r7, sp, #0 uint8_t dt[4]; buf[0] = W25_GET_JEDEC_ID; 8002626: 4b10 ldr r3, [pc, #64] ; (8002668 <W25_Read_ID+0x48>) 8002628: 229f movs r2, #159 ; 0x9f 800262a: 701a strb r2, [r3, #0] cs_set(); 800262c: 2200 movs r2, #0 800262e: 2110 movs r1, #16 8002630: 480e ldr r0, [pc, #56] ; (800266c <W25_Read_ID+0x4c>) 8002632: f001 fbc4 bl 8003dbe <HAL_GPIO_WritePin> SPI1_Send(buf, 1); 8002636: 2101 movs r1, #1 8002638: 480b ldr r0, [pc, #44] ; (8002668 <W25_Read_ID+0x48>) 800263a: f7ff fe97 bl 800236c <SPI1_Send> SPI1_Recv(dt,3); 800263e: 1d3b adds r3, r7, #4 8002640: 2103 movs r1, #3 8002642: 4618 mov r0, r3 8002644: f7ff fea6 bl 8002394 <SPI1_Recv> cs_reset(); 8002648: 2201 movs r2, #1 800264a: 2110 movs r1, #16 800264c: 4807 ldr r0, [pc, #28] ; (800266c <W25_Read_ID+0x4c>) 800264e: f001 fbb6 bl 8003dbe <HAL_GPIO_WritePin> return (dt[0] << 16) | (dt[1] << 8) | dt[2]; 8002652: 793b ldrb r3, [r7, #4] 8002654: 041a lsls r2, r3, #16 8002656: 797b ldrb r3, [r7, #5] 8002658: 021b lsls r3, r3, #8 800265a: 4313 orrs r3, r2 800265c: 79ba ldrb r2, [r7, #6] 800265e: 4313 orrs r3, r2 } 8002660: 4618 mov r0, r3 8002662: 3708 adds r7, #8 8002664: 46bd mov sp, r7 8002666: bd80 pop {r7, pc} 8002668: 2000078c .word 0x2000078c 800266c: 40010800 .word 0x40010800 08002670 <W25_Ini>: //------------------------------------------------------------- void W25_Ini(char need_report) { 8002670: b580 push {r7, lr} 8002672: b084 sub sp, #16 8002674: af00 add r7, sp, #0 8002676: 4603 mov r3, r0 8002678: 71fb strb r3, [r7, #7] unsigned int id = W25_Read_ID(); 800267a: f7ff ffd1 bl 8002620 <W25_Read_ID> 800267e: 60f8 str r0, [r7, #12] HAL_Delay(100); 8002680: 2064 movs r0, #100 ; 0x64 8002682: f000 fa79 bl 8002b78 <HAL_Delay> W25_Reset(); 8002686: f7ff fe99 bl 80023bc <W25_Reset> HAL_Delay(100); 800268a: 2064 movs r0, #100 ; 0x64 800268c: f000 fa74 bl 8002b78 <HAL_Delay> if (need_report) 8002690: 79fb ldrb r3, [r7, #7] 8002692: 2b00 cmp r3, #0 8002694: d016 beq.n 80026c4 <W25_Ini+0x54> { HAL_UART_Transmit(&huart1,(uint8_t*)"\r\n",2,0x1000); 8002696: f44f 5380 mov.w r3, #4096 ; 0x1000 800269a: 2202 movs r2, #2 800269c: 4950 ldr r1, [pc, #320] ; (80027e0 <W25_Ini+0x170>) 800269e: 4851 ldr r0, [pc, #324] ; (80027e4 <W25_Ini+0x174>) 80026a0: f004 f9b0 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"ID:0x%X\r\n",id); 80026a4: 68fa ldr r2, [r7, #12] 80026a6: 4950 ldr r1, [pc, #320] ; (80027e8 <W25_Ini+0x178>) 80026a8: 4850 ldr r0, [pc, #320] ; (80027ec <W25_Ini+0x17c>) 80026aa: f005 f99f bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80026ae: 484f ldr r0, [pc, #316] ; (80027ec <W25_Ini+0x17c>) 80026b0: f7fd fd4e bl 8000150 <strlen> 80026b4: 4603 mov r3, r0 80026b6: b29a uxth r2, r3 80026b8: f44f 5380 mov.w r3, #4096 ; 0x1000 80026bc: 494b ldr r1, [pc, #300] ; (80027ec <W25_Ini+0x17c>) 80026be: 4849 ldr r0, [pc, #292] ; (80027e4 <W25_Ini+0x174>) 80026c0: f004 f9a0 bl 8006a04 <HAL_UART_Transmit> } id &= 0x0000ffff; 80026c4: 68fb ldr r3, [r7, #12] 80026c6: b29b uxth r3, r3 80026c8: 60fb str r3, [r7, #12] w25_info.high_cap = 0; 80026ca: 4b49 ldr r3, [pc, #292] ; (80027f0 <W25_Ini+0x180>) 80026cc: 2200 movs r2, #0 80026ce: 77da strb r2, [r3, #31] switch(id) 80026d0: 68fb ldr r3, [r7, #12] 80026d2: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 80026d6: 3b11 subs r3, #17 80026d8: 2b09 cmp r3, #9 80026da: d870 bhi.n 80027be <W25_Ini+0x14e> 80026dc: a201 add r2, pc, #4 ; (adr r2, 80026e4 <W25_Ini+0x74>) 80026de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80026e2: bf00 nop 80026e4: 080027af .word 0x080027af 80026e8: 0800279f .word 0x0800279f 80026ec: 0800278f .word 0x0800278f 80026f0: 0800277f .word 0x0800277f 80026f4: 0800276f .word 0x0800276f 80026f8: 0800275f .word 0x0800275f 80026fc: 0800274f .word 0x0800274f 8002700: 0800273d .word 0x0800273d 8002704: 08002725 .word 0x08002725 8002708: 0800270d .word 0x0800270d { case 0x401A: w25_info.high_cap=1; 800270c: 4b38 ldr r3, [pc, #224] ; (80027f0 <W25_Ini+0x180>) 800270e: 2201 movs r2, #1 8002710: 77da strb r2, [r3, #31] w25_info.BlockCount=1024; 8002712: 4b37 ldr r3, [pc, #220] ; (80027f0 <W25_Ini+0x180>) 8002714: f44f 6280 mov.w r2, #1024 ; 0x400 8002718: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q512\r\n"); 800271a: 4936 ldr r1, [pc, #216] ; (80027f4 <W25_Ini+0x184>) 800271c: 4833 ldr r0, [pc, #204] ; (80027ec <W25_Ini+0x17c>) 800271e: f005 f965 bl 80079ec <siprintf> break; 8002722: e07d b.n 8002820 <W25_Ini+0x1b0> case 0x4019: w25_info.high_cap=1; 8002724: 4b32 ldr r3, [pc, #200] ; (80027f0 <W25_Ini+0x180>) 8002726: 2201 movs r2, #1 8002728: 77da strb r2, [r3, #31] w25_info.BlockCount=512; 800272a: 4b31 ldr r3, [pc, #196] ; (80027f0 <W25_Ini+0x180>) 800272c: f44f 7200 mov.w r2, #512 ; 0x200 8002730: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q256\r\n"); 8002732: 4931 ldr r1, [pc, #196] ; (80027f8 <W25_Ini+0x188>) 8002734: 482d ldr r0, [pc, #180] ; (80027ec <W25_Ini+0x17c>) 8002736: f005 f959 bl 80079ec <siprintf> break; 800273a: e071 b.n 8002820 <W25_Ini+0x1b0> case 0x4018: w25_info.BlockCount=256; 800273c: 4b2c ldr r3, [pc, #176] ; (80027f0 <W25_Ini+0x180>) 800273e: f44f 7280 mov.w r2, #256 ; 0x100 8002742: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q128\r\n"); 8002744: 492d ldr r1, [pc, #180] ; (80027fc <W25_Ini+0x18c>) 8002746: 4829 ldr r0, [pc, #164] ; (80027ec <W25_Ini+0x17c>) 8002748: f005 f950 bl 80079ec <siprintf> break; 800274c: e068 b.n 8002820 <W25_Ini+0x1b0> case 0x4017: w25_info.BlockCount=128; 800274e: 4b28 ldr r3, [pc, #160] ; (80027f0 <W25_Ini+0x180>) 8002750: 2280 movs r2, #128 ; 0x80 8002752: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q64\r\n"); 8002754: 492a ldr r1, [pc, #168] ; (8002800 <W25_Ini+0x190>) 8002756: 4825 ldr r0, [pc, #148] ; (80027ec <W25_Ini+0x17c>) 8002758: f005 f948 bl 80079ec <siprintf> break; 800275c: e060 b.n 8002820 <W25_Ini+0x1b0> case 0x4016: w25_info.BlockCount=64; 800275e: 4b24 ldr r3, [pc, #144] ; (80027f0 <W25_Ini+0x180>) 8002760: 2240 movs r2, #64 ; 0x40 8002762: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q32\r\n"); 8002764: 4927 ldr r1, [pc, #156] ; (8002804 <W25_Ini+0x194>) 8002766: 4821 ldr r0, [pc, #132] ; (80027ec <W25_Ini+0x17c>) 8002768: f005 f940 bl 80079ec <siprintf> break; 800276c: e058 b.n 8002820 <W25_Ini+0x1b0> case 0x4015: w25_info.BlockCount=32; 800276e: 4b20 ldr r3, [pc, #128] ; (80027f0 <W25_Ini+0x180>) 8002770: 2220 movs r2, #32 8002772: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q16\r\n"); 8002774: 4924 ldr r1, [pc, #144] ; (8002808 <W25_Ini+0x198>) 8002776: 481d ldr r0, [pc, #116] ; (80027ec <W25_Ini+0x17c>) 8002778: f005 f938 bl 80079ec <siprintf> break; 800277c: e050 b.n 8002820 <W25_Ini+0x1b0> case 0x4014: w25_info.BlockCount=16; 800277e: 4b1c ldr r3, [pc, #112] ; (80027f0 <W25_Ini+0x180>) 8002780: 2210 movs r2, #16 8002782: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q80\r\n"); 8002784: 4921 ldr r1, [pc, #132] ; (800280c <W25_Ini+0x19c>) 8002786: 4819 ldr r0, [pc, #100] ; (80027ec <W25_Ini+0x17c>) 8002788: f005 f930 bl 80079ec <siprintf> break; 800278c: e048 b.n 8002820 <W25_Ini+0x1b0> case 0x4013: w25_info.BlockCount=8; 800278e: 4b18 ldr r3, [pc, #96] ; (80027f0 <W25_Ini+0x180>) 8002790: 2208 movs r2, #8 8002792: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q40\r\n"); 8002794: 491e ldr r1, [pc, #120] ; (8002810 <W25_Ini+0x1a0>) 8002796: 4815 ldr r0, [pc, #84] ; (80027ec <W25_Ini+0x17c>) 8002798: f005 f928 bl 80079ec <siprintf> break; 800279c: e040 b.n 8002820 <W25_Ini+0x1b0> case 0x4012: w25_info.BlockCount=4; 800279e: 4b14 ldr r3, [pc, #80] ; (80027f0 <W25_Ini+0x180>) 80027a0: 2204 movs r2, #4 80027a2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q20\r\n"); 80027a4: 491b ldr r1, [pc, #108] ; (8002814 <W25_Ini+0x1a4>) 80027a6: 4811 ldr r0, [pc, #68] ; (80027ec <W25_Ini+0x17c>) 80027a8: f005 f920 bl 80079ec <siprintf> break; 80027ac: e038 b.n 8002820 <W25_Ini+0x1b0> case 0x4011: w25_info.BlockCount=2; 80027ae: 4b10 ldr r3, [pc, #64] ; (80027f0 <W25_Ini+0x180>) 80027b0: 2202 movs r2, #2 80027b2: 615a str r2, [r3, #20] sprintf(str1,"w25qxx Chip: w25q10\r\n"); 80027b4: 4918 ldr r1, [pc, #96] ; (8002818 <W25_Ini+0x1a8>) 80027b6: 480d ldr r0, [pc, #52] ; (80027ec <W25_Ini+0x17c>) 80027b8: f005 f918 bl 80079ec <siprintf> break; 80027bc: e030 b.n 8002820 <W25_Ini+0x1b0> default: sprintf(str1,"w25qxx Unknown ID\r\n"); 80027be: 4917 ldr r1, [pc, #92] ; (800281c <W25_Ini+0x1ac>) 80027c0: 480a ldr r0, [pc, #40] ; (80027ec <W25_Ini+0x17c>) 80027c2: f005 f913 bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80027c6: 4809 ldr r0, [pc, #36] ; (80027ec <W25_Ini+0x17c>) 80027c8: f7fd fcc2 bl 8000150 <strlen> 80027cc: 4603 mov r3, r0 80027ce: b29a uxth r2, r3 80027d0: f44f 5380 mov.w r3, #4096 ; 0x1000 80027d4: 4905 ldr r1, [pc, #20] ; (80027ec <W25_Ini+0x17c>) 80027d6: 4803 ldr r0, [pc, #12] ; (80027e4 <W25_Ini+0x174>) 80027d8: f004 f914 bl 8006a04 <HAL_UART_Transmit> return; 80027dc: e0d6 b.n 800298c <W25_Ini+0x31c> 80027de: bf00 nop 80027e0: 08008480 .word 0x08008480 80027e4: 200005f4 .word 0x200005f4 80027e8: 08008484 .word 0x08008484 80027ec: 2000076c .word 0x2000076c 80027f0: 20000748 .word 0x20000748 80027f4: 08008490 .word 0x08008490 80027f8: 080084a8 .word 0x080084a8 80027fc: 080084c0 .word 0x080084c0 8002800: 080084d8 .word 0x080084d8 8002804: 080084f0 .word 0x080084f0 8002808: 08008508 .word 0x08008508 800280c: 08008520 .word 0x08008520 8002810: 08008538 .word 0x08008538 8002814: 08008550 .word 0x08008550 8002818: 08008568 .word 0x08008568 800281c: 08008580 .word 0x08008580 } if (need_report) 8002820: 79fb ldrb r3, [r7, #7] 8002822: 2b00 cmp r3, #0 8002824: d00a beq.n 800283c <W25_Ini+0x1cc> { HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8002826: 485b ldr r0, [pc, #364] ; (8002994 <W25_Ini+0x324>) 8002828: f7fd fc92 bl 8000150 <strlen> 800282c: 4603 mov r3, r0 800282e: b29a uxth r2, r3 8002830: f44f 5380 mov.w r3, #4096 ; 0x1000 8002834: 4957 ldr r1, [pc, #348] ; (8002994 <W25_Ini+0x324>) 8002836: 4858 ldr r0, [pc, #352] ; (8002998 <W25_Ini+0x328>) 8002838: f004 f8e4 bl 8006a04 <HAL_UART_Transmit> } w25_info.PageSize=256; 800283c: 4b57 ldr r3, [pc, #348] ; (800299c <W25_Ini+0x32c>) 800283e: f44f 7280 mov.w r2, #256 ; 0x100 8002842: 801a strh r2, [r3, #0] w25_info.SectorSize=0x1000; 8002844: 4b55 ldr r3, [pc, #340] ; (800299c <W25_Ini+0x32c>) 8002846: f44f 5280 mov.w r2, #4096 ; 0x1000 800284a: 609a str r2, [r3, #8] w25_info.SectorCount=w25_info.BlockCount*16; 800284c: 4b53 ldr r3, [pc, #332] ; (800299c <W25_Ini+0x32c>) 800284e: 695b ldr r3, [r3, #20] 8002850: 011b lsls r3, r3, #4 8002852: 4a52 ldr r2, [pc, #328] ; (800299c <W25_Ini+0x32c>) 8002854: 60d3 str r3, [r2, #12] w25_info.PageCount=(w25_info.SectorCount*w25_info.SectorSize)/w25_info.PageSize; 8002856: 4b51 ldr r3, [pc, #324] ; (800299c <W25_Ini+0x32c>) 8002858: 68db ldr r3, [r3, #12] 800285a: 4a50 ldr r2, [pc, #320] ; (800299c <W25_Ini+0x32c>) 800285c: 6892 ldr r2, [r2, #8] 800285e: fb02 f303 mul.w r3, r2, r3 8002862: 4a4e ldr r2, [pc, #312] ; (800299c <W25_Ini+0x32c>) 8002864: 8812 ldrh r2, [r2, #0] 8002866: fbb3 f3f2 udiv r3, r3, r2 800286a: 4a4c ldr r2, [pc, #304] ; (800299c <W25_Ini+0x32c>) 800286c: 6053 str r3, [r2, #4] w25_info.BlockSize=w25_info.SectorSize*16; 800286e: 4b4b ldr r3, [pc, #300] ; (800299c <W25_Ini+0x32c>) 8002870: 689b ldr r3, [r3, #8] 8002872: 011b lsls r3, r3, #4 8002874: 4a49 ldr r2, [pc, #292] ; (800299c <W25_Ini+0x32c>) 8002876: 6113 str r3, [r2, #16] w25_info.NumKB=(w25_info.SectorCount*w25_info.SectorSize)/1024; 8002878: 4b48 ldr r3, [pc, #288] ; (800299c <W25_Ini+0x32c>) 800287a: 68db ldr r3, [r3, #12] 800287c: 4a47 ldr r2, [pc, #284] ; (800299c <W25_Ini+0x32c>) 800287e: 6892 ldr r2, [r2, #8] 8002880: fb02 f303 mul.w r3, r2, r3 8002884: 0a9b lsrs r3, r3, #10 8002886: 4a45 ldr r2, [pc, #276] ; (800299c <W25_Ini+0x32c>) 8002888: 6193 str r3, [r2, #24] if (need_report) 800288a: 79fb ldrb r3, [r7, #7] 800288c: 2b00 cmp r3, #0 800288e: d07d beq.n 800298c <W25_Ini+0x31c> { sprintf(str1,"Page Size: %d Bytes\r\n",(unsigned int)w25_info.PageSize);HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8002890: 4b42 ldr r3, [pc, #264] ; (800299c <W25_Ini+0x32c>) 8002892: 881b ldrh r3, [r3, #0] 8002894: 461a mov r2, r3 8002896: 4942 ldr r1, [pc, #264] ; (80029a0 <W25_Ini+0x330>) 8002898: 483e ldr r0, [pc, #248] ; (8002994 <W25_Ini+0x324>) 800289a: f005 f8a7 bl 80079ec <siprintf> 800289e: 483d ldr r0, [pc, #244] ; (8002994 <W25_Ini+0x324>) 80028a0: f7fd fc56 bl 8000150 <strlen> 80028a4: 4603 mov r3, r0 80028a6: b29a uxth r2, r3 80028a8: f44f 5380 mov.w r3, #4096 ; 0x1000 80028ac: 4939 ldr r1, [pc, #228] ; (8002994 <W25_Ini+0x324>) 80028ae: 483a ldr r0, [pc, #232] ; (8002998 <W25_Ini+0x328>) 80028b0: f004 f8a8 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Page Count: %u\r\n",(unsigned int)w25_info.PageCount); 80028b4: 4b39 ldr r3, [pc, #228] ; (800299c <W25_Ini+0x32c>) 80028b6: 685b ldr r3, [r3, #4] 80028b8: 461a mov r2, r3 80028ba: 493a ldr r1, [pc, #232] ; (80029a4 <W25_Ini+0x334>) 80028bc: 4835 ldr r0, [pc, #212] ; (8002994 <W25_Ini+0x324>) 80028be: f005 f895 bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80028c2: 4834 ldr r0, [pc, #208] ; (8002994 <W25_Ini+0x324>) 80028c4: f7fd fc44 bl 8000150 <strlen> 80028c8: 4603 mov r3, r0 80028ca: b29a uxth r2, r3 80028cc: f44f 5380 mov.w r3, #4096 ; 0x1000 80028d0: 4930 ldr r1, [pc, #192] ; (8002994 <W25_Ini+0x324>) 80028d2: 4831 ldr r0, [pc, #196] ; (8002998 <W25_Ini+0x328>) 80028d4: f004 f896 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Sector Size: %u Bytes\r\n",(unsigned int)w25_info.SectorSize); 80028d8: 4b30 ldr r3, [pc, #192] ; (800299c <W25_Ini+0x32c>) 80028da: 689b ldr r3, [r3, #8] 80028dc: 461a mov r2, r3 80028de: 4932 ldr r1, [pc, #200] ; (80029a8 <W25_Ini+0x338>) 80028e0: 482c ldr r0, [pc, #176] ; (8002994 <W25_Ini+0x324>) 80028e2: f005 f883 bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 80028e6: 482b ldr r0, [pc, #172] ; (8002994 <W25_Ini+0x324>) 80028e8: f7fd fc32 bl 8000150 <strlen> 80028ec: 4603 mov r3, r0 80028ee: b29a uxth r2, r3 80028f0: f44f 5380 mov.w r3, #4096 ; 0x1000 80028f4: 4927 ldr r1, [pc, #156] ; (8002994 <W25_Ini+0x324>) 80028f6: 4828 ldr r0, [pc, #160] ; (8002998 <W25_Ini+0x328>) 80028f8: f004 f884 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Sector Count: %u\r\n",(unsigned int)w25_info.SectorCount); 80028fc: 4b27 ldr r3, [pc, #156] ; (800299c <W25_Ini+0x32c>) 80028fe: 68db ldr r3, [r3, #12] 8002900: 461a mov r2, r3 8002902: 492a ldr r1, [pc, #168] ; (80029ac <W25_Ini+0x33c>) 8002904: 4823 ldr r0, [pc, #140] ; (8002994 <W25_Ini+0x324>) 8002906: f005 f871 bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 800290a: 4822 ldr r0, [pc, #136] ; (8002994 <W25_Ini+0x324>) 800290c: f7fd fc20 bl 8000150 <strlen> 8002910: 4603 mov r3, r0 8002912: b29a uxth r2, r3 8002914: f44f 5380 mov.w r3, #4096 ; 0x1000 8002918: 491e ldr r1, [pc, #120] ; (8002994 <W25_Ini+0x324>) 800291a: 481f ldr r0, [pc, #124] ; (8002998 <W25_Ini+0x328>) 800291c: f004 f872 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Block Size: %u Bytes\r\n",(unsigned int)w25_info.BlockSize); 8002920: 4b1e ldr r3, [pc, #120] ; (800299c <W25_Ini+0x32c>) 8002922: 691b ldr r3, [r3, #16] 8002924: 461a mov r2, r3 8002926: 4922 ldr r1, [pc, #136] ; (80029b0 <W25_Ini+0x340>) 8002928: 481a ldr r0, [pc, #104] ; (8002994 <W25_Ini+0x324>) 800292a: f005 f85f bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 800292e: 4819 ldr r0, [pc, #100] ; (8002994 <W25_Ini+0x324>) 8002930: f7fd fc0e bl 8000150 <strlen> 8002934: 4603 mov r3, r0 8002936: b29a uxth r2, r3 8002938: f44f 5380 mov.w r3, #4096 ; 0x1000 800293c: 4915 ldr r1, [pc, #84] ; (8002994 <W25_Ini+0x324>) 800293e: 4816 ldr r0, [pc, #88] ; (8002998 <W25_Ini+0x328>) 8002940: f004 f860 bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Block Count: %u\r\n",(unsigned int)w25_info.BlockCount); 8002944: 4b15 ldr r3, [pc, #84] ; (800299c <W25_Ini+0x32c>) 8002946: 695b ldr r3, [r3, #20] 8002948: 461a mov r2, r3 800294a: 491a ldr r1, [pc, #104] ; (80029b4 <W25_Ini+0x344>) 800294c: 4811 ldr r0, [pc, #68] ; (8002994 <W25_Ini+0x324>) 800294e: f005 f84d bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8002952: 4810 ldr r0, [pc, #64] ; (8002994 <W25_Ini+0x324>) 8002954: f7fd fbfc bl 8000150 <strlen> 8002958: 4603 mov r3, r0 800295a: b29a uxth r2, r3 800295c: f44f 5380 mov.w r3, #4096 ; 0x1000 8002960: 490c ldr r1, [pc, #48] ; (8002994 <W25_Ini+0x324>) 8002962: 480d ldr r0, [pc, #52] ; (8002998 <W25_Ini+0x328>) 8002964: f004 f84e bl 8006a04 <HAL_UART_Transmit> sprintf(str1,"Capacity: %u KB\r\n",(unsigned int)w25_info.NumKB); 8002968: 4b0c ldr r3, [pc, #48] ; (800299c <W25_Ini+0x32c>) 800296a: 699b ldr r3, [r3, #24] 800296c: 461a mov r2, r3 800296e: 4912 ldr r1, [pc, #72] ; (80029b8 <W25_Ini+0x348>) 8002970: 4808 ldr r0, [pc, #32] ; (8002994 <W25_Ini+0x324>) 8002972: f005 f83b bl 80079ec <siprintf> HAL_UART_Transmit(&huart1,(uint8_t*)str1,strlen(str1),0x1000); 8002976: 4807 ldr r0, [pc, #28] ; (8002994 <W25_Ini+0x324>) 8002978: f7fd fbea bl 8000150 <strlen> 800297c: 4603 mov r3, r0 800297e: b29a uxth r2, r3 8002980: f44f 5380 mov.w r3, #4096 ; 0x1000 8002984: 4903 ldr r1, [pc, #12] ; (8002994 <W25_Ini+0x324>) 8002986: 4804 ldr r0, [pc, #16] ; (8002998 <W25_Ini+0x328>) 8002988: f004 f83c bl 8006a04 <HAL_UART_Transmit> } } 800298c: 3710 adds r7, #16 800298e: 46bd mov sp, r7 8002990: bd80 pop {r7, pc} 8002992: bf00 nop 8002994: 2000076c .word 0x2000076c 8002998: 200005f4 .word 0x200005f4 800299c: 20000748 .word 0x20000748 80029a0: 08008594 .word 0x08008594 80029a4: 080085ac .word 0x080085ac 80029a8: 080085c0 .word 0x080085c0 80029ac: 0800842c .word 0x0800842c 80029b0: 080085d8 .word 0x080085d8 80029b4: 080085f0 .word 0x080085f0 80029b8: 08008604 .word 0x08008604 080029bc <W25_Read_Page>: //------------------------------------------------------------- void W25_Read_Page(uint8_t* data, uint32_t page_addr, uint32_t offset, uint32_t sz) { 80029bc: b580 push {r7, lr} 80029be: b084 sub sp, #16 80029c0: af00 add r7, sp, #0 80029c2: 60f8 str r0, [r7, #12] 80029c4: 60b9 str r1, [r7, #8] 80029c6: 607a str r2, [r7, #4] 80029c8: 603b str r3, [r7, #0] if(sz > w25_info.PageSize) 80029ca: 4b37 ldr r3, [pc, #220] ; (8002aa8 <W25_Read_Page+0xec>) 80029cc: 881b ldrh r3, [r3, #0] 80029ce: 461a mov r2, r3 80029d0: 683b ldr r3, [r7, #0] 80029d2: 4293 cmp r3, r2 80029d4: d902 bls.n 80029dc <W25_Read_Page+0x20> sz=w25_info.PageSize; 80029d6: 4b34 ldr r3, [pc, #208] ; (8002aa8 <W25_Read_Page+0xec>) 80029d8: 881b ldrh r3, [r3, #0] 80029da: 603b str r3, [r7, #0] if((offset+sz) > w25_info.PageSize) 80029dc: 687a ldr r2, [r7, #4] 80029de: 683b ldr r3, [r7, #0] 80029e0: 4413 add r3, r2 80029e2: 4a31 ldr r2, [pc, #196] ; (8002aa8 <W25_Read_Page+0xec>) 80029e4: 8812 ldrh r2, [r2, #0] 80029e6: 4293 cmp r3, r2 80029e8: d905 bls.n 80029f6 <W25_Read_Page+0x3a> sz = w25_info.PageSize - offset; 80029ea: 4b2f ldr r3, [pc, #188] ; (8002aa8 <W25_Read_Page+0xec>) 80029ec: 881b ldrh r3, [r3, #0] 80029ee: 461a mov r2, r3 80029f0: 687b ldr r3, [r7, #4] 80029f2: 1ad3 subs r3, r2, r3 80029f4: 603b str r3, [r7, #0] page_addr = page_addr * w25_info.PageSize + offset; 80029f6: 4b2c ldr r3, [pc, #176] ; (8002aa8 <W25_Read_Page+0xec>) 80029f8: 881b ldrh r3, [r3, #0] 80029fa: 461a mov r2, r3 80029fc: 68bb ldr r3, [r7, #8] 80029fe: fb02 f303 mul.w r3, r2, r3 8002a02: 687a ldr r2, [r7, #4] 8002a04: 4413 add r3, r2 8002a06: 60bb str r3, [r7, #8] buf[0] = W25_FAST_READ; 8002a08: 4b28 ldr r3, [pc, #160] ; (8002aac <W25_Read_Page+0xf0>) 8002a0a: 220b movs r2, #11 8002a0c: 701a strb r2, [r3, #0] if(w25_info.high_cap) 8002a0e: 4b26 ldr r3, [pc, #152] ; (8002aa8 <W25_Read_Page+0xec>) 8002a10: 7fdb ldrb r3, [r3, #31] 8002a12: 2b00 cmp r3, #0 8002a14: d01f beq.n 8002a56 <W25_Read_Page+0x9a> { buf[1] = (page_addr >> 24) & 0xFF; 8002a16: 68bb ldr r3, [r7, #8] 8002a18: 0e1b lsrs r3, r3, #24 8002a1a: b2da uxtb r2, r3 8002a1c: 4b23 ldr r3, [pc, #140] ; (8002aac <W25_Read_Page+0xf0>) 8002a1e: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 16) & 0xFF; 8002a20: 68bb ldr r3, [r7, #8] 8002a22: 0c1b lsrs r3, r3, #16 8002a24: b2da uxtb r2, r3 8002a26: 4b21 ldr r3, [pc, #132] ; (8002aac <W25_Read_Page+0xf0>) 8002a28: 709a strb r2, [r3, #2] buf[3] = (page_addr >> 8) & 0xFF; 8002a2a: 68bb ldr r3, [r7, #8] 8002a2c: 0a1b lsrs r3, r3, #8 8002a2e: b2da uxtb r2, r3 8002a30: 4b1e ldr r3, [pc, #120] ; (8002aac <W25_Read_Page+0xf0>) 8002a32: 70da strb r2, [r3, #3] buf[4] = page_addr & 0xFF; 8002a34: 68bb ldr r3, [r7, #8] 8002a36: b2da uxtb r2, r3 8002a38: 4b1c ldr r3, [pc, #112] ; (8002aac <W25_Read_Page+0xf0>) 8002a3a: 711a strb r2, [r3, #4] buf[5] = 0; 8002a3c: 4b1b ldr r3, [pc, #108] ; (8002aac <W25_Read_Page+0xf0>) 8002a3e: 2200 movs r2, #0 8002a40: 715a strb r2, [r3, #5] cs_set(); 8002a42: 2200 movs r2, #0 8002a44: 2110 movs r1, #16 8002a46: 481a ldr r0, [pc, #104] ; (8002ab0 <W25_Read_Page+0xf4>) 8002a48: f001 f9b9 bl 8003dbe <HAL_GPIO_WritePin> SPI1_Send(buf, 6); 8002a4c: 2106 movs r1, #6 8002a4e: 4817 ldr r0, [pc, #92] ; (8002aac <W25_Read_Page+0xf0>) 8002a50: f7ff fc8c bl 800236c <SPI1_Send> 8002a54: e019 b.n 8002a8a <W25_Read_Page+0xce> } else { buf[1] = (page_addr >> 16) & 0xFF; 8002a56: 68bb ldr r3, [r7, #8] 8002a58: 0c1b lsrs r3, r3, #16 8002a5a: b2da uxtb r2, r3 8002a5c: 4b13 ldr r3, [pc, #76] ; (8002aac <W25_Read_Page+0xf0>) 8002a5e: 705a strb r2, [r3, #1] buf[2] = (page_addr >> 8) & 0xFF; 8002a60: 68bb ldr r3, [r7, #8] 8002a62: 0a1b lsrs r3, r3, #8 8002a64: b2da uxtb r2, r3 8002a66: 4b11 ldr r3, [pc, #68] ; (8002aac <W25_Read_Page+0xf0>) 8002a68: 709a strb r2, [r3, #2] buf[3] = page_addr & 0xFF; 8002a6a: 68bb ldr r3, [r7, #8] 8002a6c: b2da uxtb r2, r3 8002a6e: 4b0f ldr r3, [pc, #60] ; (8002aac <W25_Read_Page+0xf0>) 8002a70: 70da strb r2, [r3, #3] buf[4] = 0; 8002a72: 4b0e ldr r3, [pc, #56] ; (8002aac <W25_Read_Page+0xf0>) 8002a74: 2200 movs r2, #0 8002a76: 711a strb r2, [r3, #4] cs_set(); 8002a78: 2200 movs r2, #0 8002a7a: 2110 movs r1, #16 8002a7c: 480c ldr r0, [pc, #48] ; (8002ab0 <W25_Read_Page+0xf4>) 8002a7e: f001 f99e bl 8003dbe <HAL_GPIO_WritePin> SPI1_Send(buf, 5); 8002a82: 2105 movs r1, #5 8002a84: 4809 ldr r0, [pc, #36] ; (8002aac <W25_Read_Page+0xf0>) 8002a86: f7ff fc71 bl 800236c <SPI1_Send> } SPI1_Recv(data, sz); 8002a8a: 683b ldr r3, [r7, #0] 8002a8c: b29b uxth r3, r3 8002a8e: 4619 mov r1, r3 8002a90: 68f8 ldr r0, [r7, #12] 8002a92: f7ff fc7f bl 8002394 <SPI1_Recv> cs_reset(); 8002a96: 2201 movs r2, #1 8002a98: 2110 movs r1, #16 8002a9a: 4805 ldr r0, [pc, #20] ; (8002ab0 <W25_Read_Page+0xf4>) 8002a9c: f001 f98f bl 8003dbe <HAL_GPIO_WritePin> } 8002aa0: bf00 nop 8002aa2: 3710 adds r7, #16 8002aa4: 46bd mov sp, r7 8002aa6: bd80 pop {r7, pc} 8002aa8: 20000748 .word 0x20000748 8002aac: 2000078c .word 0x2000078c 8002ab0: 40010800 .word 0x40010800 08002ab4 <HAL_Init>: * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002ab4: b580 push {r7, lr} 8002ab6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002ab8: 4b08 ldr r3, [pc, #32] ; (8002adc <HAL_Init+0x28>) 8002aba: 681b ldr r3, [r3, #0] 8002abc: 4a07 ldr r2, [pc, #28] ; (8002adc <HAL_Init+0x28>) 8002abe: f043 0310 orr.w r3, r3, #16 8002ac2: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002ac4: 2003 movs r0, #3 8002ac6: f000 ff25 bl 8003914 <HAL_NVIC_SetPriorityGrouping> /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002aca: 200f movs r0, #15 8002acc: f000 f808 bl 8002ae0 <HAL_InitTick> /* Init the low level hardware */ HAL_MspInit(); 8002ad0: f7ff f976 bl 8001dc0 <HAL_MspInit> /* Return function status */ return HAL_OK; 8002ad4: 2300 movs r3, #0 } 8002ad6: 4618 mov r0, r3 8002ad8: bd80 pop {r7, pc} 8002ada: bf00 nop 8002adc: 40022000 .word 0x40022000 08002ae0 <HAL_InitTick>: * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8002ae0: b580 push {r7, lr} 8002ae2: b082 sub sp, #8 8002ae4: af00 add r7, sp, #0 8002ae6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8002ae8: 4b12 ldr r3, [pc, #72] ; (8002b34 <HAL_InitTick+0x54>) 8002aea: 681a ldr r2, [r3, #0] 8002aec: 4b12 ldr r3, [pc, #72] ; (8002b38 <HAL_InitTick+0x58>) 8002aee: 781b ldrb r3, [r3, #0] 8002af0: 4619 mov r1, r3 8002af2: f44f 737a mov.w r3, #1000 ; 0x3e8 8002af6: fbb3 f3f1 udiv r3, r3, r1 8002afa: fbb2 f3f3 udiv r3, r2, r3 8002afe: 4618 mov r0, r3 8002b00: f000 ff3d bl 800397e <HAL_SYSTICK_Config> 8002b04: 4603 mov r3, r0 8002b06: 2b00 cmp r3, #0 8002b08: d001 beq.n 8002b0e <HAL_InitTick+0x2e> { return HAL_ERROR; 8002b0a: 2301 movs r3, #1 8002b0c: e00e b.n 8002b2c <HAL_InitTick+0x4c> } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8002b0e: 687b ldr r3, [r7, #4] 8002b10: 2b0f cmp r3, #15 8002b12: d80a bhi.n 8002b2a <HAL_InitTick+0x4a> { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8002b14: 2200 movs r2, #0 8002b16: 6879 ldr r1, [r7, #4] 8002b18: f04f 30ff mov.w r0, #4294967295 8002b1c: f000 ff05 bl 800392a <HAL_NVIC_SetPriority> uwTickPrio = TickPriority; 8002b20: 4a06 ldr r2, [pc, #24] ; (8002b3c <HAL_InitTick+0x5c>) 8002b22: 687b ldr r3, [r7, #4] 8002b24: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8002b26: 2300 movs r3, #0 8002b28: e000 b.n 8002b2c <HAL_InitTick+0x4c> return HAL_ERROR; 8002b2a: 2301 movs r3, #1 } 8002b2c: 4618 mov r0, r3 8002b2e: 3708 adds r7, #8 8002b30: 46bd mov sp, r7 8002b32: bd80 pop {r7, pc} 8002b34: 20000008 .word 0x20000008 8002b38: 20000010 .word 0x20000010 8002b3c: 2000000c .word 0x2000000c 08002b40 <HAL_IncTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8002b40: b480 push {r7} 8002b42: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002b44: 4b05 ldr r3, [pc, #20] ; (8002b5c <HAL_IncTick+0x1c>) 8002b46: 781b ldrb r3, [r3, #0] 8002b48: 461a mov r2, r3 8002b4a: 4b05 ldr r3, [pc, #20] ; (8002b60 <HAL_IncTick+0x20>) 8002b4c: 681b ldr r3, [r3, #0] 8002b4e: 4413 add r3, r2 8002b50: 4a03 ldr r2, [pc, #12] ; (8002b60 <HAL_IncTick+0x20>) 8002b52: 6013 str r3, [r2, #0] } 8002b54: bf00 nop 8002b56: 46bd mov sp, r7 8002b58: bc80 pop {r7} 8002b5a: 4770 bx lr 8002b5c: 20000010 .word 0x20000010 8002b60: 20000798 .word 0x20000798 08002b64 <HAL_GetTick>: * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002b64: b480 push {r7} 8002b66: af00 add r7, sp, #0 return uwTick; 8002b68: 4b02 ldr r3, [pc, #8] ; (8002b74 <HAL_GetTick+0x10>) 8002b6a: 681b ldr r3, [r3, #0] } 8002b6c: 4618 mov r0, r3 8002b6e: 46bd mov sp, r7 8002b70: bc80 pop {r7} 8002b72: 4770 bx lr 8002b74: 20000798 .word 0x20000798 08002b78 <HAL_Delay>: * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8002b78: b580 push {r7, lr} 8002b7a: b084 sub sp, #16 8002b7c: af00 add r7, sp, #0 8002b7e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8002b80: f7ff fff0 bl 8002b64 <HAL_GetTick> 8002b84: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8002b86: 687b ldr r3, [r7, #4] 8002b88: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8002b8a: 68fb ldr r3, [r7, #12] 8002b8c: f1b3 3fff cmp.w r3, #4294967295 8002b90: d005 beq.n 8002b9e <HAL_Delay+0x26> { wait += (uint32_t)(uwTickFreq); 8002b92: 4b0a ldr r3, [pc, #40] ; (8002bbc <HAL_Delay+0x44>) 8002b94: 781b ldrb r3, [r3, #0] 8002b96: 461a mov r2, r3 8002b98: 68fb ldr r3, [r7, #12] 8002b9a: 4413 add r3, r2 8002b9c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8002b9e: bf00 nop 8002ba0: f7ff ffe0 bl 8002b64 <HAL_GetTick> 8002ba4: 4602 mov r2, r0 8002ba6: 68bb ldr r3, [r7, #8] 8002ba8: 1ad3 subs r3, r2, r3 8002baa: 68fa ldr r2, [r7, #12] 8002bac: 429a cmp r2, r3 8002bae: d8f7 bhi.n 8002ba0 <HAL_Delay+0x28> { } } 8002bb0: bf00 nop 8002bb2: bf00 nop 8002bb4: 3710 adds r7, #16 8002bb6: 46bd mov sp, r7 8002bb8: bd80 pop {r7, pc} 8002bba: bf00 nop 8002bbc: 20000010 .word 0x20000010 08002bc0 <HAL_ADC_Init>: * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8002bc0: b580 push {r7, lr} 8002bc2: b086 sub sp, #24 8002bc4: af00 add r7, sp, #0 8002bc6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002bc8: 2300 movs r3, #0 8002bca: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8002bcc: 2300 movs r3, #0 8002bce: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8002bd0: 2300 movs r3, #0 8002bd2: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8002bd4: 2300 movs r3, #0 8002bd6: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8002bd8: 687b ldr r3, [r7, #4] 8002bda: 2b00 cmp r3, #0 8002bdc: d101 bne.n 8002be2 <HAL_ADC_Init+0x22> { return HAL_ERROR; 8002bde: 2301 movs r3, #1 8002be0: e0be b.n 8002d60 <HAL_ADC_Init+0x1a0> assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8002be2: 687b ldr r3, [r7, #4] 8002be4: 689b ldr r3, [r3, #8] 8002be6: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8002be8: 687b ldr r3, [r7, #4] 8002bea: 6a9b ldr r3, [r3, #40] ; 0x28 8002bec: 2b00 cmp r3, #0 8002bee: d109 bne.n 8002c04 <HAL_ADC_Init+0x44> { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8002bf0: 687b ldr r3, [r7, #4] 8002bf2: 2200 movs r2, #0 8002bf4: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8002bf6: 687b ldr r3, [r7, #4] 8002bf8: 2200 movs r2, #0 8002bfa: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8002bfe: 6878 ldr r0, [r7, #4] 8002c00: f7ff f910 bl 8001e24 <HAL_ADC_MspInit> /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8002c04: 6878 ldr r0, [r7, #4] 8002c06: f000 fd6f bl 80036e8 <ADC_ConversionStop_Disable> 8002c0a: 4603 mov r3, r0 8002c0c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8002c0e: 687b ldr r3, [r7, #4] 8002c10: 6a9b ldr r3, [r3, #40] ; 0x28 8002c12: f003 0310 and.w r3, r3, #16 8002c16: 2b00 cmp r3, #0 8002c18: f040 8099 bne.w 8002d4e <HAL_ADC_Init+0x18e> 8002c1c: 7dfb ldrb r3, [r7, #23] 8002c1e: 2b00 cmp r3, #0 8002c20: f040 8095 bne.w 8002d4e <HAL_ADC_Init+0x18e> (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002c24: 687b ldr r3, [r7, #4] 8002c26: 6a9b ldr r3, [r3, #40] ; 0x28 8002c28: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8002c2c: f023 0302 bic.w r3, r3, #2 8002c30: f043 0202 orr.w r2, r3, #2 8002c34: 687b ldr r3, [r7, #4] 8002c36: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8002c38: 687b ldr r3, [r7, #4] 8002c3a: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002c3c: 687b ldr r3, [r7, #4] 8002c3e: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8002c40: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8002c42: 687b ldr r3, [r7, #4] 8002c44: 7b1b ldrb r3, [r3, #12] 8002c46: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002c48: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8002c4a: 68ba ldr r2, [r7, #8] 8002c4c: 4313 orrs r3, r2 8002c4e: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8002c50: 687b ldr r3, [r7, #4] 8002c52: 689b ldr r3, [r3, #8] 8002c54: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002c58: d003 beq.n 8002c62 <HAL_ADC_Init+0xa2> 8002c5a: 687b ldr r3, [r7, #4] 8002c5c: 689b ldr r3, [r3, #8] 8002c5e: 2b01 cmp r3, #1 8002c60: d102 bne.n 8002c68 <HAL_ADC_Init+0xa8> 8002c62: f44f 7380 mov.w r3, #256 ; 0x100 8002c66: e000 b.n 8002c6a <HAL_ADC_Init+0xaa> 8002c68: 2300 movs r3, #0 8002c6a: 693a ldr r2, [r7, #16] 8002c6c: 4313 orrs r3, r2 8002c6e: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8002c70: 687b ldr r3, [r7, #4] 8002c72: 7d1b ldrb r3, [r3, #20] 8002c74: 2b01 cmp r3, #1 8002c76: d119 bne.n 8002cac <HAL_ADC_Init+0xec> { if (hadc->Init.ContinuousConvMode == DISABLE) 8002c78: 687b ldr r3, [r7, #4] 8002c7a: 7b1b ldrb r3, [r3, #12] 8002c7c: 2b00 cmp r3, #0 8002c7e: d109 bne.n 8002c94 <HAL_ADC_Init+0xd4> { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8002c80: 687b ldr r3, [r7, #4] 8002c82: 699b ldr r3, [r3, #24] 8002c84: 3b01 subs r3, #1 8002c86: 035a lsls r2, r3, #13 8002c88: 693b ldr r3, [r7, #16] 8002c8a: 4313 orrs r3, r2 8002c8c: f443 6300 orr.w r3, r3, #2048 ; 0x800 8002c90: 613b str r3, [r7, #16] 8002c92: e00b b.n 8002cac <HAL_ADC_Init+0xec> { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002c94: 687b ldr r3, [r7, #4] 8002c96: 6a9b ldr r3, [r3, #40] ; 0x28 8002c98: f043 0220 orr.w r2, r3, #32 8002c9c: 687b ldr r3, [r7, #4] 8002c9e: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 6adb ldr r3, [r3, #44] ; 0x2c 8002ca4: f043 0201 orr.w r2, r3, #1 8002ca8: 687b ldr r3, [r7, #4] 8002caa: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8002cac: 687b ldr r3, [r7, #4] 8002cae: 681b ldr r3, [r3, #0] 8002cb0: 685b ldr r3, [r3, #4] 8002cb2: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8002cb6: 687b ldr r3, [r7, #4] 8002cb8: 681b ldr r3, [r3, #0] 8002cba: 693a ldr r2, [r7, #16] 8002cbc: 430a orrs r2, r1 8002cbe: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8002cc0: 687b ldr r3, [r7, #4] 8002cc2: 681b ldr r3, [r3, #0] 8002cc4: 689a ldr r2, [r3, #8] 8002cc6: 4b28 ldr r3, [pc, #160] ; (8002d68 <HAL_ADC_Init+0x1a8>) 8002cc8: 4013 ands r3, r2 8002cca: 687a ldr r2, [r7, #4] 8002ccc: 6812 ldr r2, [r2, #0] 8002cce: 68b9 ldr r1, [r7, #8] 8002cd0: 430b orrs r3, r1 8002cd2: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8002cd4: 687b ldr r3, [r7, #4] 8002cd6: 689b ldr r3, [r3, #8] 8002cd8: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002cdc: d003 beq.n 8002ce6 <HAL_ADC_Init+0x126> 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 689b ldr r3, [r3, #8] 8002ce2: 2b01 cmp r3, #1 8002ce4: d104 bne.n 8002cf0 <HAL_ADC_Init+0x130> { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 691b ldr r3, [r3, #16] 8002cea: 3b01 subs r3, #1 8002cec: 051b lsls r3, r3, #20 8002cee: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8002cf0: 687b ldr r3, [r7, #4] 8002cf2: 681b ldr r3, [r3, #0] 8002cf4: 6adb ldr r3, [r3, #44] ; 0x2c 8002cf6: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8002cfa: 687b ldr r3, [r7, #4] 8002cfc: 681b ldr r3, [r3, #0] 8002cfe: 68fa ldr r2, [r7, #12] 8002d00: 430a orrs r2, r1 8002d02: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002d04: 687b ldr r3, [r7, #4] 8002d06: 681b ldr r3, [r3, #0] 8002d08: 689a ldr r2, [r3, #8] 8002d0a: 4b18 ldr r3, [pc, #96] ; (8002d6c <HAL_ADC_Init+0x1ac>) 8002d0c: 4013 ands r3, r2 8002d0e: 68ba ldr r2, [r7, #8] 8002d10: 429a cmp r2, r3 8002d12: d10b bne.n 8002d2c <HAL_ADC_Init+0x16c> ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8002d14: 687b ldr r3, [r7, #4] 8002d16: 2200 movs r2, #0 8002d18: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002d1a: 687b ldr r3, [r7, #4] 8002d1c: 6a9b ldr r3, [r3, #40] ; 0x28 8002d1e: f023 0303 bic.w r3, r3, #3 8002d22: f043 0201 orr.w r2, r3, #1 8002d26: 687b ldr r3, [r7, #4] 8002d28: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002d2a: e018 b.n 8002d5e <HAL_ADC_Init+0x19e> HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002d2c: 687b ldr r3, [r7, #4] 8002d2e: 6a9b ldr r3, [r3, #40] ; 0x28 8002d30: f023 0312 bic.w r3, r3, #18 8002d34: f043 0210 orr.w r2, r3, #16 8002d38: 687b ldr r3, [r7, #4] 8002d3a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002d3c: 687b ldr r3, [r7, #4] 8002d3e: 6adb ldr r3, [r3, #44] ; 0x2c 8002d40: f043 0201 orr.w r2, r3, #1 8002d44: 687b ldr r3, [r7, #4] 8002d46: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8002d48: 2301 movs r3, #1 8002d4a: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002d4c: e007 b.n 8002d5e <HAL_ADC_Init+0x19e> } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002d4e: 687b ldr r3, [r7, #4] 8002d50: 6a9b ldr r3, [r3, #40] ; 0x28 8002d52: f043 0210 orr.w r2, r3, #16 8002d56: 687b ldr r3, [r7, #4] 8002d58: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8002d5a: 2301 movs r3, #1 8002d5c: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8002d5e: 7dfb ldrb r3, [r7, #23] } 8002d60: 4618 mov r0, r3 8002d62: 3718 adds r7, #24 8002d64: 46bd mov sp, r7 8002d66: bd80 pop {r7, pc} 8002d68: ffe1f7fd .word 0xffe1f7fd 8002d6c: ff1f0efe .word 0xff1f0efe 08002d70 <HAL_ADC_Start>: * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8002d70: b580 push {r7, lr} 8002d72: b084 sub sp, #16 8002d74: af00 add r7, sp, #0 8002d76: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002d78: 2300 movs r3, #0 8002d7a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8002d7c: 687b ldr r3, [r7, #4] 8002d7e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8002d82: 2b01 cmp r3, #1 8002d84: d101 bne.n 8002d8a <HAL_ADC_Start+0x1a> 8002d86: 2302 movs r3, #2 8002d88: e098 b.n 8002ebc <HAL_ADC_Start+0x14c> 8002d8a: 687b ldr r3, [r7, #4] 8002d8c: 2201 movs r2, #1 8002d8e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8002d92: 6878 ldr r0, [r7, #4] 8002d94: f000 fc4e bl 8003634 <ADC_Enable> 8002d98: 4603 mov r3, r0 8002d9a: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8002d9c: 7bfb ldrb r3, [r7, #15] 8002d9e: 2b00 cmp r3, #0 8002da0: f040 8087 bne.w 8002eb2 <HAL_ADC_Start+0x142> { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8002da4: 687b ldr r3, [r7, #4] 8002da6: 6a9b ldr r3, [r3, #40] ; 0x28 8002da8: f423 7340 bic.w r3, r3, #768 ; 0x300 8002dac: f023 0301 bic.w r3, r3, #1 8002db0: f443 7280 orr.w r2, r3, #256 ; 0x100 8002db4: 687b ldr r3, [r7, #4] 8002db6: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8002db8: 687b ldr r3, [r7, #4] 8002dba: 681b ldr r3, [r3, #0] 8002dbc: 4a41 ldr r2, [pc, #260] ; (8002ec4 <HAL_ADC_Start+0x154>) 8002dbe: 4293 cmp r3, r2 8002dc0: d105 bne.n 8002dce <HAL_ADC_Start+0x5e> 8002dc2: 4b41 ldr r3, [pc, #260] ; (8002ec8 <HAL_ADC_Start+0x158>) 8002dc4: 685b ldr r3, [r3, #4] 8002dc6: f403 2370 and.w r3, r3, #983040 ; 0xf0000 8002dca: 2b00 cmp r3, #0 8002dcc: d115 bne.n 8002dfa <HAL_ADC_Start+0x8a> { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002dce: 687b ldr r3, [r7, #4] 8002dd0: 6a9b ldr r3, [r3, #40] ; 0x28 8002dd2: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8002dd6: 687b ldr r3, [r7, #4] 8002dd8: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 681b ldr r3, [r3, #0] 8002dde: 685b ldr r3, [r3, #4] 8002de0: f403 6380 and.w r3, r3, #1024 ; 0x400 8002de4: 2b00 cmp r3, #0 8002de6: d026 beq.n 8002e36 <HAL_ADC_Start+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8002de8: 687b ldr r3, [r7, #4] 8002dea: 6a9b ldr r3, [r3, #40] ; 0x28 8002dec: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8002df0: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8002df4: 687b ldr r3, [r7, #4] 8002df6: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8002df8: e01d b.n 8002e36 <HAL_ADC_Start+0xc6> } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002dfa: 687b ldr r3, [r7, #4] 8002dfc: 6a9b ldr r3, [r3, #40] ; 0x28 8002dfe: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8002e02: 687b ldr r3, [r7, #4] 8002e04: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8002e06: 687b ldr r3, [r7, #4] 8002e08: 681b ldr r3, [r3, #0] 8002e0a: 4a2f ldr r2, [pc, #188] ; (8002ec8 <HAL_ADC_Start+0x158>) 8002e0c: 4293 cmp r3, r2 8002e0e: d004 beq.n 8002e1a <HAL_ADC_Start+0xaa> 8002e10: 687b ldr r3, [r7, #4] 8002e12: 681b ldr r3, [r3, #0] 8002e14: 4a2b ldr r2, [pc, #172] ; (8002ec4 <HAL_ADC_Start+0x154>) 8002e16: 4293 cmp r3, r2 8002e18: d10d bne.n 8002e36 <HAL_ADC_Start+0xc6> 8002e1a: 4b2b ldr r3, [pc, #172] ; (8002ec8 <HAL_ADC_Start+0x158>) 8002e1c: 685b ldr r3, [r3, #4] 8002e1e: f403 6380 and.w r3, r3, #1024 ; 0x400 8002e22: 2b00 cmp r3, #0 8002e24: d007 beq.n 8002e36 <HAL_ADC_Start+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8002e26: 687b ldr r3, [r7, #4] 8002e28: 6a9b ldr r3, [r3, #40] ; 0x28 8002e2a: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8002e2e: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8002e32: 687b ldr r3, [r7, #4] 8002e34: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002e36: 687b ldr r3, [r7, #4] 8002e38: 6a9b ldr r3, [r3, #40] ; 0x28 8002e3a: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002e3e: 2b00 cmp r3, #0 8002e40: d006 beq.n 8002e50 <HAL_ADC_Start+0xe0> { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8002e42: 687b ldr r3, [r7, #4] 8002e44: 6adb ldr r3, [r3, #44] ; 0x2c 8002e46: f023 0206 bic.w r2, r3, #6 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 62da str r2, [r3, #44] ; 0x2c 8002e4e: e002 b.n 8002e56 <HAL_ADC_Start+0xe6> } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8002e50: 687b ldr r3, [r7, #4] 8002e52: 2200 movs r2, #0 8002e54: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8002e56: 687b ldr r3, [r7, #4] 8002e58: 2200 movs r2, #0 8002e5a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8002e5e: 687b ldr r3, [r7, #4] 8002e60: 681b ldr r3, [r3, #0] 8002e62: f06f 0202 mvn.w r2, #2 8002e66: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002e68: 687b ldr r3, [r7, #4] 8002e6a: 681b ldr r3, [r3, #0] 8002e6c: 689b ldr r3, [r3, #8] 8002e6e: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8002e72: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002e76: d113 bne.n 8002ea0 <HAL_ADC_Start+0x130> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8002e78: 687b ldr r3, [r7, #4] 8002e7a: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002e7c: 4a11 ldr r2, [pc, #68] ; (8002ec4 <HAL_ADC_Start+0x154>) 8002e7e: 4293 cmp r3, r2 8002e80: d105 bne.n 8002e8e <HAL_ADC_Start+0x11e> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8002e82: 4b11 ldr r3, [pc, #68] ; (8002ec8 <HAL_ADC_Start+0x158>) 8002e84: 685b ldr r3, [r3, #4] 8002e86: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002e8a: 2b00 cmp r3, #0 8002e8c: d108 bne.n 8002ea0 <HAL_ADC_Start+0x130> { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8002e8e: 687b ldr r3, [r7, #4] 8002e90: 681b ldr r3, [r3, #0] 8002e92: 689a ldr r2, [r3, #8] 8002e94: 687b ldr r3, [r7, #4] 8002e96: 681b ldr r3, [r3, #0] 8002e98: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8002e9c: 609a str r2, [r3, #8] 8002e9e: e00c b.n 8002eba <HAL_ADC_Start+0x14a> } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8002ea0: 687b ldr r3, [r7, #4] 8002ea2: 681b ldr r3, [r3, #0] 8002ea4: 689a ldr r2, [r3, #8] 8002ea6: 687b ldr r3, [r7, #4] 8002ea8: 681b ldr r3, [r3, #0] 8002eaa: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8002eae: 609a str r2, [r3, #8] 8002eb0: e003 b.n 8002eba <HAL_ADC_Start+0x14a> } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8002eb2: 687b ldr r3, [r7, #4] 8002eb4: 2200 movs r2, #0 8002eb6: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 8002eba: 7bfb ldrb r3, [r7, #15] } 8002ebc: 4618 mov r0, r3 8002ebe: 3710 adds r7, #16 8002ec0: 46bd mov sp, r7 8002ec2: bd80 pop {r7, pc} 8002ec4: 40012800 .word 0x40012800 8002ec8: 40012400 .word 0x40012400 08002ecc <HAL_ADC_Stop>: * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8002ecc: b580 push {r7, lr} 8002ece: b084 sub sp, #16 8002ed0: af00 add r7, sp, #0 8002ed2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002ed4: 2300 movs r3, #0 8002ed6: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8002ed8: 687b ldr r3, [r7, #4] 8002eda: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8002ede: 2b01 cmp r3, #1 8002ee0: d101 bne.n 8002ee6 <HAL_ADC_Stop+0x1a> 8002ee2: 2302 movs r3, #2 8002ee4: e01a b.n 8002f1c <HAL_ADC_Stop+0x50> 8002ee6: 687b ldr r3, [r7, #4] 8002ee8: 2201 movs r2, #1 8002eea: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8002eee: 6878 ldr r0, [r7, #4] 8002ef0: f000 fbfa bl 80036e8 <ADC_ConversionStop_Disable> 8002ef4: 4603 mov r3, r0 8002ef6: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8002ef8: 7bfb ldrb r3, [r7, #15] 8002efa: 2b00 cmp r3, #0 8002efc: d109 bne.n 8002f12 <HAL_ADC_Stop+0x46> { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002efe: 687b ldr r3, [r7, #4] 8002f00: 6a9b ldr r3, [r3, #40] ; 0x28 8002f02: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8002f06: f023 0301 bic.w r3, r3, #1 8002f0a: f043 0201 orr.w r2, r3, #1 8002f0e: 687b ldr r3, [r7, #4] 8002f10: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002f12: 687b ldr r3, [r7, #4] 8002f14: 2200 movs r2, #0 8002f16: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8002f1a: 7bfb ldrb r3, [r7, #15] } 8002f1c: 4618 mov r0, r3 8002f1e: 3710 adds r7, #16 8002f20: 46bd mov sp, r7 8002f22: bd80 pop {r7, pc} 08002f24 <HAL_ADC_PollForConversion>: * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8002f24: b590 push {r4, r7, lr} 8002f26: b087 sub sp, #28 8002f28: af00 add r7, sp, #0 8002f2a: 6078 str r0, [r7, #4] 8002f2c: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8002f2e: 2300 movs r3, #0 8002f30: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 8002f32: 2300 movs r3, #0 8002f34: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 8002f36: 2300 movs r3, #0 8002f38: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 8002f3a: f7ff fe13 bl 8002b64 <HAL_GetTick> 8002f3e: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 8002f40: 687b ldr r3, [r7, #4] 8002f42: 681b ldr r3, [r3, #0] 8002f44: 689b ldr r3, [r3, #8] 8002f46: f403 7380 and.w r3, r3, #256 ; 0x100 8002f4a: 2b00 cmp r3, #0 8002f4c: d00b beq.n 8002f66 <HAL_ADC_PollForConversion+0x42> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002f4e: 687b ldr r3, [r7, #4] 8002f50: 6a9b ldr r3, [r3, #40] ; 0x28 8002f52: f043 0220 orr.w r2, r3, #32 8002f56: 687b ldr r3, [r7, #4] 8002f58: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8002f5a: 687b ldr r3, [r7, #4] 8002f5c: 2200 movs r2, #0 8002f5e: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002f62: 2301 movs r3, #1 8002f64: e0d3 b.n 800310e <HAL_ADC_PollForConversion+0x1ea> /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8002f66: 687b ldr r3, [r7, #4] 8002f68: 681b ldr r3, [r3, #0] 8002f6a: 685b ldr r3, [r3, #4] 8002f6c: f403 7380 and.w r3, r3, #256 ; 0x100 8002f70: 2b00 cmp r3, #0 8002f72: d131 bne.n 8002fd8 <HAL_ADC_PollForConversion+0xb4> HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 8002f74: 687b ldr r3, [r7, #4] 8002f76: 681b ldr r3, [r3, #0] 8002f78: 6adb ldr r3, [r3, #44] ; 0x2c 8002f7a: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8002f7e: 2b00 cmp r3, #0 8002f80: d12a bne.n 8002fd8 <HAL_ADC_PollForConversion+0xb4> { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8002f82: e021 b.n 8002fc8 <HAL_ADC_PollForConversion+0xa4> { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8002f84: 683b ldr r3, [r7, #0] 8002f86: f1b3 3fff cmp.w r3, #4294967295 8002f8a: d01d beq.n 8002fc8 <HAL_ADC_PollForConversion+0xa4> { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 8002f8c: 683b ldr r3, [r7, #0] 8002f8e: 2b00 cmp r3, #0 8002f90: d007 beq.n 8002fa2 <HAL_ADC_PollForConversion+0x7e> 8002f92: f7ff fde7 bl 8002b64 <HAL_GetTick> 8002f96: 4602 mov r2, r0 8002f98: 697b ldr r3, [r7, #20] 8002f9a: 1ad3 subs r3, r2, r3 8002f9c: 683a ldr r2, [r7, #0] 8002f9e: 429a cmp r2, r3 8002fa0: d212 bcs.n 8002fc8 <HAL_ADC_PollForConversion+0xa4> { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8002fa2: 687b ldr r3, [r7, #4] 8002fa4: 681b ldr r3, [r3, #0] 8002fa6: 681b ldr r3, [r3, #0] 8002fa8: f003 0302 and.w r3, r3, #2 8002fac: 2b00 cmp r3, #0 8002fae: d10b bne.n 8002fc8 <HAL_ADC_PollForConversion+0xa4> { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8002fb0: 687b ldr r3, [r7, #4] 8002fb2: 6a9b ldr r3, [r3, #40] ; 0x28 8002fb4: f043 0204 orr.w r2, r3, #4 8002fb8: 687b ldr r3, [r7, #4] 8002fba: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8002fbc: 687b ldr r3, [r7, #4] 8002fbe: 2200 movs r2, #0 8002fc0: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 8002fc4: 2303 movs r3, #3 8002fc6: e0a2 b.n 800310e <HAL_ADC_PollForConversion+0x1ea> while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 8002fc8: 687b ldr r3, [r7, #4] 8002fca: 681b ldr r3, [r3, #0] 8002fcc: 681b ldr r3, [r3, #0] 8002fce: f003 0302 and.w r3, r3, #2 8002fd2: 2b00 cmp r3, #0 8002fd4: d0d6 beq.n 8002f84 <HAL_ADC_PollForConversion+0x60> if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8002fd6: e070 b.n 80030ba <HAL_ADC_PollForConversion+0x196> /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 8002fd8: 4b4f ldr r3, [pc, #316] ; (8003118 <HAL_ADC_PollForConversion+0x1f4>) 8002fda: 681c ldr r4, [r3, #0] 8002fdc: 2002 movs r0, #2 8002fde: f001 fbff bl 80047e0 <HAL_RCCEx_GetPeriphCLKFreq> 8002fe2: 4603 mov r3, r0 8002fe4: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 8002fe8: 687b ldr r3, [r7, #4] 8002fea: 681b ldr r3, [r3, #0] 8002fec: 6919 ldr r1, [r3, #16] 8002fee: 4b4b ldr r3, [pc, #300] ; (800311c <HAL_ADC_PollForConversion+0x1f8>) 8002ff0: 400b ands r3, r1 8002ff2: 2b00 cmp r3, #0 8002ff4: d118 bne.n 8003028 <HAL_ADC_PollForConversion+0x104> 8002ff6: 687b ldr r3, [r7, #4] 8002ff8: 681b ldr r3, [r3, #0] 8002ffa: 68d9 ldr r1, [r3, #12] 8002ffc: 4b48 ldr r3, [pc, #288] ; (8003120 <HAL_ADC_PollForConversion+0x1fc>) 8002ffe: 400b ands r3, r1 8003000: 2b00 cmp r3, #0 8003002: d111 bne.n 8003028 <HAL_ADC_PollForConversion+0x104> 8003004: 687b ldr r3, [r7, #4] 8003006: 681b ldr r3, [r3, #0] 8003008: 6919 ldr r1, [r3, #16] 800300a: 4b46 ldr r3, [pc, #280] ; (8003124 <HAL_ADC_PollForConversion+0x200>) 800300c: 400b ands r3, r1 800300e: 2b00 cmp r3, #0 8003010: d108 bne.n 8003024 <HAL_ADC_PollForConversion+0x100> 8003012: 687b ldr r3, [r7, #4] 8003014: 681b ldr r3, [r3, #0] 8003016: 68d9 ldr r1, [r3, #12] 8003018: 4b43 ldr r3, [pc, #268] ; (8003128 <HAL_ADC_PollForConversion+0x204>) 800301a: 400b ands r3, r1 800301c: 2b00 cmp r3, #0 800301e: d101 bne.n 8003024 <HAL_ADC_PollForConversion+0x100> 8003020: 2314 movs r3, #20 8003022: e020 b.n 8003066 <HAL_ADC_PollForConversion+0x142> 8003024: 2329 movs r3, #41 ; 0x29 8003026: e01e b.n 8003066 <HAL_ADC_PollForConversion+0x142> 8003028: 687b ldr r3, [r7, #4] 800302a: 681b ldr r3, [r3, #0] 800302c: 6919 ldr r1, [r3, #16] 800302e: 4b3d ldr r3, [pc, #244] ; (8003124 <HAL_ADC_PollForConversion+0x200>) 8003030: 400b ands r3, r1 8003032: 2b00 cmp r3, #0 8003034: d106 bne.n 8003044 <HAL_ADC_PollForConversion+0x120> 8003036: 687b ldr r3, [r7, #4] 8003038: 681b ldr r3, [r3, #0] 800303a: 68d9 ldr r1, [r3, #12] 800303c: 4b3a ldr r3, [pc, #232] ; (8003128 <HAL_ADC_PollForConversion+0x204>) 800303e: 400b ands r3, r1 8003040: 2b00 cmp r3, #0 8003042: d00d beq.n 8003060 <HAL_ADC_PollForConversion+0x13c> 8003044: 687b ldr r3, [r7, #4] 8003046: 681b ldr r3, [r3, #0] 8003048: 6919 ldr r1, [r3, #16] 800304a: 4b38 ldr r3, [pc, #224] ; (800312c <HAL_ADC_PollForConversion+0x208>) 800304c: 400b ands r3, r1 800304e: 2b00 cmp r3, #0 8003050: d108 bne.n 8003064 <HAL_ADC_PollForConversion+0x140> 8003052: 687b ldr r3, [r7, #4] 8003054: 681b ldr r3, [r3, #0] 8003056: 68d9 ldr r1, [r3, #12] 8003058: 4b34 ldr r3, [pc, #208] ; (800312c <HAL_ADC_PollForConversion+0x208>) 800305a: 400b ands r3, r1 800305c: 2b00 cmp r3, #0 800305e: d101 bne.n 8003064 <HAL_ADC_PollForConversion+0x140> 8003060: 2354 movs r3, #84 ; 0x54 8003062: e000 b.n 8003066 <HAL_ADC_PollForConversion+0x142> 8003064: 23fc movs r3, #252 ; 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 8003066: fb02 f303 mul.w r3, r2, r3 800306a: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800306c: e021 b.n 80030b2 <HAL_ADC_PollForConversion+0x18e> { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800306e: 683b ldr r3, [r7, #0] 8003070: f1b3 3fff cmp.w r3, #4294967295 8003074: d01a beq.n 80030ac <HAL_ADC_PollForConversion+0x188> { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 8003076: 683b ldr r3, [r7, #0] 8003078: 2b00 cmp r3, #0 800307a: d007 beq.n 800308c <HAL_ADC_PollForConversion+0x168> 800307c: f7ff fd72 bl 8002b64 <HAL_GetTick> 8003080: 4602 mov r2, r0 8003082: 697b ldr r3, [r7, #20] 8003084: 1ad3 subs r3, r2, r3 8003086: 683a ldr r2, [r7, #0] 8003088: 429a cmp r2, r3 800308a: d20f bcs.n 80030ac <HAL_ADC_PollForConversion+0x188> { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800308c: 68fb ldr r3, [r7, #12] 800308e: 693a ldr r2, [r7, #16] 8003090: 429a cmp r2, r3 8003092: d90b bls.n 80030ac <HAL_ADC_PollForConversion+0x188> { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8003094: 687b ldr r3, [r7, #4] 8003096: 6a9b ldr r3, [r3, #40] ; 0x28 8003098: f043 0204 orr.w r2, r3, #4 800309c: 687b ldr r3, [r7, #4] 800309e: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80030a0: 687b ldr r3, [r7, #4] 80030a2: 2200 movs r2, #0 80030a4: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80030a8: 2303 movs r3, #3 80030aa: e030 b.n 800310e <HAL_ADC_PollForConversion+0x1ea> } } } Conversion_Timeout_CPU_cycles ++; 80030ac: 68fb ldr r3, [r7, #12] 80030ae: 3301 adds r3, #1 80030b0: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 80030b2: 68fb ldr r3, [r7, #12] 80030b4: 693a ldr r2, [r7, #16] 80030b6: 429a cmp r2, r3 80030b8: d8d9 bhi.n 800306e <HAL_ADC_PollForConversion+0x14a> } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 80030ba: 687b ldr r3, [r7, #4] 80030bc: 681b ldr r3, [r3, #0] 80030be: f06f 0212 mvn.w r2, #18 80030c2: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80030c4: 687b ldr r3, [r7, #4] 80030c6: 6a9b ldr r3, [r3, #40] ; 0x28 80030c8: f443 7200 orr.w r2, r3, #512 ; 0x200 80030cc: 687b ldr r3, [r7, #4] 80030ce: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80030d0: 687b ldr r3, [r7, #4] 80030d2: 681b ldr r3, [r3, #0] 80030d4: 689b ldr r3, [r3, #8] 80030d6: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80030da: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80030de: d115 bne.n 800310c <HAL_ADC_PollForConversion+0x1e8> (hadc->Init.ContinuousConvMode == DISABLE) ) 80030e0: 687b ldr r3, [r7, #4] 80030e2: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80030e4: 2b00 cmp r3, #0 80030e6: d111 bne.n 800310c <HAL_ADC_PollForConversion+0x1e8> { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80030e8: 687b ldr r3, [r7, #4] 80030ea: 6a9b ldr r3, [r3, #40] ; 0x28 80030ec: f423 7280 bic.w r2, r3, #256 ; 0x100 80030f0: 687b ldr r3, [r7, #4] 80030f2: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80030f4: 687b ldr r3, [r7, #4] 80030f6: 6a9b ldr r3, [r3, #40] ; 0x28 80030f8: f403 5380 and.w r3, r3, #4096 ; 0x1000 80030fc: 2b00 cmp r3, #0 80030fe: d105 bne.n 800310c <HAL_ADC_PollForConversion+0x1e8> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8003100: 687b ldr r3, [r7, #4] 8003102: 6a9b ldr r3, [r3, #40] ; 0x28 8003104: f043 0201 orr.w r2, r3, #1 8003108: 687b ldr r3, [r7, #4] 800310a: 629a str r2, [r3, #40] ; 0x28 } } /* Return ADC state */ return HAL_OK; 800310c: 2300 movs r3, #0 } 800310e: 4618 mov r0, r3 8003110: 371c adds r7, #28 8003112: 46bd mov sp, r7 8003114: bd90 pop {r4, r7, pc} 8003116: bf00 nop 8003118: 20000008 .word 0x20000008 800311c: 24924924 .word 0x24924924 8003120: 00924924 .word 0x00924924 8003124: 12492492 .word 0x12492492 8003128: 00492492 .word 0x00492492 800312c: 00249249 .word 0x00249249 08003130 <HAL_ADC_Start_IT>: * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { 8003130: b580 push {r7, lr} 8003132: b084 sub sp, #16 8003134: af00 add r7, sp, #0 8003136: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003138: 2300 movs r3, #0 800313a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800313c: 687b ldr r3, [r7, #4] 800313e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8003142: 2b01 cmp r3, #1 8003144: d101 bne.n 800314a <HAL_ADC_Start_IT+0x1a> 8003146: 2302 movs r3, #2 8003148: e0a0 b.n 800328c <HAL_ADC_Start_IT+0x15c> 800314a: 687b ldr r3, [r7, #4] 800314c: 2201 movs r2, #1 800314e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8003152: 6878 ldr r0, [r7, #4] 8003154: f000 fa6e bl 8003634 <ADC_Enable> 8003158: 4603 mov r3, r0 800315a: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800315c: 7bfb ldrb r3, [r7, #15] 800315e: 2b00 cmp r3, #0 8003160: f040 808f bne.w 8003282 <HAL_ADC_Start_IT+0x152> { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8003164: 687b ldr r3, [r7, #4] 8003166: 6a9b ldr r3, [r3, #40] ; 0x28 8003168: f423 6370 bic.w r3, r3, #3840 ; 0xf00 800316c: f023 0301 bic.w r3, r3, #1 8003170: f443 7280 orr.w r2, r3, #256 ; 0x100 8003174: 687b ldr r3, [r7, #4] 8003176: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8003178: 687b ldr r3, [r7, #4] 800317a: 681b ldr r3, [r3, #0] 800317c: 4a45 ldr r2, [pc, #276] ; (8003294 <HAL_ADC_Start_IT+0x164>) 800317e: 4293 cmp r3, r2 8003180: d105 bne.n 800318e <HAL_ADC_Start_IT+0x5e> 8003182: 4b45 ldr r3, [pc, #276] ; (8003298 <HAL_ADC_Start_IT+0x168>) 8003184: 685b ldr r3, [r3, #4] 8003186: f403 2370 and.w r3, r3, #983040 ; 0xf0000 800318a: 2b00 cmp r3, #0 800318c: d115 bne.n 80031ba <HAL_ADC_Start_IT+0x8a> { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800318e: 687b ldr r3, [r7, #4] 8003190: 6a9b ldr r3, [r3, #40] ; 0x28 8003192: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8003196: 687b ldr r3, [r7, #4] 8003198: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800319a: 687b ldr r3, [r7, #4] 800319c: 681b ldr r3, [r3, #0] 800319e: 685b ldr r3, [r3, #4] 80031a0: f403 6380 and.w r3, r3, #1024 ; 0x400 80031a4: 2b00 cmp r3, #0 80031a6: d026 beq.n 80031f6 <HAL_ADC_Start_IT+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 80031a8: 687b ldr r3, [r7, #4] 80031aa: 6a9b ldr r3, [r3, #40] ; 0x28 80031ac: f423 5340 bic.w r3, r3, #12288 ; 0x3000 80031b0: f443 5280 orr.w r2, r3, #4096 ; 0x1000 80031b4: 687b ldr r3, [r7, #4] 80031b6: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 80031b8: e01d b.n 80031f6 <HAL_ADC_Start_IT+0xc6> } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80031ba: 687b ldr r3, [r7, #4] 80031bc: 6a9b ldr r3, [r3, #40] ; 0x28 80031be: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 80031c2: 687b ldr r3, [r7, #4] 80031c4: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 80031c6: 687b ldr r3, [r7, #4] 80031c8: 681b ldr r3, [r3, #0] 80031ca: 4a33 ldr r2, [pc, #204] ; (8003298 <HAL_ADC_Start_IT+0x168>) 80031cc: 4293 cmp r3, r2 80031ce: d004 beq.n 80031da <HAL_ADC_Start_IT+0xaa> 80031d0: 687b ldr r3, [r7, #4] 80031d2: 681b ldr r3, [r3, #0] 80031d4: 4a2f ldr r2, [pc, #188] ; (8003294 <HAL_ADC_Start_IT+0x164>) 80031d6: 4293 cmp r3, r2 80031d8: d10d bne.n 80031f6 <HAL_ADC_Start_IT+0xc6> 80031da: 4b2f ldr r3, [pc, #188] ; (8003298 <HAL_ADC_Start_IT+0x168>) 80031dc: 685b ldr r3, [r3, #4] 80031de: f403 6380 and.w r3, r3, #1024 ; 0x400 80031e2: 2b00 cmp r3, #0 80031e4: d007 beq.n 80031f6 <HAL_ADC_Start_IT+0xc6> { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 80031e6: 687b ldr r3, [r7, #4] 80031e8: 6a9b ldr r3, [r3, #40] ; 0x28 80031ea: f423 5340 bic.w r3, r3, #12288 ; 0x3000 80031ee: f443 5280 orr.w r2, r3, #4096 ; 0x1000 80031f2: 687b ldr r3, [r7, #4] 80031f4: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80031f6: 687b ldr r3, [r7, #4] 80031f8: 6a9b ldr r3, [r3, #40] ; 0x28 80031fa: f403 5380 and.w r3, r3, #4096 ; 0x1000 80031fe: 2b00 cmp r3, #0 8003200: d006 beq.n 8003210 <HAL_ADC_Start_IT+0xe0> { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8003202: 687b ldr r3, [r7, #4] 8003204: 6adb ldr r3, [r3, #44] ; 0x2c 8003206: f023 0206 bic.w r2, r3, #6 800320a: 687b ldr r3, [r7, #4] 800320c: 62da str r2, [r3, #44] ; 0x2c 800320e: e002 b.n 8003216 <HAL_ADC_Start_IT+0xe6> } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8003210: 687b ldr r3, [r7, #4] 8003212: 2200 movs r2, #0 8003214: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8003216: 687b ldr r3, [r7, #4] 8003218: 2200 movs r2, #0 800321a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800321e: 687b ldr r3, [r7, #4] 8003220: 681b ldr r3, [r3, #0] 8003222: f06f 0202 mvn.w r2, #2 8003226: 601a str r2, [r3, #0] /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); 8003228: 687b ldr r3, [r7, #4] 800322a: 681b ldr r3, [r3, #0] 800322c: 685a ldr r2, [r3, #4] 800322e: 687b ldr r3, [r7, #4] 8003230: 681b ldr r3, [r3, #0] 8003232: f042 0220 orr.w r2, r2, #32 8003236: 605a str r2, [r3, #4] /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8003238: 687b ldr r3, [r7, #4] 800323a: 681b ldr r3, [r3, #0] 800323c: 689b ldr r3, [r3, #8] 800323e: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8003242: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8003246: d113 bne.n 8003270 <HAL_ADC_Start_IT+0x140> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8003248: 687b ldr r3, [r7, #4] 800324a: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800324c: 4a11 ldr r2, [pc, #68] ; (8003294 <HAL_ADC_Start_IT+0x164>) 800324e: 4293 cmp r3, r2 8003250: d105 bne.n 800325e <HAL_ADC_Start_IT+0x12e> ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8003252: 4b11 ldr r3, [pc, #68] ; (8003298 <HAL_ADC_Start_IT+0x168>) 8003254: 685b ldr r3, [r3, #4] 8003256: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800325a: 2b00 cmp r3, #0 800325c: d108 bne.n 8003270 <HAL_ADC_Start_IT+0x140> { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800325e: 687b ldr r3, [r7, #4] 8003260: 681b ldr r3, [r3, #0] 8003262: 689a ldr r2, [r3, #8] 8003264: 687b ldr r3, [r7, #4] 8003266: 681b ldr r3, [r3, #0] 8003268: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 800326c: 609a str r2, [r3, #8] 800326e: e00c b.n 800328a <HAL_ADC_Start_IT+0x15a> } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8003270: 687b ldr r3, [r7, #4] 8003272: 681b ldr r3, [r3, #0] 8003274: 689a ldr r2, [r3, #8] 8003276: 687b ldr r3, [r7, #4] 8003278: 681b ldr r3, [r3, #0] 800327a: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 800327e: 609a str r2, [r3, #8] 8003280: e003 b.n 800328a <HAL_ADC_Start_IT+0x15a> } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8003282: 687b ldr r3, [r7, #4] 8003284: 2200 movs r2, #0 8003286: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 800328a: 7bfb ldrb r3, [r7, #15] } 800328c: 4618 mov r0, r3 800328e: 3710 adds r7, #16 8003290: 46bd mov sp, r7 8003292: bd80 pop {r7, pc} 8003294: 40012800 .word 0x40012800 8003298: 40012400 .word 0x40012400 0800329c <HAL_ADC_GetValue>: * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800329c: b480 push {r7} 800329e: b083 sub sp, #12 80032a0: af00 add r7, sp, #0 80032a2: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 80032a4: 687b ldr r3, [r7, #4] 80032a6: 681b ldr r3, [r3, #0] 80032a8: 6cdb ldr r3, [r3, #76] ; 0x4c } 80032aa: 4618 mov r0, r3 80032ac: 370c adds r7, #12 80032ae: 46bd mov sp, r7 80032b0: bc80 pop {r7} 80032b2: 4770 bx lr 080032b4 <HAL_ADC_IRQHandler>: * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 80032b4: b580 push {r7, lr} 80032b6: b084 sub sp, #16 80032b8: af00 add r7, sp, #0 80032ba: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 80032bc: 687b ldr r3, [r7, #4] 80032be: 681b ldr r3, [r3, #0] 80032c0: 681b ldr r3, [r3, #0] 80032c2: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 80032c4: 687b ldr r3, [r7, #4] 80032c6: 681b ldr r3, [r3, #0] 80032c8: 685b ldr r3, [r3, #4] 80032ca: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 80032cc: 68bb ldr r3, [r7, #8] 80032ce: f003 0320 and.w r3, r3, #32 80032d2: 2b00 cmp r3, #0 80032d4: d03e beq.n 8003354 <HAL_ADC_IRQHandler+0xa0> { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 80032d6: 68fb ldr r3, [r7, #12] 80032d8: f003 0302 and.w r3, r3, #2 80032dc: 2b00 cmp r3, #0 80032de: d039 beq.n 8003354 <HAL_ADC_IRQHandler+0xa0> { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80032e0: 687b ldr r3, [r7, #4] 80032e2: 6a9b ldr r3, [r3, #40] ; 0x28 80032e4: f003 0310 and.w r3, r3, #16 80032e8: 2b00 cmp r3, #0 80032ea: d105 bne.n 80032f8 <HAL_ADC_IRQHandler+0x44> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80032ec: 687b ldr r3, [r7, #4] 80032ee: 6a9b ldr r3, [r3, #40] ; 0x28 80032f0: f443 7200 orr.w r2, r3, #512 ; 0x200 80032f4: 687b ldr r3, [r7, #4] 80032f6: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80032f8: 687b ldr r3, [r7, #4] 80032fa: 681b ldr r3, [r3, #0] 80032fc: 689b ldr r3, [r3, #8] 80032fe: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8003302: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8003306: d11d bne.n 8003344 <HAL_ADC_IRQHandler+0x90> (hadc->Init.ContinuousConvMode == DISABLE) ) 8003308: 687b ldr r3, [r7, #4] 800330a: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800330c: 2b00 cmp r3, #0 800330e: d119 bne.n 8003344 <HAL_ADC_IRQHandler+0x90> { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 8003310: 687b ldr r3, [r7, #4] 8003312: 681b ldr r3, [r3, #0] 8003314: 685a ldr r2, [r3, #4] 8003316: 687b ldr r3, [r7, #4] 8003318: 681b ldr r3, [r3, #0] 800331a: f022 0220 bic.w r2, r2, #32 800331e: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8003320: 687b ldr r3, [r7, #4] 8003322: 6a9b ldr r3, [r3, #40] ; 0x28 8003324: f423 7280 bic.w r2, r3, #256 ; 0x100 8003328: 687b ldr r3, [r7, #4] 800332a: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800332c: 687b ldr r3, [r7, #4] 800332e: 6a9b ldr r3, [r3, #40] ; 0x28 8003330: f403 5380 and.w r3, r3, #4096 ; 0x1000 8003334: 2b00 cmp r3, #0 8003336: d105 bne.n 8003344 <HAL_ADC_IRQHandler+0x90> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8003338: 687b ldr r3, [r7, #4] 800333a: 6a9b ldr r3, [r3, #40] ; 0x28 800333c: f043 0201 orr.w r2, r3, #1 8003340: 687b ldr r3, [r7, #4] 8003342: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8003344: 6878 ldr r0, [r7, #4] 8003346: f7fe f945 bl 80015d4 <HAL_ADC_ConvCpltCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800334a: 687b ldr r3, [r7, #4] 800334c: 681b ldr r3, [r3, #0] 800334e: f06f 0212 mvn.w r2, #18 8003352: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 8003354: 68bb ldr r3, [r7, #8] 8003356: f003 0380 and.w r3, r3, #128 ; 0x80 800335a: 2b00 cmp r3, #0 800335c: d04d beq.n 80033fa <HAL_ADC_IRQHandler+0x146> { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800335e: 68fb ldr r3, [r7, #12] 8003360: f003 0304 and.w r3, r3, #4 8003364: 2b00 cmp r3, #0 8003366: d048 beq.n 80033fa <HAL_ADC_IRQHandler+0x146> { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8003368: 687b ldr r3, [r7, #4] 800336a: 6a9b ldr r3, [r3, #40] ; 0x28 800336c: f003 0310 and.w r3, r3, #16 8003370: 2b00 cmp r3, #0 8003372: d105 bne.n 8003380 <HAL_ADC_IRQHandler+0xcc> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 8003374: 687b ldr r3, [r7, #4] 8003376: 6a9b ldr r3, [r3, #40] ; 0x28 8003378: f443 5200 orr.w r2, r3, #8192 ; 0x2000 800337c: 687b ldr r3, [r7, #4] 800337e: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 8003380: 687b ldr r3, [r7, #4] 8003382: 681b ldr r3, [r3, #0] 8003384: 689b ldr r3, [r3, #8] 8003386: f403 43e0 and.w r3, r3, #28672 ; 0x7000 800338a: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 800338e: d012 beq.n 80033b6 <HAL_ADC_IRQHandler+0x102> (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 8003390: 687b ldr r3, [r7, #4] 8003392: 681b ldr r3, [r3, #0] 8003394: 685b ldr r3, [r3, #4] 8003396: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800339a: 2b00 cmp r3, #0 800339c: d125 bne.n 80033ea <HAL_ADC_IRQHandler+0x136> (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800339e: 687b ldr r3, [r7, #4] 80033a0: 681b ldr r3, [r3, #0] 80033a2: 689b ldr r3, [r3, #8] 80033a4: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80033a8: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80033ac: d11d bne.n 80033ea <HAL_ADC_IRQHandler+0x136> (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 80033ae: 687b ldr r3, [r7, #4] 80033b0: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80033b2: 2b00 cmp r3, #0 80033b4: d119 bne.n 80033ea <HAL_ADC_IRQHandler+0x136> { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 80033b6: 687b ldr r3, [r7, #4] 80033b8: 681b ldr r3, [r3, #0] 80033ba: 685a ldr r2, [r3, #4] 80033bc: 687b ldr r3, [r7, #4] 80033be: 681b ldr r3, [r3, #0] 80033c0: f022 0280 bic.w r2, r2, #128 ; 0x80 80033c4: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 80033c6: 687b ldr r3, [r7, #4] 80033c8: 6a9b ldr r3, [r3, #40] ; 0x28 80033ca: f423 5280 bic.w r2, r3, #4096 ; 0x1000 80033ce: 687b ldr r3, [r7, #4] 80033d0: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 80033d2: 687b ldr r3, [r7, #4] 80033d4: 6a9b ldr r3, [r3, #40] ; 0x28 80033d6: f403 7380 and.w r3, r3, #256 ; 0x100 80033da: 2b00 cmp r3, #0 80033dc: d105 bne.n 80033ea <HAL_ADC_IRQHandler+0x136> { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80033de: 687b ldr r3, [r7, #4] 80033e0: 6a9b ldr r3, [r3, #40] ; 0x28 80033e2: f043 0201 orr.w r2, r3, #1 80033e6: 687b ldr r3, [r7, #4] 80033e8: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 80033ea: 6878 ldr r0, [r7, #4] 80033ec: f000 f9bd bl 800376a <HAL_ADCEx_InjectedConvCpltCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 80033f0: 687b ldr r3, [r7, #4] 80033f2: 681b ldr r3, [r3, #0] 80033f4: f06f 020c mvn.w r2, #12 80033f8: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 80033fa: 68bb ldr r3, [r7, #8] 80033fc: f003 0340 and.w r3, r3, #64 ; 0x40 8003400: 2b00 cmp r3, #0 8003402: d012 beq.n 800342a <HAL_ADC_IRQHandler+0x176> { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 8003404: 68fb ldr r3, [r7, #12] 8003406: f003 0301 and.w r3, r3, #1 800340a: 2b00 cmp r3, #0 800340c: d00d beq.n 800342a <HAL_ADC_IRQHandler+0x176> { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800340e: 687b ldr r3, [r7, #4] 8003410: 6a9b ldr r3, [r3, #40] ; 0x28 8003412: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8003416: 687b ldr r3, [r7, #4] 8003418: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800341a: 6878 ldr r0, [r7, #4] 800341c: f000 f809 bl 8003432 <HAL_ADC_LevelOutOfWindowCallback> #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 8003420: 687b ldr r3, [r7, #4] 8003422: 681b ldr r3, [r3, #0] 8003424: f06f 0201 mvn.w r2, #1 8003428: 601a str r2, [r3, #0] } } } 800342a: bf00 nop 800342c: 3710 adds r7, #16 800342e: 46bd mov sp, r7 8003430: bd80 pop {r7, pc} 08003432 <HAL_ADC_LevelOutOfWindowCallback>: * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 8003432: b480 push {r7} 8003434: b083 sub sp, #12 8003436: af00 add r7, sp, #0 8003438: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800343a: bf00 nop 800343c: 370c adds r7, #12 800343e: 46bd mov sp, r7 8003440: bc80 pop {r7} 8003442: 4770 bx lr 08003444 <HAL_ADC_ConfigChannel>: * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8003444: b480 push {r7} 8003446: b085 sub sp, #20 8003448: af00 add r7, sp, #0 800344a: 6078 str r0, [r7, #4] 800344c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800344e: 2300 movs r3, #0 8003450: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8003452: 2300 movs r3, #0 8003454: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8003456: 687b ldr r3, [r7, #4] 8003458: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800345c: 2b01 cmp r3, #1 800345e: d101 bne.n 8003464 <HAL_ADC_ConfigChannel+0x20> 8003460: 2302 movs r3, #2 8003462: e0dc b.n 800361e <HAL_ADC_ConfigChannel+0x1da> 8003464: 687b ldr r3, [r7, #4] 8003466: 2201 movs r2, #1 8003468: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800346c: 683b ldr r3, [r7, #0] 800346e: 685b ldr r3, [r3, #4] 8003470: 2b06 cmp r3, #6 8003472: d81c bhi.n 80034ae <HAL_ADC_ConfigChannel+0x6a> { MODIFY_REG(hadc->Instance->SQR3 , 8003474: 687b ldr r3, [r7, #4] 8003476: 681b ldr r3, [r3, #0] 8003478: 6b59 ldr r1, [r3, #52] ; 0x34 800347a: 683b ldr r3, [r7, #0] 800347c: 685a ldr r2, [r3, #4] 800347e: 4613 mov r3, r2 8003480: 009b lsls r3, r3, #2 8003482: 4413 add r3, r2 8003484: 3b05 subs r3, #5 8003486: 221f movs r2, #31 8003488: fa02 f303 lsl.w r3, r2, r3 800348c: 43db mvns r3, r3 800348e: 4019 ands r1, r3 8003490: 683b ldr r3, [r7, #0] 8003492: 6818 ldr r0, [r3, #0] 8003494: 683b ldr r3, [r7, #0] 8003496: 685a ldr r2, [r3, #4] 8003498: 4613 mov r3, r2 800349a: 009b lsls r3, r3, #2 800349c: 4413 add r3, r2 800349e: 3b05 subs r3, #5 80034a0: fa00 f203 lsl.w r2, r0, r3 80034a4: 687b ldr r3, [r7, #4] 80034a6: 681b ldr r3, [r3, #0] 80034a8: 430a orrs r2, r1 80034aa: 635a str r2, [r3, #52] ; 0x34 80034ac: e03c b.n 8003528 <HAL_ADC_ConfigChannel+0xe4> ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80034ae: 683b ldr r3, [r7, #0] 80034b0: 685b ldr r3, [r3, #4] 80034b2: 2b0c cmp r3, #12 80034b4: d81c bhi.n 80034f0 <HAL_ADC_ConfigChannel+0xac> { MODIFY_REG(hadc->Instance->SQR2 , 80034b6: 687b ldr r3, [r7, #4] 80034b8: 681b ldr r3, [r3, #0] 80034ba: 6b19 ldr r1, [r3, #48] ; 0x30 80034bc: 683b ldr r3, [r7, #0] 80034be: 685a ldr r2, [r3, #4] 80034c0: 4613 mov r3, r2 80034c2: 009b lsls r3, r3, #2 80034c4: 4413 add r3, r2 80034c6: 3b23 subs r3, #35 ; 0x23 80034c8: 221f movs r2, #31 80034ca: fa02 f303 lsl.w r3, r2, r3 80034ce: 43db mvns r3, r3 80034d0: 4019 ands r1, r3 80034d2: 683b ldr r3, [r7, #0] 80034d4: 6818 ldr r0, [r3, #0] 80034d6: 683b ldr r3, [r7, #0] 80034d8: 685a ldr r2, [r3, #4] 80034da: 4613 mov r3, r2 80034dc: 009b lsls r3, r3, #2 80034de: 4413 add r3, r2 80034e0: 3b23 subs r3, #35 ; 0x23 80034e2: fa00 f203 lsl.w r2, r0, r3 80034e6: 687b ldr r3, [r7, #4] 80034e8: 681b ldr r3, [r3, #0] 80034ea: 430a orrs r2, r1 80034ec: 631a str r2, [r3, #48] ; 0x30 80034ee: e01b b.n 8003528 <HAL_ADC_ConfigChannel+0xe4> ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 80034f0: 687b ldr r3, [r7, #4] 80034f2: 681b ldr r3, [r3, #0] 80034f4: 6ad9 ldr r1, [r3, #44] ; 0x2c 80034f6: 683b ldr r3, [r7, #0] 80034f8: 685a ldr r2, [r3, #4] 80034fa: 4613 mov r3, r2 80034fc: 009b lsls r3, r3, #2 80034fe: 4413 add r3, r2 8003500: 3b41 subs r3, #65 ; 0x41 8003502: 221f movs r2, #31 8003504: fa02 f303 lsl.w r3, r2, r3 8003508: 43db mvns r3, r3 800350a: 4019 ands r1, r3 800350c: 683b ldr r3, [r7, #0] 800350e: 6818 ldr r0, [r3, #0] 8003510: 683b ldr r3, [r7, #0] 8003512: 685a ldr r2, [r3, #4] 8003514: 4613 mov r3, r2 8003516: 009b lsls r3, r3, #2 8003518: 4413 add r3, r2 800351a: 3b41 subs r3, #65 ; 0x41 800351c: fa00 f203 lsl.w r2, r0, r3 8003520: 687b ldr r3, [r7, #4] 8003522: 681b ldr r3, [r3, #0] 8003524: 430a orrs r2, r1 8003526: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8003528: 683b ldr r3, [r7, #0] 800352a: 681b ldr r3, [r3, #0] 800352c: 2b09 cmp r3, #9 800352e: d91c bls.n 800356a <HAL_ADC_ConfigChannel+0x126> { MODIFY_REG(hadc->Instance->SMPR1 , 8003530: 687b ldr r3, [r7, #4] 8003532: 681b ldr r3, [r3, #0] 8003534: 68d9 ldr r1, [r3, #12] 8003536: 683b ldr r3, [r7, #0] 8003538: 681a ldr r2, [r3, #0] 800353a: 4613 mov r3, r2 800353c: 005b lsls r3, r3, #1 800353e: 4413 add r3, r2 8003540: 3b1e subs r3, #30 8003542: 2207 movs r2, #7 8003544: fa02 f303 lsl.w r3, r2, r3 8003548: 43db mvns r3, r3 800354a: 4019 ands r1, r3 800354c: 683b ldr r3, [r7, #0] 800354e: 6898 ldr r0, [r3, #8] 8003550: 683b ldr r3, [r7, #0] 8003552: 681a ldr r2, [r3, #0] 8003554: 4613 mov r3, r2 8003556: 005b lsls r3, r3, #1 8003558: 4413 add r3, r2 800355a: 3b1e subs r3, #30 800355c: fa00 f203 lsl.w r2, r0, r3 8003560: 687b ldr r3, [r7, #4] 8003562: 681b ldr r3, [r3, #0] 8003564: 430a orrs r2, r1 8003566: 60da str r2, [r3, #12] 8003568: e019 b.n 800359e <HAL_ADC_ConfigChannel+0x15a> ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800356a: 687b ldr r3, [r7, #4] 800356c: 681b ldr r3, [r3, #0] 800356e: 6919 ldr r1, [r3, #16] 8003570: 683b ldr r3, [r7, #0] 8003572: 681a ldr r2, [r3, #0] 8003574: 4613 mov r3, r2 8003576: 005b lsls r3, r3, #1 8003578: 4413 add r3, r2 800357a: 2207 movs r2, #7 800357c: fa02 f303 lsl.w r3, r2, r3 8003580: 43db mvns r3, r3 8003582: 4019 ands r1, r3 8003584: 683b ldr r3, [r7, #0] 8003586: 6898 ldr r0, [r3, #8] 8003588: 683b ldr r3, [r7, #0] 800358a: 681a ldr r2, [r3, #0] 800358c: 4613 mov r3, r2 800358e: 005b lsls r3, r3, #1 8003590: 4413 add r3, r2 8003592: fa00 f203 lsl.w r2, r0, r3 8003596: 687b ldr r3, [r7, #4] 8003598: 681b ldr r3, [r3, #0] 800359a: 430a orrs r2, r1 800359c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800359e: 683b ldr r3, [r7, #0] 80035a0: 681b ldr r3, [r3, #0] 80035a2: 2b10 cmp r3, #16 80035a4: d003 beq.n 80035ae <HAL_ADC_ConfigChannel+0x16a> (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80035a6: 683b ldr r3, [r7, #0] 80035a8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80035aa: 2b11 cmp r3, #17 80035ac: d132 bne.n 8003614 <HAL_ADC_ConfigChannel+0x1d0> { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80035ae: 687b ldr r3, [r7, #4] 80035b0: 681b ldr r3, [r3, #0] 80035b2: 4a1d ldr r2, [pc, #116] ; (8003628 <HAL_ADC_ConfigChannel+0x1e4>) 80035b4: 4293 cmp r3, r2 80035b6: d125 bne.n 8003604 <HAL_ADC_ConfigChannel+0x1c0> { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80035b8: 687b ldr r3, [r7, #4] 80035ba: 681b ldr r3, [r3, #0] 80035bc: 689b ldr r3, [r3, #8] 80035be: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80035c2: 2b00 cmp r3, #0 80035c4: d126 bne.n 8003614 <HAL_ADC_ConfigChannel+0x1d0> { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80035c6: 687b ldr r3, [r7, #4] 80035c8: 681b ldr r3, [r3, #0] 80035ca: 689a ldr r2, [r3, #8] 80035cc: 687b ldr r3, [r7, #4] 80035ce: 681b ldr r3, [r3, #0] 80035d0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 80035d4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 80035d6: 683b ldr r3, [r7, #0] 80035d8: 681b ldr r3, [r3, #0] 80035da: 2b10 cmp r3, #16 80035dc: d11a bne.n 8003614 <HAL_ADC_ConfigChannel+0x1d0> { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 80035de: 4b13 ldr r3, [pc, #76] ; (800362c <HAL_ADC_ConfigChannel+0x1e8>) 80035e0: 681b ldr r3, [r3, #0] 80035e2: 4a13 ldr r2, [pc, #76] ; (8003630 <HAL_ADC_ConfigChannel+0x1ec>) 80035e4: fba2 2303 umull r2, r3, r2, r3 80035e8: 0c9a lsrs r2, r3, #18 80035ea: 4613 mov r3, r2 80035ec: 009b lsls r3, r3, #2 80035ee: 4413 add r3, r2 80035f0: 005b lsls r3, r3, #1 80035f2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80035f4: e002 b.n 80035fc <HAL_ADC_ConfigChannel+0x1b8> { wait_loop_index--; 80035f6: 68bb ldr r3, [r7, #8] 80035f8: 3b01 subs r3, #1 80035fa: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80035fc: 68bb ldr r3, [r7, #8] 80035fe: 2b00 cmp r3, #0 8003600: d1f9 bne.n 80035f6 <HAL_ADC_ConfigChannel+0x1b2> 8003602: e007 b.n 8003614 <HAL_ADC_ConfigChannel+0x1d0> } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003604: 687b ldr r3, [r7, #4] 8003606: 6a9b ldr r3, [r3, #40] ; 0x28 8003608: f043 0220 orr.w r2, r3, #32 800360c: 687b ldr r3, [r7, #4] 800360e: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8003610: 2301 movs r3, #1 8003612: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8003614: 687b ldr r3, [r7, #4] 8003616: 2200 movs r2, #0 8003618: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800361c: 7bfb ldrb r3, [r7, #15] } 800361e: 4618 mov r0, r3 8003620: 3714 adds r7, #20 8003622: 46bd mov sp, r7 8003624: bc80 pop {r7} 8003626: 4770 bx lr 8003628: 40012400 .word 0x40012400 800362c: 20000008 .word 0x20000008 8003630: 431bde83 .word 0x431bde83 08003634 <ADC_Enable>: * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8003634: b580 push {r7, lr} 8003636: b084 sub sp, #16 8003638: af00 add r7, sp, #0 800363a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800363c: 2300 movs r3, #0 800363e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8003640: 2300 movs r3, #0 8003642: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8003644: 687b ldr r3, [r7, #4] 8003646: 681b ldr r3, [r3, #0] 8003648: 689b ldr r3, [r3, #8] 800364a: f003 0301 and.w r3, r3, #1 800364e: 2b01 cmp r3, #1 8003650: d040 beq.n 80036d4 <ADC_Enable+0xa0> { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8003652: 687b ldr r3, [r7, #4] 8003654: 681b ldr r3, [r3, #0] 8003656: 689a ldr r2, [r3, #8] 8003658: 687b ldr r3, [r7, #4] 800365a: 681b ldr r3, [r3, #0] 800365c: f042 0201 orr.w r2, r2, #1 8003660: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8003662: 4b1f ldr r3, [pc, #124] ; (80036e0 <ADC_Enable+0xac>) 8003664: 681b ldr r3, [r3, #0] 8003666: 4a1f ldr r2, [pc, #124] ; (80036e4 <ADC_Enable+0xb0>) 8003668: fba2 2303 umull r2, r3, r2, r3 800366c: 0c9b lsrs r3, r3, #18 800366e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8003670: e002 b.n 8003678 <ADC_Enable+0x44> { wait_loop_index--; 8003672: 68bb ldr r3, [r7, #8] 8003674: 3b01 subs r3, #1 8003676: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8003678: 68bb ldr r3, [r7, #8] 800367a: 2b00 cmp r3, #0 800367c: d1f9 bne.n 8003672 <ADC_Enable+0x3e> } /* Get tick count */ tickstart = HAL_GetTick(); 800367e: f7ff fa71 bl 8002b64 <HAL_GetTick> 8003682: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8003684: e01f b.n 80036c6 <ADC_Enable+0x92> { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8003686: f7ff fa6d bl 8002b64 <HAL_GetTick> 800368a: 4602 mov r2, r0 800368c: 68fb ldr r3, [r7, #12] 800368e: 1ad3 subs r3, r2, r3 8003690: 2b02 cmp r3, #2 8003692: d918 bls.n 80036c6 <ADC_Enable+0x92> { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 8003694: 687b ldr r3, [r7, #4] 8003696: 681b ldr r3, [r3, #0] 8003698: 689b ldr r3, [r3, #8] 800369a: f003 0301 and.w r3, r3, #1 800369e: 2b01 cmp r3, #1 80036a0: d011 beq.n 80036c6 <ADC_Enable+0x92> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80036a2: 687b ldr r3, [r7, #4] 80036a4: 6a9b ldr r3, [r3, #40] ; 0x28 80036a6: f043 0210 orr.w r2, r3, #16 80036aa: 687b ldr r3, [r7, #4] 80036ac: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80036ae: 687b ldr r3, [r7, #4] 80036b0: 6adb ldr r3, [r3, #44] ; 0x2c 80036b2: f043 0201 orr.w r2, r3, #1 80036b6: 687b ldr r3, [r7, #4] 80036b8: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80036ba: 687b ldr r3, [r7, #4] 80036bc: 2200 movs r2, #0 80036be: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80036c2: 2301 movs r3, #1 80036c4: e007 b.n 80036d6 <ADC_Enable+0xa2> while(ADC_IS_ENABLE(hadc) == RESET) 80036c6: 687b ldr r3, [r7, #4] 80036c8: 681b ldr r3, [r3, #0] 80036ca: 689b ldr r3, [r3, #8] 80036cc: f003 0301 and.w r3, r3, #1 80036d0: 2b01 cmp r3, #1 80036d2: d1d8 bne.n 8003686 <ADC_Enable+0x52> } } } /* Return HAL status */ return HAL_OK; 80036d4: 2300 movs r3, #0 } 80036d6: 4618 mov r0, r3 80036d8: 3710 adds r7, #16 80036da: 46bd mov sp, r7 80036dc: bd80 pop {r7, pc} 80036de: bf00 nop 80036e0: 20000008 .word 0x20000008 80036e4: 431bde83 .word 0x431bde83 080036e8 <ADC_ConversionStop_Disable>: * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 80036e8: b580 push {r7, lr} 80036ea: b084 sub sp, #16 80036ec: af00 add r7, sp, #0 80036ee: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80036f0: 2300 movs r3, #0 80036f2: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 80036f4: 687b ldr r3, [r7, #4] 80036f6: 681b ldr r3, [r3, #0] 80036f8: 689b ldr r3, [r3, #8] 80036fa: f003 0301 and.w r3, r3, #1 80036fe: 2b01 cmp r3, #1 8003700: d12e bne.n 8003760 <ADC_ConversionStop_Disable+0x78> { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8003702: 687b ldr r3, [r7, #4] 8003704: 681b ldr r3, [r3, #0] 8003706: 689a ldr r2, [r3, #8] 8003708: 687b ldr r3, [r7, #4] 800370a: 681b ldr r3, [r3, #0] 800370c: f022 0201 bic.w r2, r2, #1 8003710: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8003712: f7ff fa27 bl 8002b64 <HAL_GetTick> 8003716: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8003718: e01b b.n 8003752 <ADC_ConversionStop_Disable+0x6a> { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800371a: f7ff fa23 bl 8002b64 <HAL_GetTick> 800371e: 4602 mov r2, r0 8003720: 68fb ldr r3, [r7, #12] 8003722: 1ad3 subs r3, r2, r3 8003724: 2b02 cmp r3, #2 8003726: d914 bls.n 8003752 <ADC_ConversionStop_Disable+0x6a> { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8003728: 687b ldr r3, [r7, #4] 800372a: 681b ldr r3, [r3, #0] 800372c: 689b ldr r3, [r3, #8] 800372e: f003 0301 and.w r3, r3, #1 8003732: 2b01 cmp r3, #1 8003734: d10d bne.n 8003752 <ADC_ConversionStop_Disable+0x6a> { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8003736: 687b ldr r3, [r7, #4] 8003738: 6a9b ldr r3, [r3, #40] ; 0x28 800373a: f043 0210 orr.w r2, r3, #16 800373e: 687b ldr r3, [r7, #4] 8003740: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003742: 687b ldr r3, [r7, #4] 8003744: 6adb ldr r3, [r3, #44] ; 0x2c 8003746: f043 0201 orr.w r2, r3, #1 800374a: 687b ldr r3, [r7, #4] 800374c: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800374e: 2301 movs r3, #1 8003750: e007 b.n 8003762 <ADC_ConversionStop_Disable+0x7a> while(ADC_IS_ENABLE(hadc) != RESET) 8003752: 687b ldr r3, [r7, #4] 8003754: 681b ldr r3, [r3, #0] 8003756: 689b ldr r3, [r3, #8] 8003758: f003 0301 and.w r3, r3, #1 800375c: 2b01 cmp r3, #1 800375e: d0dc beq.n 800371a <ADC_ConversionStop_Disable+0x32> } } } /* Return HAL status */ return HAL_OK; 8003760: 2300 movs r3, #0 } 8003762: 4618 mov r0, r3 8003764: 3710 adds r7, #16 8003766: 46bd mov sp, r7 8003768: bd80 pop {r7, pc} 0800376a <HAL_ADCEx_InjectedConvCpltCallback>: * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800376a: b480 push {r7} 800376c: b083 sub sp, #12 800376e: af00 add r7, sp, #0 8003770: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 8003772: bf00 nop 8003774: 370c adds r7, #12 8003776: 46bd mov sp, r7 8003778: bc80 pop {r7} 800377a: 4770 bx lr 0800377c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800377c: b480 push {r7} 800377e: b085 sub sp, #20 8003780: af00 add r7, sp, #0 8003782: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003784: 687b ldr r3, [r7, #4] 8003786: f003 0307 and.w r3, r3, #7 800378a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800378c: 4b0c ldr r3, [pc, #48] ; (80037c0 <__NVIC_SetPriorityGrouping+0x44>) 800378e: 68db ldr r3, [r3, #12] 8003790: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8003792: 68ba ldr r2, [r7, #8] 8003794: f64f 03ff movw r3, #63743 ; 0xf8ff 8003798: 4013 ands r3, r2 800379a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800379c: 68fb ldr r3, [r7, #12] 800379e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80037a0: 68bb ldr r3, [r7, #8] 80037a2: 4313 orrs r3, r2 reg_value = (reg_value | 80037a4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80037a8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80037ac: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80037ae: 4a04 ldr r2, [pc, #16] ; (80037c0 <__NVIC_SetPriorityGrouping+0x44>) 80037b0: 68bb ldr r3, [r7, #8] 80037b2: 60d3 str r3, [r2, #12] } 80037b4: bf00 nop 80037b6: 3714 adds r7, #20 80037b8: 46bd mov sp, r7 80037ba: bc80 pop {r7} 80037bc: 4770 bx lr 80037be: bf00 nop 80037c0: e000ed00 .word 0xe000ed00 080037c4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80037c4: b480 push {r7} 80037c6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80037c8: 4b04 ldr r3, [pc, #16] ; (80037dc <__NVIC_GetPriorityGrouping+0x18>) 80037ca: 68db ldr r3, [r3, #12] 80037cc: 0a1b lsrs r3, r3, #8 80037ce: f003 0307 and.w r3, r3, #7 } 80037d2: 4618 mov r0, r3 80037d4: 46bd mov sp, r7 80037d6: bc80 pop {r7} 80037d8: 4770 bx lr 80037da: bf00 nop 80037dc: e000ed00 .word 0xe000ed00 080037e0 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80037e0: b480 push {r7} 80037e2: b083 sub sp, #12 80037e4: af00 add r7, sp, #0 80037e6: 4603 mov r3, r0 80037e8: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80037ea: f997 3007 ldrsb.w r3, [r7, #7] 80037ee: 2b00 cmp r3, #0 80037f0: db0b blt.n 800380a <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80037f2: 79fb ldrb r3, [r7, #7] 80037f4: f003 021f and.w r2, r3, #31 80037f8: 4906 ldr r1, [pc, #24] ; (8003814 <__NVIC_EnableIRQ+0x34>) 80037fa: f997 3007 ldrsb.w r3, [r7, #7] 80037fe: 095b lsrs r3, r3, #5 8003800: 2001 movs r0, #1 8003802: fa00 f202 lsl.w r2, r0, r2 8003806: f841 2023 str.w r2, [r1, r3, lsl #2] } } 800380a: bf00 nop 800380c: 370c adds r7, #12 800380e: 46bd mov sp, r7 8003810: bc80 pop {r7} 8003812: 4770 bx lr 8003814: e000e100 .word 0xe000e100 08003818 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8003818: b480 push {r7} 800381a: b083 sub sp, #12 800381c: af00 add r7, sp, #0 800381e: 4603 mov r3, r0 8003820: 6039 str r1, [r7, #0] 8003822: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003824: f997 3007 ldrsb.w r3, [r7, #7] 8003828: 2b00 cmp r3, #0 800382a: db0a blt.n 8003842 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800382c: 683b ldr r3, [r7, #0] 800382e: b2da uxtb r2, r3 8003830: 490c ldr r1, [pc, #48] ; (8003864 <__NVIC_SetPriority+0x4c>) 8003832: f997 3007 ldrsb.w r3, [r7, #7] 8003836: 0112 lsls r2, r2, #4 8003838: b2d2 uxtb r2, r2 800383a: 440b add r3, r1 800383c: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8003840: e00a b.n 8003858 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003842: 683b ldr r3, [r7, #0] 8003844: b2da uxtb r2, r3 8003846: 4908 ldr r1, [pc, #32] ; (8003868 <__NVIC_SetPriority+0x50>) 8003848: 79fb ldrb r3, [r7, #7] 800384a: f003 030f and.w r3, r3, #15 800384e: 3b04 subs r3, #4 8003850: 0112 lsls r2, r2, #4 8003852: b2d2 uxtb r2, r2 8003854: 440b add r3, r1 8003856: 761a strb r2, [r3, #24] } 8003858: bf00 nop 800385a: 370c adds r7, #12 800385c: 46bd mov sp, r7 800385e: bc80 pop {r7} 8003860: 4770 bx lr 8003862: bf00 nop 8003864: e000e100 .word 0xe000e100 8003868: e000ed00 .word 0xe000ed00 0800386c <NVIC_EncodePriority>: \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 800386c: b480 push {r7} 800386e: b089 sub sp, #36 ; 0x24 8003870: af00 add r7, sp, #0 8003872: 60f8 str r0, [r7, #12] 8003874: 60b9 str r1, [r7, #8] 8003876: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003878: 68fb ldr r3, [r7, #12] 800387a: f003 0307 and.w r3, r3, #7 800387e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8003880: 69fb ldr r3, [r7, #28] 8003882: f1c3 0307 rsb r3, r3, #7 8003886: 2b04 cmp r3, #4 8003888: bf28 it cs 800388a: 2304 movcs r3, #4 800388c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800388e: 69fb ldr r3, [r7, #28] 8003890: 3304 adds r3, #4 8003892: 2b06 cmp r3, #6 8003894: d902 bls.n 800389c <NVIC_EncodePriority+0x30> 8003896: 69fb ldr r3, [r7, #28] 8003898: 3b03 subs r3, #3 800389a: e000 b.n 800389e <NVIC_EncodePriority+0x32> 800389c: 2300 movs r3, #0 800389e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80038a0: f04f 32ff mov.w r2, #4294967295 80038a4: 69bb ldr r3, [r7, #24] 80038a6: fa02 f303 lsl.w r3, r2, r3 80038aa: 43da mvns r2, r3 80038ac: 68bb ldr r3, [r7, #8] 80038ae: 401a ands r2, r3 80038b0: 697b ldr r3, [r7, #20] 80038b2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80038b4: f04f 31ff mov.w r1, #4294967295 80038b8: 697b ldr r3, [r7, #20] 80038ba: fa01 f303 lsl.w r3, r1, r3 80038be: 43d9 mvns r1, r3 80038c0: 687b ldr r3, [r7, #4] 80038c2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80038c4: 4313 orrs r3, r2 ); } 80038c6: 4618 mov r0, r3 80038c8: 3724 adds r7, #36 ; 0x24 80038ca: 46bd mov sp, r7 80038cc: bc80 pop {r7} 80038ce: 4770 bx lr 080038d0 <SysTick_Config>: \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80038d0: b580 push {r7, lr} 80038d2: b082 sub sp, #8 80038d4: af00 add r7, sp, #0 80038d6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80038d8: 687b ldr r3, [r7, #4] 80038da: 3b01 subs r3, #1 80038dc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80038e0: d301 bcc.n 80038e6 <SysTick_Config+0x16> { return (1UL); /* Reload value impossible */ 80038e2: 2301 movs r3, #1 80038e4: e00f b.n 8003906 <SysTick_Config+0x36> } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80038e6: 4a0a ldr r2, [pc, #40] ; (8003910 <SysTick_Config+0x40>) 80038e8: 687b ldr r3, [r7, #4] 80038ea: 3b01 subs r3, #1 80038ec: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80038ee: 210f movs r1, #15 80038f0: f04f 30ff mov.w r0, #4294967295 80038f4: f7ff ff90 bl 8003818 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80038f8: 4b05 ldr r3, [pc, #20] ; (8003910 <SysTick_Config+0x40>) 80038fa: 2200 movs r2, #0 80038fc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80038fe: 4b04 ldr r3, [pc, #16] ; (8003910 <SysTick_Config+0x40>) 8003900: 2207 movs r2, #7 8003902: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003904: 2300 movs r3, #0 } 8003906: 4618 mov r0, r3 8003908: 3708 adds r7, #8 800390a: 46bd mov sp, r7 800390c: bd80 pop {r7, pc} 800390e: bf00 nop 8003910: e000e010 .word 0xe000e010 08003914 <HAL_NVIC_SetPriorityGrouping>: * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003914: b580 push {r7, lr} 8003916: b082 sub sp, #8 8003918: af00 add r7, sp, #0 800391a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800391c: 6878 ldr r0, [r7, #4] 800391e: f7ff ff2d bl 800377c <__NVIC_SetPriorityGrouping> } 8003922: bf00 nop 8003924: 3708 adds r7, #8 8003926: 46bd mov sp, r7 8003928: bd80 pop {r7, pc} 0800392a <HAL_NVIC_SetPriority>: * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800392a: b580 push {r7, lr} 800392c: b086 sub sp, #24 800392e: af00 add r7, sp, #0 8003930: 4603 mov r3, r0 8003932: 60b9 str r1, [r7, #8] 8003934: 607a str r2, [r7, #4] 8003936: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8003938: 2300 movs r3, #0 800393a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800393c: f7ff ff42 bl 80037c4 <__NVIC_GetPriorityGrouping> 8003940: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8003942: 687a ldr r2, [r7, #4] 8003944: 68b9 ldr r1, [r7, #8] 8003946: 6978 ldr r0, [r7, #20] 8003948: f7ff ff90 bl 800386c <NVIC_EncodePriority> 800394c: 4602 mov r2, r0 800394e: f997 300f ldrsb.w r3, [r7, #15] 8003952: 4611 mov r1, r2 8003954: 4618 mov r0, r3 8003956: f7ff ff5f bl 8003818 <__NVIC_SetPriority> } 800395a: bf00 nop 800395c: 3718 adds r7, #24 800395e: 46bd mov sp, r7 8003960: bd80 pop {r7, pc} 08003962 <HAL_NVIC_EnableIRQ>: * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8003962: b580 push {r7, lr} 8003964: b082 sub sp, #8 8003966: af00 add r7, sp, #0 8003968: 4603 mov r3, r0 800396a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800396c: f997 3007 ldrsb.w r3, [r7, #7] 8003970: 4618 mov r0, r3 8003972: f7ff ff35 bl 80037e0 <__NVIC_EnableIRQ> } 8003976: bf00 nop 8003978: 3708 adds r7, #8 800397a: 46bd mov sp, r7 800397c: bd80 pop {r7, pc} 0800397e <HAL_SYSTICK_Config>: * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800397e: b580 push {r7, lr} 8003980: b082 sub sp, #8 8003982: af00 add r7, sp, #0 8003984: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8003986: 6878 ldr r0, [r7, #4] 8003988: f7ff ffa2 bl 80038d0 <SysTick_Config> 800398c: 4603 mov r3, r0 } 800398e: 4618 mov r0, r3 8003990: 3708 adds r7, #8 8003992: 46bd mov sp, r7 8003994: bd80 pop {r7, pc} ... 08003998 <HAL_DMA_Abort_IT>: * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003998: b580 push {r7, lr} 800399a: b084 sub sp, #16 800399c: af00 add r7, sp, #0 800399e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80039a0: 2300 movs r3, #0 80039a2: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 80039a4: 687b ldr r3, [r7, #4] 80039a6: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 80039aa: b2db uxtb r3, r3 80039ac: 2b02 cmp r3, #2 80039ae: d005 beq.n 80039bc <HAL_DMA_Abort_IT+0x24> { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80039b0: 687b ldr r3, [r7, #4] 80039b2: 2204 movs r2, #4 80039b4: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 80039b6: 2301 movs r3, #1 80039b8: 73fb strb r3, [r7, #15] 80039ba: e051 b.n 8003a60 <HAL_DMA_Abort_IT+0xc8> } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80039bc: 687b ldr r3, [r7, #4] 80039be: 681b ldr r3, [r3, #0] 80039c0: 681a ldr r2, [r3, #0] 80039c2: 687b ldr r3, [r7, #4] 80039c4: 681b ldr r3, [r3, #0] 80039c6: f022 020e bic.w r2, r2, #14 80039ca: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80039cc: 687b ldr r3, [r7, #4] 80039ce: 681b ldr r3, [r3, #0] 80039d0: 681a ldr r2, [r3, #0] 80039d2: 687b ldr r3, [r7, #4] 80039d4: 681b ldr r3, [r3, #0] 80039d6: f022 0201 bic.w r2, r2, #1 80039da: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80039dc: 687b ldr r3, [r7, #4] 80039de: 681b ldr r3, [r3, #0] 80039e0: 4a22 ldr r2, [pc, #136] ; (8003a6c <HAL_DMA_Abort_IT+0xd4>) 80039e2: 4293 cmp r3, r2 80039e4: d029 beq.n 8003a3a <HAL_DMA_Abort_IT+0xa2> 80039e6: 687b ldr r3, [r7, #4] 80039e8: 681b ldr r3, [r3, #0] 80039ea: 4a21 ldr r2, [pc, #132] ; (8003a70 <HAL_DMA_Abort_IT+0xd8>) 80039ec: 4293 cmp r3, r2 80039ee: d022 beq.n 8003a36 <HAL_DMA_Abort_IT+0x9e> 80039f0: 687b ldr r3, [r7, #4] 80039f2: 681b ldr r3, [r3, #0] 80039f4: 4a1f ldr r2, [pc, #124] ; (8003a74 <HAL_DMA_Abort_IT+0xdc>) 80039f6: 4293 cmp r3, r2 80039f8: d01a beq.n 8003a30 <HAL_DMA_Abort_IT+0x98> 80039fa: 687b ldr r3, [r7, #4] 80039fc: 681b ldr r3, [r3, #0] 80039fe: 4a1e ldr r2, [pc, #120] ; (8003a78 <HAL_DMA_Abort_IT+0xe0>) 8003a00: 4293 cmp r3, r2 8003a02: d012 beq.n 8003a2a <HAL_DMA_Abort_IT+0x92> 8003a04: 687b ldr r3, [r7, #4] 8003a06: 681b ldr r3, [r3, #0] 8003a08: 4a1c ldr r2, [pc, #112] ; (8003a7c <HAL_DMA_Abort_IT+0xe4>) 8003a0a: 4293 cmp r3, r2 8003a0c: d00a beq.n 8003a24 <HAL_DMA_Abort_IT+0x8c> 8003a0e: 687b ldr r3, [r7, #4] 8003a10: 681b ldr r3, [r3, #0] 8003a12: 4a1b ldr r2, [pc, #108] ; (8003a80 <HAL_DMA_Abort_IT+0xe8>) 8003a14: 4293 cmp r3, r2 8003a16: d102 bne.n 8003a1e <HAL_DMA_Abort_IT+0x86> 8003a18: f44f 1380 mov.w r3, #1048576 ; 0x100000 8003a1c: e00e b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a1e: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003a22: e00b b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a24: f44f 3380 mov.w r3, #65536 ; 0x10000 8003a28: e008 b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a2a: f44f 5380 mov.w r3, #4096 ; 0x1000 8003a2e: e005 b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a30: f44f 7380 mov.w r3, #256 ; 0x100 8003a34: e002 b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a36: 2310 movs r3, #16 8003a38: e000 b.n 8003a3c <HAL_DMA_Abort_IT+0xa4> 8003a3a: 2301 movs r3, #1 8003a3c: 4a11 ldr r2, [pc, #68] ; (8003a84 <HAL_DMA_Abort_IT+0xec>) 8003a3e: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003a40: 687b ldr r3, [r7, #4] 8003a42: 2201 movs r2, #1 8003a44: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003a48: 687b ldr r3, [r7, #4] 8003a4a: 2200 movs r2, #0 8003a4c: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8003a50: 687b ldr r3, [r7, #4] 8003a52: 6b5b ldr r3, [r3, #52] ; 0x34 8003a54: 2b00 cmp r3, #0 8003a56: d003 beq.n 8003a60 <HAL_DMA_Abort_IT+0xc8> { hdma->XferAbortCallback(hdma); 8003a58: 687b ldr r3, [r7, #4] 8003a5a: 6b5b ldr r3, [r3, #52] ; 0x34 8003a5c: 6878 ldr r0, [r7, #4] 8003a5e: 4798 blx r3 } } return status; 8003a60: 7bfb ldrb r3, [r7, #15] } 8003a62: 4618 mov r0, r3 8003a64: 3710 adds r7, #16 8003a66: 46bd mov sp, r7 8003a68: bd80 pop {r7, pc} 8003a6a: bf00 nop 8003a6c: 40020008 .word 0x40020008 8003a70: 4002001c .word 0x4002001c 8003a74: 40020030 .word 0x40020030 8003a78: 40020044 .word 0x40020044 8003a7c: 40020058 .word 0x40020058 8003a80: 4002006c .word 0x4002006c 8003a84: 40020000 .word 0x40020000 08003a88 <HAL_GPIO_Init>: * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8003a88: b480 push {r7} 8003a8a: b08b sub sp, #44 ; 0x2c 8003a8c: af00 add r7, sp, #0 8003a8e: 6078 str r0, [r7, #4] 8003a90: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003a92: 2300 movs r3, #0 8003a94: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8003a96: 2300 movs r3, #0 8003a98: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8003a9a: e169 b.n 8003d70 <HAL_GPIO_Init+0x2e8> { /* Get the IO position */ ioposition = (0x01uL << position); 8003a9c: 2201 movs r2, #1 8003a9e: 6a7b ldr r3, [r7, #36] ; 0x24 8003aa0: fa02 f303 lsl.w r3, r2, r3 8003aa4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8003aa6: 683b ldr r3, [r7, #0] 8003aa8: 681b ldr r3, [r3, #0] 8003aaa: 69fa ldr r2, [r7, #28] 8003aac: 4013 ands r3, r2 8003aae: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8003ab0: 69ba ldr r2, [r7, #24] 8003ab2: 69fb ldr r3, [r7, #28] 8003ab4: 429a cmp r2, r3 8003ab6: f040 8158 bne.w 8003d6a <HAL_GPIO_Init+0x2e2> { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8003aba: 683b ldr r3, [r7, #0] 8003abc: 685b ldr r3, [r3, #4] 8003abe: 4a9a ldr r2, [pc, #616] ; (8003d28 <HAL_GPIO_Init+0x2a0>) 8003ac0: 4293 cmp r3, r2 8003ac2: d05e beq.n 8003b82 <HAL_GPIO_Init+0xfa> 8003ac4: 4a98 ldr r2, [pc, #608] ; (8003d28 <HAL_GPIO_Init+0x2a0>) 8003ac6: 4293 cmp r3, r2 8003ac8: d875 bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003aca: 4a98 ldr r2, [pc, #608] ; (8003d2c <HAL_GPIO_Init+0x2a4>) 8003acc: 4293 cmp r3, r2 8003ace: d058 beq.n 8003b82 <HAL_GPIO_Init+0xfa> 8003ad0: 4a96 ldr r2, [pc, #600] ; (8003d2c <HAL_GPIO_Init+0x2a4>) 8003ad2: 4293 cmp r3, r2 8003ad4: d86f bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003ad6: 4a96 ldr r2, [pc, #600] ; (8003d30 <HAL_GPIO_Init+0x2a8>) 8003ad8: 4293 cmp r3, r2 8003ada: d052 beq.n 8003b82 <HAL_GPIO_Init+0xfa> 8003adc: 4a94 ldr r2, [pc, #592] ; (8003d30 <HAL_GPIO_Init+0x2a8>) 8003ade: 4293 cmp r3, r2 8003ae0: d869 bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003ae2: 4a94 ldr r2, [pc, #592] ; (8003d34 <HAL_GPIO_Init+0x2ac>) 8003ae4: 4293 cmp r3, r2 8003ae6: d04c beq.n 8003b82 <HAL_GPIO_Init+0xfa> 8003ae8: 4a92 ldr r2, [pc, #584] ; (8003d34 <HAL_GPIO_Init+0x2ac>) 8003aea: 4293 cmp r3, r2 8003aec: d863 bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003aee: 4a92 ldr r2, [pc, #584] ; (8003d38 <HAL_GPIO_Init+0x2b0>) 8003af0: 4293 cmp r3, r2 8003af2: d046 beq.n 8003b82 <HAL_GPIO_Init+0xfa> 8003af4: 4a90 ldr r2, [pc, #576] ; (8003d38 <HAL_GPIO_Init+0x2b0>) 8003af6: 4293 cmp r3, r2 8003af8: d85d bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003afa: 2b12 cmp r3, #18 8003afc: d82a bhi.n 8003b54 <HAL_GPIO_Init+0xcc> 8003afe: 2b12 cmp r3, #18 8003b00: d859 bhi.n 8003bb6 <HAL_GPIO_Init+0x12e> 8003b02: a201 add r2, pc, #4 ; (adr r2, 8003b08 <HAL_GPIO_Init+0x80>) 8003b04: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003b08: 08003b83 .word 0x08003b83 8003b0c: 08003b5d .word 0x08003b5d 8003b10: 08003b6f .word 0x08003b6f 8003b14: 08003bb1 .word 0x08003bb1 8003b18: 08003bb7 .word 0x08003bb7 8003b1c: 08003bb7 .word 0x08003bb7 8003b20: 08003bb7 .word 0x08003bb7 8003b24: 08003bb7 .word 0x08003bb7 8003b28: 08003bb7 .word 0x08003bb7 8003b2c: 08003bb7 .word 0x08003bb7 8003b30: 08003bb7 .word 0x08003bb7 8003b34: 08003bb7 .word 0x08003bb7 8003b38: 08003bb7 .word 0x08003bb7 8003b3c: 08003bb7 .word 0x08003bb7 8003b40: 08003bb7 .word 0x08003bb7 8003b44: 08003bb7 .word 0x08003bb7 8003b48: 08003bb7 .word 0x08003bb7 8003b4c: 08003b65 .word 0x08003b65 8003b50: 08003b79 .word 0x08003b79 8003b54: 4a79 ldr r2, [pc, #484] ; (8003d3c <HAL_GPIO_Init+0x2b4>) 8003b56: 4293 cmp r3, r2 8003b58: d013 beq.n 8003b82 <HAL_GPIO_Init+0xfa> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8003b5a: e02c b.n 8003bb6 <HAL_GPIO_Init+0x12e> config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8003b5c: 683b ldr r3, [r7, #0] 8003b5e: 68db ldr r3, [r3, #12] 8003b60: 623b str r3, [r7, #32] break; 8003b62: e029 b.n 8003bb8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8003b64: 683b ldr r3, [r7, #0] 8003b66: 68db ldr r3, [r3, #12] 8003b68: 3304 adds r3, #4 8003b6a: 623b str r3, [r7, #32] break; 8003b6c: e024 b.n 8003bb8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8003b6e: 683b ldr r3, [r7, #0] 8003b70: 68db ldr r3, [r3, #12] 8003b72: 3308 adds r3, #8 8003b74: 623b str r3, [r7, #32] break; 8003b76: e01f b.n 8003bb8 <HAL_GPIO_Init+0x130> config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8003b78: 683b ldr r3, [r7, #0] 8003b7a: 68db ldr r3, [r3, #12] 8003b7c: 330c adds r3, #12 8003b7e: 623b str r3, [r7, #32] break; 8003b80: e01a b.n 8003bb8 <HAL_GPIO_Init+0x130> if (GPIO_Init->Pull == GPIO_NOPULL) 8003b82: 683b ldr r3, [r7, #0] 8003b84: 689b ldr r3, [r3, #8] 8003b86: 2b00 cmp r3, #0 8003b88: d102 bne.n 8003b90 <HAL_GPIO_Init+0x108> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8003b8a: 2304 movs r3, #4 8003b8c: 623b str r3, [r7, #32] break; 8003b8e: e013 b.n 8003bb8 <HAL_GPIO_Init+0x130> else if (GPIO_Init->Pull == GPIO_PULLUP) 8003b90: 683b ldr r3, [r7, #0] 8003b92: 689b ldr r3, [r3, #8] 8003b94: 2b01 cmp r3, #1 8003b96: d105 bne.n 8003ba4 <HAL_GPIO_Init+0x11c> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8003b98: 2308 movs r3, #8 8003b9a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8003b9c: 687b ldr r3, [r7, #4] 8003b9e: 69fa ldr r2, [r7, #28] 8003ba0: 611a str r2, [r3, #16] break; 8003ba2: e009 b.n 8003bb8 <HAL_GPIO_Init+0x130> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8003ba4: 2308 movs r3, #8 8003ba6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8003ba8: 687b ldr r3, [r7, #4] 8003baa: 69fa ldr r2, [r7, #28] 8003bac: 615a str r2, [r3, #20] break; 8003bae: e003 b.n 8003bb8 <HAL_GPIO_Init+0x130> config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8003bb0: 2300 movs r3, #0 8003bb2: 623b str r3, [r7, #32] break; 8003bb4: e000 b.n 8003bb8 <HAL_GPIO_Init+0x130> break; 8003bb6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8003bb8: 69bb ldr r3, [r7, #24] 8003bba: 2bff cmp r3, #255 ; 0xff 8003bbc: d801 bhi.n 8003bc2 <HAL_GPIO_Init+0x13a> 8003bbe: 687b ldr r3, [r7, #4] 8003bc0: e001 b.n 8003bc6 <HAL_GPIO_Init+0x13e> 8003bc2: 687b ldr r3, [r7, #4] 8003bc4: 3304 adds r3, #4 8003bc6: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8003bc8: 69bb ldr r3, [r7, #24] 8003bca: 2bff cmp r3, #255 ; 0xff 8003bcc: d802 bhi.n 8003bd4 <HAL_GPIO_Init+0x14c> 8003bce: 6a7b ldr r3, [r7, #36] ; 0x24 8003bd0: 009b lsls r3, r3, #2 8003bd2: e002 b.n 8003bda <HAL_GPIO_Init+0x152> 8003bd4: 6a7b ldr r3, [r7, #36] ; 0x24 8003bd6: 3b08 subs r3, #8 8003bd8: 009b lsls r3, r3, #2 8003bda: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8003bdc: 697b ldr r3, [r7, #20] 8003bde: 681a ldr r2, [r3, #0] 8003be0: 210f movs r1, #15 8003be2: 693b ldr r3, [r7, #16] 8003be4: fa01 f303 lsl.w r3, r1, r3 8003be8: 43db mvns r3, r3 8003bea: 401a ands r2, r3 8003bec: 6a39 ldr r1, [r7, #32] 8003bee: 693b ldr r3, [r7, #16] 8003bf0: fa01 f303 lsl.w r3, r1, r3 8003bf4: 431a orrs r2, r3 8003bf6: 697b ldr r3, [r7, #20] 8003bf8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8003bfa: 683b ldr r3, [r7, #0] 8003bfc: 685b ldr r3, [r3, #4] 8003bfe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003c02: 2b00 cmp r3, #0 8003c04: f000 80b1 beq.w 8003d6a <HAL_GPIO_Init+0x2e2> { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8003c08: 4b4d ldr r3, [pc, #308] ; (8003d40 <HAL_GPIO_Init+0x2b8>) 8003c0a: 699b ldr r3, [r3, #24] 8003c0c: 4a4c ldr r2, [pc, #304] ; (8003d40 <HAL_GPIO_Init+0x2b8>) 8003c0e: f043 0301 orr.w r3, r3, #1 8003c12: 6193 str r3, [r2, #24] 8003c14: 4b4a ldr r3, [pc, #296] ; (8003d40 <HAL_GPIO_Init+0x2b8>) 8003c16: 699b ldr r3, [r3, #24] 8003c18: f003 0301 and.w r3, r3, #1 8003c1c: 60bb str r3, [r7, #8] 8003c1e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8003c20: 4a48 ldr r2, [pc, #288] ; (8003d44 <HAL_GPIO_Init+0x2bc>) 8003c22: 6a7b ldr r3, [r7, #36] ; 0x24 8003c24: 089b lsrs r3, r3, #2 8003c26: 3302 adds r3, #2 8003c28: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003c2c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8003c2e: 6a7b ldr r3, [r7, #36] ; 0x24 8003c30: f003 0303 and.w r3, r3, #3 8003c34: 009b lsls r3, r3, #2 8003c36: 220f movs r2, #15 8003c38: fa02 f303 lsl.w r3, r2, r3 8003c3c: 43db mvns r3, r3 8003c3e: 68fa ldr r2, [r7, #12] 8003c40: 4013 ands r3, r2 8003c42: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8003c44: 687b ldr r3, [r7, #4] 8003c46: 4a40 ldr r2, [pc, #256] ; (8003d48 <HAL_GPIO_Init+0x2c0>) 8003c48: 4293 cmp r3, r2 8003c4a: d013 beq.n 8003c74 <HAL_GPIO_Init+0x1ec> 8003c4c: 687b ldr r3, [r7, #4] 8003c4e: 4a3f ldr r2, [pc, #252] ; (8003d4c <HAL_GPIO_Init+0x2c4>) 8003c50: 4293 cmp r3, r2 8003c52: d00d beq.n 8003c70 <HAL_GPIO_Init+0x1e8> 8003c54: 687b ldr r3, [r7, #4] 8003c56: 4a3e ldr r2, [pc, #248] ; (8003d50 <HAL_GPIO_Init+0x2c8>) 8003c58: 4293 cmp r3, r2 8003c5a: d007 beq.n 8003c6c <HAL_GPIO_Init+0x1e4> 8003c5c: 687b ldr r3, [r7, #4] 8003c5e: 4a3d ldr r2, [pc, #244] ; (8003d54 <HAL_GPIO_Init+0x2cc>) 8003c60: 4293 cmp r3, r2 8003c62: d101 bne.n 8003c68 <HAL_GPIO_Init+0x1e0> 8003c64: 2303 movs r3, #3 8003c66: e006 b.n 8003c76 <HAL_GPIO_Init+0x1ee> 8003c68: 2304 movs r3, #4 8003c6a: e004 b.n 8003c76 <HAL_GPIO_Init+0x1ee> 8003c6c: 2302 movs r3, #2 8003c6e: e002 b.n 8003c76 <HAL_GPIO_Init+0x1ee> 8003c70: 2301 movs r3, #1 8003c72: e000 b.n 8003c76 <HAL_GPIO_Init+0x1ee> 8003c74: 2300 movs r3, #0 8003c76: 6a7a ldr r2, [r7, #36] ; 0x24 8003c78: f002 0203 and.w r2, r2, #3 8003c7c: 0092 lsls r2, r2, #2 8003c7e: 4093 lsls r3, r2 8003c80: 68fa ldr r2, [r7, #12] 8003c82: 4313 orrs r3, r2 8003c84: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8003c86: 492f ldr r1, [pc, #188] ; (8003d44 <HAL_GPIO_Init+0x2bc>) 8003c88: 6a7b ldr r3, [r7, #36] ; 0x24 8003c8a: 089b lsrs r3, r3, #2 8003c8c: 3302 adds r3, #2 8003c8e: 68fa ldr r2, [r7, #12] 8003c90: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8003c94: 683b ldr r3, [r7, #0] 8003c96: 685b ldr r3, [r3, #4] 8003c98: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8003c9c: 2b00 cmp r3, #0 8003c9e: d006 beq.n 8003cae <HAL_GPIO_Init+0x226> { SET_BIT(EXTI->RTSR, iocurrent); 8003ca0: 4b2d ldr r3, [pc, #180] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003ca2: 689a ldr r2, [r3, #8] 8003ca4: 492c ldr r1, [pc, #176] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003ca6: 69bb ldr r3, [r7, #24] 8003ca8: 4313 orrs r3, r2 8003caa: 608b str r3, [r1, #8] 8003cac: e006 b.n 8003cbc <HAL_GPIO_Init+0x234> } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8003cae: 4b2a ldr r3, [pc, #168] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cb0: 689a ldr r2, [r3, #8] 8003cb2: 69bb ldr r3, [r7, #24] 8003cb4: 43db mvns r3, r3 8003cb6: 4928 ldr r1, [pc, #160] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cb8: 4013 ands r3, r2 8003cba: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8003cbc: 683b ldr r3, [r7, #0] 8003cbe: 685b ldr r3, [r3, #4] 8003cc0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8003cc4: 2b00 cmp r3, #0 8003cc6: d006 beq.n 8003cd6 <HAL_GPIO_Init+0x24e> { SET_BIT(EXTI->FTSR, iocurrent); 8003cc8: 4b23 ldr r3, [pc, #140] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cca: 68da ldr r2, [r3, #12] 8003ccc: 4922 ldr r1, [pc, #136] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cce: 69bb ldr r3, [r7, #24] 8003cd0: 4313 orrs r3, r2 8003cd2: 60cb str r3, [r1, #12] 8003cd4: e006 b.n 8003ce4 <HAL_GPIO_Init+0x25c> } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8003cd6: 4b20 ldr r3, [pc, #128] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cd8: 68da ldr r2, [r3, #12] 8003cda: 69bb ldr r3, [r7, #24] 8003cdc: 43db mvns r3, r3 8003cde: 491e ldr r1, [pc, #120] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003ce0: 4013 ands r3, r2 8003ce2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8003ce4: 683b ldr r3, [r7, #0] 8003ce6: 685b ldr r3, [r3, #4] 8003ce8: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003cec: 2b00 cmp r3, #0 8003cee: d006 beq.n 8003cfe <HAL_GPIO_Init+0x276> { SET_BIT(EXTI->EMR, iocurrent); 8003cf0: 4b19 ldr r3, [pc, #100] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cf2: 685a ldr r2, [r3, #4] 8003cf4: 4918 ldr r1, [pc, #96] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003cf6: 69bb ldr r3, [r7, #24] 8003cf8: 4313 orrs r3, r2 8003cfa: 604b str r3, [r1, #4] 8003cfc: e006 b.n 8003d0c <HAL_GPIO_Init+0x284> } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8003cfe: 4b16 ldr r3, [pc, #88] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003d00: 685a ldr r2, [r3, #4] 8003d02: 69bb ldr r3, [r7, #24] 8003d04: 43db mvns r3, r3 8003d06: 4914 ldr r1, [pc, #80] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003d08: 4013 ands r3, r2 8003d0a: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8003d0c: 683b ldr r3, [r7, #0] 8003d0e: 685b ldr r3, [r3, #4] 8003d10: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003d14: 2b00 cmp r3, #0 8003d16: d021 beq.n 8003d5c <HAL_GPIO_Init+0x2d4> { SET_BIT(EXTI->IMR, iocurrent); 8003d18: 4b0f ldr r3, [pc, #60] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003d1a: 681a ldr r2, [r3, #0] 8003d1c: 490e ldr r1, [pc, #56] ; (8003d58 <HAL_GPIO_Init+0x2d0>) 8003d1e: 69bb ldr r3, [r7, #24] 8003d20: 4313 orrs r3, r2 8003d22: 600b str r3, [r1, #0] 8003d24: e021 b.n 8003d6a <HAL_GPIO_Init+0x2e2> 8003d26: bf00 nop 8003d28: 10320000 .word 0x10320000 8003d2c: 10310000 .word 0x10310000 8003d30: 10220000 .word 0x10220000 8003d34: 10210000 .word 0x10210000 8003d38: 10120000 .word 0x10120000 8003d3c: 10110000 .word 0x10110000 8003d40: 40021000 .word 0x40021000 8003d44: 40010000 .word 0x40010000 8003d48: 40010800 .word 0x40010800 8003d4c: 40010c00 .word 0x40010c00 8003d50: 40011000 .word 0x40011000 8003d54: 40011400 .word 0x40011400 8003d58: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8003d5c: 4b0b ldr r3, [pc, #44] ; (8003d8c <HAL_GPIO_Init+0x304>) 8003d5e: 681a ldr r2, [r3, #0] 8003d60: 69bb ldr r3, [r7, #24] 8003d62: 43db mvns r3, r3 8003d64: 4909 ldr r1, [pc, #36] ; (8003d8c <HAL_GPIO_Init+0x304>) 8003d66: 4013 ands r3, r2 8003d68: 600b str r3, [r1, #0] } } } position++; 8003d6a: 6a7b ldr r3, [r7, #36] ; 0x24 8003d6c: 3301 adds r3, #1 8003d6e: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8003d70: 683b ldr r3, [r7, #0] 8003d72: 681a ldr r2, [r3, #0] 8003d74: 6a7b ldr r3, [r7, #36] ; 0x24 8003d76: fa22 f303 lsr.w r3, r2, r3 8003d7a: 2b00 cmp r3, #0 8003d7c: f47f ae8e bne.w 8003a9c <HAL_GPIO_Init+0x14> } } 8003d80: bf00 nop 8003d82: bf00 nop 8003d84: 372c adds r7, #44 ; 0x2c 8003d86: 46bd mov sp, r7 8003d88: bc80 pop {r7} 8003d8a: 4770 bx lr 8003d8c: 40010400 .word 0x40010400 08003d90 <HAL_GPIO_ReadPin>: * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8003d90: b480 push {r7} 8003d92: b085 sub sp, #20 8003d94: af00 add r7, sp, #0 8003d96: 6078 str r0, [r7, #4] 8003d98: 460b mov r3, r1 8003d9a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8003d9c: 687b ldr r3, [r7, #4] 8003d9e: 689a ldr r2, [r3, #8] 8003da0: 887b ldrh r3, [r7, #2] 8003da2: 4013 ands r3, r2 8003da4: 2b00 cmp r3, #0 8003da6: d002 beq.n 8003dae <HAL_GPIO_ReadPin+0x1e> { bitstatus = GPIO_PIN_SET; 8003da8: 2301 movs r3, #1 8003daa: 73fb strb r3, [r7, #15] 8003dac: e001 b.n 8003db2 <HAL_GPIO_ReadPin+0x22> } else { bitstatus = GPIO_PIN_RESET; 8003dae: 2300 movs r3, #0 8003db0: 73fb strb r3, [r7, #15] } return bitstatus; 8003db2: 7bfb ldrb r3, [r7, #15] } 8003db4: 4618 mov r0, r3 8003db6: 3714 adds r7, #20 8003db8: 46bd mov sp, r7 8003dba: bc80 pop {r7} 8003dbc: 4770 bx lr 08003dbe <HAL_GPIO_WritePin>: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8003dbe: b480 push {r7} 8003dc0: b083 sub sp, #12 8003dc2: af00 add r7, sp, #0 8003dc4: 6078 str r0, [r7, #4] 8003dc6: 460b mov r3, r1 8003dc8: 807b strh r3, [r7, #2] 8003dca: 4613 mov r3, r2 8003dcc: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8003dce: 787b ldrb r3, [r7, #1] 8003dd0: 2b00 cmp r3, #0 8003dd2: d003 beq.n 8003ddc <HAL_GPIO_WritePin+0x1e> { GPIOx->BSRR = GPIO_Pin; 8003dd4: 887a ldrh r2, [r7, #2] 8003dd6: 687b ldr r3, [r7, #4] 8003dd8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8003dda: e003 b.n 8003de4 <HAL_GPIO_WritePin+0x26> GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8003ddc: 887b ldrh r3, [r7, #2] 8003dde: 041a lsls r2, r3, #16 8003de0: 687b ldr r3, [r7, #4] 8003de2: 611a str r2, [r3, #16] } 8003de4: bf00 nop 8003de6: 370c adds r7, #12 8003de8: 46bd mov sp, r7 8003dea: bc80 pop {r7} 8003dec: 4770 bx lr 08003dee <HAL_GPIO_TogglePin>: * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8003dee: b480 push {r7} 8003df0: b085 sub sp, #20 8003df2: af00 add r7, sp, #0 8003df4: 6078 str r0, [r7, #4] 8003df6: 460b mov r3, r1 8003df8: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8003dfa: 687b ldr r3, [r7, #4] 8003dfc: 68db ldr r3, [r3, #12] 8003dfe: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8003e00: 887a ldrh r2, [r7, #2] 8003e02: 68fb ldr r3, [r7, #12] 8003e04: 4013 ands r3, r2 8003e06: 041a lsls r2, r3, #16 8003e08: 68fb ldr r3, [r7, #12] 8003e0a: 43d9 mvns r1, r3 8003e0c: 887b ldrh r3, [r7, #2] 8003e0e: 400b ands r3, r1 8003e10: 431a orrs r2, r3 8003e12: 687b ldr r3, [r7, #4] 8003e14: 611a str r2, [r3, #16] } 8003e16: bf00 nop 8003e18: 3714 adds r7, #20 8003e1a: 46bd mov sp, r7 8003e1c: bc80 pop {r7} 8003e1e: 4770 bx lr 08003e20 <HAL_GPIO_EXTI_IRQHandler>: * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8003e20: b580 push {r7, lr} 8003e22: b082 sub sp, #8 8003e24: af00 add r7, sp, #0 8003e26: 4603 mov r3, r0 8003e28: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 8003e2a: 4b08 ldr r3, [pc, #32] ; (8003e4c <HAL_GPIO_EXTI_IRQHandler+0x2c>) 8003e2c: 695a ldr r2, [r3, #20] 8003e2e: 88fb ldrh r3, [r7, #6] 8003e30: 4013 ands r3, r2 8003e32: 2b00 cmp r3, #0 8003e34: d006 beq.n 8003e44 <HAL_GPIO_EXTI_IRQHandler+0x24> { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8003e36: 4a05 ldr r2, [pc, #20] ; (8003e4c <HAL_GPIO_EXTI_IRQHandler+0x2c>) 8003e38: 88fb ldrh r3, [r7, #6] 8003e3a: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8003e3c: 88fb ldrh r3, [r7, #6] 8003e3e: 4618 mov r0, r3 8003e40: f002 ffb4 bl 8006dac <HAL_GPIO_EXTI_Callback> } } 8003e44: bf00 nop 8003e46: 3708 adds r7, #8 8003e48: 46bd mov sp, r7 8003e4a: bd80 pop {r7, pc} 8003e4c: 40010400 .word 0x40010400 08003e50 <HAL_RCC_OscConfig>: * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003e50: b580 push {r7, lr} 8003e52: b086 sub sp, #24 8003e54: af00 add r7, sp, #0 8003e56: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003e58: 687b ldr r3, [r7, #4] 8003e5a: 2b00 cmp r3, #0 8003e5c: d101 bne.n 8003e62 <HAL_RCC_OscConfig+0x12> { return HAL_ERROR; 8003e5e: 2301 movs r3, #1 8003e60: e272 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003e62: 687b ldr r3, [r7, #4] 8003e64: 681b ldr r3, [r3, #0] 8003e66: f003 0301 and.w r3, r3, #1 8003e6a: 2b00 cmp r3, #0 8003e6c: f000 8087 beq.w 8003f7e <HAL_RCC_OscConfig+0x12e> { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8003e70: 4b92 ldr r3, [pc, #584] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003e72: 685b ldr r3, [r3, #4] 8003e74: f003 030c and.w r3, r3, #12 8003e78: 2b04 cmp r3, #4 8003e7a: d00c beq.n 8003e96 <HAL_RCC_OscConfig+0x46> || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8003e7c: 4b8f ldr r3, [pc, #572] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003e7e: 685b ldr r3, [r3, #4] 8003e80: f003 030c and.w r3, r3, #12 8003e84: 2b08 cmp r3, #8 8003e86: d112 bne.n 8003eae <HAL_RCC_OscConfig+0x5e> 8003e88: 4b8c ldr r3, [pc, #560] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003e8a: 685b ldr r3, [r3, #4] 8003e8c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003e90: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003e94: d10b bne.n 8003eae <HAL_RCC_OscConfig+0x5e> { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003e96: 4b89 ldr r3, [pc, #548] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003e98: 681b ldr r3, [r3, #0] 8003e9a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003e9e: 2b00 cmp r3, #0 8003ea0: d06c beq.n 8003f7c <HAL_RCC_OscConfig+0x12c> 8003ea2: 687b ldr r3, [r7, #4] 8003ea4: 685b ldr r3, [r3, #4] 8003ea6: 2b00 cmp r3, #0 8003ea8: d168 bne.n 8003f7c <HAL_RCC_OscConfig+0x12c> { return HAL_ERROR; 8003eaa: 2301 movs r3, #1 8003eac: e24c b.n 8004348 <HAL_RCC_OscConfig+0x4f8> } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 685b ldr r3, [r3, #4] 8003eb2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003eb6: d106 bne.n 8003ec6 <HAL_RCC_OscConfig+0x76> 8003eb8: 4b80 ldr r3, [pc, #512] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003eba: 681b ldr r3, [r3, #0] 8003ebc: 4a7f ldr r2, [pc, #508] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ebe: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003ec2: 6013 str r3, [r2, #0] 8003ec4: e02e b.n 8003f24 <HAL_RCC_OscConfig+0xd4> 8003ec6: 687b ldr r3, [r7, #4] 8003ec8: 685b ldr r3, [r3, #4] 8003eca: 2b00 cmp r3, #0 8003ecc: d10c bne.n 8003ee8 <HAL_RCC_OscConfig+0x98> 8003ece: 4b7b ldr r3, [pc, #492] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ed0: 681b ldr r3, [r3, #0] 8003ed2: 4a7a ldr r2, [pc, #488] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ed4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003ed8: 6013 str r3, [r2, #0] 8003eda: 4b78 ldr r3, [pc, #480] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003edc: 681b ldr r3, [r3, #0] 8003ede: 4a77 ldr r2, [pc, #476] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ee0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003ee4: 6013 str r3, [r2, #0] 8003ee6: e01d b.n 8003f24 <HAL_RCC_OscConfig+0xd4> 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 685b ldr r3, [r3, #4] 8003eec: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003ef0: d10c bne.n 8003f0c <HAL_RCC_OscConfig+0xbc> 8003ef2: 4b72 ldr r3, [pc, #456] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ef4: 681b ldr r3, [r3, #0] 8003ef6: 4a71 ldr r2, [pc, #452] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003ef8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003efc: 6013 str r3, [r2, #0] 8003efe: 4b6f ldr r3, [pc, #444] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f00: 681b ldr r3, [r3, #0] 8003f02: 4a6e ldr r2, [pc, #440] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f04: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003f08: 6013 str r3, [r2, #0] 8003f0a: e00b b.n 8003f24 <HAL_RCC_OscConfig+0xd4> 8003f0c: 4b6b ldr r3, [pc, #428] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f0e: 681b ldr r3, [r3, #0] 8003f10: 4a6a ldr r2, [pc, #424] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f12: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003f16: 6013 str r3, [r2, #0] 8003f18: 4b68 ldr r3, [pc, #416] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f1a: 681b ldr r3, [r3, #0] 8003f1c: 4a67 ldr r2, [pc, #412] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f1e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003f22: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003f24: 687b ldr r3, [r7, #4] 8003f26: 685b ldr r3, [r3, #4] 8003f28: 2b00 cmp r3, #0 8003f2a: d013 beq.n 8003f54 <HAL_RCC_OscConfig+0x104> { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003f2c: f7fe fe1a bl 8002b64 <HAL_GetTick> 8003f30: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003f32: e008 b.n 8003f46 <HAL_RCC_OscConfig+0xf6> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003f34: f7fe fe16 bl 8002b64 <HAL_GetTick> 8003f38: 4602 mov r2, r0 8003f3a: 693b ldr r3, [r7, #16] 8003f3c: 1ad3 subs r3, r2, r3 8003f3e: 2b64 cmp r3, #100 ; 0x64 8003f40: d901 bls.n 8003f46 <HAL_RCC_OscConfig+0xf6> { return HAL_TIMEOUT; 8003f42: 2303 movs r3, #3 8003f44: e200 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003f46: 4b5d ldr r3, [pc, #372] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f48: 681b ldr r3, [r3, #0] 8003f4a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003f4e: 2b00 cmp r3, #0 8003f50: d0f0 beq.n 8003f34 <HAL_RCC_OscConfig+0xe4> 8003f52: e014 b.n 8003f7e <HAL_RCC_OscConfig+0x12e> } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003f54: f7fe fe06 bl 8002b64 <HAL_GetTick> 8003f58: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8003f5a: e008 b.n 8003f6e <HAL_RCC_OscConfig+0x11e> { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003f5c: f7fe fe02 bl 8002b64 <HAL_GetTick> 8003f60: 4602 mov r2, r0 8003f62: 693b ldr r3, [r7, #16] 8003f64: 1ad3 subs r3, r2, r3 8003f66: 2b64 cmp r3, #100 ; 0x64 8003f68: d901 bls.n 8003f6e <HAL_RCC_OscConfig+0x11e> { return HAL_TIMEOUT; 8003f6a: 2303 movs r3, #3 8003f6c: e1ec b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8003f6e: 4b53 ldr r3, [pc, #332] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f70: 681b ldr r3, [r3, #0] 8003f72: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003f76: 2b00 cmp r3, #0 8003f78: d1f0 bne.n 8003f5c <HAL_RCC_OscConfig+0x10c> 8003f7a: e000 b.n 8003f7e <HAL_RCC_OscConfig+0x12e> if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003f7c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003f7e: 687b ldr r3, [r7, #4] 8003f80: 681b ldr r3, [r3, #0] 8003f82: f003 0302 and.w r3, r3, #2 8003f86: 2b00 cmp r3, #0 8003f88: d063 beq.n 8004052 <HAL_RCC_OscConfig+0x202> /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8003f8a: 4b4c ldr r3, [pc, #304] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f8c: 685b ldr r3, [r3, #4] 8003f8e: f003 030c and.w r3, r3, #12 8003f92: 2b00 cmp r3, #0 8003f94: d00b beq.n 8003fae <HAL_RCC_OscConfig+0x15e> || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8003f96: 4b49 ldr r3, [pc, #292] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003f98: 685b ldr r3, [r3, #4] 8003f9a: f003 030c and.w r3, r3, #12 8003f9e: 2b08 cmp r3, #8 8003fa0: d11c bne.n 8003fdc <HAL_RCC_OscConfig+0x18c> 8003fa2: 4b46 ldr r3, [pc, #280] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003fa4: 685b ldr r3, [r3, #4] 8003fa6: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003faa: 2b00 cmp r3, #0 8003fac: d116 bne.n 8003fdc <HAL_RCC_OscConfig+0x18c> { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8003fae: 4b43 ldr r3, [pc, #268] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003fb0: 681b ldr r3, [r3, #0] 8003fb2: f003 0302 and.w r3, r3, #2 8003fb6: 2b00 cmp r3, #0 8003fb8: d005 beq.n 8003fc6 <HAL_RCC_OscConfig+0x176> 8003fba: 687b ldr r3, [r7, #4] 8003fbc: 691b ldr r3, [r3, #16] 8003fbe: 2b01 cmp r3, #1 8003fc0: d001 beq.n 8003fc6 <HAL_RCC_OscConfig+0x176> { return HAL_ERROR; 8003fc2: 2301 movs r3, #1 8003fc4: e1c0 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003fc6: 4b3d ldr r3, [pc, #244] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003fc8: 681b ldr r3, [r3, #0] 8003fca: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003fce: 687b ldr r3, [r7, #4] 8003fd0: 695b ldr r3, [r3, #20] 8003fd2: 00db lsls r3, r3, #3 8003fd4: 4939 ldr r1, [pc, #228] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8003fd6: 4313 orrs r3, r2 8003fd8: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8003fda: e03a b.n 8004052 <HAL_RCC_OscConfig+0x202> } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003fdc: 687b ldr r3, [r7, #4] 8003fde: 691b ldr r3, [r3, #16] 8003fe0: 2b00 cmp r3, #0 8003fe2: d020 beq.n 8004026 <HAL_RCC_OscConfig+0x1d6> { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003fe4: 4b36 ldr r3, [pc, #216] ; (80040c0 <HAL_RCC_OscConfig+0x270>) 8003fe6: 2201 movs r2, #1 8003fe8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003fea: f7fe fdbb bl 8002b64 <HAL_GetTick> 8003fee: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003ff0: e008 b.n 8004004 <HAL_RCC_OscConfig+0x1b4> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003ff2: f7fe fdb7 bl 8002b64 <HAL_GetTick> 8003ff6: 4602 mov r2, r0 8003ff8: 693b ldr r3, [r7, #16] 8003ffa: 1ad3 subs r3, r2, r3 8003ffc: 2b02 cmp r3, #2 8003ffe: d901 bls.n 8004004 <HAL_RCC_OscConfig+0x1b4> { return HAL_TIMEOUT; 8004000: 2303 movs r3, #3 8004002: e1a1 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004004: 4b2d ldr r3, [pc, #180] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8004006: 681b ldr r3, [r3, #0] 8004008: f003 0302 and.w r3, r3, #2 800400c: 2b00 cmp r3, #0 800400e: d0f0 beq.n 8003ff2 <HAL_RCC_OscConfig+0x1a2> } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004010: 4b2a ldr r3, [pc, #168] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8004012: 681b ldr r3, [r3, #0] 8004014: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8004018: 687b ldr r3, [r7, #4] 800401a: 695b ldr r3, [r3, #20] 800401c: 00db lsls r3, r3, #3 800401e: 4927 ldr r1, [pc, #156] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8004020: 4313 orrs r3, r2 8004022: 600b str r3, [r1, #0] 8004024: e015 b.n 8004052 <HAL_RCC_OscConfig+0x202> } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004026: 4b26 ldr r3, [pc, #152] ; (80040c0 <HAL_RCC_OscConfig+0x270>) 8004028: 2200 movs r2, #0 800402a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800402c: f7fe fd9a bl 8002b64 <HAL_GetTick> 8004030: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004032: e008 b.n 8004046 <HAL_RCC_OscConfig+0x1f6> { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004034: f7fe fd96 bl 8002b64 <HAL_GetTick> 8004038: 4602 mov r2, r0 800403a: 693b ldr r3, [r7, #16] 800403c: 1ad3 subs r3, r2, r3 800403e: 2b02 cmp r3, #2 8004040: d901 bls.n 8004046 <HAL_RCC_OscConfig+0x1f6> { return HAL_TIMEOUT; 8004042: 2303 movs r3, #3 8004044: e180 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004046: 4b1d ldr r3, [pc, #116] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8004048: 681b ldr r3, [r3, #0] 800404a: f003 0302 and.w r3, r3, #2 800404e: 2b00 cmp r3, #0 8004050: d1f0 bne.n 8004034 <HAL_RCC_OscConfig+0x1e4> } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004052: 687b ldr r3, [r7, #4] 8004054: 681b ldr r3, [r3, #0] 8004056: f003 0308 and.w r3, r3, #8 800405a: 2b00 cmp r3, #0 800405c: d03a beq.n 80040d4 <HAL_RCC_OscConfig+0x284> { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800405e: 687b ldr r3, [r7, #4] 8004060: 699b ldr r3, [r3, #24] 8004062: 2b00 cmp r3, #0 8004064: d019 beq.n 800409a <HAL_RCC_OscConfig+0x24a> { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004066: 4b17 ldr r3, [pc, #92] ; (80040c4 <HAL_RCC_OscConfig+0x274>) 8004068: 2201 movs r2, #1 800406a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800406c: f7fe fd7a bl 8002b64 <HAL_GetTick> 8004070: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004072: e008 b.n 8004086 <HAL_RCC_OscConfig+0x236> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004074: f7fe fd76 bl 8002b64 <HAL_GetTick> 8004078: 4602 mov r2, r0 800407a: 693b ldr r3, [r7, #16] 800407c: 1ad3 subs r3, r2, r3 800407e: 2b02 cmp r3, #2 8004080: d901 bls.n 8004086 <HAL_RCC_OscConfig+0x236> { return HAL_TIMEOUT; 8004082: 2303 movs r3, #3 8004084: e160 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004086: 4b0d ldr r3, [pc, #52] ; (80040bc <HAL_RCC_OscConfig+0x26c>) 8004088: 6a5b ldr r3, [r3, #36] ; 0x24 800408a: f003 0302 and.w r3, r3, #2 800408e: 2b00 cmp r3, #0 8004090: d0f0 beq.n 8004074 <HAL_RCC_OscConfig+0x224> } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8004092: 2001 movs r0, #1 8004094: f000 fad0 bl 8004638 <RCC_Delay> 8004098: e01c b.n 80040d4 <HAL_RCC_OscConfig+0x284> } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800409a: 4b0a ldr r3, [pc, #40] ; (80040c4 <HAL_RCC_OscConfig+0x274>) 800409c: 2200 movs r2, #0 800409e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80040a0: f7fe fd60 bl 8002b64 <HAL_GetTick> 80040a4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80040a6: e00f b.n 80040c8 <HAL_RCC_OscConfig+0x278> { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80040a8: f7fe fd5c bl 8002b64 <HAL_GetTick> 80040ac: 4602 mov r2, r0 80040ae: 693b ldr r3, [r7, #16] 80040b0: 1ad3 subs r3, r2, r3 80040b2: 2b02 cmp r3, #2 80040b4: d908 bls.n 80040c8 <HAL_RCC_OscConfig+0x278> { return HAL_TIMEOUT; 80040b6: 2303 movs r3, #3 80040b8: e146 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> 80040ba: bf00 nop 80040bc: 40021000 .word 0x40021000 80040c0: 42420000 .word 0x42420000 80040c4: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80040c8: 4b92 ldr r3, [pc, #584] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80040ca: 6a5b ldr r3, [r3, #36] ; 0x24 80040cc: f003 0302 and.w r3, r3, #2 80040d0: 2b00 cmp r3, #0 80040d2: d1e9 bne.n 80040a8 <HAL_RCC_OscConfig+0x258> } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80040d4: 687b ldr r3, [r7, #4] 80040d6: 681b ldr r3, [r3, #0] 80040d8: f003 0304 and.w r3, r3, #4 80040dc: 2b00 cmp r3, #0 80040de: f000 80a6 beq.w 800422e <HAL_RCC_OscConfig+0x3de> { FlagStatus pwrclkchanged = RESET; 80040e2: 2300 movs r3, #0 80040e4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80040e6: 4b8b ldr r3, [pc, #556] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80040e8: 69db ldr r3, [r3, #28] 80040ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80040ee: 2b00 cmp r3, #0 80040f0: d10d bne.n 800410e <HAL_RCC_OscConfig+0x2be> { __HAL_RCC_PWR_CLK_ENABLE(); 80040f2: 4b88 ldr r3, [pc, #544] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80040f4: 69db ldr r3, [r3, #28] 80040f6: 4a87 ldr r2, [pc, #540] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80040f8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80040fc: 61d3 str r3, [r2, #28] 80040fe: 4b85 ldr r3, [pc, #532] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004100: 69db ldr r3, [r3, #28] 8004102: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004106: 60bb str r3, [r7, #8] 8004108: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800410a: 2301 movs r3, #1 800410c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800410e: 4b82 ldr r3, [pc, #520] ; (8004318 <HAL_RCC_OscConfig+0x4c8>) 8004110: 681b ldr r3, [r3, #0] 8004112: f403 7380 and.w r3, r3, #256 ; 0x100 8004116: 2b00 cmp r3, #0 8004118: d118 bne.n 800414c <HAL_RCC_OscConfig+0x2fc> { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800411a: 4b7f ldr r3, [pc, #508] ; (8004318 <HAL_RCC_OscConfig+0x4c8>) 800411c: 681b ldr r3, [r3, #0] 800411e: 4a7e ldr r2, [pc, #504] ; (8004318 <HAL_RCC_OscConfig+0x4c8>) 8004120: f443 7380 orr.w r3, r3, #256 ; 0x100 8004124: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004126: f7fe fd1d bl 8002b64 <HAL_GetTick> 800412a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800412c: e008 b.n 8004140 <HAL_RCC_OscConfig+0x2f0> { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800412e: f7fe fd19 bl 8002b64 <HAL_GetTick> 8004132: 4602 mov r2, r0 8004134: 693b ldr r3, [r7, #16] 8004136: 1ad3 subs r3, r2, r3 8004138: 2b64 cmp r3, #100 ; 0x64 800413a: d901 bls.n 8004140 <HAL_RCC_OscConfig+0x2f0> { return HAL_TIMEOUT; 800413c: 2303 movs r3, #3 800413e: e103 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004140: 4b75 ldr r3, [pc, #468] ; (8004318 <HAL_RCC_OscConfig+0x4c8>) 8004142: 681b ldr r3, [r3, #0] 8004144: f403 7380 and.w r3, r3, #256 ; 0x100 8004148: 2b00 cmp r3, #0 800414a: d0f0 beq.n 800412e <HAL_RCC_OscConfig+0x2de> } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800414c: 687b ldr r3, [r7, #4] 800414e: 68db ldr r3, [r3, #12] 8004150: 2b01 cmp r3, #1 8004152: d106 bne.n 8004162 <HAL_RCC_OscConfig+0x312> 8004154: 4b6f ldr r3, [pc, #444] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004156: 6a1b ldr r3, [r3, #32] 8004158: 4a6e ldr r2, [pc, #440] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800415a: f043 0301 orr.w r3, r3, #1 800415e: 6213 str r3, [r2, #32] 8004160: e02d b.n 80041be <HAL_RCC_OscConfig+0x36e> 8004162: 687b ldr r3, [r7, #4] 8004164: 68db ldr r3, [r3, #12] 8004166: 2b00 cmp r3, #0 8004168: d10c bne.n 8004184 <HAL_RCC_OscConfig+0x334> 800416a: 4b6a ldr r3, [pc, #424] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800416c: 6a1b ldr r3, [r3, #32] 800416e: 4a69 ldr r2, [pc, #420] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004170: f023 0301 bic.w r3, r3, #1 8004174: 6213 str r3, [r2, #32] 8004176: 4b67 ldr r3, [pc, #412] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004178: 6a1b ldr r3, [r3, #32] 800417a: 4a66 ldr r2, [pc, #408] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800417c: f023 0304 bic.w r3, r3, #4 8004180: 6213 str r3, [r2, #32] 8004182: e01c b.n 80041be <HAL_RCC_OscConfig+0x36e> 8004184: 687b ldr r3, [r7, #4] 8004186: 68db ldr r3, [r3, #12] 8004188: 2b05 cmp r3, #5 800418a: d10c bne.n 80041a6 <HAL_RCC_OscConfig+0x356> 800418c: 4b61 ldr r3, [pc, #388] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800418e: 6a1b ldr r3, [r3, #32] 8004190: 4a60 ldr r2, [pc, #384] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004192: f043 0304 orr.w r3, r3, #4 8004196: 6213 str r3, [r2, #32] 8004198: 4b5e ldr r3, [pc, #376] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800419a: 6a1b ldr r3, [r3, #32] 800419c: 4a5d ldr r2, [pc, #372] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800419e: f043 0301 orr.w r3, r3, #1 80041a2: 6213 str r3, [r2, #32] 80041a4: e00b b.n 80041be <HAL_RCC_OscConfig+0x36e> 80041a6: 4b5b ldr r3, [pc, #364] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80041a8: 6a1b ldr r3, [r3, #32] 80041aa: 4a5a ldr r2, [pc, #360] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80041ac: f023 0301 bic.w r3, r3, #1 80041b0: 6213 str r3, [r2, #32] 80041b2: 4b58 ldr r3, [pc, #352] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80041b4: 6a1b ldr r3, [r3, #32] 80041b6: 4a57 ldr r2, [pc, #348] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80041b8: f023 0304 bic.w r3, r3, #4 80041bc: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80041be: 687b ldr r3, [r7, #4] 80041c0: 68db ldr r3, [r3, #12] 80041c2: 2b00 cmp r3, #0 80041c4: d015 beq.n 80041f2 <HAL_RCC_OscConfig+0x3a2> { /* Get Start Tick */ tickstart = HAL_GetTick(); 80041c6: f7fe fccd bl 8002b64 <HAL_GetTick> 80041ca: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80041cc: e00a b.n 80041e4 <HAL_RCC_OscConfig+0x394> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80041ce: f7fe fcc9 bl 8002b64 <HAL_GetTick> 80041d2: 4602 mov r2, r0 80041d4: 693b ldr r3, [r7, #16] 80041d6: 1ad3 subs r3, r2, r3 80041d8: f241 3288 movw r2, #5000 ; 0x1388 80041dc: 4293 cmp r3, r2 80041de: d901 bls.n 80041e4 <HAL_RCC_OscConfig+0x394> { return HAL_TIMEOUT; 80041e0: 2303 movs r3, #3 80041e2: e0b1 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80041e4: 4b4b ldr r3, [pc, #300] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80041e6: 6a1b ldr r3, [r3, #32] 80041e8: f003 0302 and.w r3, r3, #2 80041ec: 2b00 cmp r3, #0 80041ee: d0ee beq.n 80041ce <HAL_RCC_OscConfig+0x37e> 80041f0: e014 b.n 800421c <HAL_RCC_OscConfig+0x3cc> } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80041f2: f7fe fcb7 bl 8002b64 <HAL_GetTick> 80041f6: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80041f8: e00a b.n 8004210 <HAL_RCC_OscConfig+0x3c0> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80041fa: f7fe fcb3 bl 8002b64 <HAL_GetTick> 80041fe: 4602 mov r2, r0 8004200: 693b ldr r3, [r7, #16] 8004202: 1ad3 subs r3, r2, r3 8004204: f241 3288 movw r2, #5000 ; 0x1388 8004208: 4293 cmp r3, r2 800420a: d901 bls.n 8004210 <HAL_RCC_OscConfig+0x3c0> { return HAL_TIMEOUT; 800420c: 2303 movs r3, #3 800420e: e09b b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004210: 4b40 ldr r3, [pc, #256] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004212: 6a1b ldr r3, [r3, #32] 8004214: f003 0302 and.w r3, r3, #2 8004218: 2b00 cmp r3, #0 800421a: d1ee bne.n 80041fa <HAL_RCC_OscConfig+0x3aa> } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800421c: 7dfb ldrb r3, [r7, #23] 800421e: 2b01 cmp r3, #1 8004220: d105 bne.n 800422e <HAL_RCC_OscConfig+0x3de> { __HAL_RCC_PWR_CLK_DISABLE(); 8004222: 4b3c ldr r3, [pc, #240] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004224: 69db ldr r3, [r3, #28] 8004226: 4a3b ldr r2, [pc, #236] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004228: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800422c: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800422e: 687b ldr r3, [r7, #4] 8004230: 69db ldr r3, [r3, #28] 8004232: 2b00 cmp r3, #0 8004234: f000 8087 beq.w 8004346 <HAL_RCC_OscConfig+0x4f6> { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8004238: 4b36 ldr r3, [pc, #216] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800423a: 685b ldr r3, [r3, #4] 800423c: f003 030c and.w r3, r3, #12 8004240: 2b08 cmp r3, #8 8004242: d061 beq.n 8004308 <HAL_RCC_OscConfig+0x4b8> { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004244: 687b ldr r3, [r7, #4] 8004246: 69db ldr r3, [r3, #28] 8004248: 2b02 cmp r3, #2 800424a: d146 bne.n 80042da <HAL_RCC_OscConfig+0x48a> /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800424c: 4b33 ldr r3, [pc, #204] ; (800431c <HAL_RCC_OscConfig+0x4cc>) 800424e: 2200 movs r2, #0 8004250: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004252: f7fe fc87 bl 8002b64 <HAL_GetTick> 8004256: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004258: e008 b.n 800426c <HAL_RCC_OscConfig+0x41c> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800425a: f7fe fc83 bl 8002b64 <HAL_GetTick> 800425e: 4602 mov r2, r0 8004260: 693b ldr r3, [r7, #16] 8004262: 1ad3 subs r3, r2, r3 8004264: 2b02 cmp r3, #2 8004266: d901 bls.n 800426c <HAL_RCC_OscConfig+0x41c> { return HAL_TIMEOUT; 8004268: 2303 movs r3, #3 800426a: e06d b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800426c: 4b29 ldr r3, [pc, #164] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 800426e: 681b ldr r3, [r3, #0] 8004270: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004274: 2b00 cmp r3, #0 8004276: d1f0 bne.n 800425a <HAL_RCC_OscConfig+0x40a> } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8004278: 687b ldr r3, [r7, #4] 800427a: 6a1b ldr r3, [r3, #32] 800427c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004280: d108 bne.n 8004294 <HAL_RCC_OscConfig+0x444> /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8004282: 4b24 ldr r3, [pc, #144] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004284: 685b ldr r3, [r3, #4] 8004286: f423 3200 bic.w r2, r3, #131072 ; 0x20000 800428a: 687b ldr r3, [r7, #4] 800428c: 689b ldr r3, [r3, #8] 800428e: 4921 ldr r1, [pc, #132] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004290: 4313 orrs r3, r2 8004292: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8004294: 4b1f ldr r3, [pc, #124] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 8004296: 685b ldr r3, [r3, #4] 8004298: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 800429c: 687b ldr r3, [r7, #4] 800429e: 6a19 ldr r1, [r3, #32] 80042a0: 687b ldr r3, [r7, #4] 80042a2: 6a5b ldr r3, [r3, #36] ; 0x24 80042a4: 430b orrs r3, r1 80042a6: 491b ldr r1, [pc, #108] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80042a8: 4313 orrs r3, r2 80042aa: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80042ac: 4b1b ldr r3, [pc, #108] ; (800431c <HAL_RCC_OscConfig+0x4cc>) 80042ae: 2201 movs r2, #1 80042b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80042b2: f7fe fc57 bl 8002b64 <HAL_GetTick> 80042b6: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80042b8: e008 b.n 80042cc <HAL_RCC_OscConfig+0x47c> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80042ba: f7fe fc53 bl 8002b64 <HAL_GetTick> 80042be: 4602 mov r2, r0 80042c0: 693b ldr r3, [r7, #16] 80042c2: 1ad3 subs r3, r2, r3 80042c4: 2b02 cmp r3, #2 80042c6: d901 bls.n 80042cc <HAL_RCC_OscConfig+0x47c> { return HAL_TIMEOUT; 80042c8: 2303 movs r3, #3 80042ca: e03d b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80042cc: 4b11 ldr r3, [pc, #68] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80042ce: 681b ldr r3, [r3, #0] 80042d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80042d4: 2b00 cmp r3, #0 80042d6: d0f0 beq.n 80042ba <HAL_RCC_OscConfig+0x46a> 80042d8: e035 b.n 8004346 <HAL_RCC_OscConfig+0x4f6> } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80042da: 4b10 ldr r3, [pc, #64] ; (800431c <HAL_RCC_OscConfig+0x4cc>) 80042dc: 2200 movs r2, #0 80042de: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80042e0: f7fe fc40 bl 8002b64 <HAL_GetTick> 80042e4: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80042e6: e008 b.n 80042fa <HAL_RCC_OscConfig+0x4aa> { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80042e8: f7fe fc3c bl 8002b64 <HAL_GetTick> 80042ec: 4602 mov r2, r0 80042ee: 693b ldr r3, [r7, #16] 80042f0: 1ad3 subs r3, r2, r3 80042f2: 2b02 cmp r3, #2 80042f4: d901 bls.n 80042fa <HAL_RCC_OscConfig+0x4aa> { return HAL_TIMEOUT; 80042f6: 2303 movs r3, #3 80042f8: e026 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80042fa: 4b06 ldr r3, [pc, #24] ; (8004314 <HAL_RCC_OscConfig+0x4c4>) 80042fc: 681b ldr r3, [r3, #0] 80042fe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004302: 2b00 cmp r3, #0 8004304: d1f0 bne.n 80042e8 <HAL_RCC_OscConfig+0x498> 8004306: e01e b.n 8004346 <HAL_RCC_OscConfig+0x4f6> } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8004308: 687b ldr r3, [r7, #4] 800430a: 69db ldr r3, [r3, #28] 800430c: 2b01 cmp r3, #1 800430e: d107 bne.n 8004320 <HAL_RCC_OscConfig+0x4d0> { return HAL_ERROR; 8004310: 2301 movs r3, #1 8004312: e019 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> 8004314: 40021000 .word 0x40021000 8004318: 40007000 .word 0x40007000 800431c: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8004320: 4b0b ldr r3, [pc, #44] ; (8004350 <HAL_RCC_OscConfig+0x500>) 8004322: 685b ldr r3, [r3, #4] 8004324: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004326: 68fb ldr r3, [r7, #12] 8004328: f403 3280 and.w r2, r3, #65536 ; 0x10000 800432c: 687b ldr r3, [r7, #4] 800432e: 6a1b ldr r3, [r3, #32] 8004330: 429a cmp r2, r3 8004332: d106 bne.n 8004342 <HAL_RCC_OscConfig+0x4f2> (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8004334: 68fb ldr r3, [r7, #12] 8004336: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 800433a: 687b ldr r3, [r7, #4] 800433c: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800433e: 429a cmp r2, r3 8004340: d001 beq.n 8004346 <HAL_RCC_OscConfig+0x4f6> { return HAL_ERROR; 8004342: 2301 movs r3, #1 8004344: e000 b.n 8004348 <HAL_RCC_OscConfig+0x4f8> } } } } return HAL_OK; 8004346: 2300 movs r3, #0 } 8004348: 4618 mov r0, r3 800434a: 3718 adds r7, #24 800434c: 46bd mov sp, r7 800434e: bd80 pop {r7, pc} 8004350: 40021000 .word 0x40021000 08004354 <HAL_RCC_ClockConfig>: * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004354: b580 push {r7, lr} 8004356: b084 sub sp, #16 8004358: af00 add r7, sp, #0 800435a: 6078 str r0, [r7, #4] 800435c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800435e: 687b ldr r3, [r7, #4] 8004360: 2b00 cmp r3, #0 8004362: d101 bne.n 8004368 <HAL_RCC_ClockConfig+0x14> { return HAL_ERROR; 8004364: 2301 movs r3, #1 8004366: e0d0 b.n 800450a <HAL_RCC_ClockConfig+0x1b6> must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004368: 4b6a ldr r3, [pc, #424] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 800436a: 681b ldr r3, [r3, #0] 800436c: f003 0307 and.w r3, r3, #7 8004370: 683a ldr r2, [r7, #0] 8004372: 429a cmp r2, r3 8004374: d910 bls.n 8004398 <HAL_RCC_ClockConfig+0x44> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004376: 4b67 ldr r3, [pc, #412] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004378: 681b ldr r3, [r3, #0] 800437a: f023 0207 bic.w r2, r3, #7 800437e: 4965 ldr r1, [pc, #404] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004380: 683b ldr r3, [r7, #0] 8004382: 4313 orrs r3, r2 8004384: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004386: 4b63 ldr r3, [pc, #396] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004388: 681b ldr r3, [r3, #0] 800438a: f003 0307 and.w r3, r3, #7 800438e: 683a ldr r2, [r7, #0] 8004390: 429a cmp r2, r3 8004392: d001 beq.n 8004398 <HAL_RCC_ClockConfig+0x44> { return HAL_ERROR; 8004394: 2301 movs r3, #1 8004396: e0b8 b.n 800450a <HAL_RCC_ClockConfig+0x1b6> } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004398: 687b ldr r3, [r7, #4] 800439a: 681b ldr r3, [r3, #0] 800439c: f003 0302 and.w r3, r3, #2 80043a0: 2b00 cmp r3, #0 80043a2: d020 beq.n 80043e6 <HAL_RCC_ClockConfig+0x92> { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80043a4: 687b ldr r3, [r7, #4] 80043a6: 681b ldr r3, [r3, #0] 80043a8: f003 0304 and.w r3, r3, #4 80043ac: 2b00 cmp r3, #0 80043ae: d005 beq.n 80043bc <HAL_RCC_ClockConfig+0x68> { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80043b0: 4b59 ldr r3, [pc, #356] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043b2: 685b ldr r3, [r3, #4] 80043b4: 4a58 ldr r2, [pc, #352] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043b6: f443 63e0 orr.w r3, r3, #1792 ; 0x700 80043ba: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80043bc: 687b ldr r3, [r7, #4] 80043be: 681b ldr r3, [r3, #0] 80043c0: f003 0308 and.w r3, r3, #8 80043c4: 2b00 cmp r3, #0 80043c6: d005 beq.n 80043d4 <HAL_RCC_ClockConfig+0x80> { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80043c8: 4b53 ldr r3, [pc, #332] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043ca: 685b ldr r3, [r3, #4] 80043cc: 4a52 ldr r2, [pc, #328] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043ce: f443 5360 orr.w r3, r3, #14336 ; 0x3800 80043d2: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80043d4: 4b50 ldr r3, [pc, #320] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043d6: 685b ldr r3, [r3, #4] 80043d8: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80043dc: 687b ldr r3, [r7, #4] 80043de: 689b ldr r3, [r3, #8] 80043e0: 494d ldr r1, [pc, #308] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043e2: 4313 orrs r3, r2 80043e4: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80043e6: 687b ldr r3, [r7, #4] 80043e8: 681b ldr r3, [r3, #0] 80043ea: f003 0301 and.w r3, r3, #1 80043ee: 2b00 cmp r3, #0 80043f0: d040 beq.n 8004474 <HAL_RCC_ClockConfig+0x120> { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80043f2: 687b ldr r3, [r7, #4] 80043f4: 685b ldr r3, [r3, #4] 80043f6: 2b01 cmp r3, #1 80043f8: d107 bne.n 800440a <HAL_RCC_ClockConfig+0xb6> { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80043fa: 4b47 ldr r3, [pc, #284] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80043fc: 681b ldr r3, [r3, #0] 80043fe: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004402: 2b00 cmp r3, #0 8004404: d115 bne.n 8004432 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 8004406: 2301 movs r3, #1 8004408: e07f b.n 800450a <HAL_RCC_ClockConfig+0x1b6> } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800440a: 687b ldr r3, [r7, #4] 800440c: 685b ldr r3, [r3, #4] 800440e: 2b02 cmp r3, #2 8004410: d107 bne.n 8004422 <HAL_RCC_ClockConfig+0xce> { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004412: 4b41 ldr r3, [pc, #260] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 8004414: 681b ldr r3, [r3, #0] 8004416: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800441a: 2b00 cmp r3, #0 800441c: d109 bne.n 8004432 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 800441e: 2301 movs r3, #1 8004420: e073 b.n 800450a <HAL_RCC_ClockConfig+0x1b6> } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004422: 4b3d ldr r3, [pc, #244] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 8004424: 681b ldr r3, [r3, #0] 8004426: f003 0302 and.w r3, r3, #2 800442a: 2b00 cmp r3, #0 800442c: d101 bne.n 8004432 <HAL_RCC_ClockConfig+0xde> { return HAL_ERROR; 800442e: 2301 movs r3, #1 8004430: e06b b.n 800450a <HAL_RCC_ClockConfig+0x1b6> } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004432: 4b39 ldr r3, [pc, #228] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 8004434: 685b ldr r3, [r3, #4] 8004436: f023 0203 bic.w r2, r3, #3 800443a: 687b ldr r3, [r7, #4] 800443c: 685b ldr r3, [r3, #4] 800443e: 4936 ldr r1, [pc, #216] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 8004440: 4313 orrs r3, r2 8004442: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004444: f7fe fb8e bl 8002b64 <HAL_GetTick> 8004448: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800444a: e00a b.n 8004462 <HAL_RCC_ClockConfig+0x10e> { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800444c: f7fe fb8a bl 8002b64 <HAL_GetTick> 8004450: 4602 mov r2, r0 8004452: 68fb ldr r3, [r7, #12] 8004454: 1ad3 subs r3, r2, r3 8004456: f241 3288 movw r2, #5000 ; 0x1388 800445a: 4293 cmp r3, r2 800445c: d901 bls.n 8004462 <HAL_RCC_ClockConfig+0x10e> { return HAL_TIMEOUT; 800445e: 2303 movs r3, #3 8004460: e053 b.n 800450a <HAL_RCC_ClockConfig+0x1b6> while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004462: 4b2d ldr r3, [pc, #180] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 8004464: 685b ldr r3, [r3, #4] 8004466: f003 020c and.w r2, r3, #12 800446a: 687b ldr r3, [r7, #4] 800446c: 685b ldr r3, [r3, #4] 800446e: 009b lsls r3, r3, #2 8004470: 429a cmp r2, r3 8004472: d1eb bne.n 800444c <HAL_RCC_ClockConfig+0xf8> } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004474: 4b27 ldr r3, [pc, #156] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004476: 681b ldr r3, [r3, #0] 8004478: f003 0307 and.w r3, r3, #7 800447c: 683a ldr r2, [r7, #0] 800447e: 429a cmp r2, r3 8004480: d210 bcs.n 80044a4 <HAL_RCC_ClockConfig+0x150> { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004482: 4b24 ldr r3, [pc, #144] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004484: 681b ldr r3, [r3, #0] 8004486: f023 0207 bic.w r2, r3, #7 800448a: 4922 ldr r1, [pc, #136] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 800448c: 683b ldr r3, [r7, #0] 800448e: 4313 orrs r3, r2 8004490: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004492: 4b20 ldr r3, [pc, #128] ; (8004514 <HAL_RCC_ClockConfig+0x1c0>) 8004494: 681b ldr r3, [r3, #0] 8004496: f003 0307 and.w r3, r3, #7 800449a: 683a ldr r2, [r7, #0] 800449c: 429a cmp r2, r3 800449e: d001 beq.n 80044a4 <HAL_RCC_ClockConfig+0x150> { return HAL_ERROR; 80044a0: 2301 movs r3, #1 80044a2: e032 b.n 800450a <HAL_RCC_ClockConfig+0x1b6> } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80044a4: 687b ldr r3, [r7, #4] 80044a6: 681b ldr r3, [r3, #0] 80044a8: f003 0304 and.w r3, r3, #4 80044ac: 2b00 cmp r3, #0 80044ae: d008 beq.n 80044c2 <HAL_RCC_ClockConfig+0x16e> { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80044b0: 4b19 ldr r3, [pc, #100] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80044b2: 685b ldr r3, [r3, #4] 80044b4: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80044b8: 687b ldr r3, [r7, #4] 80044ba: 68db ldr r3, [r3, #12] 80044bc: 4916 ldr r1, [pc, #88] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80044be: 4313 orrs r3, r2 80044c0: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80044c2: 687b ldr r3, [r7, #4] 80044c4: 681b ldr r3, [r3, #0] 80044c6: f003 0308 and.w r3, r3, #8 80044ca: 2b00 cmp r3, #0 80044cc: d009 beq.n 80044e2 <HAL_RCC_ClockConfig+0x18e> { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80044ce: 4b12 ldr r3, [pc, #72] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80044d0: 685b ldr r3, [r3, #4] 80044d2: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80044d6: 687b ldr r3, [r7, #4] 80044d8: 691b ldr r3, [r3, #16] 80044da: 00db lsls r3, r3, #3 80044dc: 490e ldr r1, [pc, #56] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80044de: 4313 orrs r3, r2 80044e0: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80044e2: f000 f821 bl 8004528 <HAL_RCC_GetSysClockFreq> 80044e6: 4602 mov r2, r0 80044e8: 4b0b ldr r3, [pc, #44] ; (8004518 <HAL_RCC_ClockConfig+0x1c4>) 80044ea: 685b ldr r3, [r3, #4] 80044ec: 091b lsrs r3, r3, #4 80044ee: f003 030f and.w r3, r3, #15 80044f2: 490a ldr r1, [pc, #40] ; (800451c <HAL_RCC_ClockConfig+0x1c8>) 80044f4: 5ccb ldrb r3, [r1, r3] 80044f6: fa22 f303 lsr.w r3, r2, r3 80044fa: 4a09 ldr r2, [pc, #36] ; (8004520 <HAL_RCC_ClockConfig+0x1cc>) 80044fc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80044fe: 4b09 ldr r3, [pc, #36] ; (8004524 <HAL_RCC_ClockConfig+0x1d0>) 8004500: 681b ldr r3, [r3, #0] 8004502: 4618 mov r0, r3 8004504: f7fe faec bl 8002ae0 <HAL_InitTick> return HAL_OK; 8004508: 2300 movs r3, #0 } 800450a: 4618 mov r0, r3 800450c: 3710 adds r7, #16 800450e: 46bd mov sp, r7 8004510: bd80 pop {r7, pc} 8004512: bf00 nop 8004514: 40022000 .word 0x40022000 8004518: 40021000 .word 0x40021000 800451c: 08008618 .word 0x08008618 8004520: 20000008 .word 0x20000008 8004524: 2000000c .word 0x2000000c 08004528 <HAL_RCC_GetSysClockFreq>: * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004528: b480 push {r7} 800452a: b087 sub sp, #28 800452c: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800452e: 2300 movs r3, #0 8004530: 60fb str r3, [r7, #12] 8004532: 2300 movs r3, #0 8004534: 60bb str r3, [r7, #8] 8004536: 2300 movs r3, #0 8004538: 617b str r3, [r7, #20] 800453a: 2300 movs r3, #0 800453c: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 800453e: 2300 movs r3, #0 8004540: 613b str r3, [r7, #16] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8004542: 4b1e ldr r3, [pc, #120] ; (80045bc <HAL_RCC_GetSysClockFreq+0x94>) 8004544: 685b ldr r3, [r3, #4] 8004546: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8004548: 68fb ldr r3, [r7, #12] 800454a: f003 030c and.w r3, r3, #12 800454e: 2b04 cmp r3, #4 8004550: d002 beq.n 8004558 <HAL_RCC_GetSysClockFreq+0x30> 8004552: 2b08 cmp r3, #8 8004554: d003 beq.n 800455e <HAL_RCC_GetSysClockFreq+0x36> 8004556: e027 b.n 80045a8 <HAL_RCC_GetSysClockFreq+0x80> { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8004558: 4b19 ldr r3, [pc, #100] ; (80045c0 <HAL_RCC_GetSysClockFreq+0x98>) 800455a: 613b str r3, [r7, #16] break; 800455c: e027 b.n 80045ae <HAL_RCC_GetSysClockFreq+0x86> } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 800455e: 68fb ldr r3, [r7, #12] 8004560: 0c9b lsrs r3, r3, #18 8004562: f003 030f and.w r3, r3, #15 8004566: 4a17 ldr r2, [pc, #92] ; (80045c4 <HAL_RCC_GetSysClockFreq+0x9c>) 8004568: 5cd3 ldrb r3, [r2, r3] 800456a: 607b str r3, [r7, #4] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 800456c: 68fb ldr r3, [r7, #12] 800456e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004572: 2b00 cmp r3, #0 8004574: d010 beq.n 8004598 <HAL_RCC_GetSysClockFreq+0x70> { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004576: 4b11 ldr r3, [pc, #68] ; (80045bc <HAL_RCC_GetSysClockFreq+0x94>) 8004578: 685b ldr r3, [r3, #4] 800457a: 0c5b lsrs r3, r3, #17 800457c: f003 0301 and.w r3, r3, #1 8004580: 4a11 ldr r2, [pc, #68] ; (80045c8 <HAL_RCC_GetSysClockFreq+0xa0>) 8004582: 5cd3 ldrb r3, [r2, r3] 8004584: 60bb str r3, [r7, #8] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8004586: 687b ldr r3, [r7, #4] 8004588: 4a0d ldr r2, [pc, #52] ; (80045c0 <HAL_RCC_GetSysClockFreq+0x98>) 800458a: fb03 f202 mul.w r2, r3, r2 800458e: 68bb ldr r3, [r7, #8] 8004590: fbb2 f3f3 udiv r3, r2, r3 8004594: 617b str r3, [r7, #20] 8004596: e004 b.n 80045a2 <HAL_RCC_GetSysClockFreq+0x7a> #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8004598: 687b ldr r3, [r7, #4] 800459a: 4a0c ldr r2, [pc, #48] ; (80045cc <HAL_RCC_GetSysClockFreq+0xa4>) 800459c: fb02 f303 mul.w r3, r2, r3 80045a0: 617b str r3, [r7, #20] } sysclockfreq = pllclk; 80045a2: 697b ldr r3, [r7, #20] 80045a4: 613b str r3, [r7, #16] break; 80045a6: e002 b.n 80045ae <HAL_RCC_GetSysClockFreq+0x86> } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80045a8: 4b09 ldr r3, [pc, #36] ; (80045d0 <HAL_RCC_GetSysClockFreq+0xa8>) 80045aa: 613b str r3, [r7, #16] break; 80045ac: bf00 nop } } return sysclockfreq; 80045ae: 693b ldr r3, [r7, #16] } 80045b0: 4618 mov r0, r3 80045b2: 371c adds r7, #28 80045b4: 46bd mov sp, r7 80045b6: bc80 pop {r7} 80045b8: 4770 bx lr 80045ba: bf00 nop 80045bc: 40021000 .word 0x40021000 80045c0: 00f42400 .word 0x00f42400 80045c4: 08008630 .word 0x08008630 80045c8: 08008640 .word 0x08008640 80045cc: 003d0900 .word 0x003d0900 80045d0: 007a1200 .word 0x007a1200 080045d4 <HAL_RCC_GetHCLKFreq>: * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80045d4: b480 push {r7} 80045d6: af00 add r7, sp, #0 return SystemCoreClock; 80045d8: 4b02 ldr r3, [pc, #8] ; (80045e4 <HAL_RCC_GetHCLKFreq+0x10>) 80045da: 681b ldr r3, [r3, #0] } 80045dc: 4618 mov r0, r3 80045de: 46bd mov sp, r7 80045e0: bc80 pop {r7} 80045e2: 4770 bx lr 80045e4: 20000008 .word 0x20000008 080045e8 <HAL_RCC_GetPCLK1Freq>: * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80045e8: b580 push {r7, lr} 80045ea: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80045ec: f7ff fff2 bl 80045d4 <HAL_RCC_GetHCLKFreq> 80045f0: 4602 mov r2, r0 80045f2: 4b05 ldr r3, [pc, #20] ; (8004608 <HAL_RCC_GetPCLK1Freq+0x20>) 80045f4: 685b ldr r3, [r3, #4] 80045f6: 0a1b lsrs r3, r3, #8 80045f8: f003 0307 and.w r3, r3, #7 80045fc: 4903 ldr r1, [pc, #12] ; (800460c <HAL_RCC_GetPCLK1Freq+0x24>) 80045fe: 5ccb ldrb r3, [r1, r3] 8004600: fa22 f303 lsr.w r3, r2, r3 } 8004604: 4618 mov r0, r3 8004606: bd80 pop {r7, pc} 8004608: 40021000 .word 0x40021000 800460c: 08008628 .word 0x08008628 08004610 <HAL_RCC_GetPCLK2Freq>: * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004610: b580 push {r7, lr} 8004612: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004614: f7ff ffde bl 80045d4 <HAL_RCC_GetHCLKFreq> 8004618: 4602 mov r2, r0 800461a: 4b05 ldr r3, [pc, #20] ; (8004630 <HAL_RCC_GetPCLK2Freq+0x20>) 800461c: 685b ldr r3, [r3, #4] 800461e: 0adb lsrs r3, r3, #11 8004620: f003 0307 and.w r3, r3, #7 8004624: 4903 ldr r1, [pc, #12] ; (8004634 <HAL_RCC_GetPCLK2Freq+0x24>) 8004626: 5ccb ldrb r3, [r1, r3] 8004628: fa22 f303 lsr.w r3, r2, r3 } 800462c: 4618 mov r0, r3 800462e: bd80 pop {r7, pc} 8004630: 40021000 .word 0x40021000 8004634: 08008628 .word 0x08008628 08004638 <RCC_Delay>: * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8004638: b480 push {r7} 800463a: b085 sub sp, #20 800463c: af00 add r7, sp, #0 800463e: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8004640: 4b0a ldr r3, [pc, #40] ; (800466c <RCC_Delay+0x34>) 8004642: 681b ldr r3, [r3, #0] 8004644: 4a0a ldr r2, [pc, #40] ; (8004670 <RCC_Delay+0x38>) 8004646: fba2 2303 umull r2, r3, r2, r3 800464a: 0a5b lsrs r3, r3, #9 800464c: 687a ldr r2, [r7, #4] 800464e: fb02 f303 mul.w r3, r2, r3 8004652: 60fb str r3, [r7, #12] do { __NOP(); 8004654: bf00 nop } while (Delay --); 8004656: 68fb ldr r3, [r7, #12] 8004658: 1e5a subs r2, r3, #1 800465a: 60fa str r2, [r7, #12] 800465c: 2b00 cmp r3, #0 800465e: d1f9 bne.n 8004654 <RCC_Delay+0x1c> } 8004660: bf00 nop 8004662: bf00 nop 8004664: 3714 adds r7, #20 8004666: 46bd mov sp, r7 8004668: bc80 pop {r7} 800466a: 4770 bx lr 800466c: 20000008 .word 0x20000008 8004670: 10624dd3 .word 0x10624dd3 08004674 <HAL_RCCEx_PeriphCLKConfig>: * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004674: b580 push {r7, lr} 8004676: b086 sub sp, #24 8004678: af00 add r7, sp, #0 800467a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 800467c: 2300 movs r3, #0 800467e: 613b str r3, [r7, #16] 8004680: 2300 movs r3, #0 8004682: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8004684: 687b ldr r3, [r7, #4] 8004686: 681b ldr r3, [r3, #0] 8004688: f003 0301 and.w r3, r3, #1 800468c: 2b00 cmp r3, #0 800468e: d07d beq.n 800478c <HAL_RCCEx_PeriphCLKConfig+0x118> { FlagStatus pwrclkchanged = RESET; 8004690: 2300 movs r3, #0 8004692: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004694: 4b4f ldr r3, [pc, #316] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004696: 69db ldr r3, [r3, #28] 8004698: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800469c: 2b00 cmp r3, #0 800469e: d10d bne.n 80046bc <HAL_RCCEx_PeriphCLKConfig+0x48> { __HAL_RCC_PWR_CLK_ENABLE(); 80046a0: 4b4c ldr r3, [pc, #304] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80046a2: 69db ldr r3, [r3, #28] 80046a4: 4a4b ldr r2, [pc, #300] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80046a6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80046aa: 61d3 str r3, [r2, #28] 80046ac: 4b49 ldr r3, [pc, #292] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80046ae: 69db ldr r3, [r3, #28] 80046b0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80046b4: 60bb str r3, [r7, #8] 80046b6: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80046b8: 2301 movs r3, #1 80046ba: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80046bc: 4b46 ldr r3, [pc, #280] ; (80047d8 <HAL_RCCEx_PeriphCLKConfig+0x164>) 80046be: 681b ldr r3, [r3, #0] 80046c0: f403 7380 and.w r3, r3, #256 ; 0x100 80046c4: 2b00 cmp r3, #0 80046c6: d118 bne.n 80046fa <HAL_RCCEx_PeriphCLKConfig+0x86> { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80046c8: 4b43 ldr r3, [pc, #268] ; (80047d8 <HAL_RCCEx_PeriphCLKConfig+0x164>) 80046ca: 681b ldr r3, [r3, #0] 80046cc: 4a42 ldr r2, [pc, #264] ; (80047d8 <HAL_RCCEx_PeriphCLKConfig+0x164>) 80046ce: f443 7380 orr.w r3, r3, #256 ; 0x100 80046d2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80046d4: f7fe fa46 bl 8002b64 <HAL_GetTick> 80046d8: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80046da: e008 b.n 80046ee <HAL_RCCEx_PeriphCLKConfig+0x7a> { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80046dc: f7fe fa42 bl 8002b64 <HAL_GetTick> 80046e0: 4602 mov r2, r0 80046e2: 693b ldr r3, [r7, #16] 80046e4: 1ad3 subs r3, r2, r3 80046e6: 2b64 cmp r3, #100 ; 0x64 80046e8: d901 bls.n 80046ee <HAL_RCCEx_PeriphCLKConfig+0x7a> { return HAL_TIMEOUT; 80046ea: 2303 movs r3, #3 80046ec: e06d b.n 80047ca <HAL_RCCEx_PeriphCLKConfig+0x156> while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80046ee: 4b3a ldr r3, [pc, #232] ; (80047d8 <HAL_RCCEx_PeriphCLKConfig+0x164>) 80046f0: 681b ldr r3, [r3, #0] 80046f2: f403 7380 and.w r3, r3, #256 ; 0x100 80046f6: 2b00 cmp r3, #0 80046f8: d0f0 beq.n 80046dc <HAL_RCCEx_PeriphCLKConfig+0x68> } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 80046fa: 4b36 ldr r3, [pc, #216] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80046fc: 6a1b ldr r3, [r3, #32] 80046fe: f403 7340 and.w r3, r3, #768 ; 0x300 8004702: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8004704: 68fb ldr r3, [r7, #12] 8004706: 2b00 cmp r3, #0 8004708: d02e beq.n 8004768 <HAL_RCCEx_PeriphCLKConfig+0xf4> 800470a: 687b ldr r3, [r7, #4] 800470c: 685b ldr r3, [r3, #4] 800470e: f403 7340 and.w r3, r3, #768 ; 0x300 8004712: 68fa ldr r2, [r7, #12] 8004714: 429a cmp r2, r3 8004716: d027 beq.n 8004768 <HAL_RCCEx_PeriphCLKConfig+0xf4> { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8004718: 4b2e ldr r3, [pc, #184] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800471a: 6a1b ldr r3, [r3, #32] 800471c: f423 7340 bic.w r3, r3, #768 ; 0x300 8004720: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004722: 4b2e ldr r3, [pc, #184] ; (80047dc <HAL_RCCEx_PeriphCLKConfig+0x168>) 8004724: 2201 movs r2, #1 8004726: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8004728: 4b2c ldr r3, [pc, #176] ; (80047dc <HAL_RCCEx_PeriphCLKConfig+0x168>) 800472a: 2200 movs r2, #0 800472c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 800472e: 4a29 ldr r2, [pc, #164] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004730: 68fb ldr r3, [r7, #12] 8004732: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8004734: 68fb ldr r3, [r7, #12] 8004736: f003 0301 and.w r3, r3, #1 800473a: 2b00 cmp r3, #0 800473c: d014 beq.n 8004768 <HAL_RCCEx_PeriphCLKConfig+0xf4> { /* Get Start Tick */ tickstart = HAL_GetTick(); 800473e: f7fe fa11 bl 8002b64 <HAL_GetTick> 8004742: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004744: e00a b.n 800475c <HAL_RCCEx_PeriphCLKConfig+0xe8> { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004746: f7fe fa0d bl 8002b64 <HAL_GetTick> 800474a: 4602 mov r2, r0 800474c: 693b ldr r3, [r7, #16] 800474e: 1ad3 subs r3, r2, r3 8004750: f241 3288 movw r2, #5000 ; 0x1388 8004754: 4293 cmp r3, r2 8004756: d901 bls.n 800475c <HAL_RCCEx_PeriphCLKConfig+0xe8> { return HAL_TIMEOUT; 8004758: 2303 movs r3, #3 800475a: e036 b.n 80047ca <HAL_RCCEx_PeriphCLKConfig+0x156> while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800475c: 4b1d ldr r3, [pc, #116] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800475e: 6a1b ldr r3, [r3, #32] 8004760: f003 0302 and.w r3, r3, #2 8004764: 2b00 cmp r3, #0 8004766: d0ee beq.n 8004746 <HAL_RCCEx_PeriphCLKConfig+0xd2> } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004768: 4b1a ldr r3, [pc, #104] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800476a: 6a1b ldr r3, [r3, #32] 800476c: f423 7240 bic.w r2, r3, #768 ; 0x300 8004770: 687b ldr r3, [r7, #4] 8004772: 685b ldr r3, [r3, #4] 8004774: 4917 ldr r1, [pc, #92] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004776: 4313 orrs r3, r2 8004778: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800477a: 7dfb ldrb r3, [r7, #23] 800477c: 2b01 cmp r3, #1 800477e: d105 bne.n 800478c <HAL_RCCEx_PeriphCLKConfig+0x118> { __HAL_RCC_PWR_CLK_DISABLE(); 8004780: 4b14 ldr r3, [pc, #80] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004782: 69db ldr r3, [r3, #28] 8004784: 4a13 ldr r2, [pc, #76] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 8004786: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800478a: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800478c: 687b ldr r3, [r7, #4] 800478e: 681b ldr r3, [r3, #0] 8004790: f003 0302 and.w r3, r3, #2 8004794: 2b00 cmp r3, #0 8004796: d008 beq.n 80047aa <HAL_RCCEx_PeriphCLKConfig+0x136> { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8004798: 4b0e ldr r3, [pc, #56] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 800479a: 685b ldr r3, [r3, #4] 800479c: f423 4240 bic.w r2, r3, #49152 ; 0xc000 80047a0: 687b ldr r3, [r7, #4] 80047a2: 689b ldr r3, [r3, #8] 80047a4: 490b ldr r1, [pc, #44] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80047a6: 4313 orrs r3, r2 80047a8: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80047aa: 687b ldr r3, [r7, #4] 80047ac: 681b ldr r3, [r3, #0] 80047ae: f003 0310 and.w r3, r3, #16 80047b2: 2b00 cmp r3, #0 80047b4: d008 beq.n 80047c8 <HAL_RCCEx_PeriphCLKConfig+0x154> { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80047b6: 4b07 ldr r3, [pc, #28] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80047b8: 685b ldr r3, [r3, #4] 80047ba: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 80047be: 687b ldr r3, [r7, #4] 80047c0: 68db ldr r3, [r3, #12] 80047c2: 4904 ldr r1, [pc, #16] ; (80047d4 <HAL_RCCEx_PeriphCLKConfig+0x160>) 80047c4: 4313 orrs r3, r2 80047c6: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80047c8: 2300 movs r3, #0 } 80047ca: 4618 mov r0, r3 80047cc: 3718 adds r7, #24 80047ce: 46bd mov sp, r7 80047d0: bd80 pop {r7, pc} 80047d2: bf00 nop 80047d4: 40021000 .word 0x40021000 80047d8: 40007000 .word 0x40007000 80047dc: 42420440 .word 0x42420440 080047e0 <HAL_RCCEx_GetPeriphCLKFreq>: * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80047e0: b580 push {r7, lr} 80047e2: b088 sub sp, #32 80047e4: af00 add r7, sp, #0 80047e6: 6078 str r0, [r7, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 80047e8: 2300 movs r3, #0 80047ea: 617b str r3, [r7, #20] 80047ec: 2300 movs r3, #0 80047ee: 61fb str r3, [r7, #28] 80047f0: 2300 movs r3, #0 80047f2: 613b str r3, [r7, #16] #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 80047f4: 2300 movs r3, #0 80047f6: 60fb str r3, [r7, #12] 80047f8: 2300 movs r3, #0 80047fa: 61bb str r3, [r7, #24] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 80047fc: 687b ldr r3, [r7, #4] 80047fe: 2b10 cmp r3, #16 8004800: d00a beq.n 8004818 <HAL_RCCEx_GetPeriphCLKFreq+0x38> 8004802: 687b ldr r3, [r7, #4] 8004804: 2b10 cmp r3, #16 8004806: f200 8089 bhi.w 800491c <HAL_RCCEx_GetPeriphCLKFreq+0x13c> 800480a: 687b ldr r3, [r7, #4] 800480c: 2b01 cmp r3, #1 800480e: d045 beq.n 800489c <HAL_RCCEx_GetPeriphCLKFreq+0xbc> 8004810: 687b ldr r3, [r7, #4] 8004812: 2b02 cmp r3, #2 8004814: d074 beq.n 8004900 <HAL_RCCEx_GetPeriphCLKFreq+0x120> frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8004816: e081 b.n 800491c <HAL_RCCEx_GetPeriphCLKFreq+0x13c> temp_reg = RCC->CFGR; 8004818: 4b45 ldr r3, [pc, #276] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 800481a: 685b ldr r3, [r3, #4] 800481c: 60fb str r3, [r7, #12] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 800481e: 4b44 ldr r3, [pc, #272] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 8004820: 681b ldr r3, [r3, #0] 8004822: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004826: 2b00 cmp r3, #0 8004828: d07a beq.n 8004920 <HAL_RCCEx_GetPeriphCLKFreq+0x140> pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 800482a: 68fb ldr r3, [r7, #12] 800482c: 0c9b lsrs r3, r3, #18 800482e: f003 030f and.w r3, r3, #15 8004832: 4a40 ldr r2, [pc, #256] ; (8004934 <HAL_RCCEx_GetPeriphCLKFreq+0x154>) 8004834: 5cd3 ldrb r3, [r2, r3] 8004836: 613b str r3, [r7, #16] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8004838: 68fb ldr r3, [r7, #12] 800483a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800483e: 2b00 cmp r3, #0 8004840: d015 beq.n 800486e <HAL_RCCEx_GetPeriphCLKFreq+0x8e> prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004842: 4b3b ldr r3, [pc, #236] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 8004844: 685b ldr r3, [r3, #4] 8004846: 0c5b lsrs r3, r3, #17 8004848: f003 0301 and.w r3, r3, #1 800484c: 4a3a ldr r2, [pc, #232] ; (8004938 <HAL_RCCEx_GetPeriphCLKFreq+0x158>) 800484e: 5cd3 ldrb r3, [r2, r3] 8004850: 617b str r3, [r7, #20] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8004852: 68fb ldr r3, [r7, #12] 8004854: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004858: 2b00 cmp r3, #0 800485a: d00d beq.n 8004878 <HAL_RCCEx_GetPeriphCLKFreq+0x98> pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 800485c: 4a37 ldr r2, [pc, #220] ; (800493c <HAL_RCCEx_GetPeriphCLKFreq+0x15c>) 800485e: 697b ldr r3, [r7, #20] 8004860: fbb2 f2f3 udiv r2, r2, r3 8004864: 693b ldr r3, [r7, #16] 8004866: fb02 f303 mul.w r3, r2, r3 800486a: 61fb str r3, [r7, #28] 800486c: e004 b.n 8004878 <HAL_RCCEx_GetPeriphCLKFreq+0x98> pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 800486e: 693b ldr r3, [r7, #16] 8004870: 4a33 ldr r2, [pc, #204] ; (8004940 <HAL_RCCEx_GetPeriphCLKFreq+0x160>) 8004872: fb02 f303 mul.w r3, r2, r3 8004876: 61fb str r3, [r7, #28] if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) 8004878: 4b2d ldr r3, [pc, #180] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 800487a: 685b ldr r3, [r3, #4] 800487c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8004880: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8004884: d102 bne.n 800488c <HAL_RCCEx_GetPeriphCLKFreq+0xac> frequency = pllclk; 8004886: 69fb ldr r3, [r7, #28] 8004888: 61bb str r3, [r7, #24] break; 800488a: e049 b.n 8004920 <HAL_RCCEx_GetPeriphCLKFreq+0x140> frequency = (pllclk * 2) / 3; 800488c: 69fb ldr r3, [r7, #28] 800488e: 005b lsls r3, r3, #1 8004890: 4a2c ldr r2, [pc, #176] ; (8004944 <HAL_RCCEx_GetPeriphCLKFreq+0x164>) 8004892: fba2 2303 umull r2, r3, r2, r3 8004896: 085b lsrs r3, r3, #1 8004898: 61bb str r3, [r7, #24] break; 800489a: e041 b.n 8004920 <HAL_RCCEx_GetPeriphCLKFreq+0x140> temp_reg = RCC->BDCR; 800489c: 4b24 ldr r3, [pc, #144] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 800489e: 6a1b ldr r3, [r3, #32] 80048a0: 60fb str r3, [r7, #12] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 80048a2: 68fb ldr r3, [r7, #12] 80048a4: f403 7340 and.w r3, r3, #768 ; 0x300 80048a8: f5b3 7f80 cmp.w r3, #256 ; 0x100 80048ac: d108 bne.n 80048c0 <HAL_RCCEx_GetPeriphCLKFreq+0xe0> 80048ae: 68fb ldr r3, [r7, #12] 80048b0: f003 0302 and.w r3, r3, #2 80048b4: 2b00 cmp r3, #0 80048b6: d003 beq.n 80048c0 <HAL_RCCEx_GetPeriphCLKFreq+0xe0> frequency = LSE_VALUE; 80048b8: f44f 4300 mov.w r3, #32768 ; 0x8000 80048bc: 61bb str r3, [r7, #24] 80048be: e01e b.n 80048fe <HAL_RCCEx_GetPeriphCLKFreq+0x11e> else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 80048c0: 68fb ldr r3, [r7, #12] 80048c2: f403 7340 and.w r3, r3, #768 ; 0x300 80048c6: f5b3 7f00 cmp.w r3, #512 ; 0x200 80048ca: d109 bne.n 80048e0 <HAL_RCCEx_GetPeriphCLKFreq+0x100> 80048cc: 4b18 ldr r3, [pc, #96] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 80048ce: 6a5b ldr r3, [r3, #36] ; 0x24 80048d0: f003 0302 and.w r3, r3, #2 80048d4: 2b00 cmp r3, #0 80048d6: d003 beq.n 80048e0 <HAL_RCCEx_GetPeriphCLKFreq+0x100> frequency = LSI_VALUE; 80048d8: f649 4340 movw r3, #40000 ; 0x9c40 80048dc: 61bb str r3, [r7, #24] 80048de: e00e b.n 80048fe <HAL_RCCEx_GetPeriphCLKFreq+0x11e> else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 80048e0: 68fb ldr r3, [r7, #12] 80048e2: f403 7340 and.w r3, r3, #768 ; 0x300 80048e6: f5b3 7f40 cmp.w r3, #768 ; 0x300 80048ea: d11b bne.n 8004924 <HAL_RCCEx_GetPeriphCLKFreq+0x144> 80048ec: 4b10 ldr r3, [pc, #64] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 80048ee: 681b ldr r3, [r3, #0] 80048f0: f403 3300 and.w r3, r3, #131072 ; 0x20000 80048f4: 2b00 cmp r3, #0 80048f6: d015 beq.n 8004924 <HAL_RCCEx_GetPeriphCLKFreq+0x144> frequency = HSE_VALUE / 128U; 80048f8: 4b13 ldr r3, [pc, #76] ; (8004948 <HAL_RCCEx_GetPeriphCLKFreq+0x168>) 80048fa: 61bb str r3, [r7, #24] break; 80048fc: e012 b.n 8004924 <HAL_RCCEx_GetPeriphCLKFreq+0x144> 80048fe: e011 b.n 8004924 <HAL_RCCEx_GetPeriphCLKFreq+0x144> frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8004900: f7ff fe86 bl 8004610 <HAL_RCC_GetPCLK2Freq> 8004904: 4602 mov r2, r0 8004906: 4b0a ldr r3, [pc, #40] ; (8004930 <HAL_RCCEx_GetPeriphCLKFreq+0x150>) 8004908: 685b ldr r3, [r3, #4] 800490a: 0b9b lsrs r3, r3, #14 800490c: f003 0303 and.w r3, r3, #3 8004910: 3301 adds r3, #1 8004912: 005b lsls r3, r3, #1 8004914: fbb2 f3f3 udiv r3, r2, r3 8004918: 61bb str r3, [r7, #24] break; 800491a: e004 b.n 8004926 <HAL_RCCEx_GetPeriphCLKFreq+0x146> break; 800491c: bf00 nop 800491e: e002 b.n 8004926 <HAL_RCCEx_GetPeriphCLKFreq+0x146> break; 8004920: bf00 nop 8004922: e000 b.n 8004926 <HAL_RCCEx_GetPeriphCLKFreq+0x146> break; 8004924: bf00 nop } } return (frequency); 8004926: 69bb ldr r3, [r7, #24] } 8004928: 4618 mov r0, r3 800492a: 3720 adds r7, #32 800492c: 46bd mov sp, r7 800492e: bd80 pop {r7, pc} 8004930: 40021000 .word 0x40021000 8004934: 08008644 .word 0x08008644 8004938: 08008654 .word 0x08008654 800493c: 00f42400 .word 0x00f42400 8004940: 003d0900 .word 0x003d0900 8004944: aaaaaaab .word 0xaaaaaaab 8004948: 0001e848 .word 0x0001e848 0800494c <HAL_SPI_Init>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 800494c: b580 push {r7, lr} 800494e: b082 sub sp, #8 8004950: af00 add r7, sp, #0 8004952: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) 8004954: 687b ldr r3, [r7, #4] 8004956: 2b00 cmp r3, #0 8004958: d101 bne.n 800495e <HAL_SPI_Init+0x12> { return HAL_ERROR; 800495a: 2301 movs r3, #1 800495c: e076 b.n 8004a4c <HAL_SPI_Init+0x100> assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); /* TI mode is not supported on this device. TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 800495e: 687b ldr r3, [r7, #4] 8004960: 6a5b ldr r3, [r3, #36] ; 0x24 8004962: 2b00 cmp r3, #0 8004964: d108 bne.n 8004978 <HAL_SPI_Init+0x2c> { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8004966: 687b ldr r3, [r7, #4] 8004968: 685b ldr r3, [r3, #4] 800496a: f5b3 7f82 cmp.w r3, #260 ; 0x104 800496e: d009 beq.n 8004984 <HAL_SPI_Init+0x38> assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8004970: 687b ldr r3, [r7, #4] 8004972: 2200 movs r2, #0 8004974: 61da str r2, [r3, #28] 8004976: e005 b.n 8004984 <HAL_SPI_Init+0x38> else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8004978: 687b ldr r3, [r7, #4] 800497a: 2200 movs r2, #0 800497c: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 800497e: 687b ldr r3, [r7, #4] 8004980: 2200 movs r2, #0 8004982: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004984: 687b ldr r3, [r7, #4] 8004986: 2200 movs r2, #0 8004988: 629a str r2, [r3, #40] ; 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 800498a: 687b ldr r3, [r7, #4] 800498c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004990: b2db uxtb r3, r3 8004992: 2b00 cmp r3, #0 8004994: d106 bne.n 80049a4 <HAL_SPI_Init+0x58> { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8004996: 687b ldr r3, [r7, #4] 8004998: 2200 movs r2, #0 800499a: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800499e: 6878 ldr r0, [r7, #4] 80049a0: f7fd fab6 bl 8001f10 <HAL_SPI_MspInit> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 80049a4: 687b ldr r3, [r7, #4] 80049a6: 2202 movs r2, #2 80049a8: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80049ac: 687b ldr r3, [r7, #4] 80049ae: 681b ldr r3, [r3, #0] 80049b0: 681a ldr r2, [r3, #0] 80049b2: 687b ldr r3, [r7, #4] 80049b4: 681b ldr r3, [r3, #0] 80049b6: f022 0240 bic.w r2, r2, #64 ; 0x40 80049ba: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 80049bc: 687b ldr r3, [r7, #4] 80049be: 685b ldr r3, [r3, #4] 80049c0: f403 7282 and.w r2, r3, #260 ; 0x104 80049c4: 687b ldr r3, [r7, #4] 80049c6: 689b ldr r3, [r3, #8] 80049c8: f403 4304 and.w r3, r3, #33792 ; 0x8400 80049cc: 431a orrs r2, r3 80049ce: 687b ldr r3, [r7, #4] 80049d0: 68db ldr r3, [r3, #12] 80049d2: f403 6300 and.w r3, r3, #2048 ; 0x800 80049d6: 431a orrs r2, r3 80049d8: 687b ldr r3, [r7, #4] 80049da: 691b ldr r3, [r3, #16] 80049dc: f003 0302 and.w r3, r3, #2 80049e0: 431a orrs r2, r3 80049e2: 687b ldr r3, [r7, #4] 80049e4: 695b ldr r3, [r3, #20] 80049e6: f003 0301 and.w r3, r3, #1 80049ea: 431a orrs r2, r3 80049ec: 687b ldr r3, [r7, #4] 80049ee: 699b ldr r3, [r3, #24] 80049f0: f403 7300 and.w r3, r3, #512 ; 0x200 80049f4: 431a orrs r2, r3 80049f6: 687b ldr r3, [r7, #4] 80049f8: 69db ldr r3, [r3, #28] 80049fa: f003 0338 and.w r3, r3, #56 ; 0x38 80049fe: 431a orrs r2, r3 8004a00: 687b ldr r3, [r7, #4] 8004a02: 6a1b ldr r3, [r3, #32] 8004a04: f003 0380 and.w r3, r3, #128 ; 0x80 8004a08: ea42 0103 orr.w r1, r2, r3 8004a0c: 687b ldr r3, [r7, #4] 8004a0e: 6a9b ldr r3, [r3, #40] ; 0x28 8004a10: f403 5200 and.w r2, r3, #8192 ; 0x2000 8004a14: 687b ldr r3, [r7, #4] 8004a16: 681b ldr r3, [r3, #0] 8004a18: 430a orrs r2, r1 8004a1a: 601a str r2, [r3, #0] (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management */ WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); 8004a1c: 687b ldr r3, [r7, #4] 8004a1e: 699b ldr r3, [r3, #24] 8004a20: 0c1a lsrs r2, r3, #16 8004a22: 687b ldr r3, [r7, #4] 8004a24: 681b ldr r3, [r3, #0] 8004a26: f002 0204 and.w r2, r2, #4 8004a2a: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8004a2c: 687b ldr r3, [r7, #4] 8004a2e: 681b ldr r3, [r3, #0] 8004a30: 69da ldr r2, [r3, #28] 8004a32: 687b ldr r3, [r7, #4] 8004a34: 681b ldr r3, [r3, #0] 8004a36: f422 6200 bic.w r2, r2, #2048 ; 0x800 8004a3a: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004a3c: 687b ldr r3, [r7, #4] 8004a3e: 2200 movs r2, #0 8004a40: 655a str r2, [r3, #84] ; 0x54 hspi->State = HAL_SPI_STATE_READY; 8004a42: 687b ldr r3, [r7, #4] 8004a44: 2201 movs r2, #1 8004a46: f883 2051 strb.w r2, [r3, #81] ; 0x51 return HAL_OK; 8004a4a: 2300 movs r3, #0 } 8004a4c: 4618 mov r0, r3 8004a4e: 3708 adds r7, #8 8004a50: 46bd mov sp, r7 8004a52: bd80 pop {r7, pc} 08004a54 <HAL_SPI_Transmit>: * @param Size amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004a54: b580 push {r7, lr} 8004a56: b088 sub sp, #32 8004a58: af00 add r7, sp, #0 8004a5a: 60f8 str r0, [r7, #12] 8004a5c: 60b9 str r1, [r7, #8] 8004a5e: 603b str r3, [r7, #0] 8004a60: 4613 mov r3, r2 8004a62: 80fb strh r3, [r7, #6] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8004a64: f7fe f87e bl 8002b64 <HAL_GetTick> 8004a68: 61f8 str r0, [r7, #28] initial_TxXferCount = Size; 8004a6a: 88fb ldrh r3, [r7, #6] 8004a6c: 837b strh r3, [r7, #26] if (hspi->State != HAL_SPI_STATE_READY) 8004a6e: 68fb ldr r3, [r7, #12] 8004a70: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004a74: b2db uxtb r3, r3 8004a76: 2b01 cmp r3, #1 8004a78: d001 beq.n 8004a7e <HAL_SPI_Transmit+0x2a> { return HAL_BUSY; 8004a7a: 2302 movs r3, #2 8004a7c: e12a b.n 8004cd4 <HAL_SPI_Transmit+0x280> } if ((pData == NULL) || (Size == 0U)) 8004a7e: 68bb ldr r3, [r7, #8] 8004a80: 2b00 cmp r3, #0 8004a82: d002 beq.n 8004a8a <HAL_SPI_Transmit+0x36> 8004a84: 88fb ldrh r3, [r7, #6] 8004a86: 2b00 cmp r3, #0 8004a88: d101 bne.n 8004a8e <HAL_SPI_Transmit+0x3a> { return HAL_ERROR; 8004a8a: 2301 movs r3, #1 8004a8c: e122 b.n 8004cd4 <HAL_SPI_Transmit+0x280> } /* Process Locked */ __HAL_LOCK(hspi); 8004a8e: 68fb ldr r3, [r7, #12] 8004a90: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 8004a94: 2b01 cmp r3, #1 8004a96: d101 bne.n 8004a9c <HAL_SPI_Transmit+0x48> 8004a98: 2302 movs r3, #2 8004a9a: e11b b.n 8004cd4 <HAL_SPI_Transmit+0x280> 8004a9c: 68fb ldr r3, [r7, #12] 8004a9e: 2201 movs r2, #1 8004aa0: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 8004aa4: 68fb ldr r3, [r7, #12] 8004aa6: 2203 movs r2, #3 8004aa8: f883 2051 strb.w r2, [r3, #81] ; 0x51 hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004aac: 68fb ldr r3, [r7, #12] 8004aae: 2200 movs r2, #0 8004ab0: 655a str r2, [r3, #84] ; 0x54 hspi->pTxBuffPtr = (const uint8_t *)pData; 8004ab2: 68fb ldr r3, [r7, #12] 8004ab4: 68ba ldr r2, [r7, #8] 8004ab6: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = Size; 8004ab8: 68fb ldr r3, [r7, #12] 8004aba: 88fa ldrh r2, [r7, #6] 8004abc: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = Size; 8004abe: 68fb ldr r3, [r7, #12] 8004ac0: 88fa ldrh r2, [r7, #6] 8004ac2: 86da strh r2, [r3, #54] ; 0x36 /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 8004ac4: 68fb ldr r3, [r7, #12] 8004ac6: 2200 movs r2, #0 8004ac8: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = 0U; 8004aca: 68fb ldr r3, [r7, #12] 8004acc: 2200 movs r2, #0 8004ace: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = 0U; 8004ad0: 68fb ldr r3, [r7, #12] 8004ad2: 2200 movs r2, #0 8004ad4: 87da strh r2, [r3, #62] ; 0x3e hspi->TxISR = NULL; 8004ad6: 68fb ldr r3, [r7, #12] 8004ad8: 2200 movs r2, #0 8004ada: 645a str r2, [r3, #68] ; 0x44 hspi->RxISR = NULL; 8004adc: 68fb ldr r3, [r7, #12] 8004ade: 2200 movs r2, #0 8004ae0: 641a str r2, [r3, #64] ; 0x40 /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 8004ae2: 68fb ldr r3, [r7, #12] 8004ae4: 689b ldr r3, [r3, #8] 8004ae6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004aea: d10f bne.n 8004b0c <HAL_SPI_Transmit+0xb8> { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8004aec: 68fb ldr r3, [r7, #12] 8004aee: 681b ldr r3, [r3, #0] 8004af0: 681a ldr r2, [r3, #0] 8004af2: 68fb ldr r3, [r7, #12] 8004af4: 681b ldr r3, [r3, #0] 8004af6: f022 0240 bic.w r2, r2, #64 ; 0x40 8004afa: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 8004afc: 68fb ldr r3, [r7, #12] 8004afe: 681b ldr r3, [r3, #0] 8004b00: 681a ldr r2, [r3, #0] 8004b02: 68fb ldr r3, [r7, #12] 8004b04: 681b ldr r3, [r3, #0] 8004b06: f442 4280 orr.w r2, r2, #16384 ; 0x4000 8004b0a: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004b0c: 68fb ldr r3, [r7, #12] 8004b0e: 681b ldr r3, [r3, #0] 8004b10: 681b ldr r3, [r3, #0] 8004b12: f003 0340 and.w r3, r3, #64 ; 0x40 8004b16: 2b40 cmp r3, #64 ; 0x40 8004b18: d007 beq.n 8004b2a <HAL_SPI_Transmit+0xd6> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004b1a: 68fb ldr r3, [r7, #12] 8004b1c: 681b ldr r3, [r3, #0] 8004b1e: 681a ldr r2, [r3, #0] 8004b20: 68fb ldr r3, [r7, #12] 8004b22: 681b ldr r3, [r3, #0] 8004b24: f042 0240 orr.w r2, r2, #64 ; 0x40 8004b28: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) 8004b2a: 68fb ldr r3, [r7, #12] 8004b2c: 68db ldr r3, [r3, #12] 8004b2e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8004b32: d152 bne.n 8004bda <HAL_SPI_Transmit+0x186> { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004b34: 68fb ldr r3, [r7, #12] 8004b36: 685b ldr r3, [r3, #4] 8004b38: 2b00 cmp r3, #0 8004b3a: d002 beq.n 8004b42 <HAL_SPI_Transmit+0xee> 8004b3c: 8b7b ldrh r3, [r7, #26] 8004b3e: 2b01 cmp r3, #1 8004b40: d145 bne.n 8004bce <HAL_SPI_Transmit+0x17a> { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8004b42: 68fb ldr r3, [r7, #12] 8004b44: 6b1b ldr r3, [r3, #48] ; 0x30 8004b46: 881a ldrh r2, [r3, #0] 8004b48: 68fb ldr r3, [r7, #12] 8004b4a: 681b ldr r3, [r3, #0] 8004b4c: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8004b4e: 68fb ldr r3, [r7, #12] 8004b50: 6b1b ldr r3, [r3, #48] ; 0x30 8004b52: 1c9a adds r2, r3, #2 8004b54: 68fb ldr r3, [r7, #12] 8004b56: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004b58: 68fb ldr r3, [r7, #12] 8004b5a: 8edb ldrh r3, [r3, #54] ; 0x36 8004b5c: b29b uxth r3, r3 8004b5e: 3b01 subs r3, #1 8004b60: b29a uxth r2, r3 8004b62: 68fb ldr r3, [r7, #12] 8004b64: 86da strh r2, [r3, #54] ; 0x36 } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 8004b66: e032 b.n 8004bce <HAL_SPI_Transmit+0x17a> { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8004b68: 68fb ldr r3, [r7, #12] 8004b6a: 681b ldr r3, [r3, #0] 8004b6c: 689b ldr r3, [r3, #8] 8004b6e: f003 0302 and.w r3, r3, #2 8004b72: 2b02 cmp r3, #2 8004b74: d112 bne.n 8004b9c <HAL_SPI_Transmit+0x148> { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8004b76: 68fb ldr r3, [r7, #12] 8004b78: 6b1b ldr r3, [r3, #48] ; 0x30 8004b7a: 881a ldrh r2, [r3, #0] 8004b7c: 68fb ldr r3, [r7, #12] 8004b7e: 681b ldr r3, [r3, #0] 8004b80: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8004b82: 68fb ldr r3, [r7, #12] 8004b84: 6b1b ldr r3, [r3, #48] ; 0x30 8004b86: 1c9a adds r2, r3, #2 8004b88: 68fb ldr r3, [r7, #12] 8004b8a: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004b8c: 68fb ldr r3, [r7, #12] 8004b8e: 8edb ldrh r3, [r3, #54] ; 0x36 8004b90: b29b uxth r3, r3 8004b92: 3b01 subs r3, #1 8004b94: b29a uxth r2, r3 8004b96: 68fb ldr r3, [r7, #12] 8004b98: 86da strh r2, [r3, #54] ; 0x36 8004b9a: e018 b.n 8004bce <HAL_SPI_Transmit+0x17a> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8004b9c: f7fd ffe2 bl 8002b64 <HAL_GetTick> 8004ba0: 4602 mov r2, r0 8004ba2: 69fb ldr r3, [r7, #28] 8004ba4: 1ad3 subs r3, r2, r3 8004ba6: 683a ldr r2, [r7, #0] 8004ba8: 429a cmp r2, r3 8004baa: d803 bhi.n 8004bb4 <HAL_SPI_Transmit+0x160> 8004bac: 683b ldr r3, [r7, #0] 8004bae: f1b3 3fff cmp.w r3, #4294967295 8004bb2: d102 bne.n 8004bba <HAL_SPI_Transmit+0x166> 8004bb4: 683b ldr r3, [r7, #0] 8004bb6: 2b00 cmp r3, #0 8004bb8: d109 bne.n 8004bce <HAL_SPI_Transmit+0x17a> { hspi->State = HAL_SPI_STATE_READY; 8004bba: 68fb ldr r3, [r7, #12] 8004bbc: 2201 movs r2, #1 8004bbe: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004bc2: 68fb ldr r3, [r7, #12] 8004bc4: 2200 movs r2, #0 8004bc6: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 8004bca: 2303 movs r3, #3 8004bcc: e082 b.n 8004cd4 <HAL_SPI_Transmit+0x280> while (hspi->TxXferCount > 0U) 8004bce: 68fb ldr r3, [r7, #12] 8004bd0: 8edb ldrh r3, [r3, #54] ; 0x36 8004bd2: b29b uxth r3, r3 8004bd4: 2b00 cmp r3, #0 8004bd6: d1c7 bne.n 8004b68 <HAL_SPI_Transmit+0x114> 8004bd8: e053 b.n 8004c82 <HAL_SPI_Transmit+0x22e> } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004bda: 68fb ldr r3, [r7, #12] 8004bdc: 685b ldr r3, [r3, #4] 8004bde: 2b00 cmp r3, #0 8004be0: d002 beq.n 8004be8 <HAL_SPI_Transmit+0x194> 8004be2: 8b7b ldrh r3, [r7, #26] 8004be4: 2b01 cmp r3, #1 8004be6: d147 bne.n 8004c78 <HAL_SPI_Transmit+0x224> { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 8004be8: 68fb ldr r3, [r7, #12] 8004bea: 6b1a ldr r2, [r3, #48] ; 0x30 8004bec: 68fb ldr r3, [r7, #12] 8004bee: 681b ldr r3, [r3, #0] 8004bf0: 330c adds r3, #12 8004bf2: 7812 ldrb r2, [r2, #0] 8004bf4: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8004bf6: 68fb ldr r3, [r7, #12] 8004bf8: 6b1b ldr r3, [r3, #48] ; 0x30 8004bfa: 1c5a adds r2, r3, #1 8004bfc: 68fb ldr r3, [r7, #12] 8004bfe: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004c00: 68fb ldr r3, [r7, #12] 8004c02: 8edb ldrh r3, [r3, #54] ; 0x36 8004c04: b29b uxth r3, r3 8004c06: 3b01 subs r3, #1 8004c08: b29a uxth r2, r3 8004c0a: 68fb ldr r3, [r7, #12] 8004c0c: 86da strh r2, [r3, #54] ; 0x36 } while (hspi->TxXferCount > 0U) 8004c0e: e033 b.n 8004c78 <HAL_SPI_Transmit+0x224> { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8004c10: 68fb ldr r3, [r7, #12] 8004c12: 681b ldr r3, [r3, #0] 8004c14: 689b ldr r3, [r3, #8] 8004c16: f003 0302 and.w r3, r3, #2 8004c1a: 2b02 cmp r3, #2 8004c1c: d113 bne.n 8004c46 <HAL_SPI_Transmit+0x1f2> { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 8004c1e: 68fb ldr r3, [r7, #12] 8004c20: 6b1a ldr r2, [r3, #48] ; 0x30 8004c22: 68fb ldr r3, [r7, #12] 8004c24: 681b ldr r3, [r3, #0] 8004c26: 330c adds r3, #12 8004c28: 7812 ldrb r2, [r2, #0] 8004c2a: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8004c2c: 68fb ldr r3, [r7, #12] 8004c2e: 6b1b ldr r3, [r3, #48] ; 0x30 8004c30: 1c5a adds r2, r3, #1 8004c32: 68fb ldr r3, [r7, #12] 8004c34: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8004c36: 68fb ldr r3, [r7, #12] 8004c38: 8edb ldrh r3, [r3, #54] ; 0x36 8004c3a: b29b uxth r3, r3 8004c3c: 3b01 subs r3, #1 8004c3e: b29a uxth r2, r3 8004c40: 68fb ldr r3, [r7, #12] 8004c42: 86da strh r2, [r3, #54] ; 0x36 8004c44: e018 b.n 8004c78 <HAL_SPI_Transmit+0x224> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8004c46: f7fd ff8d bl 8002b64 <HAL_GetTick> 8004c4a: 4602 mov r2, r0 8004c4c: 69fb ldr r3, [r7, #28] 8004c4e: 1ad3 subs r3, r2, r3 8004c50: 683a ldr r2, [r7, #0] 8004c52: 429a cmp r2, r3 8004c54: d803 bhi.n 8004c5e <HAL_SPI_Transmit+0x20a> 8004c56: 683b ldr r3, [r7, #0] 8004c58: f1b3 3fff cmp.w r3, #4294967295 8004c5c: d102 bne.n 8004c64 <HAL_SPI_Transmit+0x210> 8004c5e: 683b ldr r3, [r7, #0] 8004c60: 2b00 cmp r3, #0 8004c62: d109 bne.n 8004c78 <HAL_SPI_Transmit+0x224> { hspi->State = HAL_SPI_STATE_READY; 8004c64: 68fb ldr r3, [r7, #12] 8004c66: 2201 movs r2, #1 8004c68: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004c6c: 68fb ldr r3, [r7, #12] 8004c6e: 2200 movs r2, #0 8004c70: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 8004c74: 2303 movs r3, #3 8004c76: e02d b.n 8004cd4 <HAL_SPI_Transmit+0x280> while (hspi->TxXferCount > 0U) 8004c78: 68fb ldr r3, [r7, #12] 8004c7a: 8edb ldrh r3, [r3, #54] ; 0x36 8004c7c: b29b uxth r3, r3 8004c7e: 2b00 cmp r3, #0 8004c80: d1c6 bne.n 8004c10 <HAL_SPI_Transmit+0x1bc> SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 8004c82: 69fa ldr r2, [r7, #28] 8004c84: 6839 ldr r1, [r7, #0] 8004c86: 68f8 ldr r0, [r7, #12] 8004c88: f000 fe16 bl 80058b8 <SPI_EndRxTxTransaction> 8004c8c: 4603 mov r3, r0 8004c8e: 2b00 cmp r3, #0 8004c90: d002 beq.n 8004c98 <HAL_SPI_Transmit+0x244> { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8004c92: 68fb ldr r3, [r7, #12] 8004c94: 2220 movs r2, #32 8004c96: 655a str r2, [r3, #84] ; 0x54 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 8004c98: 68fb ldr r3, [r7, #12] 8004c9a: 689b ldr r3, [r3, #8] 8004c9c: 2b00 cmp r3, #0 8004c9e: d10a bne.n 8004cb6 <HAL_SPI_Transmit+0x262> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8004ca0: 2300 movs r3, #0 8004ca2: 617b str r3, [r7, #20] 8004ca4: 68fb ldr r3, [r7, #12] 8004ca6: 681b ldr r3, [r3, #0] 8004ca8: 68db ldr r3, [r3, #12] 8004caa: 617b str r3, [r7, #20] 8004cac: 68fb ldr r3, [r7, #12] 8004cae: 681b ldr r3, [r3, #0] 8004cb0: 689b ldr r3, [r3, #8] 8004cb2: 617b str r3, [r7, #20] 8004cb4: 697b ldr r3, [r7, #20] } hspi->State = HAL_SPI_STATE_READY; 8004cb6: 68fb ldr r3, [r7, #12] 8004cb8: 2201 movs r2, #1 8004cba: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); 8004cbe: 68fb ldr r3, [r7, #12] 8004cc0: 2200 movs r2, #0 8004cc2: f883 2050 strb.w r2, [r3, #80] ; 0x50 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8004cc6: 68fb ldr r3, [r7, #12] 8004cc8: 6d5b ldr r3, [r3, #84] ; 0x54 8004cca: 2b00 cmp r3, #0 8004ccc: d001 beq.n 8004cd2 <HAL_SPI_Transmit+0x27e> { return HAL_ERROR; 8004cce: 2301 movs r3, #1 8004cd0: e000 b.n 8004cd4 <HAL_SPI_Transmit+0x280> } else { return HAL_OK; 8004cd2: 2300 movs r3, #0 } } 8004cd4: 4618 mov r0, r3 8004cd6: 3720 adds r7, #32 8004cd8: 46bd mov sp, r7 8004cda: bd80 pop {r7, pc} 08004cdc <HAL_SPI_Receive>: * @param Size amount of data to be received * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004cdc: b580 push {r7, lr} 8004cde: b088 sub sp, #32 8004ce0: af02 add r7, sp, #8 8004ce2: 60f8 str r0, [r7, #12] 8004ce4: 60b9 str r1, [r7, #8] 8004ce6: 603b str r3, [r7, #0] 8004ce8: 4613 mov r3, r2 8004cea: 80fb strh r3, [r7, #6] #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ uint32_t tickstart; if (hspi->State != HAL_SPI_STATE_READY) 8004cec: 68fb ldr r3, [r7, #12] 8004cee: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004cf2: b2db uxtb r3, r3 8004cf4: 2b01 cmp r3, #1 8004cf6: d001 beq.n 8004cfc <HAL_SPI_Receive+0x20> { return HAL_BUSY; 8004cf8: 2302 movs r3, #2 8004cfa: e104 b.n 8004f06 <HAL_SPI_Receive+0x22a> } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) 8004cfc: 68fb ldr r3, [r7, #12] 8004cfe: 685b ldr r3, [r3, #4] 8004d00: f5b3 7f82 cmp.w r3, #260 ; 0x104 8004d04: d112 bne.n 8004d2c <HAL_SPI_Receive+0x50> 8004d06: 68fb ldr r3, [r7, #12] 8004d08: 689b ldr r3, [r3, #8] 8004d0a: 2b00 cmp r3, #0 8004d0c: d10e bne.n 8004d2c <HAL_SPI_Receive+0x50> { hspi->State = HAL_SPI_STATE_BUSY_RX; 8004d0e: 68fb ldr r3, [r7, #12] 8004d10: 2204 movs r2, #4 8004d12: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); 8004d16: 88fa ldrh r2, [r7, #6] 8004d18: 683b ldr r3, [r7, #0] 8004d1a: 9300 str r3, [sp, #0] 8004d1c: 4613 mov r3, r2 8004d1e: 68ba ldr r2, [r7, #8] 8004d20: 68b9 ldr r1, [r7, #8] 8004d22: 68f8 ldr r0, [r7, #12] 8004d24: f000 f8f3 bl 8004f0e <HAL_SPI_TransmitReceive> 8004d28: 4603 mov r3, r0 8004d2a: e0ec b.n 8004f06 <HAL_SPI_Receive+0x22a> } /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8004d2c: f7fd ff1a bl 8002b64 <HAL_GetTick> 8004d30: 6178 str r0, [r7, #20] if ((pData == NULL) || (Size == 0U)) 8004d32: 68bb ldr r3, [r7, #8] 8004d34: 2b00 cmp r3, #0 8004d36: d002 beq.n 8004d3e <HAL_SPI_Receive+0x62> 8004d38: 88fb ldrh r3, [r7, #6] 8004d3a: 2b00 cmp r3, #0 8004d3c: d101 bne.n 8004d42 <HAL_SPI_Receive+0x66> { return HAL_ERROR; 8004d3e: 2301 movs r3, #1 8004d40: e0e1 b.n 8004f06 <HAL_SPI_Receive+0x22a> } /* Process Locked */ __HAL_LOCK(hspi); 8004d42: 68fb ldr r3, [r7, #12] 8004d44: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 8004d48: 2b01 cmp r3, #1 8004d4a: d101 bne.n 8004d50 <HAL_SPI_Receive+0x74> 8004d4c: 2302 movs r3, #2 8004d4e: e0da b.n 8004f06 <HAL_SPI_Receive+0x22a> 8004d50: 68fb ldr r3, [r7, #12] 8004d52: 2201 movs r2, #1 8004d54: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; 8004d58: 68fb ldr r3, [r7, #12] 8004d5a: 2204 movs r2, #4 8004d5c: f883 2051 strb.w r2, [r3, #81] ; 0x51 hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004d60: 68fb ldr r3, [r7, #12] 8004d62: 2200 movs r2, #0 8004d64: 655a str r2, [r3, #84] ; 0x54 hspi->pRxBuffPtr = (uint8_t *)pData; 8004d66: 68fb ldr r3, [r7, #12] 8004d68: 68ba ldr r2, [r7, #8] 8004d6a: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = Size; 8004d6c: 68fb ldr r3, [r7, #12] 8004d6e: 88fa ldrh r2, [r7, #6] 8004d70: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = Size; 8004d72: 68fb ldr r3, [r7, #12] 8004d74: 88fa ldrh r2, [r7, #6] 8004d76: 87da strh r2, [r3, #62] ; 0x3e /*Init field not used in handle to zero */ hspi->pTxBuffPtr = (uint8_t *)NULL; 8004d78: 68fb ldr r3, [r7, #12] 8004d7a: 2200 movs r2, #0 8004d7c: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = 0U; 8004d7e: 68fb ldr r3, [r7, #12] 8004d80: 2200 movs r2, #0 8004d82: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = 0U; 8004d84: 68fb ldr r3, [r7, #12] 8004d86: 2200 movs r2, #0 8004d88: 86da strh r2, [r3, #54] ; 0x36 hspi->RxISR = NULL; 8004d8a: 68fb ldr r3, [r7, #12] 8004d8c: 2200 movs r2, #0 8004d8e: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = NULL; 8004d90: 68fb ldr r3, [r7, #12] 8004d92: 2200 movs r2, #0 8004d94: 645a str r2, [r3, #68] ; 0x44 hspi->RxXferCount--; } #endif /* USE_SPI_CRC */ /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 8004d96: 68fb ldr r3, [r7, #12] 8004d98: 689b ldr r3, [r3, #8] 8004d9a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004d9e: d10f bne.n 8004dc0 <HAL_SPI_Receive+0xe4> { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8004da0: 68fb ldr r3, [r7, #12] 8004da2: 681b ldr r3, [r3, #0] 8004da4: 681a ldr r2, [r3, #0] 8004da6: 68fb ldr r3, [r7, #12] 8004da8: 681b ldr r3, [r3, #0] 8004daa: f022 0240 bic.w r2, r2, #64 ; 0x40 8004dae: 601a str r2, [r3, #0] SPI_1LINE_RX(hspi); 8004db0: 68fb ldr r3, [r7, #12] 8004db2: 681b ldr r3, [r3, #0] 8004db4: 681a ldr r2, [r3, #0] 8004db6: 68fb ldr r3, [r7, #12] 8004db8: 681b ldr r3, [r3, #0] 8004dba: f422 4280 bic.w r2, r2, #16384 ; 0x4000 8004dbe: 601a str r2, [r3, #0] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004dc0: 68fb ldr r3, [r7, #12] 8004dc2: 681b ldr r3, [r3, #0] 8004dc4: 681b ldr r3, [r3, #0] 8004dc6: f003 0340 and.w r3, r3, #64 ; 0x40 8004dca: 2b40 cmp r3, #64 ; 0x40 8004dcc: d007 beq.n 8004dde <HAL_SPI_Receive+0x102> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004dce: 68fb ldr r3, [r7, #12] 8004dd0: 681b ldr r3, [r3, #0] 8004dd2: 681a ldr r2, [r3, #0] 8004dd4: 68fb ldr r3, [r7, #12] 8004dd6: 681b ldr r3, [r3, #0] 8004dd8: f042 0240 orr.w r2, r2, #64 ; 0x40 8004ddc: 601a str r2, [r3, #0] } /* Receive data in 8 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) 8004dde: 68fb ldr r3, [r7, #12] 8004de0: 68db ldr r3, [r3, #12] 8004de2: 2b00 cmp r3, #0 8004de4: d170 bne.n 8004ec8 <HAL_SPI_Receive+0x1ec> { /* Transfer loop */ while (hspi->RxXferCount > 0U) 8004de6: e035 b.n 8004e54 <HAL_SPI_Receive+0x178> { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 8004de8: 68fb ldr r3, [r7, #12] 8004dea: 681b ldr r3, [r3, #0] 8004dec: 689b ldr r3, [r3, #8] 8004dee: f003 0301 and.w r3, r3, #1 8004df2: 2b01 cmp r3, #1 8004df4: d115 bne.n 8004e22 <HAL_SPI_Receive+0x146> { /* read the received data */ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 8004df6: 68fb ldr r3, [r7, #12] 8004df8: 681b ldr r3, [r3, #0] 8004dfa: f103 020c add.w r2, r3, #12 8004dfe: 68fb ldr r3, [r7, #12] 8004e00: 6b9b ldr r3, [r3, #56] ; 0x38 8004e02: 7812 ldrb r2, [r2, #0] 8004e04: b2d2 uxtb r2, r2 8004e06: 701a strb r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint8_t); 8004e08: 68fb ldr r3, [r7, #12] 8004e0a: 6b9b ldr r3, [r3, #56] ; 0x38 8004e0c: 1c5a adds r2, r3, #1 8004e0e: 68fb ldr r3, [r7, #12] 8004e10: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8004e12: 68fb ldr r3, [r7, #12] 8004e14: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004e16: b29b uxth r3, r3 8004e18: 3b01 subs r3, #1 8004e1a: b29a uxth r2, r3 8004e1c: 68fb ldr r3, [r7, #12] 8004e1e: 87da strh r2, [r3, #62] ; 0x3e 8004e20: e018 b.n 8004e54 <HAL_SPI_Receive+0x178> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8004e22: f7fd fe9f bl 8002b64 <HAL_GetTick> 8004e26: 4602 mov r2, r0 8004e28: 697b ldr r3, [r7, #20] 8004e2a: 1ad3 subs r3, r2, r3 8004e2c: 683a ldr r2, [r7, #0] 8004e2e: 429a cmp r2, r3 8004e30: d803 bhi.n 8004e3a <HAL_SPI_Receive+0x15e> 8004e32: 683b ldr r3, [r7, #0] 8004e34: f1b3 3fff cmp.w r3, #4294967295 8004e38: d102 bne.n 8004e40 <HAL_SPI_Receive+0x164> 8004e3a: 683b ldr r3, [r7, #0] 8004e3c: 2b00 cmp r3, #0 8004e3e: d109 bne.n 8004e54 <HAL_SPI_Receive+0x178> { hspi->State = HAL_SPI_STATE_READY; 8004e40: 68fb ldr r3, [r7, #12] 8004e42: 2201 movs r2, #1 8004e44: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004e48: 68fb ldr r3, [r7, #12] 8004e4a: 2200 movs r2, #0 8004e4c: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 8004e50: 2303 movs r3, #3 8004e52: e058 b.n 8004f06 <HAL_SPI_Receive+0x22a> while (hspi->RxXferCount > 0U) 8004e54: 68fb ldr r3, [r7, #12] 8004e56: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004e58: b29b uxth r3, r3 8004e5a: 2b00 cmp r3, #0 8004e5c: d1c4 bne.n 8004de8 <HAL_SPI_Receive+0x10c> 8004e5e: e038 b.n 8004ed2 <HAL_SPI_Receive+0x1f6> { /* Transfer loop */ while (hspi->RxXferCount > 0U) { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 8004e60: 68fb ldr r3, [r7, #12] 8004e62: 681b ldr r3, [r3, #0] 8004e64: 689b ldr r3, [r3, #8] 8004e66: f003 0301 and.w r3, r3, #1 8004e6a: 2b01 cmp r3, #1 8004e6c: d113 bne.n 8004e96 <HAL_SPI_Receive+0x1ba> { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 8004e6e: 68fb ldr r3, [r7, #12] 8004e70: 681b ldr r3, [r3, #0] 8004e72: 68da ldr r2, [r3, #12] 8004e74: 68fb ldr r3, [r7, #12] 8004e76: 6b9b ldr r3, [r3, #56] ; 0x38 8004e78: b292 uxth r2, r2 8004e7a: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8004e7c: 68fb ldr r3, [r7, #12] 8004e7e: 6b9b ldr r3, [r3, #56] ; 0x38 8004e80: 1c9a adds r2, r3, #2 8004e82: 68fb ldr r3, [r7, #12] 8004e84: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8004e86: 68fb ldr r3, [r7, #12] 8004e88: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004e8a: b29b uxth r3, r3 8004e8c: 3b01 subs r3, #1 8004e8e: b29a uxth r2, r3 8004e90: 68fb ldr r3, [r7, #12] 8004e92: 87da strh r2, [r3, #62] ; 0x3e 8004e94: e018 b.n 8004ec8 <HAL_SPI_Receive+0x1ec> } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8004e96: f7fd fe65 bl 8002b64 <HAL_GetTick> 8004e9a: 4602 mov r2, r0 8004e9c: 697b ldr r3, [r7, #20] 8004e9e: 1ad3 subs r3, r2, r3 8004ea0: 683a ldr r2, [r7, #0] 8004ea2: 429a cmp r2, r3 8004ea4: d803 bhi.n 8004eae <HAL_SPI_Receive+0x1d2> 8004ea6: 683b ldr r3, [r7, #0] 8004ea8: f1b3 3fff cmp.w r3, #4294967295 8004eac: d102 bne.n 8004eb4 <HAL_SPI_Receive+0x1d8> 8004eae: 683b ldr r3, [r7, #0] 8004eb0: 2b00 cmp r3, #0 8004eb2: d109 bne.n 8004ec8 <HAL_SPI_Receive+0x1ec> { hspi->State = HAL_SPI_STATE_READY; 8004eb4: 68fb ldr r3, [r7, #12] 8004eb6: 2201 movs r2, #1 8004eb8: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 8004ebc: 68fb ldr r3, [r7, #12] 8004ebe: 2200 movs r2, #0 8004ec0: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 8004ec4: 2303 movs r3, #3 8004ec6: e01e b.n 8004f06 <HAL_SPI_Receive+0x22a> while (hspi->RxXferCount > 0U) 8004ec8: 68fb ldr r3, [r7, #12] 8004eca: 8fdb ldrh r3, [r3, #62] ; 0x3e 8004ecc: b29b uxth r3, r3 8004ece: 2b00 cmp r3, #0 8004ed0: d1c6 bne.n 8004e60 <HAL_SPI_Receive+0x184> UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) 8004ed2: 697a ldr r2, [r7, #20] 8004ed4: 6839 ldr r1, [r7, #0] 8004ed6: 68f8 ldr r0, [r7, #12] 8004ed8: f000 fc9c bl 8005814 <SPI_EndRxTransaction> 8004edc: 4603 mov r3, r0 8004ede: 2b00 cmp r3, #0 8004ee0: d002 beq.n 8004ee8 <HAL_SPI_Receive+0x20c> { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8004ee2: 68fb ldr r3, [r7, #12] 8004ee4: 2220 movs r2, #32 8004ee6: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } #endif /* USE_SPI_CRC */ hspi->State = HAL_SPI_STATE_READY; 8004ee8: 68fb ldr r3, [r7, #12] 8004eea: 2201 movs r2, #1 8004eec: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Unlock the process */ __HAL_UNLOCK(hspi); 8004ef0: 68fb ldr r3, [r7, #12] 8004ef2: 2200 movs r2, #0 8004ef4: f883 2050 strb.w r2, [r3, #80] ; 0x50 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8004ef8: 68fb ldr r3, [r7, #12] 8004efa: 6d5b ldr r3, [r3, #84] ; 0x54 8004efc: 2b00 cmp r3, #0 8004efe: d001 beq.n 8004f04 <HAL_SPI_Receive+0x228> { return HAL_ERROR; 8004f00: 2301 movs r3, #1 8004f02: e000 b.n 8004f06 <HAL_SPI_Receive+0x22a> } else { return HAL_OK; 8004f04: 2300 movs r3, #0 } } 8004f06: 4618 mov r0, r3 8004f08: 3718 adds r7, #24 8004f0a: 46bd mov sp, r7 8004f0c: bd80 pop {r7, pc} 08004f0e <HAL_SPI_TransmitReceive>: * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 8004f0e: b580 push {r7, lr} 8004f10: b08a sub sp, #40 ; 0x28 8004f12: af00 add r7, sp, #0 8004f14: 60f8 str r0, [r7, #12] 8004f16: 60b9 str r1, [r7, #8] 8004f18: 607a str r2, [r7, #4] 8004f1a: 807b strh r3, [r7, #2] #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 8004f1c: 2301 movs r3, #1 8004f1e: 627b str r3, [r7, #36] ; 0x24 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8004f20: f7fd fe20 bl 8002b64 <HAL_GetTick> 8004f24: 6238 str r0, [r7, #32] /* Init temporary variables */ tmp_state = hspi->State; 8004f26: 68fb ldr r3, [r7, #12] 8004f28: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004f2c: 77fb strb r3, [r7, #31] tmp_mode = hspi->Init.Mode; 8004f2e: 68fb ldr r3, [r7, #12] 8004f30: 685b ldr r3, [r3, #4] 8004f32: 61bb str r3, [r7, #24] initial_TxXferCount = Size; 8004f34: 887b ldrh r3, [r7, #2] 8004f36: 82fb strh r3, [r7, #22] if (!((tmp_state == HAL_SPI_STATE_READY) || \ 8004f38: 7ffb ldrb r3, [r7, #31] 8004f3a: 2b01 cmp r3, #1 8004f3c: d00c beq.n 8004f58 <HAL_SPI_TransmitReceive+0x4a> 8004f3e: 69bb ldr r3, [r7, #24] 8004f40: f5b3 7f82 cmp.w r3, #260 ; 0x104 8004f44: d106 bne.n 8004f54 <HAL_SPI_TransmitReceive+0x46> ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 8004f46: 68fb ldr r3, [r7, #12] 8004f48: 689b ldr r3, [r3, #8] 8004f4a: 2b00 cmp r3, #0 8004f4c: d102 bne.n 8004f54 <HAL_SPI_TransmitReceive+0x46> 8004f4e: 7ffb ldrb r3, [r7, #31] 8004f50: 2b04 cmp r3, #4 8004f52: d001 beq.n 8004f58 <HAL_SPI_TransmitReceive+0x4a> (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 8004f54: 2302 movs r3, #2 8004f56: e17f b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 8004f58: 68bb ldr r3, [r7, #8] 8004f5a: 2b00 cmp r3, #0 8004f5c: d005 beq.n 8004f6a <HAL_SPI_TransmitReceive+0x5c> 8004f5e: 687b ldr r3, [r7, #4] 8004f60: 2b00 cmp r3, #0 8004f62: d002 beq.n 8004f6a <HAL_SPI_TransmitReceive+0x5c> 8004f64: 887b ldrh r3, [r7, #2] 8004f66: 2b00 cmp r3, #0 8004f68: d101 bne.n 8004f6e <HAL_SPI_TransmitReceive+0x60> { return HAL_ERROR; 8004f6a: 2301 movs r3, #1 8004f6c: e174 b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> } /* Process Locked */ __HAL_LOCK(hspi); 8004f6e: 68fb ldr r3, [r7, #12] 8004f70: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 8004f74: 2b01 cmp r3, #1 8004f76: d101 bne.n 8004f7c <HAL_SPI_TransmitReceive+0x6e> 8004f78: 2302 movs r3, #2 8004f7a: e16d b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> 8004f7c: 68fb ldr r3, [r7, #12] 8004f7e: 2201 movs r2, #1 8004f80: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 8004f84: 68fb ldr r3, [r7, #12] 8004f86: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004f8a: b2db uxtb r3, r3 8004f8c: 2b04 cmp r3, #4 8004f8e: d003 beq.n 8004f98 <HAL_SPI_TransmitReceive+0x8a> { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 8004f90: 68fb ldr r3, [r7, #12] 8004f92: 2205 movs r2, #5 8004f94: f883 2051 strb.w r2, [r3, #81] ; 0x51 } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004f98: 68fb ldr r3, [r7, #12] 8004f9a: 2200 movs r2, #0 8004f9c: 655a str r2, [r3, #84] ; 0x54 hspi->pRxBuffPtr = (uint8_t *)pRxData; 8004f9e: 68fb ldr r3, [r7, #12] 8004fa0: 687a ldr r2, [r7, #4] 8004fa2: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount = Size; 8004fa4: 68fb ldr r3, [r7, #12] 8004fa6: 887a ldrh r2, [r7, #2] 8004fa8: 87da strh r2, [r3, #62] ; 0x3e hspi->RxXferSize = Size; 8004faa: 68fb ldr r3, [r7, #12] 8004fac: 887a ldrh r2, [r7, #2] 8004fae: 879a strh r2, [r3, #60] ; 0x3c hspi->pTxBuffPtr = (const uint8_t *)pTxData; 8004fb0: 68fb ldr r3, [r7, #12] 8004fb2: 68ba ldr r2, [r7, #8] 8004fb4: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount = Size; 8004fb6: 68fb ldr r3, [r7, #12] 8004fb8: 887a ldrh r2, [r7, #2] 8004fba: 86da strh r2, [r3, #54] ; 0x36 hspi->TxXferSize = Size; 8004fbc: 68fb ldr r3, [r7, #12] 8004fbe: 887a ldrh r2, [r7, #2] 8004fc0: 869a strh r2, [r3, #52] ; 0x34 /*Init field not used in handle to zero */ hspi->RxISR = NULL; 8004fc2: 68fb ldr r3, [r7, #12] 8004fc4: 2200 movs r2, #0 8004fc6: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = NULL; 8004fc8: 68fb ldr r3, [r7, #12] 8004fca: 2200 movs r2, #0 8004fcc: 645a str r2, [r3, #68] ; 0x44 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004fce: 68fb ldr r3, [r7, #12] 8004fd0: 681b ldr r3, [r3, #0] 8004fd2: 681b ldr r3, [r3, #0] 8004fd4: f003 0340 and.w r3, r3, #64 ; 0x40 8004fd8: 2b40 cmp r3, #64 ; 0x40 8004fda: d007 beq.n 8004fec <HAL_SPI_TransmitReceive+0xde> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004fdc: 68fb ldr r3, [r7, #12] 8004fde: 681b ldr r3, [r3, #0] 8004fe0: 681a ldr r2, [r3, #0] 8004fe2: 68fb ldr r3, [r7, #12] 8004fe4: 681b ldr r3, [r3, #0] 8004fe6: f042 0240 orr.w r2, r2, #64 ; 0x40 8004fea: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) 8004fec: 68fb ldr r3, [r7, #12] 8004fee: 68db ldr r3, [r3, #12] 8004ff0: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8004ff4: d17e bne.n 80050f4 <HAL_SPI_TransmitReceive+0x1e6> { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004ff6: 68fb ldr r3, [r7, #12] 8004ff8: 685b ldr r3, [r3, #4] 8004ffa: 2b00 cmp r3, #0 8004ffc: d002 beq.n 8005004 <HAL_SPI_TransmitReceive+0xf6> 8004ffe: 8afb ldrh r3, [r7, #22] 8005000: 2b01 cmp r3, #1 8005002: d16c bne.n 80050de <HAL_SPI_TransmitReceive+0x1d0> { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8005004: 68fb ldr r3, [r7, #12] 8005006: 6b1b ldr r3, [r3, #48] ; 0x30 8005008: 881a ldrh r2, [r3, #0] 800500a: 68fb ldr r3, [r7, #12] 800500c: 681b ldr r3, [r3, #0] 800500e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8005010: 68fb ldr r3, [r7, #12] 8005012: 6b1b ldr r3, [r3, #48] ; 0x30 8005014: 1c9a adds r2, r3, #2 8005016: 68fb ldr r3, [r7, #12] 8005018: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 800501a: 68fb ldr r3, [r7, #12] 800501c: 8edb ldrh r3, [r3, #54] ; 0x36 800501e: b29b uxth r3, r3 8005020: 3b01 subs r3, #1 8005022: b29a uxth r2, r3 8005024: 68fb ldr r3, [r7, #12] 8005026: 86da strh r2, [r3, #54] ; 0x36 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8005028: e059 b.n 80050de <HAL_SPI_TransmitReceive+0x1d0> { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800502a: 68fb ldr r3, [r7, #12] 800502c: 681b ldr r3, [r3, #0] 800502e: 689b ldr r3, [r3, #8] 8005030: f003 0302 and.w r3, r3, #2 8005034: 2b02 cmp r3, #2 8005036: d11b bne.n 8005070 <HAL_SPI_TransmitReceive+0x162> 8005038: 68fb ldr r3, [r7, #12] 800503a: 8edb ldrh r3, [r3, #54] ; 0x36 800503c: b29b uxth r3, r3 800503e: 2b00 cmp r3, #0 8005040: d016 beq.n 8005070 <HAL_SPI_TransmitReceive+0x162> 8005042: 6a7b ldr r3, [r7, #36] ; 0x24 8005044: 2b01 cmp r3, #1 8005046: d113 bne.n 8005070 <HAL_SPI_TransmitReceive+0x162> { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8005048: 68fb ldr r3, [r7, #12] 800504a: 6b1b ldr r3, [r3, #48] ; 0x30 800504c: 881a ldrh r2, [r3, #0] 800504e: 68fb ldr r3, [r7, #12] 8005050: 681b ldr r3, [r3, #0] 8005052: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8005054: 68fb ldr r3, [r7, #12] 8005056: 6b1b ldr r3, [r3, #48] ; 0x30 8005058: 1c9a adds r2, r3, #2 800505a: 68fb ldr r3, [r7, #12] 800505c: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 800505e: 68fb ldr r3, [r7, #12] 8005060: 8edb ldrh r3, [r3, #54] ; 0x36 8005062: b29b uxth r3, r3 8005064: 3b01 subs r3, #1 8005066: b29a uxth r2, r3 8005068: 68fb ldr r3, [r7, #12] 800506a: 86da strh r2, [r3, #54] ; 0x36 /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800506c: 2300 movs r3, #0 800506e: 627b str r3, [r7, #36] ; 0x24 } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 8005070: 68fb ldr r3, [r7, #12] 8005072: 681b ldr r3, [r3, #0] 8005074: 689b ldr r3, [r3, #8] 8005076: f003 0301 and.w r3, r3, #1 800507a: 2b01 cmp r3, #1 800507c: d119 bne.n 80050b2 <HAL_SPI_TransmitReceive+0x1a4> 800507e: 68fb ldr r3, [r7, #12] 8005080: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005082: b29b uxth r3, r3 8005084: 2b00 cmp r3, #0 8005086: d014 beq.n 80050b2 <HAL_SPI_TransmitReceive+0x1a4> { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 8005088: 68fb ldr r3, [r7, #12] 800508a: 681b ldr r3, [r3, #0] 800508c: 68da ldr r2, [r3, #12] 800508e: 68fb ldr r3, [r7, #12] 8005090: 6b9b ldr r3, [r3, #56] ; 0x38 8005092: b292 uxth r2, r2 8005094: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8005096: 68fb ldr r3, [r7, #12] 8005098: 6b9b ldr r3, [r3, #56] ; 0x38 800509a: 1c9a adds r2, r3, #2 800509c: 68fb ldr r3, [r7, #12] 800509e: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 80050a0: 68fb ldr r3, [r7, #12] 80050a2: 8fdb ldrh r3, [r3, #62] ; 0x3e 80050a4: b29b uxth r3, r3 80050a6: 3b01 subs r3, #1 80050a8: b29a uxth r2, r3 80050aa: 68fb ldr r3, [r7, #12] 80050ac: 87da strh r2, [r3, #62] ; 0x3e /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 80050ae: 2301 movs r3, #1 80050b0: 627b str r3, [r7, #36] ; 0x24 } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 80050b2: f7fd fd57 bl 8002b64 <HAL_GetTick> 80050b6: 4602 mov r2, r0 80050b8: 6a3b ldr r3, [r7, #32] 80050ba: 1ad3 subs r3, r2, r3 80050bc: 6b3a ldr r2, [r7, #48] ; 0x30 80050be: 429a cmp r2, r3 80050c0: d80d bhi.n 80050de <HAL_SPI_TransmitReceive+0x1d0> 80050c2: 6b3b ldr r3, [r7, #48] ; 0x30 80050c4: f1b3 3fff cmp.w r3, #4294967295 80050c8: d009 beq.n 80050de <HAL_SPI_TransmitReceive+0x1d0> { hspi->State = HAL_SPI_STATE_READY; 80050ca: 68fb ldr r3, [r7, #12] 80050cc: 2201 movs r2, #1 80050ce: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 80050d2: 68fb ldr r3, [r7, #12] 80050d4: 2200 movs r2, #0 80050d6: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 80050da: 2303 movs r3, #3 80050dc: e0bc b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 80050de: 68fb ldr r3, [r7, #12] 80050e0: 8edb ldrh r3, [r3, #54] ; 0x36 80050e2: b29b uxth r3, r3 80050e4: 2b00 cmp r3, #0 80050e6: d1a0 bne.n 800502a <HAL_SPI_TransmitReceive+0x11c> 80050e8: 68fb ldr r3, [r7, #12] 80050ea: 8fdb ldrh r3, [r3, #62] ; 0x3e 80050ec: b29b uxth r3, r3 80050ee: 2b00 cmp r3, #0 80050f0: d19b bne.n 800502a <HAL_SPI_TransmitReceive+0x11c> 80050f2: e082 b.n 80051fa <HAL_SPI_TransmitReceive+0x2ec> } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 80050f4: 68fb ldr r3, [r7, #12] 80050f6: 685b ldr r3, [r3, #4] 80050f8: 2b00 cmp r3, #0 80050fa: d002 beq.n 8005102 <HAL_SPI_TransmitReceive+0x1f4> 80050fc: 8afb ldrh r3, [r7, #22] 80050fe: 2b01 cmp r3, #1 8005100: d171 bne.n 80051e6 <HAL_SPI_TransmitReceive+0x2d8> { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 8005102: 68fb ldr r3, [r7, #12] 8005104: 6b1a ldr r2, [r3, #48] ; 0x30 8005106: 68fb ldr r3, [r7, #12] 8005108: 681b ldr r3, [r3, #0] 800510a: 330c adds r3, #12 800510c: 7812 ldrb r2, [r2, #0] 800510e: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8005110: 68fb ldr r3, [r7, #12] 8005112: 6b1b ldr r3, [r3, #48] ; 0x30 8005114: 1c5a adds r2, r3, #1 8005116: 68fb ldr r3, [r7, #12] 8005118: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 800511a: 68fb ldr r3, [r7, #12] 800511c: 8edb ldrh r3, [r3, #54] ; 0x36 800511e: b29b uxth r3, r3 8005120: 3b01 subs r3, #1 8005122: b29a uxth r2, r3 8005124: 68fb ldr r3, [r7, #12] 8005126: 86da strh r2, [r3, #54] ; 0x36 { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8005128: e05d b.n 80051e6 <HAL_SPI_TransmitReceive+0x2d8> { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800512a: 68fb ldr r3, [r7, #12] 800512c: 681b ldr r3, [r3, #0] 800512e: 689b ldr r3, [r3, #8] 8005130: f003 0302 and.w r3, r3, #2 8005134: 2b02 cmp r3, #2 8005136: d11c bne.n 8005172 <HAL_SPI_TransmitReceive+0x264> 8005138: 68fb ldr r3, [r7, #12] 800513a: 8edb ldrh r3, [r3, #54] ; 0x36 800513c: b29b uxth r3, r3 800513e: 2b00 cmp r3, #0 8005140: d017 beq.n 8005172 <HAL_SPI_TransmitReceive+0x264> 8005142: 6a7b ldr r3, [r7, #36] ; 0x24 8005144: 2b01 cmp r3, #1 8005146: d114 bne.n 8005172 <HAL_SPI_TransmitReceive+0x264> { *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 8005148: 68fb ldr r3, [r7, #12] 800514a: 6b1a ldr r2, [r3, #48] ; 0x30 800514c: 68fb ldr r3, [r7, #12] 800514e: 681b ldr r3, [r3, #0] 8005150: 330c adds r3, #12 8005152: 7812 ldrb r2, [r2, #0] 8005154: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8005156: 68fb ldr r3, [r7, #12] 8005158: 6b1b ldr r3, [r3, #48] ; 0x30 800515a: 1c5a adds r2, r3, #1 800515c: 68fb ldr r3, [r7, #12] 800515e: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8005160: 68fb ldr r3, [r7, #12] 8005162: 8edb ldrh r3, [r3, #54] ; 0x36 8005164: b29b uxth r3, r3 8005166: 3b01 subs r3, #1 8005168: b29a uxth r2, r3 800516a: 68fb ldr r3, [r7, #12] 800516c: 86da strh r2, [r3, #54] ; 0x36 /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800516e: 2300 movs r3, #0 8005170: 627b str r3, [r7, #36] ; 0x24 } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 8005172: 68fb ldr r3, [r7, #12] 8005174: 681b ldr r3, [r3, #0] 8005176: 689b ldr r3, [r3, #8] 8005178: f003 0301 and.w r3, r3, #1 800517c: 2b01 cmp r3, #1 800517e: d119 bne.n 80051b4 <HAL_SPI_TransmitReceive+0x2a6> 8005180: 68fb ldr r3, [r7, #12] 8005182: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005184: b29b uxth r3, r3 8005186: 2b00 cmp r3, #0 8005188: d014 beq.n 80051b4 <HAL_SPI_TransmitReceive+0x2a6> { (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; 800518a: 68fb ldr r3, [r7, #12] 800518c: 681b ldr r3, [r3, #0] 800518e: 68da ldr r2, [r3, #12] 8005190: 68fb ldr r3, [r7, #12] 8005192: 6b9b ldr r3, [r3, #56] ; 0x38 8005194: b2d2 uxtb r2, r2 8005196: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 8005198: 68fb ldr r3, [r7, #12] 800519a: 6b9b ldr r3, [r3, #56] ; 0x38 800519c: 1c5a adds r2, r3, #1 800519e: 68fb ldr r3, [r7, #12] 80051a0: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 80051a2: 68fb ldr r3, [r7, #12] 80051a4: 8fdb ldrh r3, [r3, #62] ; 0x3e 80051a6: b29b uxth r3, r3 80051a8: 3b01 subs r3, #1 80051aa: b29a uxth r2, r3 80051ac: 68fb ldr r3, [r7, #12] 80051ae: 87da strh r2, [r3, #62] ; 0x3e /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 80051b0: 2301 movs r3, #1 80051b2: 627b str r3, [r7, #36] ; 0x24 } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 80051b4: f7fd fcd6 bl 8002b64 <HAL_GetTick> 80051b8: 4602 mov r2, r0 80051ba: 6a3b ldr r3, [r7, #32] 80051bc: 1ad3 subs r3, r2, r3 80051be: 6b3a ldr r2, [r7, #48] ; 0x30 80051c0: 429a cmp r2, r3 80051c2: d803 bhi.n 80051cc <HAL_SPI_TransmitReceive+0x2be> 80051c4: 6b3b ldr r3, [r7, #48] ; 0x30 80051c6: f1b3 3fff cmp.w r3, #4294967295 80051ca: d102 bne.n 80051d2 <HAL_SPI_TransmitReceive+0x2c4> 80051cc: 6b3b ldr r3, [r7, #48] ; 0x30 80051ce: 2b00 cmp r3, #0 80051d0: d109 bne.n 80051e6 <HAL_SPI_TransmitReceive+0x2d8> { hspi->State = HAL_SPI_STATE_READY; 80051d2: 68fb ldr r3, [r7, #12] 80051d4: 2201 movs r2, #1 80051d6: f883 2051 strb.w r2, [r3, #81] ; 0x51 __HAL_UNLOCK(hspi); 80051da: 68fb ldr r3, [r7, #12] 80051dc: 2200 movs r2, #0 80051de: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 80051e2: 2303 movs r3, #3 80051e4: e038 b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 80051e6: 68fb ldr r3, [r7, #12] 80051e8: 8edb ldrh r3, [r3, #54] ; 0x36 80051ea: b29b uxth r3, r3 80051ec: 2b00 cmp r3, #0 80051ee: d19c bne.n 800512a <HAL_SPI_TransmitReceive+0x21c> 80051f0: 68fb ldr r3, [r7, #12] 80051f2: 8fdb ldrh r3, [r3, #62] ; 0x3e 80051f4: b29b uxth r3, r3 80051f6: 2b00 cmp r3, #0 80051f8: d197 bne.n 800512a <HAL_SPI_TransmitReceive+0x21c> } } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 80051fa: 6a3a ldr r2, [r7, #32] 80051fc: 6b39 ldr r1, [r7, #48] ; 0x30 80051fe: 68f8 ldr r0, [r7, #12] 8005200: f000 fb5a bl 80058b8 <SPI_EndRxTxTransaction> 8005204: 4603 mov r3, r0 8005206: 2b00 cmp r3, #0 8005208: d008 beq.n 800521c <HAL_SPI_TransmitReceive+0x30e> { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800520a: 68fb ldr r3, [r7, #12] 800520c: 2220 movs r2, #32 800520e: 655a str r2, [r3, #84] ; 0x54 __HAL_UNLOCK(hspi); 8005210: 68fb ldr r3, [r7, #12] 8005212: 2200 movs r2, #0 8005214: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_ERROR; 8005218: 2301 movs r3, #1 800521a: e01d b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 800521c: 68fb ldr r3, [r7, #12] 800521e: 689b ldr r3, [r3, #8] 8005220: 2b00 cmp r3, #0 8005222: d10a bne.n 800523a <HAL_SPI_TransmitReceive+0x32c> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8005224: 2300 movs r3, #0 8005226: 613b str r3, [r7, #16] 8005228: 68fb ldr r3, [r7, #12] 800522a: 681b ldr r3, [r3, #0] 800522c: 68db ldr r3, [r3, #12] 800522e: 613b str r3, [r7, #16] 8005230: 68fb ldr r3, [r7, #12] 8005232: 681b ldr r3, [r3, #0] 8005234: 689b ldr r3, [r3, #8] 8005236: 613b str r3, [r7, #16] 8005238: 693b ldr r3, [r7, #16] } hspi->State = HAL_SPI_STATE_READY; 800523a: 68fb ldr r3, [r7, #12] 800523c: 2201 movs r2, #1 800523e: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Unlock the process */ __HAL_UNLOCK(hspi); 8005242: 68fb ldr r3, [r7, #12] 8005244: 2200 movs r2, #0 8005246: f883 2050 strb.w r2, [r3, #80] ; 0x50 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800524a: 68fb ldr r3, [r7, #12] 800524c: 6d5b ldr r3, [r3, #84] ; 0x54 800524e: 2b00 cmp r3, #0 8005250: d001 beq.n 8005256 <HAL_SPI_TransmitReceive+0x348> { return HAL_ERROR; 8005252: 2301 movs r3, #1 8005254: e000 b.n 8005258 <HAL_SPI_TransmitReceive+0x34a> } else { return HAL_OK; 8005256: 2300 movs r3, #0 } } 8005258: 4618 mov r0, r3 800525a: 3728 adds r7, #40 ; 0x28 800525c: 46bd mov sp, r7 800525e: bd80 pop {r7, pc} 08005260 <HAL_SPI_TransmitReceive_IT>: * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { 8005260: b480 push {r7} 8005262: b087 sub sp, #28 8005264: af00 add r7, sp, #0 8005266: 60f8 str r0, [r7, #12] 8005268: 60b9 str r1, [r7, #8] 800526a: 607a str r2, [r7, #4] 800526c: 807b strh r3, [r7, #2] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init temporary variables */ tmp_state = hspi->State; 800526e: 68fb ldr r3, [r7, #12] 8005270: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8005274: 75fb strb r3, [r7, #23] tmp_mode = hspi->Init.Mode; 8005276: 68fb ldr r3, [r7, #12] 8005278: 685b ldr r3, [r3, #4] 800527a: 613b str r3, [r7, #16] if (!((tmp_state == HAL_SPI_STATE_READY) || \ 800527c: 7dfb ldrb r3, [r7, #23] 800527e: 2b01 cmp r3, #1 8005280: d00c beq.n 800529c <HAL_SPI_TransmitReceive_IT+0x3c> 8005282: 693b ldr r3, [r7, #16] 8005284: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005288: d106 bne.n 8005298 <HAL_SPI_TransmitReceive_IT+0x38> ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 800528a: 68fb ldr r3, [r7, #12] 800528c: 689b ldr r3, [r3, #8] 800528e: 2b00 cmp r3, #0 8005290: d102 bne.n 8005298 <HAL_SPI_TransmitReceive_IT+0x38> 8005292: 7dfb ldrb r3, [r7, #23] 8005294: 2b04 cmp r3, #4 8005296: d001 beq.n 800529c <HAL_SPI_TransmitReceive_IT+0x3c> (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 8005298: 2302 movs r3, #2 800529a: e061 b.n 8005360 <HAL_SPI_TransmitReceive_IT+0x100> } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 800529c: 68bb ldr r3, [r7, #8] 800529e: 2b00 cmp r3, #0 80052a0: d005 beq.n 80052ae <HAL_SPI_TransmitReceive_IT+0x4e> 80052a2: 687b ldr r3, [r7, #4] 80052a4: 2b00 cmp r3, #0 80052a6: d002 beq.n 80052ae <HAL_SPI_TransmitReceive_IT+0x4e> 80052a8: 887b ldrh r3, [r7, #2] 80052aa: 2b00 cmp r3, #0 80052ac: d101 bne.n 80052b2 <HAL_SPI_TransmitReceive_IT+0x52> { return HAL_ERROR; 80052ae: 2301 movs r3, #1 80052b0: e056 b.n 8005360 <HAL_SPI_TransmitReceive_IT+0x100> } /* Process locked */ __HAL_LOCK(hspi); 80052b2: 68fb ldr r3, [r7, #12] 80052b4: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 80052b8: 2b01 cmp r3, #1 80052ba: d101 bne.n 80052c0 <HAL_SPI_TransmitReceive_IT+0x60> 80052bc: 2302 movs r3, #2 80052be: e04f b.n 8005360 <HAL_SPI_TransmitReceive_IT+0x100> 80052c0: 68fb ldr r3, [r7, #12] 80052c2: 2201 movs r2, #1 80052c4: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 80052c8: 68fb ldr r3, [r7, #12] 80052ca: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80052ce: b2db uxtb r3, r3 80052d0: 2b04 cmp r3, #4 80052d2: d003 beq.n 80052dc <HAL_SPI_TransmitReceive_IT+0x7c> { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 80052d4: 68fb ldr r3, [r7, #12] 80052d6: 2205 movs r2, #5 80052d8: f883 2051 strb.w r2, [r3, #81] ; 0x51 } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80052dc: 68fb ldr r3, [r7, #12] 80052de: 2200 movs r2, #0 80052e0: 655a str r2, [r3, #84] ; 0x54 hspi->pTxBuffPtr = (const uint8_t *)pTxData; 80052e2: 68fb ldr r3, [r7, #12] 80052e4: 68ba ldr r2, [r7, #8] 80052e6: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferSize = Size; 80052e8: 68fb ldr r3, [r7, #12] 80052ea: 887a ldrh r2, [r7, #2] 80052ec: 869a strh r2, [r3, #52] ; 0x34 hspi->TxXferCount = Size; 80052ee: 68fb ldr r3, [r7, #12] 80052f0: 887a ldrh r2, [r7, #2] 80052f2: 86da strh r2, [r3, #54] ; 0x36 hspi->pRxBuffPtr = (uint8_t *)pRxData; 80052f4: 68fb ldr r3, [r7, #12] 80052f6: 687a ldr r2, [r7, #4] 80052f8: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferSize = Size; 80052fa: 68fb ldr r3, [r7, #12] 80052fc: 887a ldrh r2, [r7, #2] 80052fe: 879a strh r2, [r3, #60] ; 0x3c hspi->RxXferCount = Size; 8005300: 68fb ldr r3, [r7, #12] 8005302: 887a ldrh r2, [r7, #2] 8005304: 87da strh r2, [r3, #62] ; 0x3e /* Set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8005306: 68fb ldr r3, [r7, #12] 8005308: 68db ldr r3, [r3, #12] 800530a: 2b00 cmp r3, #0 800530c: d006 beq.n 800531c <HAL_SPI_TransmitReceive_IT+0xbc> { hspi->RxISR = SPI_2linesRxISR_16BIT; 800530e: 68fb ldr r3, [r7, #12] 8005310: 4a16 ldr r2, [pc, #88] ; (800536c <HAL_SPI_TransmitReceive_IT+0x10c>) 8005312: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = SPI_2linesTxISR_16BIT; 8005314: 68fb ldr r3, [r7, #12] 8005316: 4a16 ldr r2, [pc, #88] ; (8005370 <HAL_SPI_TransmitReceive_IT+0x110>) 8005318: 645a str r2, [r3, #68] ; 0x44 800531a: e005 b.n 8005328 <HAL_SPI_TransmitReceive_IT+0xc8> } else { hspi->RxISR = SPI_2linesRxISR_8BIT; 800531c: 68fb ldr r3, [r7, #12] 800531e: 4a15 ldr r2, [pc, #84] ; (8005374 <HAL_SPI_TransmitReceive_IT+0x114>) 8005320: 641a str r2, [r3, #64] ; 0x40 hspi->TxISR = SPI_2linesTxISR_8BIT; 8005322: 68fb ldr r3, [r7, #12] 8005324: 4a14 ldr r2, [pc, #80] ; (8005378 <HAL_SPI_TransmitReceive_IT+0x118>) 8005326: 645a str r2, [r3, #68] ; 0x44 } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8005328: 68fb ldr r3, [r7, #12] 800532a: 681b ldr r3, [r3, #0] 800532c: 681b ldr r3, [r3, #0] 800532e: f003 0340 and.w r3, r3, #64 ; 0x40 8005332: 2b40 cmp r3, #64 ; 0x40 8005334: d007 beq.n 8005346 <HAL_SPI_TransmitReceive_IT+0xe6> { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8005336: 68fb ldr r3, [r7, #12] 8005338: 681b ldr r3, [r3, #0] 800533a: 681a ldr r2, [r3, #0] 800533c: 68fb ldr r3, [r7, #12] 800533e: 681b ldr r3, [r3, #0] 8005340: f042 0240 orr.w r2, r2, #64 ; 0x40 8005344: 601a str r2, [r3, #0] } /* Process Unlocked */ __HAL_UNLOCK(hspi); 8005346: 68fb ldr r3, [r7, #12] 8005348: 2200 movs r2, #0 800534a: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800534e: 68fb ldr r3, [r7, #12] 8005350: 681b ldr r3, [r3, #0] 8005352: 685a ldr r2, [r3, #4] 8005354: 68fb ldr r3, [r7, #12] 8005356: 681b ldr r3, [r3, #0] 8005358: f042 02e0 orr.w r2, r2, #224 ; 0xe0 800535c: 605a str r2, [r3, #4] return HAL_OK; 800535e: 2300 movs r3, #0 } 8005360: 4618 mov r0, r3 8005362: 371c adds r7, #28 8005364: 46bd mov sp, r7 8005366: bc80 pop {r7} 8005368: 4770 bx lr 800536a: bf00 nop 800536c: 08005647 .word 0x08005647 8005370: 080056a7 .word 0x080056a7 8005374: 08005583 .word 0x08005583 8005378: 080055e7 .word 0x080055e7 0800537c <HAL_SPI_IRQHandler>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { 800537c: b580 push {r7, lr} 800537e: b088 sub sp, #32 8005380: af00 add r7, sp, #0 8005382: 6078 str r0, [r7, #4] uint32_t itsource = hspi->Instance->CR2; 8005384: 687b ldr r3, [r7, #4] 8005386: 681b ldr r3, [r3, #0] 8005388: 685b ldr r3, [r3, #4] 800538a: 61fb str r3, [r7, #28] uint32_t itflag = hspi->Instance->SR; 800538c: 687b ldr r3, [r7, #4] 800538e: 681b ldr r3, [r3, #0] 8005390: 689b ldr r3, [r3, #8] 8005392: 61bb str r3, [r7, #24] /* SPI in mode Receiver ----------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 8005394: 69bb ldr r3, [r7, #24] 8005396: 099b lsrs r3, r3, #6 8005398: f003 0301 and.w r3, r3, #1 800539c: 2b00 cmp r3, #0 800539e: d10f bne.n 80053c0 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 80053a0: 69bb ldr r3, [r7, #24] 80053a2: f003 0301 and.w r3, r3, #1 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && 80053a6: 2b00 cmp r3, #0 80053a8: d00a beq.n 80053c0 <HAL_SPI_IRQHandler+0x44> (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) 80053aa: 69fb ldr r3, [r7, #28] 80053ac: 099b lsrs r3, r3, #6 80053ae: f003 0301 and.w r3, r3, #1 80053b2: 2b00 cmp r3, #0 80053b4: d004 beq.n 80053c0 <HAL_SPI_IRQHandler+0x44> { hspi->RxISR(hspi); 80053b6: 687b ldr r3, [r7, #4] 80053b8: 6c1b ldr r3, [r3, #64] ; 0x40 80053ba: 6878 ldr r0, [r7, #4] 80053bc: 4798 blx r3 return; 80053be: e0be b.n 800553e <HAL_SPI_IRQHandler+0x1c2> } /* SPI in mode Transmitter -------------------------------------------------*/ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) 80053c0: 69bb ldr r3, [r7, #24] 80053c2: 085b lsrs r3, r3, #1 80053c4: f003 0301 and.w r3, r3, #1 80053c8: 2b00 cmp r3, #0 80053ca: d00a beq.n 80053e2 <HAL_SPI_IRQHandler+0x66> 80053cc: 69fb ldr r3, [r7, #28] 80053ce: 09db lsrs r3, r3, #7 80053d0: f003 0301 and.w r3, r3, #1 80053d4: 2b00 cmp r3, #0 80053d6: d004 beq.n 80053e2 <HAL_SPI_IRQHandler+0x66> { hspi->TxISR(hspi); 80053d8: 687b ldr r3, [r7, #4] 80053da: 6c5b ldr r3, [r3, #68] ; 0x44 80053dc: 6878 ldr r0, [r7, #4] 80053de: 4798 blx r3 return; 80053e0: e0ad b.n 800553e <HAL_SPI_IRQHandler+0x1c2> } /* SPI in Error Treatment --------------------------------------------------*/ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)) 80053e2: 69bb ldr r3, [r7, #24] 80053e4: 095b lsrs r3, r3, #5 80053e6: f003 0301 and.w r3, r3, #1 80053ea: 2b00 cmp r3, #0 80053ec: d106 bne.n 80053fc <HAL_SPI_IRQHandler+0x80> 80053ee: 69bb ldr r3, [r7, #24] 80053f0: 099b lsrs r3, r3, #6 80053f2: f003 0301 and.w r3, r3, #1 80053f6: 2b00 cmp r3, #0 80053f8: f000 80a1 beq.w 800553e <HAL_SPI_IRQHandler+0x1c2> && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) 80053fc: 69fb ldr r3, [r7, #28] 80053fe: 095b lsrs r3, r3, #5 8005400: f003 0301 and.w r3, r3, #1 8005404: 2b00 cmp r3, #0 8005406: f000 809a beq.w 800553e <HAL_SPI_IRQHandler+0x1c2> { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) 800540a: 69bb ldr r3, [r7, #24] 800540c: 099b lsrs r3, r3, #6 800540e: f003 0301 and.w r3, r3, #1 8005412: 2b00 cmp r3, #0 8005414: d023 beq.n 800545e <HAL_SPI_IRQHandler+0xe2> { if (hspi->State != HAL_SPI_STATE_BUSY_TX) 8005416: 687b ldr r3, [r7, #4] 8005418: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 800541c: b2db uxtb r3, r3 800541e: 2b03 cmp r3, #3 8005420: d011 beq.n 8005446 <HAL_SPI_IRQHandler+0xca> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); 8005422: 687b ldr r3, [r7, #4] 8005424: 6d5b ldr r3, [r3, #84] ; 0x54 8005426: f043 0204 orr.w r2, r3, #4 800542a: 687b ldr r3, [r7, #4] 800542c: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_OVRFLAG(hspi); 800542e: 2300 movs r3, #0 8005430: 617b str r3, [r7, #20] 8005432: 687b ldr r3, [r7, #4] 8005434: 681b ldr r3, [r3, #0] 8005436: 68db ldr r3, [r3, #12] 8005438: 617b str r3, [r7, #20] 800543a: 687b ldr r3, [r7, #4] 800543c: 681b ldr r3, [r3, #0] 800543e: 689b ldr r3, [r3, #8] 8005440: 617b str r3, [r7, #20] 8005442: 697b ldr r3, [r7, #20] 8005444: e00b b.n 800545e <HAL_SPI_IRQHandler+0xe2> } else { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8005446: 2300 movs r3, #0 8005448: 613b str r3, [r7, #16] 800544a: 687b ldr r3, [r7, #4] 800544c: 681b ldr r3, [r3, #0] 800544e: 68db ldr r3, [r3, #12] 8005450: 613b str r3, [r7, #16] 8005452: 687b ldr r3, [r7, #4] 8005454: 681b ldr r3, [r3, #0] 8005456: 689b ldr r3, [r3, #8] 8005458: 613b str r3, [r7, #16] 800545a: 693b ldr r3, [r7, #16] return; 800545c: e06f b.n 800553e <HAL_SPI_IRQHandler+0x1c2> } } /* SPI Mode Fault error interrupt occurred -------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) 800545e: 69bb ldr r3, [r7, #24] 8005460: 095b lsrs r3, r3, #5 8005462: f003 0301 and.w r3, r3, #1 8005466: 2b00 cmp r3, #0 8005468: d014 beq.n 8005494 <HAL_SPI_IRQHandler+0x118> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); 800546a: 687b ldr r3, [r7, #4] 800546c: 6d5b ldr r3, [r3, #84] ; 0x54 800546e: f043 0201 orr.w r2, r3, #1 8005472: 687b ldr r3, [r7, #4] 8005474: 655a str r2, [r3, #84] ; 0x54 __HAL_SPI_CLEAR_MODFFLAG(hspi); 8005476: 2300 movs r3, #0 8005478: 60fb str r3, [r7, #12] 800547a: 687b ldr r3, [r7, #4] 800547c: 681b ldr r3, [r3, #0] 800547e: 689b ldr r3, [r3, #8] 8005480: 60fb str r3, [r7, #12] 8005482: 687b ldr r3, [r7, #4] 8005484: 681b ldr r3, [r3, #0] 8005486: 681a ldr r2, [r3, #0] 8005488: 687b ldr r3, [r7, #4] 800548a: 681b ldr r3, [r3, #0] 800548c: f022 0240 bic.w r2, r2, #64 ; 0x40 8005490: 601a str r2, [r3, #0] 8005492: 68fb ldr r3, [r7, #12] } /* SPI Frame error interrupt occurred ------------------------------------*/ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8005494: 687b ldr r3, [r7, #4] 8005496: 6d5b ldr r3, [r3, #84] ; 0x54 8005498: 2b00 cmp r3, #0 800549a: d04f beq.n 800553c <HAL_SPI_IRQHandler+0x1c0> { /* Disable all interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); 800549c: 687b ldr r3, [r7, #4] 800549e: 681b ldr r3, [r3, #0] 80054a0: 685a ldr r2, [r3, #4] 80054a2: 687b ldr r3, [r7, #4] 80054a4: 681b ldr r3, [r3, #0] 80054a6: f022 02e0 bic.w r2, r2, #224 ; 0xe0 80054aa: 605a str r2, [r3, #4] hspi->State = HAL_SPI_STATE_READY; 80054ac: 687b ldr r3, [r7, #4] 80054ae: 2201 movs r2, #1 80054b0: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Disable the SPI DMA requests if enabled */ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) 80054b4: 69fb ldr r3, [r7, #28] 80054b6: f003 0302 and.w r3, r3, #2 80054ba: 2b00 cmp r3, #0 80054bc: d104 bne.n 80054c8 <HAL_SPI_IRQHandler+0x14c> 80054be: 69fb ldr r3, [r7, #28] 80054c0: f003 0301 and.w r3, r3, #1 80054c4: 2b00 cmp r3, #0 80054c6: d034 beq.n 8005532 <HAL_SPI_IRQHandler+0x1b6> { CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); 80054c8: 687b ldr r3, [r7, #4] 80054ca: 681b ldr r3, [r3, #0] 80054cc: 685a ldr r2, [r3, #4] 80054ce: 687b ldr r3, [r7, #4] 80054d0: 681b ldr r3, [r3, #0] 80054d2: f022 0203 bic.w r2, r2, #3 80054d6: 605a str r2, [r3, #4] /* Abort the SPI DMA Rx channel */ if (hspi->hdmarx != NULL) 80054d8: 687b ldr r3, [r7, #4] 80054da: 6cdb ldr r3, [r3, #76] ; 0x4c 80054dc: 2b00 cmp r3, #0 80054de: d011 beq.n 8005504 <HAL_SPI_IRQHandler+0x188> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; 80054e0: 687b ldr r3, [r7, #4] 80054e2: 6cdb ldr r3, [r3, #76] ; 0x4c 80054e4: 4a17 ldr r2, [pc, #92] ; (8005544 <HAL_SPI_IRQHandler+0x1c8>) 80054e6: 635a str r2, [r3, #52] ; 0x34 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) 80054e8: 687b ldr r3, [r7, #4] 80054ea: 6cdb ldr r3, [r3, #76] ; 0x4c 80054ec: 4618 mov r0, r3 80054ee: f7fe fa53 bl 8003998 <HAL_DMA_Abort_IT> 80054f2: 4603 mov r3, r0 80054f4: 2b00 cmp r3, #0 80054f6: d005 beq.n 8005504 <HAL_SPI_IRQHandler+0x188> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 80054f8: 687b ldr r3, [r7, #4] 80054fa: 6d5b ldr r3, [r3, #84] ; 0x54 80054fc: f043 0240 orr.w r2, r3, #64 ; 0x40 8005500: 687b ldr r3, [r7, #4] 8005502: 655a str r2, [r3, #84] ; 0x54 } } /* Abort the SPI DMA Tx channel */ if (hspi->hdmatx != NULL) 8005504: 687b ldr r3, [r7, #4] 8005506: 6c9b ldr r3, [r3, #72] ; 0x48 8005508: 2b00 cmp r3, #0 800550a: d016 beq.n 800553a <HAL_SPI_IRQHandler+0x1be> { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; 800550c: 687b ldr r3, [r7, #4] 800550e: 6c9b ldr r3, [r3, #72] ; 0x48 8005510: 4a0c ldr r2, [pc, #48] ; (8005544 <HAL_SPI_IRQHandler+0x1c8>) 8005512: 635a str r2, [r3, #52] ; 0x34 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) 8005514: 687b ldr r3, [r7, #4] 8005516: 6c9b ldr r3, [r3, #72] ; 0x48 8005518: 4618 mov r0, r3 800551a: f7fe fa3d bl 8003998 <HAL_DMA_Abort_IT> 800551e: 4603 mov r3, r0 8005520: 2b00 cmp r3, #0 8005522: d00a beq.n 800553a <HAL_SPI_IRQHandler+0x1be> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 8005524: 687b ldr r3, [r7, #4] 8005526: 6d5b ldr r3, [r3, #84] ; 0x54 8005528: f043 0240 orr.w r2, r3, #64 ; 0x40 800552c: 687b ldr r3, [r7, #4] 800552e: 655a str r2, [r3, #84] ; 0x54 if (hspi->hdmatx != NULL) 8005530: e003 b.n 800553a <HAL_SPI_IRQHandler+0x1be> { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 8005532: 6878 ldr r0, [r7, #4] 8005534: f001 fd3c bl 8006fb0 <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } return; 8005538: e000 b.n 800553c <HAL_SPI_IRQHandler+0x1c0> if (hspi->hdmatx != NULL) 800553a: bf00 nop return; 800553c: bf00 nop } } 800553e: 3720 adds r7, #32 8005540: 46bd mov sp, r7 8005542: bd80 pop {r7, pc} 8005544: 0800555b .word 0x0800555b 08005548 <HAL_SPI_RxCpltCallback>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { 8005548: b480 push {r7} 800554a: b083 sub sp, #12 800554c: af00 add r7, sp, #0 800554e: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback should be implemented in the user file */ } 8005550: bf00 nop 8005552: 370c adds r7, #12 8005554: 46bd mov sp, r7 8005556: bc80 pop {r7} 8005558: 4770 bx lr 0800555a <SPI_DMAAbortOnError>: * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800555a: b580 push {r7, lr} 800555c: b084 sub sp, #16 800555e: af00 add r7, sp, #0 8005560: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8005562: 687b ldr r3, [r7, #4] 8005564: 6a5b ldr r3, [r3, #36] ; 0x24 8005566: 60fb str r3, [r7, #12] hspi->RxXferCount = 0U; 8005568: 68fb ldr r3, [r7, #12] 800556a: 2200 movs r2, #0 800556c: 87da strh r2, [r3, #62] ; 0x3e hspi->TxXferCount = 0U; 800556e: 68fb ldr r3, [r7, #12] 8005570: 2200 movs r2, #0 8005572: 86da strh r2, [r3, #54] ; 0x36 /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 8005574: 68f8 ldr r0, [r7, #12] 8005576: f001 fd1b bl 8006fb0 <HAL_SPI_ErrorCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800557a: bf00 nop 800557c: 3710 adds r7, #16 800557e: 46bd mov sp, r7 8005580: bd80 pop {r7, pc} 08005582 <SPI_2linesRxISR_8BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { 8005582: b580 push {r7, lr} 8005584: b082 sub sp, #8 8005586: af00 add r7, sp, #0 8005588: 6078 str r0, [r7, #4] /* Receive data in 8bit mode */ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); 800558a: 687b ldr r3, [r7, #4] 800558c: 681b ldr r3, [r3, #0] 800558e: f103 020c add.w r2, r3, #12 8005592: 687b ldr r3, [r7, #4] 8005594: 6b9b ldr r3, [r3, #56] ; 0x38 8005596: 7812 ldrb r2, [r2, #0] 8005598: b2d2 uxtb r2, r2 800559a: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 800559c: 687b ldr r3, [r7, #4] 800559e: 6b9b ldr r3, [r3, #56] ; 0x38 80055a0: 1c5a adds r2, r3, #1 80055a2: 687b ldr r3, [r7, #4] 80055a4: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 80055a6: 687b ldr r3, [r7, #4] 80055a8: 8fdb ldrh r3, [r3, #62] ; 0x3e 80055aa: b29b uxth r3, r3 80055ac: 3b01 subs r3, #1 80055ae: b29a uxth r2, r3 80055b0: 687b ldr r3, [r7, #4] 80055b2: 87da strh r2, [r3, #62] ; 0x3e /* Check end of the reception */ if (hspi->RxXferCount == 0U) 80055b4: 687b ldr r3, [r7, #4] 80055b6: 8fdb ldrh r3, [r3, #62] ; 0x3e 80055b8: b29b uxth r3, r3 80055ba: 2b00 cmp r3, #0 80055bc: d10f bne.n 80055de <SPI_2linesRxISR_8BIT+0x5c> return; } #endif /* USE_SPI_CRC */ /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); 80055be: 687b ldr r3, [r7, #4] 80055c0: 681b ldr r3, [r3, #0] 80055c2: 685a ldr r2, [r3, #4] 80055c4: 687b ldr r3, [r7, #4] 80055c6: 681b ldr r3, [r3, #0] 80055c8: f022 0260 bic.w r2, r2, #96 ; 0x60 80055cc: 605a str r2, [r3, #4] if (hspi->TxXferCount == 0U) 80055ce: 687b ldr r3, [r7, #4] 80055d0: 8edb ldrh r3, [r3, #54] ; 0x36 80055d2: b29b uxth r3, r3 80055d4: 2b00 cmp r3, #0 80055d6: d102 bne.n 80055de <SPI_2linesRxISR_8BIT+0x5c> { SPI_CloseRxTx_ISR(hspi); 80055d8: 6878 ldr r0, [r7, #4] 80055da: f000 f99f bl 800591c <SPI_CloseRxTx_ISR> } } } 80055de: bf00 nop 80055e0: 3708 adds r7, #8 80055e2: 46bd mov sp, r7 80055e4: bd80 pop {r7, pc} 080055e6 <SPI_2linesTxISR_8BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { 80055e6: b580 push {r7, lr} 80055e8: b082 sub sp, #8 80055ea: af00 add r7, sp, #0 80055ec: 6078 str r0, [r7, #4] *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 80055ee: 687b ldr r3, [r7, #4] 80055f0: 6b1a ldr r2, [r3, #48] ; 0x30 80055f2: 687b ldr r3, [r7, #4] 80055f4: 681b ldr r3, [r3, #0] 80055f6: 330c adds r3, #12 80055f8: 7812 ldrb r2, [r2, #0] 80055fa: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 80055fc: 687b ldr r3, [r7, #4] 80055fe: 6b1b ldr r3, [r3, #48] ; 0x30 8005600: 1c5a adds r2, r3, #1 8005602: 687b ldr r3, [r7, #4] 8005604: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 8005606: 687b ldr r3, [r7, #4] 8005608: 8edb ldrh r3, [r3, #54] ; 0x36 800560a: b29b uxth r3, r3 800560c: 3b01 subs r3, #1 800560e: b29a uxth r2, r3 8005610: 687b ldr r3, [r7, #4] 8005612: 86da strh r2, [r3, #54] ; 0x36 /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) 8005614: 687b ldr r3, [r7, #4] 8005616: 8edb ldrh r3, [r3, #54] ; 0x36 8005618: b29b uxth r3, r3 800561a: 2b00 cmp r3, #0 800561c: d10f bne.n 800563e <SPI_2linesTxISR_8BIT+0x58> return; } #endif /* USE_SPI_CRC */ /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); 800561e: 687b ldr r3, [r7, #4] 8005620: 681b ldr r3, [r3, #0] 8005622: 685a ldr r2, [r3, #4] 8005624: 687b ldr r3, [r7, #4] 8005626: 681b ldr r3, [r3, #0] 8005628: f022 0280 bic.w r2, r2, #128 ; 0x80 800562c: 605a str r2, [r3, #4] if (hspi->RxXferCount == 0U) 800562e: 687b ldr r3, [r7, #4] 8005630: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005632: b29b uxth r3, r3 8005634: 2b00 cmp r3, #0 8005636: d102 bne.n 800563e <SPI_2linesTxISR_8BIT+0x58> { SPI_CloseRxTx_ISR(hspi); 8005638: 6878 ldr r0, [r7, #4] 800563a: f000 f96f bl 800591c <SPI_CloseRxTx_ISR> } } } 800563e: bf00 nop 8005640: 3708 adds r7, #8 8005642: 46bd mov sp, r7 8005644: bd80 pop {r7, pc} 08005646 <SPI_2linesRxISR_16BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { 8005646: b580 push {r7, lr} 8005648: b082 sub sp, #8 800564a: af00 add r7, sp, #0 800564c: 6078 str r0, [r7, #4] /* Receive data in 16 Bit mode */ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); 800564e: 687b ldr r3, [r7, #4] 8005650: 681b ldr r3, [r3, #0] 8005652: 68da ldr r2, [r3, #12] 8005654: 687b ldr r3, [r7, #4] 8005656: 6b9b ldr r3, [r3, #56] ; 0x38 8005658: b292 uxth r2, r2 800565a: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 800565c: 687b ldr r3, [r7, #4] 800565e: 6b9b ldr r3, [r3, #56] ; 0x38 8005660: 1c9a adds r2, r3, #2 8005662: 687b ldr r3, [r7, #4] 8005664: 639a str r2, [r3, #56] ; 0x38 hspi->RxXferCount--; 8005666: 687b ldr r3, [r7, #4] 8005668: 8fdb ldrh r3, [r3, #62] ; 0x3e 800566a: b29b uxth r3, r3 800566c: 3b01 subs r3, #1 800566e: b29a uxth r2, r3 8005670: 687b ldr r3, [r7, #4] 8005672: 87da strh r2, [r3, #62] ; 0x3e if (hspi->RxXferCount == 0U) 8005674: 687b ldr r3, [r7, #4] 8005676: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005678: b29b uxth r3, r3 800567a: 2b00 cmp r3, #0 800567c: d10f bne.n 800569e <SPI_2linesRxISR_16BIT+0x58> return; } #endif /* USE_SPI_CRC */ /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); 800567e: 687b ldr r3, [r7, #4] 8005680: 681b ldr r3, [r3, #0] 8005682: 685a ldr r2, [r3, #4] 8005684: 687b ldr r3, [r7, #4] 8005686: 681b ldr r3, [r3, #0] 8005688: f022 0240 bic.w r2, r2, #64 ; 0x40 800568c: 605a str r2, [r3, #4] if (hspi->TxXferCount == 0U) 800568e: 687b ldr r3, [r7, #4] 8005690: 8edb ldrh r3, [r3, #54] ; 0x36 8005692: b29b uxth r3, r3 8005694: 2b00 cmp r3, #0 8005696: d102 bne.n 800569e <SPI_2linesRxISR_16BIT+0x58> { SPI_CloseRxTx_ISR(hspi); 8005698: 6878 ldr r0, [r7, #4] 800569a: f000 f93f bl 800591c <SPI_CloseRxTx_ISR> } } } 800569e: bf00 nop 80056a0: 3708 adds r7, #8 80056a2: 46bd mov sp, r7 80056a4: bd80 pop {r7, pc} 080056a6 <SPI_2linesTxISR_16BIT>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { 80056a6: b580 push {r7, lr} 80056a8: b082 sub sp, #8 80056aa: af00 add r7, sp, #0 80056ac: 6078 str r0, [r7, #4] /* Transmit data in 16 Bit mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 80056ae: 687b ldr r3, [r7, #4] 80056b0: 6b1b ldr r3, [r3, #48] ; 0x30 80056b2: 881a ldrh r2, [r3, #0] 80056b4: 687b ldr r3, [r7, #4] 80056b6: 681b ldr r3, [r3, #0] 80056b8: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 80056ba: 687b ldr r3, [r7, #4] 80056bc: 6b1b ldr r3, [r3, #48] ; 0x30 80056be: 1c9a adds r2, r3, #2 80056c0: 687b ldr r3, [r7, #4] 80056c2: 631a str r2, [r3, #48] ; 0x30 hspi->TxXferCount--; 80056c4: 687b ldr r3, [r7, #4] 80056c6: 8edb ldrh r3, [r3, #54] ; 0x36 80056c8: b29b uxth r3, r3 80056ca: 3b01 subs r3, #1 80056cc: b29a uxth r2, r3 80056ce: 687b ldr r3, [r7, #4] 80056d0: 86da strh r2, [r3, #54] ; 0x36 /* Enable CRC Transmission */ if (hspi->TxXferCount == 0U) 80056d2: 687b ldr r3, [r7, #4] 80056d4: 8edb ldrh r3, [r3, #54] ; 0x36 80056d6: b29b uxth r3, r3 80056d8: 2b00 cmp r3, #0 80056da: d10f bne.n 80056fc <SPI_2linesTxISR_16BIT+0x56> return; } #endif /* USE_SPI_CRC */ /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); 80056dc: 687b ldr r3, [r7, #4] 80056de: 681b ldr r3, [r3, #0] 80056e0: 685a ldr r2, [r3, #4] 80056e2: 687b ldr r3, [r7, #4] 80056e4: 681b ldr r3, [r3, #0] 80056e6: f022 0280 bic.w r2, r2, #128 ; 0x80 80056ea: 605a str r2, [r3, #4] if (hspi->RxXferCount == 0U) 80056ec: 687b ldr r3, [r7, #4] 80056ee: 8fdb ldrh r3, [r3, #62] ; 0x3e 80056f0: b29b uxth r3, r3 80056f2: 2b00 cmp r3, #0 80056f4: d102 bne.n 80056fc <SPI_2linesTxISR_16BIT+0x56> { SPI_CloseRxTx_ISR(hspi); 80056f6: 6878 ldr r0, [r7, #4] 80056f8: f000 f910 bl 800591c <SPI_CloseRxTx_ISR> } } } 80056fc: bf00 nop 80056fe: 3708 adds r7, #8 8005700: 46bd mov sp, r7 8005702: bd80 pop {r7, pc} 08005704 <SPI_WaitFlagStateUntilTimeout>: * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 8005704: b580 push {r7, lr} 8005706: b088 sub sp, #32 8005708: af00 add r7, sp, #0 800570a: 60f8 str r0, [r7, #12] 800570c: 60b9 str r1, [r7, #8] 800570e: 603b str r3, [r7, #0] 8005710: 4613 mov r3, r2 8005712: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 8005714: f7fd fa26 bl 8002b64 <HAL_GetTick> 8005718: 4602 mov r2, r0 800571a: 6abb ldr r3, [r7, #40] ; 0x28 800571c: 1a9b subs r3, r3, r2 800571e: 683a ldr r2, [r7, #0] 8005720: 4413 add r3, r2 8005722: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 8005724: f7fd fa1e bl 8002b64 <HAL_GetTick> 8005728: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 800572a: 4b39 ldr r3, [pc, #228] ; (8005810 <SPI_WaitFlagStateUntilTimeout+0x10c>) 800572c: 681b ldr r3, [r3, #0] 800572e: 015b lsls r3, r3, #5 8005730: 0d1b lsrs r3, r3, #20 8005732: 69fa ldr r2, [r7, #28] 8005734: fb02 f303 mul.w r3, r2, r3 8005738: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800573a: e054 b.n 80057e6 <SPI_WaitFlagStateUntilTimeout+0xe2> { if (Timeout != HAL_MAX_DELAY) 800573c: 683b ldr r3, [r7, #0] 800573e: f1b3 3fff cmp.w r3, #4294967295 8005742: d050 beq.n 80057e6 <SPI_WaitFlagStateUntilTimeout+0xe2> { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 8005744: f7fd fa0e bl 8002b64 <HAL_GetTick> 8005748: 4602 mov r2, r0 800574a: 69bb ldr r3, [r7, #24] 800574c: 1ad3 subs r3, r2, r3 800574e: 69fa ldr r2, [r7, #28] 8005750: 429a cmp r2, r3 8005752: d902 bls.n 800575a <SPI_WaitFlagStateUntilTimeout+0x56> 8005754: 69fb ldr r3, [r7, #28] 8005756: 2b00 cmp r3, #0 8005758: d13d bne.n 80057d6 <SPI_WaitFlagStateUntilTimeout+0xd2> /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800575a: 68fb ldr r3, [r7, #12] 800575c: 681b ldr r3, [r3, #0] 800575e: 685a ldr r2, [r3, #4] 8005760: 68fb ldr r3, [r7, #12] 8005762: 681b ldr r3, [r3, #0] 8005764: f022 02e0 bic.w r2, r2, #224 ; 0xe0 8005768: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800576a: 68fb ldr r3, [r7, #12] 800576c: 685b ldr r3, [r3, #4] 800576e: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005772: d111 bne.n 8005798 <SPI_WaitFlagStateUntilTimeout+0x94> 8005774: 68fb ldr r3, [r7, #12] 8005776: 689b ldr r3, [r3, #8] 8005778: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800577c: d004 beq.n 8005788 <SPI_WaitFlagStateUntilTimeout+0x84> || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800577e: 68fb ldr r3, [r7, #12] 8005780: 689b ldr r3, [r3, #8] 8005782: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8005786: d107 bne.n 8005798 <SPI_WaitFlagStateUntilTimeout+0x94> { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8005788: 68fb ldr r3, [r7, #12] 800578a: 681b ldr r3, [r3, #0] 800578c: 681a ldr r2, [r3, #0] 800578e: 68fb ldr r3, [r7, #12] 8005790: 681b ldr r3, [r3, #0] 8005792: f022 0240 bic.w r2, r2, #64 ; 0x40 8005796: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 8005798: 68fb ldr r3, [r7, #12] 800579a: 6a9b ldr r3, [r3, #40] ; 0x28 800579c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80057a0: d10f bne.n 80057c2 <SPI_WaitFlagStateUntilTimeout+0xbe> { SPI_RESET_CRC(hspi); 80057a2: 68fb ldr r3, [r7, #12] 80057a4: 681b ldr r3, [r3, #0] 80057a6: 681a ldr r2, [r3, #0] 80057a8: 68fb ldr r3, [r7, #12] 80057aa: 681b ldr r3, [r3, #0] 80057ac: f422 5200 bic.w r2, r2, #8192 ; 0x2000 80057b0: 601a str r2, [r3, #0] 80057b2: 68fb ldr r3, [r7, #12] 80057b4: 681b ldr r3, [r3, #0] 80057b6: 681a ldr r2, [r3, #0] 80057b8: 68fb ldr r3, [r7, #12] 80057ba: 681b ldr r3, [r3, #0] 80057bc: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80057c0: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 80057c2: 68fb ldr r3, [r7, #12] 80057c4: 2201 movs r2, #1 80057c6: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); 80057ca: 68fb ldr r3, [r7, #12] 80057cc: 2200 movs r2, #0 80057ce: f883 2050 strb.w r2, [r3, #80] ; 0x50 return HAL_TIMEOUT; 80057d2: 2303 movs r3, #3 80057d4: e017 b.n 8005806 <SPI_WaitFlagStateUntilTimeout+0x102> } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 80057d6: 697b ldr r3, [r7, #20] 80057d8: 2b00 cmp r3, #0 80057da: d101 bne.n 80057e0 <SPI_WaitFlagStateUntilTimeout+0xdc> { tmp_timeout = 0U; 80057dc: 2300 movs r3, #0 80057de: 61fb str r3, [r7, #28] } count--; 80057e0: 697b ldr r3, [r7, #20] 80057e2: 3b01 subs r3, #1 80057e4: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 80057e6: 68fb ldr r3, [r7, #12] 80057e8: 681b ldr r3, [r3, #0] 80057ea: 689a ldr r2, [r3, #8] 80057ec: 68bb ldr r3, [r7, #8] 80057ee: 4013 ands r3, r2 80057f0: 68ba ldr r2, [r7, #8] 80057f2: 429a cmp r2, r3 80057f4: bf0c ite eq 80057f6: 2301 moveq r3, #1 80057f8: 2300 movne r3, #0 80057fa: b2db uxtb r3, r3 80057fc: 461a mov r2, r3 80057fe: 79fb ldrb r3, [r7, #7] 8005800: 429a cmp r2, r3 8005802: d19b bne.n 800573c <SPI_WaitFlagStateUntilTimeout+0x38> } } return HAL_OK; 8005804: 2300 movs r3, #0 } 8005806: 4618 mov r0, r3 8005808: 3720 adds r7, #32 800580a: 46bd mov sp, r7 800580c: bd80 pop {r7, pc} 800580e: bf00 nop 8005810: 20000008 .word 0x20000008 08005814 <SPI_EndRxTransaction>: * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 8005814: b580 push {r7, lr} 8005816: b086 sub sp, #24 8005818: af02 add r7, sp, #8 800581a: 60f8 str r0, [r7, #12] 800581c: 60b9 str r1, [r7, #8] 800581e: 607a str r2, [r7, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8005820: 68fb ldr r3, [r7, #12] 8005822: 685b ldr r3, [r3, #4] 8005824: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005828: d111 bne.n 800584e <SPI_EndRxTransaction+0x3a> 800582a: 68fb ldr r3, [r7, #12] 800582c: 689b ldr r3, [r3, #8] 800582e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8005832: d004 beq.n 800583e <SPI_EndRxTransaction+0x2a> || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 8005834: 68fb ldr r3, [r7, #12] 8005836: 689b ldr r3, [r3, #8] 8005838: f5b3 6f80 cmp.w r3, #1024 ; 0x400 800583c: d107 bne.n 800584e <SPI_EndRxTransaction+0x3a> { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800583e: 68fb ldr r3, [r7, #12] 8005840: 681b ldr r3, [r3, #0] 8005842: 681a ldr r2, [r3, #0] 8005844: 68fb ldr r3, [r7, #12] 8005846: 681b ldr r3, [r3, #0] 8005848: f022 0240 bic.w r2, r2, #64 ; 0x40 800584c: 601a str r2, [r3, #0] } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)) 800584e: 68fb ldr r3, [r7, #12] 8005850: 685b ldr r3, [r3, #4] 8005852: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005856: d117 bne.n 8005888 <SPI_EndRxTransaction+0x74> 8005858: 68fb ldr r3, [r7, #12] 800585a: 689b ldr r3, [r3, #8] 800585c: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8005860: d112 bne.n 8005888 <SPI_EndRxTransaction+0x74> { /* Wait the RXNE reset */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) 8005862: 687b ldr r3, [r7, #4] 8005864: 9300 str r3, [sp, #0] 8005866: 68bb ldr r3, [r7, #8] 8005868: 2200 movs r2, #0 800586a: 2101 movs r1, #1 800586c: 68f8 ldr r0, [r7, #12] 800586e: f7ff ff49 bl 8005704 <SPI_WaitFlagStateUntilTimeout> 8005872: 4603 mov r3, r0 8005874: 2b00 cmp r3, #0 8005876: d01a beq.n 80058ae <SPI_EndRxTransaction+0x9a> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005878: 68fb ldr r3, [r7, #12] 800587a: 6d5b ldr r3, [r3, #84] ; 0x54 800587c: f043 0220 orr.w r2, r3, #32 8005880: 68fb ldr r3, [r7, #12] 8005882: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 8005884: 2303 movs r3, #3 8005886: e013 b.n 80058b0 <SPI_EndRxTransaction+0x9c> } } else { /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 8005888: 687b ldr r3, [r7, #4] 800588a: 9300 str r3, [sp, #0] 800588c: 68bb ldr r3, [r7, #8] 800588e: 2200 movs r2, #0 8005890: 2180 movs r1, #128 ; 0x80 8005892: 68f8 ldr r0, [r7, #12] 8005894: f7ff ff36 bl 8005704 <SPI_WaitFlagStateUntilTimeout> 8005898: 4603 mov r3, r0 800589a: 2b00 cmp r3, #0 800589c: d007 beq.n 80058ae <SPI_EndRxTransaction+0x9a> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800589e: 68fb ldr r3, [r7, #12] 80058a0: 6d5b ldr r3, [r3, #84] ; 0x54 80058a2: f043 0220 orr.w r2, r3, #32 80058a6: 68fb ldr r3, [r7, #12] 80058a8: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 80058aa: 2303 movs r3, #3 80058ac: e000 b.n 80058b0 <SPI_EndRxTransaction+0x9c> } } return HAL_OK; 80058ae: 2300 movs r3, #0 } 80058b0: 4618 mov r0, r3 80058b2: 3710 adds r7, #16 80058b4: 46bd mov sp, r7 80058b6: bd80 pop {r7, pc} 080058b8 <SPI_EndRxTxTransaction>: * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 80058b8: b580 push {r7, lr} 80058ba: b086 sub sp, #24 80058bc: af02 add r7, sp, #8 80058be: 60f8 str r0, [r7, #12] 80058c0: 60b9 str r1, [r7, #8] 80058c2: 607a str r2, [r7, #4] /* Wait until TXE flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) 80058c4: 687b ldr r3, [r7, #4] 80058c6: 9300 str r3, [sp, #0] 80058c8: 68bb ldr r3, [r7, #8] 80058ca: 2201 movs r2, #1 80058cc: 2102 movs r1, #2 80058ce: 68f8 ldr r0, [r7, #12] 80058d0: f7ff ff18 bl 8005704 <SPI_WaitFlagStateUntilTimeout> 80058d4: 4603 mov r3, r0 80058d6: 2b00 cmp r3, #0 80058d8: d007 beq.n 80058ea <SPI_EndRxTxTransaction+0x32> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 80058da: 68fb ldr r3, [r7, #12] 80058dc: 6d5b ldr r3, [r3, #84] ; 0x54 80058de: f043 0220 orr.w r2, r3, #32 80058e2: 68fb ldr r3, [r7, #12] 80058e4: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 80058e6: 2303 movs r3, #3 80058e8: e013 b.n 8005912 <SPI_EndRxTxTransaction+0x5a> } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 80058ea: 687b ldr r3, [r7, #4] 80058ec: 9300 str r3, [sp, #0] 80058ee: 68bb ldr r3, [r7, #8] 80058f0: 2200 movs r2, #0 80058f2: 2180 movs r1, #128 ; 0x80 80058f4: 68f8 ldr r0, [r7, #12] 80058f6: f7ff ff05 bl 8005704 <SPI_WaitFlagStateUntilTimeout> 80058fa: 4603 mov r3, r0 80058fc: 2b00 cmp r3, #0 80058fe: d007 beq.n 8005910 <SPI_EndRxTxTransaction+0x58> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005900: 68fb ldr r3, [r7, #12] 8005902: 6d5b ldr r3, [r3, #84] ; 0x54 8005904: f043 0220 orr.w r2, r3, #32 8005908: 68fb ldr r3, [r7, #12] 800590a: 655a str r2, [r3, #84] ; 0x54 return HAL_TIMEOUT; 800590c: 2303 movs r3, #3 800590e: e000 b.n 8005912 <SPI_EndRxTxTransaction+0x5a> } return HAL_OK; 8005910: 2300 movs r3, #0 } 8005912: 4618 mov r0, r3 8005914: 3710 adds r7, #16 8005916: 46bd mov sp, r7 8005918: bd80 pop {r7, pc} ... 0800591c <SPI_CloseRxTx_ISR>: * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { 800591c: b580 push {r7, lr} 800591e: b086 sub sp, #24 8005920: af00 add r7, sp, #0 8005922: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); 8005924: 4b35 ldr r3, [pc, #212] ; (80059fc <SPI_CloseRxTx_ISR+0xe0>) 8005926: 681b ldr r3, [r3, #0] 8005928: 4a35 ldr r2, [pc, #212] ; (8005a00 <SPI_CloseRxTx_ISR+0xe4>) 800592a: fba2 2303 umull r2, r3, r2, r3 800592e: 0a5b lsrs r3, r3, #9 8005930: 2264 movs r2, #100 ; 0x64 8005932: fb02 f303 mul.w r3, r2, r3 8005936: 613b str r3, [r7, #16] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005938: f7fd f914 bl 8002b64 <HAL_GetTick> 800593c: 6178 str r0, [r7, #20] /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800593e: 687b ldr r3, [r7, #4] 8005940: 681b ldr r3, [r3, #0] 8005942: 685a ldr r2, [r3, #4] 8005944: 687b ldr r3, [r7, #4] 8005946: 681b ldr r3, [r3, #0] 8005948: f022 0220 bic.w r2, r2, #32 800594c: 605a str r2, [r3, #4] /* Wait until TXE flag is set */ do { if (count == 0U) 800594e: 693b ldr r3, [r7, #16] 8005950: 2b00 cmp r3, #0 8005952: d106 bne.n 8005962 <SPI_CloseRxTx_ISR+0x46> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005954: 687b ldr r3, [r7, #4] 8005956: 6d5b ldr r3, [r3, #84] ; 0x54 8005958: f043 0220 orr.w r2, r3, #32 800595c: 687b ldr r3, [r7, #4] 800595e: 655a str r2, [r3, #84] ; 0x54 break; 8005960: e009 b.n 8005976 <SPI_CloseRxTx_ISR+0x5a> } count--; 8005962: 693b ldr r3, [r7, #16] 8005964: 3b01 subs r3, #1 8005966: 613b str r3, [r7, #16] } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); 8005968: 687b ldr r3, [r7, #4] 800596a: 681b ldr r3, [r3, #0] 800596c: 689b ldr r3, [r3, #8] 800596e: f003 0302 and.w r3, r3, #2 8005972: 2b00 cmp r3, #0 8005974: d0eb beq.n 800594e <SPI_CloseRxTx_ISR+0x32> /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 8005976: 697a ldr r2, [r7, #20] 8005978: 2164 movs r1, #100 ; 0x64 800597a: 6878 ldr r0, [r7, #4] 800597c: f7ff ff9c bl 80058b8 <SPI_EndRxTxTransaction> 8005980: 4603 mov r3, r0 8005982: 2b00 cmp r3, #0 8005984: d005 beq.n 8005992 <SPI_CloseRxTx_ISR+0x76> { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8005986: 687b ldr r3, [r7, #4] 8005988: 6d5b ldr r3, [r3, #84] ; 0x54 800598a: f043 0220 orr.w r2, r3, #32 800598e: 687b ldr r3, [r7, #4] 8005990: 655a str r2, [r3, #84] ; 0x54 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 8005992: 687b ldr r3, [r7, #4] 8005994: 689b ldr r3, [r3, #8] 8005996: 2b00 cmp r3, #0 8005998: d10a bne.n 80059b0 <SPI_CloseRxTx_ISR+0x94> { __HAL_SPI_CLEAR_OVRFLAG(hspi); 800599a: 2300 movs r3, #0 800599c: 60fb str r3, [r7, #12] 800599e: 687b ldr r3, [r7, #4] 80059a0: 681b ldr r3, [r3, #0] 80059a2: 68db ldr r3, [r3, #12] 80059a4: 60fb str r3, [r7, #12] 80059a6: 687b ldr r3, [r7, #4] 80059a8: 681b ldr r3, [r3, #0] 80059aa: 689b ldr r3, [r3, #8] 80059ac: 60fb str r3, [r7, #12] 80059ae: 68fb ldr r3, [r7, #12] } } else { #endif /* USE_SPI_CRC */ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) 80059b0: 687b ldr r3, [r7, #4] 80059b2: 6d5b ldr r3, [r3, #84] ; 0x54 80059b4: 2b00 cmp r3, #0 80059b6: d115 bne.n 80059e4 <SPI_CloseRxTx_ISR+0xc8> { if (hspi->State == HAL_SPI_STATE_BUSY_RX) 80059b8: 687b ldr r3, [r7, #4] 80059ba: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 80059be: b2db uxtb r3, r3 80059c0: 2b04 cmp r3, #4 80059c2: d107 bne.n 80059d4 <SPI_CloseRxTx_ISR+0xb8> { hspi->State = HAL_SPI_STATE_READY; 80059c4: 687b ldr r3, [r7, #4] 80059c6: 2201 movs r2, #1 80059c8: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Call user Rx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxCpltCallback(hspi); #else HAL_SPI_RxCpltCallback(hspi); 80059cc: 6878 ldr r0, [r7, #4] 80059ce: f7ff fdbb bl 8005548 <HAL_SPI_RxCpltCallback> #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } #endif /* USE_SPI_CRC */ } 80059d2: e00e b.n 80059f2 <SPI_CloseRxTx_ISR+0xd6> hspi->State = HAL_SPI_STATE_READY; 80059d4: 687b ldr r3, [r7, #4] 80059d6: 2201 movs r2, #1 80059d8: f883 2051 strb.w r2, [r3, #81] ; 0x51 HAL_SPI_TxRxCpltCallback(hspi); 80059dc: 6878 ldr r0, [r7, #4] 80059de: f001 fab3 bl 8006f48 <HAL_SPI_TxRxCpltCallback> } 80059e2: e006 b.n 80059f2 <SPI_CloseRxTx_ISR+0xd6> hspi->State = HAL_SPI_STATE_READY; 80059e4: 687b ldr r3, [r7, #4] 80059e6: 2201 movs r2, #1 80059e8: f883 2051 strb.w r2, [r3, #81] ; 0x51 HAL_SPI_ErrorCallback(hspi); 80059ec: 6878 ldr r0, [r7, #4] 80059ee: f001 fadf bl 8006fb0 <HAL_SPI_ErrorCallback> } 80059f2: bf00 nop 80059f4: 3718 adds r7, #24 80059f6: 46bd mov sp, r7 80059f8: bd80 pop {r7, pc} 80059fa: bf00 nop 80059fc: 20000008 .word 0x20000008 8005a00: 057619f1 .word 0x057619f1 08005a04 <HAL_TIM_Base_Init>: * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8005a04: b580 push {r7, lr} 8005a06: b082 sub sp, #8 8005a08: af00 add r7, sp, #0 8005a0a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005a0c: 687b ldr r3, [r7, #4] 8005a0e: 2b00 cmp r3, #0 8005a10: d101 bne.n 8005a16 <HAL_TIM_Base_Init+0x12> { return HAL_ERROR; 8005a12: 2301 movs r3, #1 8005a14: e041 b.n 8005a9a <HAL_TIM_Base_Init+0x96> assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005a16: 687b ldr r3, [r7, #4] 8005a18: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005a1c: b2db uxtb r3, r3 8005a1e: 2b00 cmp r3, #0 8005a20: d106 bne.n 8005a30 <HAL_TIM_Base_Init+0x2c> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005a22: 687b ldr r3, [r7, #4] 8005a24: 2200 movs r2, #0 8005a26: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8005a2a: 6878 ldr r0, [r7, #4] 8005a2c: f7fc fafe bl 800202c <HAL_TIM_Base_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005a30: 687b ldr r3, [r7, #4] 8005a32: 2202 movs r2, #2 8005a34: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005a38: 687b ldr r3, [r7, #4] 8005a3a: 681a ldr r2, [r3, #0] 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 3304 adds r3, #4 8005a40: 4619 mov r1, r3 8005a42: 4610 mov r0, r2 8005a44: f000 fc54 bl 80062f0 <TIM_Base_SetConfig> /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005a48: 687b ldr r3, [r7, #4] 8005a4a: 2201 movs r2, #1 8005a4c: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005a50: 687b ldr r3, [r7, #4] 8005a52: 2201 movs r2, #1 8005a54: f883 203e strb.w r2, [r3, #62] ; 0x3e 8005a58: 687b ldr r3, [r7, #4] 8005a5a: 2201 movs r2, #1 8005a5c: f883 203f strb.w r2, [r3, #63] ; 0x3f 8005a60: 687b ldr r3, [r7, #4] 8005a62: 2201 movs r2, #1 8005a64: f883 2040 strb.w r2, [r3, #64] ; 0x40 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 2201 movs r2, #1 8005a6c: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005a70: 687b ldr r3, [r7, #4] 8005a72: 2201 movs r2, #1 8005a74: f883 2042 strb.w r2, [r3, #66] ; 0x42 8005a78: 687b ldr r3, [r7, #4] 8005a7a: 2201 movs r2, #1 8005a7c: f883 2043 strb.w r2, [r3, #67] ; 0x43 8005a80: 687b ldr r3, [r7, #4] 8005a82: 2201 movs r2, #1 8005a84: f883 2044 strb.w r2, [r3, #68] ; 0x44 8005a88: 687b ldr r3, [r7, #4] 8005a8a: 2201 movs r2, #1 8005a8c: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005a90: 687b ldr r3, [r7, #4] 8005a92: 2201 movs r2, #1 8005a94: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8005a98: 2300 movs r3, #0 } 8005a9a: 4618 mov r0, r3 8005a9c: 3708 adds r7, #8 8005a9e: 46bd mov sp, r7 8005aa0: bd80 pop {r7, pc} ... 08005aa4 <HAL_TIM_Base_Start_IT>: * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8005aa4: b480 push {r7} 8005aa6: b085 sub sp, #20 8005aa8: af00 add r7, sp, #0 8005aaa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8005aac: 687b ldr r3, [r7, #4] 8005aae: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005ab2: b2db uxtb r3, r3 8005ab4: 2b01 cmp r3, #1 8005ab6: d001 beq.n 8005abc <HAL_TIM_Base_Start_IT+0x18> { return HAL_ERROR; 8005ab8: 2301 movs r3, #1 8005aba: e03a b.n 8005b32 <HAL_TIM_Base_Start_IT+0x8e> } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005abc: 687b ldr r3, [r7, #4] 8005abe: 2202 movs r2, #2 8005ac0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8005ac4: 687b ldr r3, [r7, #4] 8005ac6: 681b ldr r3, [r3, #0] 8005ac8: 68da ldr r2, [r3, #12] 8005aca: 687b ldr r3, [r7, #4] 8005acc: 681b ldr r3, [r3, #0] 8005ace: f042 0201 orr.w r2, r2, #1 8005ad2: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: 681b ldr r3, [r3, #0] 8005ad8: 4a18 ldr r2, [pc, #96] ; (8005b3c <HAL_TIM_Base_Start_IT+0x98>) 8005ada: 4293 cmp r3, r2 8005adc: d00e beq.n 8005afc <HAL_TIM_Base_Start_IT+0x58> 8005ade: 687b ldr r3, [r7, #4] 8005ae0: 681b ldr r3, [r3, #0] 8005ae2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005ae6: d009 beq.n 8005afc <HAL_TIM_Base_Start_IT+0x58> 8005ae8: 687b ldr r3, [r7, #4] 8005aea: 681b ldr r3, [r3, #0] 8005aec: 4a14 ldr r2, [pc, #80] ; (8005b40 <HAL_TIM_Base_Start_IT+0x9c>) 8005aee: 4293 cmp r3, r2 8005af0: d004 beq.n 8005afc <HAL_TIM_Base_Start_IT+0x58> 8005af2: 687b ldr r3, [r7, #4] 8005af4: 681b ldr r3, [r3, #0] 8005af6: 4a13 ldr r2, [pc, #76] ; (8005b44 <HAL_TIM_Base_Start_IT+0xa0>) 8005af8: 4293 cmp r3, r2 8005afa: d111 bne.n 8005b20 <HAL_TIM_Base_Start_IT+0x7c> { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005afc: 687b ldr r3, [r7, #4] 8005afe: 681b ldr r3, [r3, #0] 8005b00: 689b ldr r3, [r3, #8] 8005b02: f003 0307 and.w r3, r3, #7 8005b06: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005b08: 68fb ldr r3, [r7, #12] 8005b0a: 2b06 cmp r3, #6 8005b0c: d010 beq.n 8005b30 <HAL_TIM_Base_Start_IT+0x8c> { __HAL_TIM_ENABLE(htim); 8005b0e: 687b ldr r3, [r7, #4] 8005b10: 681b ldr r3, [r3, #0] 8005b12: 681a ldr r2, [r3, #0] 8005b14: 687b ldr r3, [r7, #4] 8005b16: 681b ldr r3, [r3, #0] 8005b18: f042 0201 orr.w r2, r2, #1 8005b1c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005b1e: e007 b.n 8005b30 <HAL_TIM_Base_Start_IT+0x8c> } } else { __HAL_TIM_ENABLE(htim); 8005b20: 687b ldr r3, [r7, #4] 8005b22: 681b ldr r3, [r3, #0] 8005b24: 681a ldr r2, [r3, #0] 8005b26: 687b ldr r3, [r7, #4] 8005b28: 681b ldr r3, [r3, #0] 8005b2a: f042 0201 orr.w r2, r2, #1 8005b2e: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8005b30: 2300 movs r3, #0 } 8005b32: 4618 mov r0, r3 8005b34: 3714 adds r7, #20 8005b36: 46bd mov sp, r7 8005b38: bc80 pop {r7} 8005b3a: 4770 bx lr 8005b3c: 40012c00 .word 0x40012c00 8005b40: 40000400 .word 0x40000400 8005b44: 40000800 .word 0x40000800 08005b48 <HAL_TIM_Base_Stop_IT>: * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { 8005b48: b480 push {r7} 8005b4a: b083 sub sp, #12 8005b4c: af00 add r7, sp, #0 8005b4e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); 8005b50: 687b ldr r3, [r7, #4] 8005b52: 681b ldr r3, [r3, #0] 8005b54: 68da ldr r2, [r3, #12] 8005b56: 687b ldr r3, [r7, #4] 8005b58: 681b ldr r3, [r3, #0] 8005b5a: f022 0201 bic.w r2, r2, #1 8005b5e: 60da str r2, [r3, #12] /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 8005b60: 687b ldr r3, [r7, #4] 8005b62: 681b ldr r3, [r3, #0] 8005b64: 6a1a ldr r2, [r3, #32] 8005b66: f241 1311 movw r3, #4369 ; 0x1111 8005b6a: 4013 ands r3, r2 8005b6c: 2b00 cmp r3, #0 8005b6e: d10f bne.n 8005b90 <HAL_TIM_Base_Stop_IT+0x48> 8005b70: 687b ldr r3, [r7, #4] 8005b72: 681b ldr r3, [r3, #0] 8005b74: 6a1a ldr r2, [r3, #32] 8005b76: f240 4344 movw r3, #1092 ; 0x444 8005b7a: 4013 ands r3, r2 8005b7c: 2b00 cmp r3, #0 8005b7e: d107 bne.n 8005b90 <HAL_TIM_Base_Stop_IT+0x48> 8005b80: 687b ldr r3, [r7, #4] 8005b82: 681b ldr r3, [r3, #0] 8005b84: 681a ldr r2, [r3, #0] 8005b86: 687b ldr r3, [r7, #4] 8005b88: 681b ldr r3, [r3, #0] 8005b8a: f022 0201 bic.w r2, r2, #1 8005b8e: 601a str r2, [r3, #0] /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; 8005b90: 687b ldr r3, [r7, #4] 8005b92: 2201 movs r2, #1 8005b94: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Return function status */ return HAL_OK; 8005b98: 2300 movs r3, #0 } 8005b9a: 4618 mov r0, r3 8005b9c: 370c adds r7, #12 8005b9e: 46bd mov sp, r7 8005ba0: bc80 pop {r7} 8005ba2: 4770 bx lr 08005ba4 <HAL_TIM_PWM_Init>: * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8005ba4: b580 push {r7, lr} 8005ba6: b082 sub sp, #8 8005ba8: af00 add r7, sp, #0 8005baa: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005bac: 687b ldr r3, [r7, #4] 8005bae: 2b00 cmp r3, #0 8005bb0: d101 bne.n 8005bb6 <HAL_TIM_PWM_Init+0x12> { return HAL_ERROR; 8005bb2: 2301 movs r3, #1 8005bb4: e041 b.n 8005c3a <HAL_TIM_PWM_Init+0x96> assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005bb6: 687b ldr r3, [r7, #4] 8005bb8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005bbc: b2db uxtb r3, r3 8005bbe: 2b00 cmp r3, #0 8005bc0: d106 bne.n 8005bd0 <HAL_TIM_PWM_Init+0x2c> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005bc2: 687b ldr r3, [r7, #4] 8005bc4: 2200 movs r2, #0 8005bc6: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8005bca: 6878 ldr r0, [r7, #4] 8005bcc: f000 f839 bl 8005c42 <HAL_TIM_PWM_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 2202 movs r2, #2 8005bd4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005bd8: 687b ldr r3, [r7, #4] 8005bda: 681a ldr r2, [r3, #0] 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 3304 adds r3, #4 8005be0: 4619 mov r1, r3 8005be2: 4610 mov r0, r2 8005be4: f000 fb84 bl 80062f0 <TIM_Base_SetConfig> /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005be8: 687b ldr r3, [r7, #4] 8005bea: 2201 movs r2, #1 8005bec: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 2201 movs r2, #1 8005bf4: f883 203e strb.w r2, [r3, #62] ; 0x3e 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 2201 movs r2, #1 8005bfc: f883 203f strb.w r2, [r3, #63] ; 0x3f 8005c00: 687b ldr r3, [r7, #4] 8005c02: 2201 movs r2, #1 8005c04: f883 2040 strb.w r2, [r3, #64] ; 0x40 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 2201 movs r2, #1 8005c0c: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005c10: 687b ldr r3, [r7, #4] 8005c12: 2201 movs r2, #1 8005c14: f883 2042 strb.w r2, [r3, #66] ; 0x42 8005c18: 687b ldr r3, [r7, #4] 8005c1a: 2201 movs r2, #1 8005c1c: f883 2043 strb.w r2, [r3, #67] ; 0x43 8005c20: 687b ldr r3, [r7, #4] 8005c22: 2201 movs r2, #1 8005c24: f883 2044 strb.w r2, [r3, #68] ; 0x44 8005c28: 687b ldr r3, [r7, #4] 8005c2a: 2201 movs r2, #1 8005c2c: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005c30: 687b ldr r3, [r7, #4] 8005c32: 2201 movs r2, #1 8005c34: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8005c38: 2300 movs r3, #0 } 8005c3a: 4618 mov r0, r3 8005c3c: 3708 adds r7, #8 8005c3e: 46bd mov sp, r7 8005c40: bd80 pop {r7, pc} 08005c42 <HAL_TIM_PWM_MspInit>: * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8005c42: b480 push {r7} 8005c44: b083 sub sp, #12 8005c46: af00 add r7, sp, #0 8005c48: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8005c4a: bf00 nop 8005c4c: 370c adds r7, #12 8005c4e: 46bd mov sp, r7 8005c50: bc80 pop {r7} 8005c52: 4770 bx lr 08005c54 <HAL_TIM_OnePulse_Init>: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { 8005c54: b580 push {r7, lr} 8005c56: b082 sub sp, #8 8005c58: af00 add r7, sp, #0 8005c5a: 6078 str r0, [r7, #4] 8005c5c: 6039 str r1, [r7, #0] /* Check the TIM handle allocation */ if (htim == NULL) 8005c5e: 687b ldr r3, [r7, #4] 8005c60: 2b00 cmp r3, #0 8005c62: d101 bne.n 8005c68 <HAL_TIM_OnePulse_Init+0x14> { return HAL_ERROR; 8005c64: 2301 movs r3, #1 8005c66: e041 b.n 8005cec <HAL_TIM_OnePulse_Init+0x98> assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005c68: 687b ldr r3, [r7, #4] 8005c6a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005c6e: b2db uxtb r3, r3 8005c70: 2b00 cmp r3, #0 8005c72: d106 bne.n 8005c82 <HAL_TIM_OnePulse_Init+0x2e> { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005c74: 687b ldr r3, [r7, #4] 8005c76: 2200 movs r2, #0 8005c78: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); 8005c7c: 6878 ldr r0, [r7, #4] 8005c7e: f000 f839 bl 8005cf4 <HAL_TIM_OnePulse_MspInit> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005c82: 687b ldr r3, [r7, #4] 8005c84: 2202 movs r2, #2 8005c86: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005c8a: 687b ldr r3, [r7, #4] 8005c8c: 681a ldr r2, [r3, #0] 8005c8e: 687b ldr r3, [r7, #4] 8005c90: 3304 adds r3, #4 8005c92: 4619 mov r1, r3 8005c94: 4610 mov r0, r2 8005c96: f000 fb2b bl 80062f0 <TIM_Base_SetConfig> /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; 8005c9a: 687b ldr r3, [r7, #4] 8005c9c: 681b ldr r3, [r3, #0] 8005c9e: 681a ldr r2, [r3, #0] 8005ca0: 687b ldr r3, [r7, #4] 8005ca2: 681b ldr r3, [r3, #0] 8005ca4: f022 0208 bic.w r2, r2, #8 8005ca8: 601a str r2, [r3, #0] /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; 8005caa: 687b ldr r3, [r7, #4] 8005cac: 681b ldr r3, [r3, #0] 8005cae: 6819 ldr r1, [r3, #0] 8005cb0: 687b ldr r3, [r7, #4] 8005cb2: 681b ldr r3, [r3, #0] 8005cb4: 683a ldr r2, [r7, #0] 8005cb6: 430a orrs r2, r1 8005cb8: 601a str r2, [r3, #0] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005cba: 687b ldr r3, [r7, #4] 8005cbc: 2201 movs r2, #1 8005cbe: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 2201 movs r2, #1 8005cc6: f883 203e strb.w r2, [r3, #62] ; 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005cca: 687b ldr r3, [r7, #4] 8005ccc: 2201 movs r2, #1 8005cce: f883 203f strb.w r2, [r3, #63] ; 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005cd2: 687b ldr r3, [r7, #4] 8005cd4: 2201 movs r2, #1 8005cd6: f883 2042 strb.w r2, [r3, #66] ; 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005cda: 687b ldr r3, [r7, #4] 8005cdc: 2201 movs r2, #1 8005cde: f883 2043 strb.w r2, [r3, #67] ; 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005ce2: 687b ldr r3, [r7, #4] 8005ce4: 2201 movs r2, #1 8005ce6: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8005cea: 2300 movs r3, #0 } 8005cec: 4618 mov r0, r3 8005cee: 3708 adds r7, #8 8005cf0: 46bd mov sp, r7 8005cf2: bd80 pop {r7, pc} 08005cf4 <HAL_TIM_OnePulse_MspInit>: * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { 8005cf4: b480 push {r7} 8005cf6: b083 sub sp, #12 8005cf8: af00 add r7, sp, #0 8005cfa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } 8005cfc: bf00 nop 8005cfe: 370c adds r7, #12 8005d00: 46bd mov sp, r7 8005d02: bc80 pop {r7} 8005d04: 4770 bx lr ... 08005d08 <HAL_TIM_OnePulse_Start>: * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { 8005d08: b580 push {r7, lr} 8005d0a: b084 sub sp, #16 8005d0c: af00 add r7, sp, #0 8005d0e: 6078 str r0, [r7, #4] 8005d10: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 8005d12: 687b ldr r3, [r7, #4] 8005d14: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 8005d18: 73fb strb r3, [r7, #15] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 8005d1a: 687b ldr r3, [r7, #4] 8005d1c: f893 303f ldrb.w r3, [r3, #63] ; 0x3f 8005d20: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 8005d22: 687b ldr r3, [r7, #4] 8005d24: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 8005d28: 737b strb r3, [r7, #13] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 8005d2a: 687b ldr r3, [r7, #4] 8005d2c: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 8005d30: 733b strb r3, [r7, #12] /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005d32: 7bfb ldrb r3, [r7, #15] 8005d34: 2b01 cmp r3, #1 8005d36: d108 bne.n 8005d4a <HAL_TIM_OnePulse_Start+0x42> || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005d38: 7bbb ldrb r3, [r7, #14] 8005d3a: 2b01 cmp r3, #1 8005d3c: d105 bne.n 8005d4a <HAL_TIM_OnePulse_Start+0x42> || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005d3e: 7b7b ldrb r3, [r7, #13] 8005d40: 2b01 cmp r3, #1 8005d42: d102 bne.n 8005d4a <HAL_TIM_OnePulse_Start+0x42> || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005d44: 7b3b ldrb r3, [r7, #12] 8005d46: 2b01 cmp r3, #1 8005d48: d001 beq.n 8005d4e <HAL_TIM_OnePulse_Start+0x46> { return HAL_ERROR; 8005d4a: 2301 movs r3, #1 8005d4c: e02b b.n 8005da6 <HAL_TIM_OnePulse_Start+0x9e> } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005d4e: 687b ldr r3, [r7, #4] 8005d50: 2202 movs r2, #2 8005d52: f883 203e strb.w r2, [r3, #62] ; 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005d56: 687b ldr r3, [r7, #4] 8005d58: 2202 movs r2, #2 8005d5a: f883 203f strb.w r2, [r3, #63] ; 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 2202 movs r2, #2 8005d62: f883 2042 strb.w r2, [r3, #66] ; 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005d66: 687b ldr r3, [r7, #4] 8005d68: 2202 movs r2, #2 8005d6a: f883 2043 strb.w r2, [r3, #67] ; 0x43 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005d6e: 687b ldr r3, [r7, #4] 8005d70: 681b ldr r3, [r3, #0] 8005d72: 2201 movs r2, #1 8005d74: 2100 movs r1, #0 8005d76: 4618 mov r0, r3 8005d78: f000 fd5f bl 800683a <TIM_CCxChannelCmd> TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005d7c: 687b ldr r3, [r7, #4] 8005d7e: 681b ldr r3, [r3, #0] 8005d80: 2201 movs r2, #1 8005d82: 2104 movs r1, #4 8005d84: 4618 mov r0, r3 8005d86: f000 fd58 bl 800683a <TIM_CCxChannelCmd> if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 681b ldr r3, [r3, #0] 8005d8e: 4a08 ldr r2, [pc, #32] ; (8005db0 <HAL_TIM_OnePulse_Start+0xa8>) 8005d90: 4293 cmp r3, r2 8005d92: d107 bne.n 8005da4 <HAL_TIM_OnePulse_Start+0x9c> { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8005d94: 687b ldr r3, [r7, #4] 8005d96: 681b ldr r3, [r3, #0] 8005d98: 6c5a ldr r2, [r3, #68] ; 0x44 8005d9a: 687b ldr r3, [r7, #4] 8005d9c: 681b ldr r3, [r3, #0] 8005d9e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8005da2: 645a str r2, [r3, #68] ; 0x44 } /* Return function status */ return HAL_OK; 8005da4: 2300 movs r3, #0 } 8005da6: 4618 mov r0, r3 8005da8: 3710 adds r7, #16 8005daa: 46bd mov sp, r7 8005dac: bd80 pop {r7, pc} 8005dae: bf00 nop 8005db0: 40012c00 .word 0x40012c00 08005db4 <HAL_TIM_IRQHandler>: * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005db4: b580 push {r7, lr} 8005db6: b084 sub sp, #16 8005db8: af00 add r7, sp, #0 8005dba: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8005dbc: 687b ldr r3, [r7, #4] 8005dbe: 681b ldr r3, [r3, #0] 8005dc0: 68db ldr r3, [r3, #12] 8005dc2: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8005dc4: 687b ldr r3, [r7, #4] 8005dc6: 681b ldr r3, [r3, #0] 8005dc8: 691b ldr r3, [r3, #16] 8005dca: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8005dcc: 68bb ldr r3, [r7, #8] 8005dce: f003 0302 and.w r3, r3, #2 8005dd2: 2b00 cmp r3, #0 8005dd4: d020 beq.n 8005e18 <HAL_TIM_IRQHandler+0x64> { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8005dd6: 68fb ldr r3, [r7, #12] 8005dd8: f003 0302 and.w r3, r3, #2 8005ddc: 2b00 cmp r3, #0 8005dde: d01b beq.n 8005e18 <HAL_TIM_IRQHandler+0x64> { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8005de0: 687b ldr r3, [r7, #4] 8005de2: 681b ldr r3, [r3, #0] 8005de4: f06f 0202 mvn.w r2, #2 8005de8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8005dea: 687b ldr r3, [r7, #4] 8005dec: 2201 movs r2, #1 8005dee: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8005df0: 687b ldr r3, [r7, #4] 8005df2: 681b ldr r3, [r3, #0] 8005df4: 699b ldr r3, [r3, #24] 8005df6: f003 0303 and.w r3, r3, #3 8005dfa: 2b00 cmp r3, #0 8005dfc: d003 beq.n 8005e06 <HAL_TIM_IRQHandler+0x52> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005dfe: 6878 ldr r0, [r7, #4] 8005e00: f000 fa5a bl 80062b8 <HAL_TIM_IC_CaptureCallback> 8005e04: e005 b.n 8005e12 <HAL_TIM_IRQHandler+0x5e> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005e06: 6878 ldr r0, [r7, #4] 8005e08: f000 fa4d bl 80062a6 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8005e0c: 6878 ldr r0, [r7, #4] 8005e0e: f000 fa5c bl 80062ca <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005e12: 687b ldr r3, [r7, #4] 8005e14: 2200 movs r2, #0 8005e16: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8005e18: 68bb ldr r3, [r7, #8] 8005e1a: f003 0304 and.w r3, r3, #4 8005e1e: 2b00 cmp r3, #0 8005e20: d020 beq.n 8005e64 <HAL_TIM_IRQHandler+0xb0> { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8005e22: 68fb ldr r3, [r7, #12] 8005e24: f003 0304 and.w r3, r3, #4 8005e28: 2b00 cmp r3, #0 8005e2a: d01b beq.n 8005e64 <HAL_TIM_IRQHandler+0xb0> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8005e2c: 687b ldr r3, [r7, #4] 8005e2e: 681b ldr r3, [r3, #0] 8005e30: f06f 0204 mvn.w r2, #4 8005e34: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8005e36: 687b ldr r3, [r7, #4] 8005e38: 2202 movs r2, #2 8005e3a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8005e3c: 687b ldr r3, [r7, #4] 8005e3e: 681b ldr r3, [r3, #0] 8005e40: 699b ldr r3, [r3, #24] 8005e42: f403 7340 and.w r3, r3, #768 ; 0x300 8005e46: 2b00 cmp r3, #0 8005e48: d003 beq.n 8005e52 <HAL_TIM_IRQHandler+0x9e> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005e4a: 6878 ldr r0, [r7, #4] 8005e4c: f000 fa34 bl 80062b8 <HAL_TIM_IC_CaptureCallback> 8005e50: e005 b.n 8005e5e <HAL_TIM_IRQHandler+0xaa> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005e52: 6878 ldr r0, [r7, #4] 8005e54: f000 fa27 bl 80062a6 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8005e58: 6878 ldr r0, [r7, #4] 8005e5a: f000 fa36 bl 80062ca <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005e5e: 687b ldr r3, [r7, #4] 8005e60: 2200 movs r2, #0 8005e62: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8005e64: 68bb ldr r3, [r7, #8] 8005e66: f003 0308 and.w r3, r3, #8 8005e6a: 2b00 cmp r3, #0 8005e6c: d020 beq.n 8005eb0 <HAL_TIM_IRQHandler+0xfc> { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8005e6e: 68fb ldr r3, [r7, #12] 8005e70: f003 0308 and.w r3, r3, #8 8005e74: 2b00 cmp r3, #0 8005e76: d01b beq.n 8005eb0 <HAL_TIM_IRQHandler+0xfc> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8005e78: 687b ldr r3, [r7, #4] 8005e7a: 681b ldr r3, [r3, #0] 8005e7c: f06f 0208 mvn.w r2, #8 8005e80: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8005e82: 687b ldr r3, [r7, #4] 8005e84: 2204 movs r2, #4 8005e86: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8005e88: 687b ldr r3, [r7, #4] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 69db ldr r3, [r3, #28] 8005e8e: f003 0303 and.w r3, r3, #3 8005e92: 2b00 cmp r3, #0 8005e94: d003 beq.n 8005e9e <HAL_TIM_IRQHandler+0xea> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005e96: 6878 ldr r0, [r7, #4] 8005e98: f000 fa0e bl 80062b8 <HAL_TIM_IC_CaptureCallback> 8005e9c: e005 b.n 8005eaa <HAL_TIM_IRQHandler+0xf6> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005e9e: 6878 ldr r0, [r7, #4] 8005ea0: f000 fa01 bl 80062a6 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8005ea4: 6878 ldr r0, [r7, #4] 8005ea6: f000 fa10 bl 80062ca <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005eaa: 687b ldr r3, [r7, #4] 8005eac: 2200 movs r2, #0 8005eae: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8005eb0: 68bb ldr r3, [r7, #8] 8005eb2: f003 0310 and.w r3, r3, #16 8005eb6: 2b00 cmp r3, #0 8005eb8: d020 beq.n 8005efc <HAL_TIM_IRQHandler+0x148> { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8005eba: 68fb ldr r3, [r7, #12] 8005ebc: f003 0310 and.w r3, r3, #16 8005ec0: 2b00 cmp r3, #0 8005ec2: d01b beq.n 8005efc <HAL_TIM_IRQHandler+0x148> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8005ec4: 687b ldr r3, [r7, #4] 8005ec6: 681b ldr r3, [r3, #0] 8005ec8: f06f 0210 mvn.w r2, #16 8005ecc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8005ece: 687b ldr r3, [r7, #4] 8005ed0: 2208 movs r2, #8 8005ed2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005ed4: 687b ldr r3, [r7, #4] 8005ed6: 681b ldr r3, [r3, #0] 8005ed8: 69db ldr r3, [r3, #28] 8005eda: f403 7340 and.w r3, r3, #768 ; 0x300 8005ede: 2b00 cmp r3, #0 8005ee0: d003 beq.n 8005eea <HAL_TIM_IRQHandler+0x136> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005ee2: 6878 ldr r0, [r7, #4] 8005ee4: f000 f9e8 bl 80062b8 <HAL_TIM_IC_CaptureCallback> 8005ee8: e005 b.n 8005ef6 <HAL_TIM_IRQHandler+0x142> { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005eea: 6878 ldr r0, [r7, #4] 8005eec: f000 f9db bl 80062a6 <HAL_TIM_OC_DelayElapsedCallback> HAL_TIM_PWM_PulseFinishedCallback(htim); 8005ef0: 6878 ldr r0, [r7, #4] 8005ef2: f000 f9ea bl 80062ca <HAL_TIM_PWM_PulseFinishedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 2200 movs r2, #0 8005efa: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8005efc: 68bb ldr r3, [r7, #8] 8005efe: f003 0301 and.w r3, r3, #1 8005f02: 2b00 cmp r3, #0 8005f04: d00c beq.n 8005f20 <HAL_TIM_IRQHandler+0x16c> { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8005f06: 68fb ldr r3, [r7, #12] 8005f08: f003 0301 and.w r3, r3, #1 8005f0c: 2b00 cmp r3, #0 8005f0e: d007 beq.n 8005f20 <HAL_TIM_IRQHandler+0x16c> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8005f10: 687b ldr r3, [r7, #4] 8005f12: 681b ldr r3, [r3, #0] 8005f14: f06f 0201 mvn.w r2, #1 8005f18: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8005f1a: 6878 ldr r0, [r7, #4] 8005f1c: f7fb fb90 bl 8001640 <HAL_TIM_PeriodElapsedCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8005f20: 68bb ldr r3, [r7, #8] 8005f22: f003 0380 and.w r3, r3, #128 ; 0x80 8005f26: 2b00 cmp r3, #0 8005f28: d00c beq.n 8005f44 <HAL_TIM_IRQHandler+0x190> { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8005f2a: 68fb ldr r3, [r7, #12] 8005f2c: f003 0380 and.w r3, r3, #128 ; 0x80 8005f30: 2b00 cmp r3, #0 8005f32: d007 beq.n 8005f44 <HAL_TIM_IRQHandler+0x190> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8005f34: 687b ldr r3, [r7, #4] 8005f36: 681b ldr r3, [r3, #0] 8005f38: f06f 0280 mvn.w r2, #128 ; 0x80 8005f3c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8005f3e: 6878 ldr r0, [r7, #4] 8005f40: f000 fd07 bl 8006952 <HAL_TIMEx_BreakCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8005f44: 68bb ldr r3, [r7, #8] 8005f46: f003 0340 and.w r3, r3, #64 ; 0x40 8005f4a: 2b00 cmp r3, #0 8005f4c: d00c beq.n 8005f68 <HAL_TIM_IRQHandler+0x1b4> { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8005f4e: 68fb ldr r3, [r7, #12] 8005f50: f003 0340 and.w r3, r3, #64 ; 0x40 8005f54: 2b00 cmp r3, #0 8005f56: d007 beq.n 8005f68 <HAL_TIM_IRQHandler+0x1b4> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8005f58: 687b ldr r3, [r7, #4] 8005f5a: 681b ldr r3, [r3, #0] 8005f5c: f06f 0240 mvn.w r2, #64 ; 0x40 8005f60: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8005f62: 6878 ldr r0, [r7, #4] 8005f64: f000 f9ba bl 80062dc <HAL_TIM_TriggerCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8005f68: 68bb ldr r3, [r7, #8] 8005f6a: f003 0320 and.w r3, r3, #32 8005f6e: 2b00 cmp r3, #0 8005f70: d00c beq.n 8005f8c <HAL_TIM_IRQHandler+0x1d8> { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8005f72: 68fb ldr r3, [r7, #12] 8005f74: f003 0320 and.w r3, r3, #32 8005f78: 2b00 cmp r3, #0 8005f7a: d007 beq.n 8005f8c <HAL_TIM_IRQHandler+0x1d8> { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8005f7c: 687b ldr r3, [r7, #4] 8005f7e: 681b ldr r3, [r3, #0] 8005f80: f06f 0220 mvn.w r2, #32 8005f84: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8005f86: 6878 ldr r0, [r7, #4] 8005f88: f000 fcda bl 8006940 <HAL_TIMEx_CommutCallback> #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8005f8c: bf00 nop 8005f8e: 3710 adds r7, #16 8005f90: 46bd mov sp, r7 8005f92: bd80 pop {r7, pc} 08005f94 <HAL_TIM_PWM_ConfigChannel>: * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005f94: b580 push {r7, lr} 8005f96: b086 sub sp, #24 8005f98: af00 add r7, sp, #0 8005f9a: 60f8 str r0, [r7, #12] 8005f9c: 60b9 str r1, [r7, #8] 8005f9e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005fa0: 2300 movs r3, #0 8005fa2: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005fa4: 68fb ldr r3, [r7, #12] 8005fa6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8005faa: 2b01 cmp r3, #1 8005fac: d101 bne.n 8005fb2 <HAL_TIM_PWM_ConfigChannel+0x1e> 8005fae: 2302 movs r3, #2 8005fb0: e0ae b.n 8006110 <HAL_TIM_PWM_ConfigChannel+0x17c> 8005fb2: 68fb ldr r3, [r7, #12] 8005fb4: 2201 movs r2, #1 8005fb6: f883 203c strb.w r2, [r3, #60] ; 0x3c switch (Channel) 8005fba: 687b ldr r3, [r7, #4] 8005fbc: 2b0c cmp r3, #12 8005fbe: f200 809f bhi.w 8006100 <HAL_TIM_PWM_ConfigChannel+0x16c> 8005fc2: a201 add r2, pc, #4 ; (adr r2, 8005fc8 <HAL_TIM_PWM_ConfigChannel+0x34>) 8005fc4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005fc8: 08005ffd .word 0x08005ffd 8005fcc: 08006101 .word 0x08006101 8005fd0: 08006101 .word 0x08006101 8005fd4: 08006101 .word 0x08006101 8005fd8: 0800603d .word 0x0800603d 8005fdc: 08006101 .word 0x08006101 8005fe0: 08006101 .word 0x08006101 8005fe4: 08006101 .word 0x08006101 8005fe8: 0800607f .word 0x0800607f 8005fec: 08006101 .word 0x08006101 8005ff0: 08006101 .word 0x08006101 8005ff4: 08006101 .word 0x08006101 8005ff8: 080060bf .word 0x080060bf { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005ffc: 68fb ldr r3, [r7, #12] 8005ffe: 681b ldr r3, [r3, #0] 8006000: 68b9 ldr r1, [r7, #8] 8006002: 4618 mov r0, r3 8006004: f000 f9dc bl 80063c0 <TIM_OC1_SetConfig> /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8006008: 68fb ldr r3, [r7, #12] 800600a: 681b ldr r3, [r3, #0] 800600c: 699a ldr r2, [r3, #24] 800600e: 68fb ldr r3, [r7, #12] 8006010: 681b ldr r3, [r3, #0] 8006012: f042 0208 orr.w r2, r2, #8 8006016: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8006018: 68fb ldr r3, [r7, #12] 800601a: 681b ldr r3, [r3, #0] 800601c: 699a ldr r2, [r3, #24] 800601e: 68fb ldr r3, [r7, #12] 8006020: 681b ldr r3, [r3, #0] 8006022: f022 0204 bic.w r2, r2, #4 8006026: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8006028: 68fb ldr r3, [r7, #12] 800602a: 681b ldr r3, [r3, #0] 800602c: 6999 ldr r1, [r3, #24] 800602e: 68bb ldr r3, [r7, #8] 8006030: 691a ldr r2, [r3, #16] 8006032: 68fb ldr r3, [r7, #12] 8006034: 681b ldr r3, [r3, #0] 8006036: 430a orrs r2, r1 8006038: 619a str r2, [r3, #24] break; 800603a: e064 b.n 8006106 <HAL_TIM_PWM_ConfigChannel+0x172> { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800603c: 68fb ldr r3, [r7, #12] 800603e: 681b ldr r3, [r3, #0] 8006040: 68b9 ldr r1, [r7, #8] 8006042: 4618 mov r0, r3 8006044: f000 fa24 bl 8006490 <TIM_OC2_SetConfig> /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8006048: 68fb ldr r3, [r7, #12] 800604a: 681b ldr r3, [r3, #0] 800604c: 699a ldr r2, [r3, #24] 800604e: 68fb ldr r3, [r7, #12] 8006050: 681b ldr r3, [r3, #0] 8006052: f442 6200 orr.w r2, r2, #2048 ; 0x800 8006056: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8006058: 68fb ldr r3, [r7, #12] 800605a: 681b ldr r3, [r3, #0] 800605c: 699a ldr r2, [r3, #24] 800605e: 68fb ldr r3, [r7, #12] 8006060: 681b ldr r3, [r3, #0] 8006062: f422 6280 bic.w r2, r2, #1024 ; 0x400 8006066: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8006068: 68fb ldr r3, [r7, #12] 800606a: 681b ldr r3, [r3, #0] 800606c: 6999 ldr r1, [r3, #24] 800606e: 68bb ldr r3, [r7, #8] 8006070: 691b ldr r3, [r3, #16] 8006072: 021a lsls r2, r3, #8 8006074: 68fb ldr r3, [r7, #12] 8006076: 681b ldr r3, [r3, #0] 8006078: 430a orrs r2, r1 800607a: 619a str r2, [r3, #24] break; 800607c: e043 b.n 8006106 <HAL_TIM_PWM_ConfigChannel+0x172> { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800607e: 68fb ldr r3, [r7, #12] 8006080: 681b ldr r3, [r3, #0] 8006082: 68b9 ldr r1, [r7, #8] 8006084: 4618 mov r0, r3 8006086: f000 fa6f bl 8006568 <TIM_OC3_SetConfig> /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800608a: 68fb ldr r3, [r7, #12] 800608c: 681b ldr r3, [r3, #0] 800608e: 69da ldr r2, [r3, #28] 8006090: 68fb ldr r3, [r7, #12] 8006092: 681b ldr r3, [r3, #0] 8006094: f042 0208 orr.w r2, r2, #8 8006098: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800609a: 68fb ldr r3, [r7, #12] 800609c: 681b ldr r3, [r3, #0] 800609e: 69da ldr r2, [r3, #28] 80060a0: 68fb ldr r3, [r7, #12] 80060a2: 681b ldr r3, [r3, #0] 80060a4: f022 0204 bic.w r2, r2, #4 80060a8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80060aa: 68fb ldr r3, [r7, #12] 80060ac: 681b ldr r3, [r3, #0] 80060ae: 69d9 ldr r1, [r3, #28] 80060b0: 68bb ldr r3, [r7, #8] 80060b2: 691a ldr r2, [r3, #16] 80060b4: 68fb ldr r3, [r7, #12] 80060b6: 681b ldr r3, [r3, #0] 80060b8: 430a orrs r2, r1 80060ba: 61da str r2, [r3, #28] break; 80060bc: e023 b.n 8006106 <HAL_TIM_PWM_ConfigChannel+0x172> { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80060be: 68fb ldr r3, [r7, #12] 80060c0: 681b ldr r3, [r3, #0] 80060c2: 68b9 ldr r1, [r7, #8] 80060c4: 4618 mov r0, r3 80060c6: f000 fabb bl 8006640 <TIM_OC4_SetConfig> /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80060ca: 68fb ldr r3, [r7, #12] 80060cc: 681b ldr r3, [r3, #0] 80060ce: 69da ldr r2, [r3, #28] 80060d0: 68fb ldr r3, [r7, #12] 80060d2: 681b ldr r3, [r3, #0] 80060d4: f442 6200 orr.w r2, r2, #2048 ; 0x800 80060d8: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80060da: 68fb ldr r3, [r7, #12] 80060dc: 681b ldr r3, [r3, #0] 80060de: 69da ldr r2, [r3, #28] 80060e0: 68fb ldr r3, [r7, #12] 80060e2: 681b ldr r3, [r3, #0] 80060e4: f422 6280 bic.w r2, r2, #1024 ; 0x400 80060e8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80060ea: 68fb ldr r3, [r7, #12] 80060ec: 681b ldr r3, [r3, #0] 80060ee: 69d9 ldr r1, [r3, #28] 80060f0: 68bb ldr r3, [r7, #8] 80060f2: 691b ldr r3, [r3, #16] 80060f4: 021a lsls r2, r3, #8 80060f6: 68fb ldr r3, [r7, #12] 80060f8: 681b ldr r3, [r3, #0] 80060fa: 430a orrs r2, r1 80060fc: 61da str r2, [r3, #28] break; 80060fe: e002 b.n 8006106 <HAL_TIM_PWM_ConfigChannel+0x172> } default: status = HAL_ERROR; 8006100: 2301 movs r3, #1 8006102: 75fb strb r3, [r7, #23] break; 8006104: bf00 nop } __HAL_UNLOCK(htim); 8006106: 68fb ldr r3, [r7, #12] 8006108: 2200 movs r2, #0 800610a: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 800610e: 7dfb ldrb r3, [r7, #23] } 8006110: 4618 mov r0, r3 8006112: 3718 adds r7, #24 8006114: 46bd mov sp, r7 8006116: bd80 pop {r7, pc} 08006118 <HAL_TIM_ConfigClockSource>: * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8006118: b580 push {r7, lr} 800611a: b084 sub sp, #16 800611c: af00 add r7, sp, #0 800611e: 6078 str r0, [r7, #4] 8006120: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8006122: 2300 movs r3, #0 8006124: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8006126: 687b ldr r3, [r7, #4] 8006128: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800612c: 2b01 cmp r3, #1 800612e: d101 bne.n 8006134 <HAL_TIM_ConfigClockSource+0x1c> 8006130: 2302 movs r3, #2 8006132: e0b4 b.n 800629e <HAL_TIM_ConfigClockSource+0x186> 8006134: 687b ldr r3, [r7, #4] 8006136: 2201 movs r2, #1 8006138: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 800613c: 687b ldr r3, [r7, #4] 800613e: 2202 movs r2, #2 8006140: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8006144: 687b ldr r3, [r7, #4] 8006146: 681b ldr r3, [r3, #0] 8006148: 689b ldr r3, [r3, #8] 800614a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800614c: 68bb ldr r3, [r7, #8] 800614e: f023 0377 bic.w r3, r3, #119 ; 0x77 8006152: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8006154: 68bb ldr r3, [r7, #8] 8006156: f423 437f bic.w r3, r3, #65280 ; 0xff00 800615a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800615c: 687b ldr r3, [r7, #4] 800615e: 681b ldr r3, [r3, #0] 8006160: 68ba ldr r2, [r7, #8] 8006162: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8006164: 683b ldr r3, [r7, #0] 8006166: 681b ldr r3, [r3, #0] 8006168: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800616c: d03e beq.n 80061ec <HAL_TIM_ConfigClockSource+0xd4> 800616e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8006172: f200 8087 bhi.w 8006284 <HAL_TIM_ConfigClockSource+0x16c> 8006176: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800617a: f000 8086 beq.w 800628a <HAL_TIM_ConfigClockSource+0x172> 800617e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8006182: d87f bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 8006184: 2b70 cmp r3, #112 ; 0x70 8006186: d01a beq.n 80061be <HAL_TIM_ConfigClockSource+0xa6> 8006188: 2b70 cmp r3, #112 ; 0x70 800618a: d87b bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 800618c: 2b60 cmp r3, #96 ; 0x60 800618e: d050 beq.n 8006232 <HAL_TIM_ConfigClockSource+0x11a> 8006190: 2b60 cmp r3, #96 ; 0x60 8006192: d877 bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 8006194: 2b50 cmp r3, #80 ; 0x50 8006196: d03c beq.n 8006212 <HAL_TIM_ConfigClockSource+0xfa> 8006198: 2b50 cmp r3, #80 ; 0x50 800619a: d873 bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 800619c: 2b40 cmp r3, #64 ; 0x40 800619e: d058 beq.n 8006252 <HAL_TIM_ConfigClockSource+0x13a> 80061a0: 2b40 cmp r3, #64 ; 0x40 80061a2: d86f bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 80061a4: 2b30 cmp r3, #48 ; 0x30 80061a6: d064 beq.n 8006272 <HAL_TIM_ConfigClockSource+0x15a> 80061a8: 2b30 cmp r3, #48 ; 0x30 80061aa: d86b bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 80061ac: 2b20 cmp r3, #32 80061ae: d060 beq.n 8006272 <HAL_TIM_ConfigClockSource+0x15a> 80061b0: 2b20 cmp r3, #32 80061b2: d867 bhi.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> 80061b4: 2b00 cmp r3, #0 80061b6: d05c beq.n 8006272 <HAL_TIM_ConfigClockSource+0x15a> 80061b8: 2b10 cmp r3, #16 80061ba: d05a beq.n 8006272 <HAL_TIM_ConfigClockSource+0x15a> 80061bc: e062 b.n 8006284 <HAL_TIM_ConfigClockSource+0x16c> assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80061be: 687b ldr r3, [r7, #4] 80061c0: 6818 ldr r0, [r3, #0] 80061c2: 683b ldr r3, [r7, #0] 80061c4: 6899 ldr r1, [r3, #8] 80061c6: 683b ldr r3, [r7, #0] 80061c8: 685a ldr r2, [r3, #4] 80061ca: 683b ldr r3, [r7, #0] 80061cc: 68db ldr r3, [r3, #12] 80061ce: f000 fb15 bl 80067fc <TIM_ETR_SetConfig> sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80061d2: 687b ldr r3, [r7, #4] 80061d4: 681b ldr r3, [r3, #0] 80061d6: 689b ldr r3, [r3, #8] 80061d8: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80061da: 68bb ldr r3, [r7, #8] 80061dc: f043 0377 orr.w r3, r3, #119 ; 0x77 80061e0: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80061e2: 687b ldr r3, [r7, #4] 80061e4: 681b ldr r3, [r3, #0] 80061e6: 68ba ldr r2, [r7, #8] 80061e8: 609a str r2, [r3, #8] break; 80061ea: e04f b.n 800628c <HAL_TIM_ConfigClockSource+0x174> assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80061ec: 687b ldr r3, [r7, #4] 80061ee: 6818 ldr r0, [r3, #0] 80061f0: 683b ldr r3, [r7, #0] 80061f2: 6899 ldr r1, [r3, #8] 80061f4: 683b ldr r3, [r7, #0] 80061f6: 685a ldr r2, [r3, #4] 80061f8: 683b ldr r3, [r7, #0] 80061fa: 68db ldr r3, [r3, #12] 80061fc: f000 fafe bl 80067fc <TIM_ETR_SetConfig> sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8006200: 687b ldr r3, [r7, #4] 8006202: 681b ldr r3, [r3, #0] 8006204: 689a ldr r2, [r3, #8] 8006206: 687b ldr r3, [r7, #4] 8006208: 681b ldr r3, [r3, #0] 800620a: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800620e: 609a str r2, [r3, #8] break; 8006210: e03c b.n 800628c <HAL_TIM_ConfigClockSource+0x174> /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006212: 687b ldr r3, [r7, #4] 8006214: 6818 ldr r0, [r3, #0] 8006216: 683b ldr r3, [r7, #0] 8006218: 6859 ldr r1, [r3, #4] 800621a: 683b ldr r3, [r7, #0] 800621c: 68db ldr r3, [r3, #12] 800621e: 461a mov r2, r3 8006220: f000 fa5c bl 80066dc <TIM_TI1_ConfigInputStage> sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8006224: 687b ldr r3, [r7, #4] 8006226: 681b ldr r3, [r3, #0] 8006228: 2150 movs r1, #80 ; 0x50 800622a: 4618 mov r0, r3 800622c: f000 facc bl 80067c8 <TIM_ITRx_SetConfig> break; 8006230: e02c b.n 800628c <HAL_TIM_ConfigClockSource+0x174> /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8006232: 687b ldr r3, [r7, #4] 8006234: 6818 ldr r0, [r3, #0] 8006236: 683b ldr r3, [r7, #0] 8006238: 6859 ldr r1, [r3, #4] 800623a: 683b ldr r3, [r7, #0] 800623c: 68db ldr r3, [r3, #12] 800623e: 461a mov r2, r3 8006240: f000 fa86 bl 8006750 <TIM_TI2_ConfigInputStage> sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8006244: 687b ldr r3, [r7, #4] 8006246: 681b ldr r3, [r3, #0] 8006248: 2160 movs r1, #96 ; 0x60 800624a: 4618 mov r0, r3 800624c: f000 fabc bl 80067c8 <TIM_ITRx_SetConfig> break; 8006250: e01c b.n 800628c <HAL_TIM_ConfigClockSource+0x174> /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006252: 687b ldr r3, [r7, #4] 8006254: 6818 ldr r0, [r3, #0] 8006256: 683b ldr r3, [r7, #0] 8006258: 6859 ldr r1, [r3, #4] 800625a: 683b ldr r3, [r7, #0] 800625c: 68db ldr r3, [r3, #12] 800625e: 461a mov r2, r3 8006260: f000 fa3c bl 80066dc <TIM_TI1_ConfigInputStage> sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8006264: 687b ldr r3, [r7, #4] 8006266: 681b ldr r3, [r3, #0] 8006268: 2140 movs r1, #64 ; 0x40 800626a: 4618 mov r0, r3 800626c: f000 faac bl 80067c8 <TIM_ITRx_SetConfig> break; 8006270: e00c b.n 800628c <HAL_TIM_ConfigClockSource+0x174> case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8006272: 687b ldr r3, [r7, #4] 8006274: 681a ldr r2, [r3, #0] 8006276: 683b ldr r3, [r7, #0] 8006278: 681b ldr r3, [r3, #0] 800627a: 4619 mov r1, r3 800627c: 4610 mov r0, r2 800627e: f000 faa3 bl 80067c8 <TIM_ITRx_SetConfig> break; 8006282: e003 b.n 800628c <HAL_TIM_ConfigClockSource+0x174> } default: status = HAL_ERROR; 8006284: 2301 movs r3, #1 8006286: 73fb strb r3, [r7, #15] break; 8006288: e000 b.n 800628c <HAL_TIM_ConfigClockSource+0x174> break; 800628a: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800628c: 687b ldr r3, [r7, #4] 800628e: 2201 movs r2, #1 8006290: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8006294: 687b ldr r3, [r7, #4] 8006296: 2200 movs r2, #0 8006298: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 800629c: 7bfb ldrb r3, [r7, #15] } 800629e: 4618 mov r0, r3 80062a0: 3710 adds r7, #16 80062a2: 46bd mov sp, r7 80062a4: bd80 pop {r7, pc} 080062a6 <HAL_TIM_OC_DelayElapsedCallback>: * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80062a6: b480 push {r7} 80062a8: b083 sub sp, #12 80062aa: af00 add r7, sp, #0 80062ac: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80062ae: bf00 nop 80062b0: 370c adds r7, #12 80062b2: 46bd mov sp, r7 80062b4: bc80 pop {r7} 80062b6: 4770 bx lr 080062b8 <HAL_TIM_IC_CaptureCallback>: * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80062b8: b480 push {r7} 80062ba: b083 sub sp, #12 80062bc: af00 add r7, sp, #0 80062be: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80062c0: bf00 nop 80062c2: 370c adds r7, #12 80062c4: 46bd mov sp, r7 80062c6: bc80 pop {r7} 80062c8: 4770 bx lr 080062ca <HAL_TIM_PWM_PulseFinishedCallback>: * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80062ca: b480 push {r7} 80062cc: b083 sub sp, #12 80062ce: af00 add r7, sp, #0 80062d0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80062d2: bf00 nop 80062d4: 370c adds r7, #12 80062d6: 46bd mov sp, r7 80062d8: bc80 pop {r7} 80062da: 4770 bx lr 080062dc <HAL_TIM_TriggerCallback>: * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80062dc: b480 push {r7} 80062de: b083 sub sp, #12 80062e0: af00 add r7, sp, #0 80062e2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80062e4: bf00 nop 80062e6: 370c adds r7, #12 80062e8: 46bd mov sp, r7 80062ea: bc80 pop {r7} 80062ec: 4770 bx lr ... 080062f0 <TIM_Base_SetConfig>: * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80062f0: b480 push {r7} 80062f2: b085 sub sp, #20 80062f4: af00 add r7, sp, #0 80062f6: 6078 str r0, [r7, #4] 80062f8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80062fa: 687b ldr r3, [r7, #4] 80062fc: 681b ldr r3, [r3, #0] 80062fe: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8006300: 687b ldr r3, [r7, #4] 8006302: 4a2c ldr r2, [pc, #176] ; (80063b4 <TIM_Base_SetConfig+0xc4>) 8006304: 4293 cmp r3, r2 8006306: d00b beq.n 8006320 <TIM_Base_SetConfig+0x30> 8006308: 687b ldr r3, [r7, #4] 800630a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800630e: d007 beq.n 8006320 <TIM_Base_SetConfig+0x30> 8006310: 687b ldr r3, [r7, #4] 8006312: 4a29 ldr r2, [pc, #164] ; (80063b8 <TIM_Base_SetConfig+0xc8>) 8006314: 4293 cmp r3, r2 8006316: d003 beq.n 8006320 <TIM_Base_SetConfig+0x30> 8006318: 687b ldr r3, [r7, #4] 800631a: 4a28 ldr r2, [pc, #160] ; (80063bc <TIM_Base_SetConfig+0xcc>) 800631c: 4293 cmp r3, r2 800631e: d108 bne.n 8006332 <TIM_Base_SetConfig+0x42> { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8006320: 68fb ldr r3, [r7, #12] 8006322: f023 0370 bic.w r3, r3, #112 ; 0x70 8006326: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8006328: 683b ldr r3, [r7, #0] 800632a: 685b ldr r3, [r3, #4] 800632c: 68fa ldr r2, [r7, #12] 800632e: 4313 orrs r3, r2 8006330: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8006332: 687b ldr r3, [r7, #4] 8006334: 4a1f ldr r2, [pc, #124] ; (80063b4 <TIM_Base_SetConfig+0xc4>) 8006336: 4293 cmp r3, r2 8006338: d00b beq.n 8006352 <TIM_Base_SetConfig+0x62> 800633a: 687b ldr r3, [r7, #4] 800633c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8006340: d007 beq.n 8006352 <TIM_Base_SetConfig+0x62> 8006342: 687b ldr r3, [r7, #4] 8006344: 4a1c ldr r2, [pc, #112] ; (80063b8 <TIM_Base_SetConfig+0xc8>) 8006346: 4293 cmp r3, r2 8006348: d003 beq.n 8006352 <TIM_Base_SetConfig+0x62> 800634a: 687b ldr r3, [r7, #4] 800634c: 4a1b ldr r2, [pc, #108] ; (80063bc <TIM_Base_SetConfig+0xcc>) 800634e: 4293 cmp r3, r2 8006350: d108 bne.n 8006364 <TIM_Base_SetConfig+0x74> { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8006352: 68fb ldr r3, [r7, #12] 8006354: f423 7340 bic.w r3, r3, #768 ; 0x300 8006358: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800635a: 683b ldr r3, [r7, #0] 800635c: 68db ldr r3, [r3, #12] 800635e: 68fa ldr r2, [r7, #12] 8006360: 4313 orrs r3, r2 8006362: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8006364: 68fb ldr r3, [r7, #12] 8006366: f023 0280 bic.w r2, r3, #128 ; 0x80 800636a: 683b ldr r3, [r7, #0] 800636c: 695b ldr r3, [r3, #20] 800636e: 4313 orrs r3, r2 8006370: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8006372: 683b ldr r3, [r7, #0] 8006374: 689a ldr r2, [r3, #8] 8006376: 687b ldr r3, [r7, #4] 8006378: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800637a: 683b ldr r3, [r7, #0] 800637c: 681a ldr r2, [r3, #0] 800637e: 687b ldr r3, [r7, #4] 8006380: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8006382: 687b ldr r3, [r7, #4] 8006384: 4a0b ldr r2, [pc, #44] ; (80063b4 <TIM_Base_SetConfig+0xc4>) 8006386: 4293 cmp r3, r2 8006388: d103 bne.n 8006392 <TIM_Base_SetConfig+0xa2> { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800638a: 683b ldr r3, [r7, #0] 800638c: 691a ldr r2, [r3, #16] 800638e: 687b ldr r3, [r7, #4] 8006390: 631a str r2, [r3, #48] ; 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8006392: 687b ldr r3, [r7, #4] 8006394: 681b ldr r3, [r3, #0] 8006396: f043 0204 orr.w r2, r3, #4 800639a: 687b ldr r3, [r7, #4] 800639c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800639e: 687b ldr r3, [r7, #4] 80063a0: 2201 movs r2, #1 80063a2: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80063a4: 687b ldr r3, [r7, #4] 80063a6: 68fa ldr r2, [r7, #12] 80063a8: 601a str r2, [r3, #0] } 80063aa: bf00 nop 80063ac: 3714 adds r7, #20 80063ae: 46bd mov sp, r7 80063b0: bc80 pop {r7} 80063b2: 4770 bx lr 80063b4: 40012c00 .word 0x40012c00 80063b8: 40000400 .word 0x40000400 80063bc: 40000800 .word 0x40000800 080063c0 <TIM_OC1_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80063c0: b480 push {r7} 80063c2: b087 sub sp, #28 80063c4: af00 add r7, sp, #0 80063c6: 6078 str r0, [r7, #4] 80063c8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80063ca: 687b ldr r3, [r7, #4] 80063cc: 6a1b ldr r3, [r3, #32] 80063ce: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80063d0: 687b ldr r3, [r7, #4] 80063d2: 6a1b ldr r3, [r3, #32] 80063d4: f023 0201 bic.w r2, r3, #1 80063d8: 687b ldr r3, [r7, #4] 80063da: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80063dc: 687b ldr r3, [r7, #4] 80063de: 685b ldr r3, [r3, #4] 80063e0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80063e2: 687b ldr r3, [r7, #4] 80063e4: 699b ldr r3, [r3, #24] 80063e6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80063e8: 68fb ldr r3, [r7, #12] 80063ea: f023 0370 bic.w r3, r3, #112 ; 0x70 80063ee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80063f0: 68fb ldr r3, [r7, #12] 80063f2: f023 0303 bic.w r3, r3, #3 80063f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80063f8: 683b ldr r3, [r7, #0] 80063fa: 681b ldr r3, [r3, #0] 80063fc: 68fa ldr r2, [r7, #12] 80063fe: 4313 orrs r3, r2 8006400: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8006402: 697b ldr r3, [r7, #20] 8006404: f023 0302 bic.w r3, r3, #2 8006408: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800640a: 683b ldr r3, [r7, #0] 800640c: 689b ldr r3, [r3, #8] 800640e: 697a ldr r2, [r7, #20] 8006410: 4313 orrs r3, r2 8006412: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8006414: 687b ldr r3, [r7, #4] 8006416: 4a1d ldr r2, [pc, #116] ; (800648c <TIM_OC1_SetConfig+0xcc>) 8006418: 4293 cmp r3, r2 800641a: d10e bne.n 800643a <TIM_OC1_SetConfig+0x7a> { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 1N: Reset the CC1NE Bit */ TIMx->CCER &= ~TIM_CCER_CC1NE; 800641c: 687b ldr r3, [r7, #4] 800641e: 6a1b ldr r3, [r3, #32] 8006420: f023 0204 bic.w r2, r3, #4 8006424: 687b ldr r3, [r7, #4] 8006426: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8006428: 697b ldr r3, [r7, #20] 800642a: f023 0308 bic.w r3, r3, #8 800642e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8006430: 683b ldr r3, [r7, #0] 8006432: 68db ldr r3, [r3, #12] 8006434: 697a ldr r2, [r7, #20] 8006436: 4313 orrs r3, r2 8006438: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800643a: 687b ldr r3, [r7, #4] 800643c: 4a13 ldr r2, [pc, #76] ; (800648c <TIM_OC1_SetConfig+0xcc>) 800643e: 4293 cmp r3, r2 8006440: d111 bne.n 8006466 <TIM_OC1_SetConfig+0xa6> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8006442: 693b ldr r3, [r7, #16] 8006444: f423 7380 bic.w r3, r3, #256 ; 0x100 8006448: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800644a: 693b ldr r3, [r7, #16] 800644c: f423 7300 bic.w r3, r3, #512 ; 0x200 8006450: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8006452: 683b ldr r3, [r7, #0] 8006454: 695b ldr r3, [r3, #20] 8006456: 693a ldr r2, [r7, #16] 8006458: 4313 orrs r3, r2 800645a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800645c: 683b ldr r3, [r7, #0] 800645e: 699b ldr r3, [r3, #24] 8006460: 693a ldr r2, [r7, #16] 8006462: 4313 orrs r3, r2 8006464: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006466: 687b ldr r3, [r7, #4] 8006468: 693a ldr r2, [r7, #16] 800646a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800646c: 687b ldr r3, [r7, #4] 800646e: 68fa ldr r2, [r7, #12] 8006470: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8006472: 683b ldr r3, [r7, #0] 8006474: 685a ldr r2, [r3, #4] 8006476: 687b ldr r3, [r7, #4] 8006478: 635a str r2, [r3, #52] ; 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800647a: 687b ldr r3, [r7, #4] 800647c: 697a ldr r2, [r7, #20] 800647e: 621a str r2, [r3, #32] } 8006480: bf00 nop 8006482: 371c adds r7, #28 8006484: 46bd mov sp, r7 8006486: bc80 pop {r7} 8006488: 4770 bx lr 800648a: bf00 nop 800648c: 40012c00 .word 0x40012c00 08006490 <TIM_OC2_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006490: b480 push {r7} 8006492: b087 sub sp, #28 8006494: af00 add r7, sp, #0 8006496: 6078 str r0, [r7, #4] 8006498: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800649a: 687b ldr r3, [r7, #4] 800649c: 6a1b ldr r3, [r3, #32] 800649e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80064a0: 687b ldr r3, [r7, #4] 80064a2: 6a1b ldr r3, [r3, #32] 80064a4: f023 0210 bic.w r2, r3, #16 80064a8: 687b ldr r3, [r7, #4] 80064aa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80064ac: 687b ldr r3, [r7, #4] 80064ae: 685b ldr r3, [r3, #4] 80064b0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80064b2: 687b ldr r3, [r7, #4] 80064b4: 699b ldr r3, [r3, #24] 80064b6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80064b8: 68fb ldr r3, [r7, #12] 80064ba: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 80064be: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80064c0: 68fb ldr r3, [r7, #12] 80064c2: f423 7340 bic.w r3, r3, #768 ; 0x300 80064c6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80064c8: 683b ldr r3, [r7, #0] 80064ca: 681b ldr r3, [r3, #0] 80064cc: 021b lsls r3, r3, #8 80064ce: 68fa ldr r2, [r7, #12] 80064d0: 4313 orrs r3, r2 80064d2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80064d4: 697b ldr r3, [r7, #20] 80064d6: f023 0320 bic.w r3, r3, #32 80064da: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80064dc: 683b ldr r3, [r7, #0] 80064de: 689b ldr r3, [r3, #8] 80064e0: 011b lsls r3, r3, #4 80064e2: 697a ldr r2, [r7, #20] 80064e4: 4313 orrs r3, r2 80064e6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80064e8: 687b ldr r3, [r7, #4] 80064ea: 4a1e ldr r2, [pc, #120] ; (8006564 <TIM_OC2_SetConfig+0xd4>) 80064ec: 4293 cmp r3, r2 80064ee: d10f bne.n 8006510 <TIM_OC2_SetConfig+0x80> { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 2N: Reset the CC2NE Bit */ TIMx->CCER &= ~TIM_CCER_CC2NE; 80064f0: 687b ldr r3, [r7, #4] 80064f2: 6a1b ldr r3, [r3, #32] 80064f4: f023 0240 bic.w r2, r3, #64 ; 0x40 80064f8: 687b ldr r3, [r7, #4] 80064fa: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80064fc: 697b ldr r3, [r7, #20] 80064fe: f023 0380 bic.w r3, r3, #128 ; 0x80 8006502: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8006504: 683b ldr r3, [r7, #0] 8006506: 68db ldr r3, [r3, #12] 8006508: 011b lsls r3, r3, #4 800650a: 697a ldr r2, [r7, #20] 800650c: 4313 orrs r3, r2 800650e: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006510: 687b ldr r3, [r7, #4] 8006512: 4a14 ldr r2, [pc, #80] ; (8006564 <TIM_OC2_SetConfig+0xd4>) 8006514: 4293 cmp r3, r2 8006516: d113 bne.n 8006540 <TIM_OC2_SetConfig+0xb0> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8006518: 693b ldr r3, [r7, #16] 800651a: f423 6380 bic.w r3, r3, #1024 ; 0x400 800651e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8006520: 693b ldr r3, [r7, #16] 8006522: f423 6300 bic.w r3, r3, #2048 ; 0x800 8006526: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8006528: 683b ldr r3, [r7, #0] 800652a: 695b ldr r3, [r3, #20] 800652c: 009b lsls r3, r3, #2 800652e: 693a ldr r2, [r7, #16] 8006530: 4313 orrs r3, r2 8006532: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8006534: 683b ldr r3, [r7, #0] 8006536: 699b ldr r3, [r3, #24] 8006538: 009b lsls r3, r3, #2 800653a: 693a ldr r2, [r7, #16] 800653c: 4313 orrs r3, r2 800653e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006540: 687b ldr r3, [r7, #4] 8006542: 693a ldr r2, [r7, #16] 8006544: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8006546: 687b ldr r3, [r7, #4] 8006548: 68fa ldr r2, [r7, #12] 800654a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800654c: 683b ldr r3, [r7, #0] 800654e: 685a ldr r2, [r3, #4] 8006550: 687b ldr r3, [r7, #4] 8006552: 639a str r2, [r3, #56] ; 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006554: 687b ldr r3, [r7, #4] 8006556: 697a ldr r2, [r7, #20] 8006558: 621a str r2, [r3, #32] } 800655a: bf00 nop 800655c: 371c adds r7, #28 800655e: 46bd mov sp, r7 8006560: bc80 pop {r7} 8006562: 4770 bx lr 8006564: 40012c00 .word 0x40012c00 08006568 <TIM_OC3_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006568: b480 push {r7} 800656a: b087 sub sp, #28 800656c: af00 add r7, sp, #0 800656e: 6078 str r0, [r7, #4] 8006570: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006572: 687b ldr r3, [r7, #4] 8006574: 6a1b ldr r3, [r3, #32] 8006576: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8006578: 687b ldr r3, [r7, #4] 800657a: 6a1b ldr r3, [r3, #32] 800657c: f423 7280 bic.w r2, r3, #256 ; 0x100 8006580: 687b ldr r3, [r7, #4] 8006582: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006584: 687b ldr r3, [r7, #4] 8006586: 685b ldr r3, [r3, #4] 8006588: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800658a: 687b ldr r3, [r7, #4] 800658c: 69db ldr r3, [r3, #28] 800658e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8006590: 68fb ldr r3, [r7, #12] 8006592: f023 0370 bic.w r3, r3, #112 ; 0x70 8006596: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8006598: 68fb ldr r3, [r7, #12] 800659a: f023 0303 bic.w r3, r3, #3 800659e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80065a0: 683b ldr r3, [r7, #0] 80065a2: 681b ldr r3, [r3, #0] 80065a4: 68fa ldr r2, [r7, #12] 80065a6: 4313 orrs r3, r2 80065a8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80065aa: 697b ldr r3, [r7, #20] 80065ac: f423 7300 bic.w r3, r3, #512 ; 0x200 80065b0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80065b2: 683b ldr r3, [r7, #0] 80065b4: 689b ldr r3, [r3, #8] 80065b6: 021b lsls r3, r3, #8 80065b8: 697a ldr r2, [r7, #20] 80065ba: 4313 orrs r3, r2 80065bc: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80065be: 687b ldr r3, [r7, #4] 80065c0: 4a1e ldr r2, [pc, #120] ; (800663c <TIM_OC3_SetConfig+0xd4>) 80065c2: 4293 cmp r3, r2 80065c4: d10f bne.n 80065e6 <TIM_OC3_SetConfig+0x7e> { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 3N: Reset the CC3NE Bit */ TIMx->CCER &= ~TIM_CCER_CC3NE; 80065c6: 687b ldr r3, [r7, #4] 80065c8: 6a1b ldr r3, [r3, #32] 80065ca: f423 6280 bic.w r2, r3, #1024 ; 0x400 80065ce: 687b ldr r3, [r7, #4] 80065d0: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80065d2: 697b ldr r3, [r7, #20] 80065d4: f423 6300 bic.w r3, r3, #2048 ; 0x800 80065d8: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80065da: 683b ldr r3, [r7, #0] 80065dc: 68db ldr r3, [r3, #12] 80065de: 021b lsls r3, r3, #8 80065e0: 697a ldr r2, [r7, #20] 80065e2: 4313 orrs r3, r2 80065e4: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80065e6: 687b ldr r3, [r7, #4] 80065e8: 4a14 ldr r2, [pc, #80] ; (800663c <TIM_OC3_SetConfig+0xd4>) 80065ea: 4293 cmp r3, r2 80065ec: d113 bne.n 8006616 <TIM_OC3_SetConfig+0xae> /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80065ee: 693b ldr r3, [r7, #16] 80065f0: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80065f4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80065f6: 693b ldr r3, [r7, #16] 80065f8: f423 5300 bic.w r3, r3, #8192 ; 0x2000 80065fc: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80065fe: 683b ldr r3, [r7, #0] 8006600: 695b ldr r3, [r3, #20] 8006602: 011b lsls r3, r3, #4 8006604: 693a ldr r2, [r7, #16] 8006606: 4313 orrs r3, r2 8006608: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800660a: 683b ldr r3, [r7, #0] 800660c: 699b ldr r3, [r3, #24] 800660e: 011b lsls r3, r3, #4 8006610: 693a ldr r2, [r7, #16] 8006612: 4313 orrs r3, r2 8006614: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006616: 687b ldr r3, [r7, #4] 8006618: 693a ldr r2, [r7, #16] 800661a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800661c: 687b ldr r3, [r7, #4] 800661e: 68fa ldr r2, [r7, #12] 8006620: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8006622: 683b ldr r3, [r7, #0] 8006624: 685a ldr r2, [r3, #4] 8006626: 687b ldr r3, [r7, #4] 8006628: 63da str r2, [r3, #60] ; 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800662a: 687b ldr r3, [r7, #4] 800662c: 697a ldr r2, [r7, #20] 800662e: 621a str r2, [r3, #32] } 8006630: bf00 nop 8006632: 371c adds r7, #28 8006634: 46bd mov sp, r7 8006636: bc80 pop {r7} 8006638: 4770 bx lr 800663a: bf00 nop 800663c: 40012c00 .word 0x40012c00 08006640 <TIM_OC4_SetConfig>: * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006640: b480 push {r7} 8006642: b087 sub sp, #28 8006644: af00 add r7, sp, #0 8006646: 6078 str r0, [r7, #4] 8006648: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800664a: 687b ldr r3, [r7, #4] 800664c: 6a1b ldr r3, [r3, #32] 800664e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8006650: 687b ldr r3, [r7, #4] 8006652: 6a1b ldr r3, [r3, #32] 8006654: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8006658: 687b ldr r3, [r7, #4] 800665a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800665c: 687b ldr r3, [r7, #4] 800665e: 685b ldr r3, [r3, #4] 8006660: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8006662: 687b ldr r3, [r7, #4] 8006664: 69db ldr r3, [r3, #28] 8006666: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8006668: 68fb ldr r3, [r7, #12] 800666a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 800666e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8006670: 68fb ldr r3, [r7, #12] 8006672: f423 7340 bic.w r3, r3, #768 ; 0x300 8006676: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8006678: 683b ldr r3, [r7, #0] 800667a: 681b ldr r3, [r3, #0] 800667c: 021b lsls r3, r3, #8 800667e: 68fa ldr r2, [r7, #12] 8006680: 4313 orrs r3, r2 8006682: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8006684: 693b ldr r3, [r7, #16] 8006686: f423 5300 bic.w r3, r3, #8192 ; 0x2000 800668a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800668c: 683b ldr r3, [r7, #0] 800668e: 689b ldr r3, [r3, #8] 8006690: 031b lsls r3, r3, #12 8006692: 693a ldr r2, [r7, #16] 8006694: 4313 orrs r3, r2 8006696: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006698: 687b ldr r3, [r7, #4] 800669a: 4a0f ldr r2, [pc, #60] ; (80066d8 <TIM_OC4_SetConfig+0x98>) 800669c: 4293 cmp r3, r2 800669e: d109 bne.n 80066b4 <TIM_OC4_SetConfig+0x74> { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80066a0: 697b ldr r3, [r7, #20] 80066a2: f423 4380 bic.w r3, r3, #16384 ; 0x4000 80066a6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80066a8: 683b ldr r3, [r7, #0] 80066aa: 695b ldr r3, [r3, #20] 80066ac: 019b lsls r3, r3, #6 80066ae: 697a ldr r2, [r7, #20] 80066b0: 4313 orrs r3, r2 80066b2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80066b4: 687b ldr r3, [r7, #4] 80066b6: 697a ldr r2, [r7, #20] 80066b8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80066ba: 687b ldr r3, [r7, #4] 80066bc: 68fa ldr r2, [r7, #12] 80066be: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80066c0: 683b ldr r3, [r7, #0] 80066c2: 685a ldr r2, [r3, #4] 80066c4: 687b ldr r3, [r7, #4] 80066c6: 641a str r2, [r3, #64] ; 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80066c8: 687b ldr r3, [r7, #4] 80066ca: 693a ldr r2, [r7, #16] 80066cc: 621a str r2, [r3, #32] } 80066ce: bf00 nop 80066d0: 371c adds r7, #28 80066d2: 46bd mov sp, r7 80066d4: bc80 pop {r7} 80066d6: 4770 bx lr 80066d8: 40012c00 .word 0x40012c00 080066dc <TIM_TI1_ConfigInputStage>: * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80066dc: b480 push {r7} 80066de: b087 sub sp, #28 80066e0: af00 add r7, sp, #0 80066e2: 60f8 str r0, [r7, #12] 80066e4: 60b9 str r1, [r7, #8] 80066e6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80066e8: 68fb ldr r3, [r7, #12] 80066ea: 6a1b ldr r3, [r3, #32] 80066ec: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80066ee: 68fb ldr r3, [r7, #12] 80066f0: 6a1b ldr r3, [r3, #32] 80066f2: f023 0201 bic.w r2, r3, #1 80066f6: 68fb ldr r3, [r7, #12] 80066f8: 621a str r2, [r3, #32] /* Disable the Channel 1N: Reset the CC1NE Bit */ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80066fa: 68fb ldr r3, [r7, #12] 80066fc: 4a13 ldr r2, [pc, #76] ; (800674c <TIM_TI1_ConfigInputStage+0x70>) 80066fe: 4293 cmp r3, r2 8006700: d105 bne.n 800670e <TIM_TI1_ConfigInputStage+0x32> { TIMx->CCER &= ~TIM_CCER_CC1NE; 8006702: 68fb ldr r3, [r7, #12] 8006704: 6a1b ldr r3, [r3, #32] 8006706: f023 0204 bic.w r2, r3, #4 800670a: 68fb ldr r3, [r7, #12] 800670c: 621a str r2, [r3, #32] } /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; 800670e: 68fb ldr r3, [r7, #12] 8006710: 699b ldr r3, [r3, #24] 8006712: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8006714: 693b ldr r3, [r7, #16] 8006716: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800671a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 800671c: 687b ldr r3, [r7, #4] 800671e: 011b lsls r3, r3, #4 8006720: 693a ldr r2, [r7, #16] 8006722: 4313 orrs r3, r2 8006724: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8006726: 697b ldr r3, [r7, #20] 8006728: f023 030a bic.w r3, r3, #10 800672c: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800672e: 697a ldr r2, [r7, #20] 8006730: 68bb ldr r3, [r7, #8] 8006732: 4313 orrs r3, r2 8006734: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8006736: 68fb ldr r3, [r7, #12] 8006738: 693a ldr r2, [r7, #16] 800673a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 800673c: 68fb ldr r3, [r7, #12] 800673e: 697a ldr r2, [r7, #20] 8006740: 621a str r2, [r3, #32] } 8006742: bf00 nop 8006744: 371c adds r7, #28 8006746: 46bd mov sp, r7 8006748: bc80 pop {r7} 800674a: 4770 bx lr 800674c: 40012c00 .word 0x40012c00 08006750 <TIM_TI2_ConfigInputStage>: * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8006750: b480 push {r7} 8006752: b087 sub sp, #28 8006754: af00 add r7, sp, #0 8006756: 60f8 str r0, [r7, #12] 8006758: 60b9 str r1, [r7, #8] 800675a: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800675c: 68fb ldr r3, [r7, #12] 800675e: 6a1b ldr r3, [r3, #32] 8006760: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8006762: 68fb ldr r3, [r7, #12] 8006764: 6a1b ldr r3, [r3, #32] 8006766: f023 0210 bic.w r2, r3, #16 800676a: 68fb ldr r3, [r7, #12] 800676c: 621a str r2, [r3, #32] /* Disable the Channel 2N: Reset the CC2NE Bit */ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800676e: 68fb ldr r3, [r7, #12] 8006770: 4a14 ldr r2, [pc, #80] ; (80067c4 <TIM_TI2_ConfigInputStage+0x74>) 8006772: 4293 cmp r3, r2 8006774: d105 bne.n 8006782 <TIM_TI2_ConfigInputStage+0x32> { TIMx->CCER &= ~TIM_CCER_CC2NE; 8006776: 68fb ldr r3, [r7, #12] 8006778: 6a1b ldr r3, [r3, #32] 800677a: f023 0240 bic.w r2, r3, #64 ; 0x40 800677e: 68fb ldr r3, [r7, #12] 8006780: 621a str r2, [r3, #32] } /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; 8006782: 68fb ldr r3, [r7, #12] 8006784: 699b ldr r3, [r3, #24] 8006786: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8006788: 693b ldr r3, [r7, #16] 800678a: f423 4370 bic.w r3, r3, #61440 ; 0xf000 800678e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8006790: 687b ldr r3, [r7, #4] 8006792: 031b lsls r3, r3, #12 8006794: 693a ldr r2, [r7, #16] 8006796: 4313 orrs r3, r2 8006798: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 800679a: 697b ldr r3, [r7, #20] 800679c: f023 03a0 bic.w r3, r3, #160 ; 0xa0 80067a0: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 80067a2: 68bb ldr r3, [r7, #8] 80067a4: 011b lsls r3, r3, #4 80067a6: 697a ldr r2, [r7, #20] 80067a8: 4313 orrs r3, r2 80067aa: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80067ac: 68fb ldr r3, [r7, #12] 80067ae: 693a ldr r2, [r7, #16] 80067b0: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80067b2: 68fb ldr r3, [r7, #12] 80067b4: 697a ldr r2, [r7, #20] 80067b6: 621a str r2, [r3, #32] } 80067b8: bf00 nop 80067ba: 371c adds r7, #28 80067bc: 46bd mov sp, r7 80067be: bc80 pop {r7} 80067c0: 4770 bx lr 80067c2: bf00 nop 80067c4: 40012c00 .word 0x40012c00 080067c8 <TIM_ITRx_SetConfig>: * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80067c8: b480 push {r7} 80067ca: b085 sub sp, #20 80067cc: af00 add r7, sp, #0 80067ce: 6078 str r0, [r7, #4] 80067d0: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80067d2: 687b ldr r3, [r7, #4] 80067d4: 689b ldr r3, [r3, #8] 80067d6: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80067d8: 68fb ldr r3, [r7, #12] 80067da: f023 0370 bic.w r3, r3, #112 ; 0x70 80067de: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80067e0: 683a ldr r2, [r7, #0] 80067e2: 68fb ldr r3, [r7, #12] 80067e4: 4313 orrs r3, r2 80067e6: f043 0307 orr.w r3, r3, #7 80067ea: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80067ec: 687b ldr r3, [r7, #4] 80067ee: 68fa ldr r2, [r7, #12] 80067f0: 609a str r2, [r3, #8] } 80067f2: bf00 nop 80067f4: 3714 adds r7, #20 80067f6: 46bd mov sp, r7 80067f8: bc80 pop {r7} 80067fa: 4770 bx lr 080067fc <TIM_ETR_SetConfig>: * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80067fc: b480 push {r7} 80067fe: b087 sub sp, #28 8006800: af00 add r7, sp, #0 8006802: 60f8 str r0, [r7, #12] 8006804: 60b9 str r1, [r7, #8] 8006806: 607a str r2, [r7, #4] 8006808: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 800680a: 68fb ldr r3, [r7, #12] 800680c: 689b ldr r3, [r3, #8] 800680e: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8006810: 697b ldr r3, [r7, #20] 8006812: f423 437f bic.w r3, r3, #65280 ; 0xff00 8006816: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8006818: 683b ldr r3, [r7, #0] 800681a: 021a lsls r2, r3, #8 800681c: 687b ldr r3, [r7, #4] 800681e: 431a orrs r2, r3 8006820: 68bb ldr r3, [r7, #8] 8006822: 4313 orrs r3, r2 8006824: 697a ldr r2, [r7, #20] 8006826: 4313 orrs r3, r2 8006828: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800682a: 68fb ldr r3, [r7, #12] 800682c: 697a ldr r2, [r7, #20] 800682e: 609a str r2, [r3, #8] } 8006830: bf00 nop 8006832: 371c adds r7, #28 8006834: 46bd mov sp, r7 8006836: bc80 pop {r7} 8006838: 4770 bx lr 0800683a <TIM_CCxChannelCmd>: * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 800683a: b480 push {r7} 800683c: b087 sub sp, #28 800683e: af00 add r7, sp, #0 8006840: 60f8 str r0, [r7, #12] 8006842: 60b9 str r1, [r7, #8] 8006844: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8006846: 68bb ldr r3, [r7, #8] 8006848: f003 031f and.w r3, r3, #31 800684c: 2201 movs r2, #1 800684e: fa02 f303 lsl.w r3, r2, r3 8006852: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8006854: 68fb ldr r3, [r7, #12] 8006856: 6a1a ldr r2, [r3, #32] 8006858: 697b ldr r3, [r7, #20] 800685a: 43db mvns r3, r3 800685c: 401a ands r2, r3 800685e: 68fb ldr r3, [r7, #12] 8006860: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8006862: 68fb ldr r3, [r7, #12] 8006864: 6a1a ldr r2, [r3, #32] 8006866: 68bb ldr r3, [r7, #8] 8006868: f003 031f and.w r3, r3, #31 800686c: 6879 ldr r1, [r7, #4] 800686e: fa01 f303 lsl.w r3, r1, r3 8006872: 431a orrs r2, r3 8006874: 68fb ldr r3, [r7, #12] 8006876: 621a str r2, [r3, #32] } 8006878: bf00 nop 800687a: 371c adds r7, #28 800687c: 46bd mov sp, r7 800687e: bc80 pop {r7} 8006880: 4770 bx lr ... 08006884 <HAL_TIMEx_MasterConfigSynchronization>: * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8006884: b480 push {r7} 8006886: b085 sub sp, #20 8006888: af00 add r7, sp, #0 800688a: 6078 str r0, [r7, #4] 800688c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800688e: 687b ldr r3, [r7, #4] 8006890: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8006894: 2b01 cmp r3, #1 8006896: d101 bne.n 800689c <HAL_TIMEx_MasterConfigSynchronization+0x18> 8006898: 2302 movs r3, #2 800689a: e046 b.n 800692a <HAL_TIMEx_MasterConfigSynchronization+0xa6> 800689c: 687b ldr r3, [r7, #4] 800689e: 2201 movs r2, #1 80068a0: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80068a4: 687b ldr r3, [r7, #4] 80068a6: 2202 movs r2, #2 80068a8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80068ac: 687b ldr r3, [r7, #4] 80068ae: 681b ldr r3, [r3, #0] 80068b0: 685b ldr r3, [r3, #4] 80068b2: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80068b4: 687b ldr r3, [r7, #4] 80068b6: 681b ldr r3, [r3, #0] 80068b8: 689b ldr r3, [r3, #8] 80068ba: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80068bc: 68fb ldr r3, [r7, #12] 80068be: f023 0370 bic.w r3, r3, #112 ; 0x70 80068c2: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80068c4: 683b ldr r3, [r7, #0] 80068c6: 681b ldr r3, [r3, #0] 80068c8: 68fa ldr r2, [r7, #12] 80068ca: 4313 orrs r3, r2 80068cc: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80068ce: 687b ldr r3, [r7, #4] 80068d0: 681b ldr r3, [r3, #0] 80068d2: 68fa ldr r2, [r7, #12] 80068d4: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80068d6: 687b ldr r3, [r7, #4] 80068d8: 681b ldr r3, [r3, #0] 80068da: 4a16 ldr r2, [pc, #88] ; (8006934 <HAL_TIMEx_MasterConfigSynchronization+0xb0>) 80068dc: 4293 cmp r3, r2 80068de: d00e beq.n 80068fe <HAL_TIMEx_MasterConfigSynchronization+0x7a> 80068e0: 687b ldr r3, [r7, #4] 80068e2: 681b ldr r3, [r3, #0] 80068e4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80068e8: d009 beq.n 80068fe <HAL_TIMEx_MasterConfigSynchronization+0x7a> 80068ea: 687b ldr r3, [r7, #4] 80068ec: 681b ldr r3, [r3, #0] 80068ee: 4a12 ldr r2, [pc, #72] ; (8006938 <HAL_TIMEx_MasterConfigSynchronization+0xb4>) 80068f0: 4293 cmp r3, r2 80068f2: d004 beq.n 80068fe <HAL_TIMEx_MasterConfigSynchronization+0x7a> 80068f4: 687b ldr r3, [r7, #4] 80068f6: 681b ldr r3, [r3, #0] 80068f8: 4a10 ldr r2, [pc, #64] ; (800693c <HAL_TIMEx_MasterConfigSynchronization+0xb8>) 80068fa: 4293 cmp r3, r2 80068fc: d10c bne.n 8006918 <HAL_TIMEx_MasterConfigSynchronization+0x94> { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80068fe: 68bb ldr r3, [r7, #8] 8006900: f023 0380 bic.w r3, r3, #128 ; 0x80 8006904: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8006906: 683b ldr r3, [r7, #0] 8006908: 685b ldr r3, [r3, #4] 800690a: 68ba ldr r2, [r7, #8] 800690c: 4313 orrs r3, r2 800690e: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8006910: 687b ldr r3, [r7, #4] 8006912: 681b ldr r3, [r3, #0] 8006914: 68ba ldr r2, [r7, #8] 8006916: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8006918: 687b ldr r3, [r7, #4] 800691a: 2201 movs r2, #1 800691c: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8006920: 687b ldr r3, [r7, #4] 8006922: 2200 movs r2, #0 8006924: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8006928: 2300 movs r3, #0 } 800692a: 4618 mov r0, r3 800692c: 3714 adds r7, #20 800692e: 46bd mov sp, r7 8006930: bc80 pop {r7} 8006932: 4770 bx lr 8006934: 40012c00 .word 0x40012c00 8006938: 40000400 .word 0x40000400 800693c: 40000800 .word 0x40000800 08006940 <HAL_TIMEx_CommutCallback>: * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8006940: b480 push {r7} 8006942: b083 sub sp, #12 8006944: af00 add r7, sp, #0 8006946: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8006948: bf00 nop 800694a: 370c adds r7, #12 800694c: 46bd mov sp, r7 800694e: bc80 pop {r7} 8006950: 4770 bx lr 08006952 <HAL_TIMEx_BreakCallback>: * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8006952: b480 push {r7} 8006954: b083 sub sp, #12 8006956: af00 add r7, sp, #0 8006958: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800695a: bf00 nop 800695c: 370c adds r7, #12 800695e: 46bd mov sp, r7 8006960: bc80 pop {r7} 8006962: 4770 bx lr 08006964 <HAL_UART_Init>: * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006964: b580 push {r7, lr} 8006966: b082 sub sp, #8 8006968: af00 add r7, sp, #0 800696a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800696c: 687b ldr r3, [r7, #4] 800696e: 2b00 cmp r3, #0 8006970: d101 bne.n 8006976 <HAL_UART_Init+0x12> { return HAL_ERROR; 8006972: 2301 movs r3, #1 8006974: e042 b.n 80069fc <HAL_UART_Init+0x98> assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8006976: 687b ldr r3, [r7, #4] 8006978: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 800697c: b2db uxtb r3, r3 800697e: 2b00 cmp r3, #0 8006980: d106 bne.n 8006990 <HAL_UART_Init+0x2c> { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8006982: 687b ldr r3, [r7, #4] 8006984: 2200 movs r2, #0 8006986: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800698a: 6878 ldr r0, [r7, #4] 800698c: f7fb fbda bl 8002144 <HAL_UART_MspInit> #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8006990: 687b ldr r3, [r7, #4] 8006992: 2224 movs r2, #36 ; 0x24 8006994: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8006998: 687b ldr r3, [r7, #4] 800699a: 681b ldr r3, [r3, #0] 800699c: 68da ldr r2, [r3, #12] 800699e: 687b ldr r3, [r7, #4] 80069a0: 681b ldr r3, [r3, #0] 80069a2: f422 5200 bic.w r2, r2, #8192 ; 0x2000 80069a6: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 80069a8: 6878 ldr r0, [r7, #4] 80069aa: f000 f971 bl 8006c90 <UART_SetConfig> /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80069ae: 687b ldr r3, [r7, #4] 80069b0: 681b ldr r3, [r3, #0] 80069b2: 691a ldr r2, [r3, #16] 80069b4: 687b ldr r3, [r7, #4] 80069b6: 681b ldr r3, [r3, #0] 80069b8: f422 4290 bic.w r2, r2, #18432 ; 0x4800 80069bc: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80069be: 687b ldr r3, [r7, #4] 80069c0: 681b ldr r3, [r3, #0] 80069c2: 695a ldr r2, [r3, #20] 80069c4: 687b ldr r3, [r7, #4] 80069c6: 681b ldr r3, [r3, #0] 80069c8: f022 022a bic.w r2, r2, #42 ; 0x2a 80069cc: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80069ce: 687b ldr r3, [r7, #4] 80069d0: 681b ldr r3, [r3, #0] 80069d2: 68da ldr r2, [r3, #12] 80069d4: 687b ldr r3, [r7, #4] 80069d6: 681b ldr r3, [r3, #0] 80069d8: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80069dc: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80069de: 687b ldr r3, [r7, #4] 80069e0: 2200 movs r2, #0 80069e2: 645a str r2, [r3, #68] ; 0x44 huart->gState = HAL_UART_STATE_READY; 80069e4: 687b ldr r3, [r7, #4] 80069e6: 2220 movs r2, #32 80069e8: f883 2041 strb.w r2, [r3, #65] ; 0x41 huart->RxState = HAL_UART_STATE_READY; 80069ec: 687b ldr r3, [r7, #4] 80069ee: 2220 movs r2, #32 80069f0: f883 2042 strb.w r2, [r3, #66] ; 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 80069f4: 687b ldr r3, [r7, #4] 80069f6: 2200 movs r2, #0 80069f8: 635a str r2, [r3, #52] ; 0x34 return HAL_OK; 80069fa: 2300 movs r3, #0 } 80069fc: 4618 mov r0, r3 80069fe: 3708 adds r7, #8 8006a00: 46bd mov sp, r7 8006a02: bd80 pop {r7, pc} 08006a04 <HAL_UART_Transmit>: * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8006a04: b580 push {r7, lr} 8006a06: b08a sub sp, #40 ; 0x28 8006a08: af02 add r7, sp, #8 8006a0a: 60f8 str r0, [r7, #12] 8006a0c: 60b9 str r1, [r7, #8] 8006a0e: 603b str r3, [r7, #0] 8006a10: 4613 mov r3, r2 8006a12: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8006a14: 2300 movs r3, #0 8006a16: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8006a18: 68fb ldr r3, [r7, #12] 8006a1a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8006a1e: b2db uxtb r3, r3 8006a20: 2b20 cmp r3, #32 8006a22: d175 bne.n 8006b10 <HAL_UART_Transmit+0x10c> { if ((pData == NULL) || (Size == 0U)) 8006a24: 68bb ldr r3, [r7, #8] 8006a26: 2b00 cmp r3, #0 8006a28: d002 beq.n 8006a30 <HAL_UART_Transmit+0x2c> 8006a2a: 88fb ldrh r3, [r7, #6] 8006a2c: 2b00 cmp r3, #0 8006a2e: d101 bne.n 8006a34 <HAL_UART_Transmit+0x30> { return HAL_ERROR; 8006a30: 2301 movs r3, #1 8006a32: e06e b.n 8006b12 <HAL_UART_Transmit+0x10e> } huart->ErrorCode = HAL_UART_ERROR_NONE; 8006a34: 68fb ldr r3, [r7, #12] 8006a36: 2200 movs r2, #0 8006a38: 645a str r2, [r3, #68] ; 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8006a3a: 68fb ldr r3, [r7, #12] 8006a3c: 2221 movs r2, #33 ; 0x21 8006a3e: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8006a42: f7fc f88f bl 8002b64 <HAL_GetTick> 8006a46: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8006a48: 68fb ldr r3, [r7, #12] 8006a4a: 88fa ldrh r2, [r7, #6] 8006a4c: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8006a4e: 68fb ldr r3, [r7, #12] 8006a50: 88fa ldrh r2, [r7, #6] 8006a52: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006a54: 68fb ldr r3, [r7, #12] 8006a56: 689b ldr r3, [r3, #8] 8006a58: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8006a5c: d108 bne.n 8006a70 <HAL_UART_Transmit+0x6c> 8006a5e: 68fb ldr r3, [r7, #12] 8006a60: 691b ldr r3, [r3, #16] 8006a62: 2b00 cmp r3, #0 8006a64: d104 bne.n 8006a70 <HAL_UART_Transmit+0x6c> { pdata8bits = NULL; 8006a66: 2300 movs r3, #0 8006a68: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8006a6a: 68bb ldr r3, [r7, #8] 8006a6c: 61bb str r3, [r7, #24] 8006a6e: e003 b.n 8006a78 <HAL_UART_Transmit+0x74> } else { pdata8bits = pData; 8006a70: 68bb ldr r3, [r7, #8] 8006a72: 61fb str r3, [r7, #28] pdata16bits = NULL; 8006a74: 2300 movs r3, #0 8006a76: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8006a78: e02e b.n 8006ad8 <HAL_UART_Transmit+0xd4> { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8006a7a: 683b ldr r3, [r7, #0] 8006a7c: 9300 str r3, [sp, #0] 8006a7e: 697b ldr r3, [r7, #20] 8006a80: 2200 movs r2, #0 8006a82: 2180 movs r1, #128 ; 0x80 8006a84: 68f8 ldr r0, [r7, #12] 8006a86: f000 f848 bl 8006b1a <UART_WaitOnFlagUntilTimeout> 8006a8a: 4603 mov r3, r0 8006a8c: 2b00 cmp r3, #0 8006a8e: d005 beq.n 8006a9c <HAL_UART_Transmit+0x98> { huart->gState = HAL_UART_STATE_READY; 8006a90: 68fb ldr r3, [r7, #12] 8006a92: 2220 movs r2, #32 8006a94: f883 2041 strb.w r2, [r3, #65] ; 0x41 return HAL_TIMEOUT; 8006a98: 2303 movs r3, #3 8006a9a: e03a b.n 8006b12 <HAL_UART_Transmit+0x10e> } if (pdata8bits == NULL) 8006a9c: 69fb ldr r3, [r7, #28] 8006a9e: 2b00 cmp r3, #0 8006aa0: d10b bne.n 8006aba <HAL_UART_Transmit+0xb6> { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8006aa2: 69bb ldr r3, [r7, #24] 8006aa4: 881b ldrh r3, [r3, #0] 8006aa6: 461a mov r2, r3 8006aa8: 68fb ldr r3, [r7, #12] 8006aaa: 681b ldr r3, [r3, #0] 8006aac: f3c2 0208 ubfx r2, r2, #0, #9 8006ab0: 605a str r2, [r3, #4] pdata16bits++; 8006ab2: 69bb ldr r3, [r7, #24] 8006ab4: 3302 adds r3, #2 8006ab6: 61bb str r3, [r7, #24] 8006ab8: e007 b.n 8006aca <HAL_UART_Transmit+0xc6> } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8006aba: 69fb ldr r3, [r7, #28] 8006abc: 781a ldrb r2, [r3, #0] 8006abe: 68fb ldr r3, [r7, #12] 8006ac0: 681b ldr r3, [r3, #0] 8006ac2: 605a str r2, [r3, #4] pdata8bits++; 8006ac4: 69fb ldr r3, [r7, #28] 8006ac6: 3301 adds r3, #1 8006ac8: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8006aca: 68fb ldr r3, [r7, #12] 8006acc: 8cdb ldrh r3, [r3, #38] ; 0x26 8006ace: b29b uxth r3, r3 8006ad0: 3b01 subs r3, #1 8006ad2: b29a uxth r2, r3 8006ad4: 68fb ldr r3, [r7, #12] 8006ad6: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 8006ad8: 68fb ldr r3, [r7, #12] 8006ada: 8cdb ldrh r3, [r3, #38] ; 0x26 8006adc: b29b uxth r3, r3 8006ade: 2b00 cmp r3, #0 8006ae0: d1cb bne.n 8006a7a <HAL_UART_Transmit+0x76> } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8006ae2: 683b ldr r3, [r7, #0] 8006ae4: 9300 str r3, [sp, #0] 8006ae6: 697b ldr r3, [r7, #20] 8006ae8: 2200 movs r2, #0 8006aea: 2140 movs r1, #64 ; 0x40 8006aec: 68f8 ldr r0, [r7, #12] 8006aee: f000 f814 bl 8006b1a <UART_WaitOnFlagUntilTimeout> 8006af2: 4603 mov r3, r0 8006af4: 2b00 cmp r3, #0 8006af6: d005 beq.n 8006b04 <HAL_UART_Transmit+0x100> { huart->gState = HAL_UART_STATE_READY; 8006af8: 68fb ldr r3, [r7, #12] 8006afa: 2220 movs r2, #32 8006afc: f883 2041 strb.w r2, [r3, #65] ; 0x41 return HAL_TIMEOUT; 8006b00: 2303 movs r3, #3 8006b02: e006 b.n 8006b12 <HAL_UART_Transmit+0x10e> } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006b04: 68fb ldr r3, [r7, #12] 8006b06: 2220 movs r2, #32 8006b08: f883 2041 strb.w r2, [r3, #65] ; 0x41 return HAL_OK; 8006b0c: 2300 movs r3, #0 8006b0e: e000 b.n 8006b12 <HAL_UART_Transmit+0x10e> } else { return HAL_BUSY; 8006b10: 2302 movs r3, #2 } } 8006b12: 4618 mov r0, r3 8006b14: 3720 adds r7, #32 8006b16: 46bd mov sp, r7 8006b18: bd80 pop {r7, pc} 08006b1a <UART_WaitOnFlagUntilTimeout>: * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8006b1a: b580 push {r7, lr} 8006b1c: b086 sub sp, #24 8006b1e: af00 add r7, sp, #0 8006b20: 60f8 str r0, [r7, #12] 8006b22: 60b9 str r1, [r7, #8] 8006b24: 603b str r3, [r7, #0] 8006b26: 4613 mov r3, r2 8006b28: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8006b2a: e03b b.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006b2c: 6a3b ldr r3, [r7, #32] 8006b2e: f1b3 3fff cmp.w r3, #4294967295 8006b32: d037 beq.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006b34: f7fc f816 bl 8002b64 <HAL_GetTick> 8006b38: 4602 mov r2, r0 8006b3a: 683b ldr r3, [r7, #0] 8006b3c: 1ad3 subs r3, r2, r3 8006b3e: 6a3a ldr r2, [r7, #32] 8006b40: 429a cmp r2, r3 8006b42: d302 bcc.n 8006b4a <UART_WaitOnFlagUntilTimeout+0x30> 8006b44: 6a3b ldr r3, [r7, #32] 8006b46: 2b00 cmp r3, #0 8006b48: d101 bne.n 8006b4e <UART_WaitOnFlagUntilTimeout+0x34> { return HAL_TIMEOUT; 8006b4a: 2303 movs r3, #3 8006b4c: e03a b.n 8006bc4 <UART_WaitOnFlagUntilTimeout+0xaa> } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8006b4e: 68fb ldr r3, [r7, #12] 8006b50: 681b ldr r3, [r3, #0] 8006b52: 68db ldr r3, [r3, #12] 8006b54: f003 0304 and.w r3, r3, #4 8006b58: 2b00 cmp r3, #0 8006b5a: d023 beq.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> 8006b5c: 68bb ldr r3, [r7, #8] 8006b5e: 2b80 cmp r3, #128 ; 0x80 8006b60: d020 beq.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> 8006b62: 68bb ldr r3, [r7, #8] 8006b64: 2b40 cmp r3, #64 ; 0x40 8006b66: d01d beq.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8006b68: 68fb ldr r3, [r7, #12] 8006b6a: 681b ldr r3, [r3, #0] 8006b6c: 681b ldr r3, [r3, #0] 8006b6e: f003 0308 and.w r3, r3, #8 8006b72: 2b08 cmp r3, #8 8006b74: d116 bne.n 8006ba4 <UART_WaitOnFlagUntilTimeout+0x8a> { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 8006b76: 2300 movs r3, #0 8006b78: 617b str r3, [r7, #20] 8006b7a: 68fb ldr r3, [r7, #12] 8006b7c: 681b ldr r3, [r3, #0] 8006b7e: 681b ldr r3, [r3, #0] 8006b80: 617b str r3, [r7, #20] 8006b82: 68fb ldr r3, [r7, #12] 8006b84: 681b ldr r3, [r3, #0] 8006b86: 685b ldr r3, [r3, #4] 8006b88: 617b str r3, [r7, #20] 8006b8a: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8006b8c: 68f8 ldr r0, [r7, #12] 8006b8e: f000 f81d bl 8006bcc <UART_EndRxTransfer> huart->ErrorCode = HAL_UART_ERROR_ORE; 8006b92: 68fb ldr r3, [r7, #12] 8006b94: 2208 movs r2, #8 8006b96: 645a str r2, [r3, #68] ; 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 8006b98: 68fb ldr r3, [r7, #12] 8006b9a: 2200 movs r2, #0 8006b9c: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8006ba0: 2301 movs r3, #1 8006ba2: e00f b.n 8006bc4 <UART_WaitOnFlagUntilTimeout+0xaa> while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8006ba4: 68fb ldr r3, [r7, #12] 8006ba6: 681b ldr r3, [r3, #0] 8006ba8: 681a ldr r2, [r3, #0] 8006baa: 68bb ldr r3, [r7, #8] 8006bac: 4013 ands r3, r2 8006bae: 68ba ldr r2, [r7, #8] 8006bb0: 429a cmp r2, r3 8006bb2: bf0c ite eq 8006bb4: 2301 moveq r3, #1 8006bb6: 2300 movne r3, #0 8006bb8: b2db uxtb r3, r3 8006bba: 461a mov r2, r3 8006bbc: 79fb ldrb r3, [r7, #7] 8006bbe: 429a cmp r2, r3 8006bc0: d0b4 beq.n 8006b2c <UART_WaitOnFlagUntilTimeout+0x12> } } } } return HAL_OK; 8006bc2: 2300 movs r3, #0 } 8006bc4: 4618 mov r0, r3 8006bc6: 3718 adds r7, #24 8006bc8: 46bd mov sp, r7 8006bca: bd80 pop {r7, pc} 08006bcc <UART_EndRxTransfer>: * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006bcc: b480 push {r7} 8006bce: b095 sub sp, #84 ; 0x54 8006bd0: af00 add r7, sp, #0 8006bd2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006bd4: 687b ldr r3, [r7, #4] 8006bd6: 681b ldr r3, [r3, #0] 8006bd8: 330c adds r3, #12 8006bda: 637b str r3, [r7, #52] ; 0x34 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006bdc: 6b7b ldr r3, [r7, #52] ; 0x34 8006bde: e853 3f00 ldrex r3, [r3] 8006be2: 633b str r3, [r7, #48] ; 0x30 return(result); 8006be4: 6b3b ldr r3, [r7, #48] ; 0x30 8006be6: f423 7390 bic.w r3, r3, #288 ; 0x120 8006bea: 64fb str r3, [r7, #76] ; 0x4c 8006bec: 687b ldr r3, [r7, #4] 8006bee: 681b ldr r3, [r3, #0] 8006bf0: 330c adds r3, #12 8006bf2: 6cfa ldr r2, [r7, #76] ; 0x4c 8006bf4: 643a str r2, [r7, #64] ; 0x40 8006bf6: 63fb str r3, [r7, #60] ; 0x3c */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006bf8: 6bf9 ldr r1, [r7, #60] ; 0x3c 8006bfa: 6c3a ldr r2, [r7, #64] ; 0x40 8006bfc: e841 2300 strex r3, r2, [r1] 8006c00: 63bb str r3, [r7, #56] ; 0x38 return(result); 8006c02: 6bbb ldr r3, [r7, #56] ; 0x38 8006c04: 2b00 cmp r3, #0 8006c06: d1e5 bne.n 8006bd4 <UART_EndRxTransfer+0x8> ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006c08: 687b ldr r3, [r7, #4] 8006c0a: 681b ldr r3, [r3, #0] 8006c0c: 3314 adds r3, #20 8006c0e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c10: 6a3b ldr r3, [r7, #32] 8006c12: e853 3f00 ldrex r3, [r3] 8006c16: 61fb str r3, [r7, #28] return(result); 8006c18: 69fb ldr r3, [r7, #28] 8006c1a: f023 0301 bic.w r3, r3, #1 8006c1e: 64bb str r3, [r7, #72] ; 0x48 8006c20: 687b ldr r3, [r7, #4] 8006c22: 681b ldr r3, [r3, #0] 8006c24: 3314 adds r3, #20 8006c26: 6cba ldr r2, [r7, #72] ; 0x48 8006c28: 62fa str r2, [r7, #44] ; 0x2c 8006c2a: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c2c: 6ab9 ldr r1, [r7, #40] ; 0x28 8006c2e: 6afa ldr r2, [r7, #44] ; 0x2c 8006c30: e841 2300 strex r3, r2, [r1] 8006c34: 627b str r3, [r7, #36] ; 0x24 return(result); 8006c36: 6a7b ldr r3, [r7, #36] ; 0x24 8006c38: 2b00 cmp r3, #0 8006c3a: d1e5 bne.n 8006c08 <UART_EndRxTransfer+0x3c> /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006c3c: 687b ldr r3, [r7, #4] 8006c3e: 6b1b ldr r3, [r3, #48] ; 0x30 8006c40: 2b01 cmp r3, #1 8006c42: d119 bne.n 8006c78 <UART_EndRxTransfer+0xac> { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006c44: 687b ldr r3, [r7, #4] 8006c46: 681b ldr r3, [r3, #0] 8006c48: 330c adds r3, #12 8006c4a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c4c: 68fb ldr r3, [r7, #12] 8006c4e: e853 3f00 ldrex r3, [r3] 8006c52: 60bb str r3, [r7, #8] return(result); 8006c54: 68bb ldr r3, [r7, #8] 8006c56: f023 0310 bic.w r3, r3, #16 8006c5a: 647b str r3, [r7, #68] ; 0x44 8006c5c: 687b ldr r3, [r7, #4] 8006c5e: 681b ldr r3, [r3, #0] 8006c60: 330c adds r3, #12 8006c62: 6c7a ldr r2, [r7, #68] ; 0x44 8006c64: 61ba str r2, [r7, #24] 8006c66: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c68: 6979 ldr r1, [r7, #20] 8006c6a: 69ba ldr r2, [r7, #24] 8006c6c: e841 2300 strex r3, r2, [r1] 8006c70: 613b str r3, [r7, #16] return(result); 8006c72: 693b ldr r3, [r7, #16] 8006c74: 2b00 cmp r3, #0 8006c76: d1e5 bne.n 8006c44 <UART_EndRxTransfer+0x78> } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006c78: 687b ldr r3, [r7, #4] 8006c7a: 2220 movs r2, #32 8006c7c: f883 2042 strb.w r2, [r3, #66] ; 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006c80: 687b ldr r3, [r7, #4] 8006c82: 2200 movs r2, #0 8006c84: 631a str r2, [r3, #48] ; 0x30 } 8006c86: bf00 nop 8006c88: 3754 adds r7, #84 ; 0x54 8006c8a: 46bd mov sp, r7 8006c8c: bc80 pop {r7} 8006c8e: 4770 bx lr 08006c90 <UART_SetConfig>: * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006c90: b580 push {r7, lr} 8006c92: b084 sub sp, #16 8006c94: af00 add r7, sp, #0 8006c96: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006c98: 687b ldr r3, [r7, #4] 8006c9a: 681b ldr r3, [r3, #0] 8006c9c: 691b ldr r3, [r3, #16] 8006c9e: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8006ca2: 687b ldr r3, [r7, #4] 8006ca4: 68da ldr r2, [r3, #12] 8006ca6: 687b ldr r3, [r7, #4] 8006ca8: 681b ldr r3, [r3, #0] 8006caa: 430a orrs r2, r1 8006cac: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8006cae: 687b ldr r3, [r7, #4] 8006cb0: 689a ldr r2, [r3, #8] 8006cb2: 687b ldr r3, [r7, #4] 8006cb4: 691b ldr r3, [r3, #16] 8006cb6: 431a orrs r2, r3 8006cb8: 687b ldr r3, [r7, #4] 8006cba: 695b ldr r3, [r3, #20] 8006cbc: 4313 orrs r3, r2 8006cbe: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8006cc0: 687b ldr r3, [r7, #4] 8006cc2: 681b ldr r3, [r3, #0] 8006cc4: 68db ldr r3, [r3, #12] 8006cc6: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8006cca: f023 030c bic.w r3, r3, #12 8006cce: 687a ldr r2, [r7, #4] 8006cd0: 6812 ldr r2, [r2, #0] 8006cd2: 68b9 ldr r1, [r7, #8] 8006cd4: 430b orrs r3, r1 8006cd6: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8006cd8: 687b ldr r3, [r7, #4] 8006cda: 681b ldr r3, [r3, #0] 8006cdc: 695b ldr r3, [r3, #20] 8006cde: f423 7140 bic.w r1, r3, #768 ; 0x300 8006ce2: 687b ldr r3, [r7, #4] 8006ce4: 699a ldr r2, [r3, #24] 8006ce6: 687b ldr r3, [r7, #4] 8006ce8: 681b ldr r3, [r3, #0] 8006cea: 430a orrs r2, r1 8006cec: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8006cee: 687b ldr r3, [r7, #4] 8006cf0: 681b ldr r3, [r3, #0] 8006cf2: 4a2c ldr r2, [pc, #176] ; (8006da4 <UART_SetConfig+0x114>) 8006cf4: 4293 cmp r3, r2 8006cf6: d103 bne.n 8006d00 <UART_SetConfig+0x70> { pclk = HAL_RCC_GetPCLK2Freq(); 8006cf8: f7fd fc8a bl 8004610 <HAL_RCC_GetPCLK2Freq> 8006cfc: 60f8 str r0, [r7, #12] 8006cfe: e002 b.n 8006d06 <UART_SetConfig+0x76> } else { pclk = HAL_RCC_GetPCLK1Freq(); 8006d00: f7fd fc72 bl 80045e8 <HAL_RCC_GetPCLK1Freq> 8006d04: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006d06: 68fa ldr r2, [r7, #12] 8006d08: 4613 mov r3, r2 8006d0a: 009b lsls r3, r3, #2 8006d0c: 4413 add r3, r2 8006d0e: 009a lsls r2, r3, #2 8006d10: 441a add r2, r3 8006d12: 687b ldr r3, [r7, #4] 8006d14: 685b ldr r3, [r3, #4] 8006d16: 009b lsls r3, r3, #2 8006d18: fbb2 f3f3 udiv r3, r2, r3 8006d1c: 4a22 ldr r2, [pc, #136] ; (8006da8 <UART_SetConfig+0x118>) 8006d1e: fba2 2303 umull r2, r3, r2, r3 8006d22: 095b lsrs r3, r3, #5 8006d24: 0119 lsls r1, r3, #4 8006d26: 68fa ldr r2, [r7, #12] 8006d28: 4613 mov r3, r2 8006d2a: 009b lsls r3, r3, #2 8006d2c: 4413 add r3, r2 8006d2e: 009a lsls r2, r3, #2 8006d30: 441a add r2, r3 8006d32: 687b ldr r3, [r7, #4] 8006d34: 685b ldr r3, [r3, #4] 8006d36: 009b lsls r3, r3, #2 8006d38: fbb2 f2f3 udiv r2, r2, r3 8006d3c: 4b1a ldr r3, [pc, #104] ; (8006da8 <UART_SetConfig+0x118>) 8006d3e: fba3 0302 umull r0, r3, r3, r2 8006d42: 095b lsrs r3, r3, #5 8006d44: 2064 movs r0, #100 ; 0x64 8006d46: fb00 f303 mul.w r3, r0, r3 8006d4a: 1ad3 subs r3, r2, r3 8006d4c: 011b lsls r3, r3, #4 8006d4e: 3332 adds r3, #50 ; 0x32 8006d50: 4a15 ldr r2, [pc, #84] ; (8006da8 <UART_SetConfig+0x118>) 8006d52: fba2 2303 umull r2, r3, r2, r3 8006d56: 095b lsrs r3, r3, #5 8006d58: f003 03f0 and.w r3, r3, #240 ; 0xf0 8006d5c: 4419 add r1, r3 8006d5e: 68fa ldr r2, [r7, #12] 8006d60: 4613 mov r3, r2 8006d62: 009b lsls r3, r3, #2 8006d64: 4413 add r3, r2 8006d66: 009a lsls r2, r3, #2 8006d68: 441a add r2, r3 8006d6a: 687b ldr r3, [r7, #4] 8006d6c: 685b ldr r3, [r3, #4] 8006d6e: 009b lsls r3, r3, #2 8006d70: fbb2 f2f3 udiv r2, r2, r3 8006d74: 4b0c ldr r3, [pc, #48] ; (8006da8 <UART_SetConfig+0x118>) 8006d76: fba3 0302 umull r0, r3, r3, r2 8006d7a: 095b lsrs r3, r3, #5 8006d7c: 2064 movs r0, #100 ; 0x64 8006d7e: fb00 f303 mul.w r3, r0, r3 8006d82: 1ad3 subs r3, r2, r3 8006d84: 011b lsls r3, r3, #4 8006d86: 3332 adds r3, #50 ; 0x32 8006d88: 4a07 ldr r2, [pc, #28] ; (8006da8 <UART_SetConfig+0x118>) 8006d8a: fba2 2303 umull r2, r3, r2, r3 8006d8e: 095b lsrs r3, r3, #5 8006d90: f003 020f and.w r2, r3, #15 8006d94: 687b ldr r3, [r7, #4] 8006d96: 681b ldr r3, [r3, #0] 8006d98: 440a add r2, r1 8006d9a: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8006d9c: bf00 nop 8006d9e: 3710 adds r7, #16 8006da0: 46bd mov sp, r7 8006da2: bd80 pop {r7, pc} 8006da4: 40013800 .word 0x40013800 8006da8: 51eb851f .word 0x51eb851f 08006dac <HAL_GPIO_EXTI_Callback>: void switchBuffer(bool spi_state); void initResponseBuffer(); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8006dac: b580 push {r7, lr} 8006dae: b082 sub sp, #8 8006db0: af00 add r7, sp, #0 8006db2: 4603 mov r3, r0 8006db4: 80fb strh r3, [r7, #6] // Мастер опустил CS if (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == GPIO_PIN_RESET) { 8006db6: f44f 5180 mov.w r1, #4096 ; 0x1000 8006dba: 4815 ldr r0, [pc, #84] ; (8006e10 <HAL_GPIO_EXTI_Callback+0x64>) 8006dbc: f7fc ffe8 bl 8003d90 <HAL_GPIO_ReadPin> 8006dc0: 4603 mov r3, r0 8006dc2: 2b00 cmp r3, #0 8006dc4: d11f bne.n 8006e06 <HAL_GPIO_EXTI_Callback+0x5a> // проверка на наличие готового ответа для отправки if(response_ready && spi_state == SPI_MODE_TX) { // если ответ готов и датчик в режиме передатчика 8006dc6: 4b13 ldr r3, [pc, #76] ; (8006e14 <HAL_GPIO_EXTI_Callback+0x68>) 8006dc8: 781b ldrb r3, [r3, #0] 8006dca: 2b00 cmp r3, #0 8006dcc: d00b beq.n 8006de6 <HAL_GPIO_EXTI_Callback+0x3a> 8006dce: 4b12 ldr r3, [pc, #72] ; (8006e18 <HAL_GPIO_EXTI_Callback+0x6c>) 8006dd0: 781b ldrb r3, [r3, #0] 8006dd2: 2b00 cmp r3, #0 8006dd4: d007 beq.n 8006de6 <HAL_GPIO_EXTI_Callback+0x3a> spi_tx_ptr = new_response_frame; // использовать для передачи сформированный ответ 8006dd6: 4b11 ldr r3, [pc, #68] ; (8006e1c <HAL_GPIO_EXTI_Callback+0x70>) 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 4a11 ldr r2, [pc, #68] ; (8006e20 <HAL_GPIO_EXTI_Callback+0x74>) 8006ddc: 6013 str r3, [r2, #0] response_ready = false; 8006dde: 4b0d ldr r3, [pc, #52] ; (8006e14 <HAL_GPIO_EXTI_Callback+0x68>) 8006de0: 2200 movs r2, #0 8006de2: 701a strb r2, [r3, #0] 8006de4: e006 b.n 8006df4 <HAL_GPIO_EXTI_Callback+0x48> } else if (spi_state == SPI_MODE_TX){ // ответ не готов и датчик в режиме передатчика 8006de6: 4b0c ldr r3, [pc, #48] ; (8006e18 <HAL_GPIO_EXTI_Callback+0x6c>) 8006de8: 781b ldrb r3, [r3, #0] 8006dea: 2b00 cmp r3, #0 8006dec: d002 beq.n 8006df4 <HAL_GPIO_EXTI_Callback+0x48> spi_tx_ptr = wait_response_frame; // использовать для передачи кадр с состоянием STATE_WAIT 8006dee: 4b0c ldr r3, [pc, #48] ; (8006e20 <HAL_GPIO_EXTI_Callback+0x74>) 8006df0: 4a0c ldr r2, [pc, #48] ; (8006e24 <HAL_GPIO_EXTI_Callback+0x78>) 8006df2: 601a str r2, [r3, #0] } // Запускаем прием/передачу HAL_SPI_TransmitReceive_IT(&hspi2, spi_tx_ptr, spi_rx_ptr, FRAME_LEN); 8006df4: 4b0a ldr r3, [pc, #40] ; (8006e20 <HAL_GPIO_EXTI_Callback+0x74>) 8006df6: 6819 ldr r1, [r3, #0] 8006df8: 4b0b ldr r3, [pc, #44] ; (8006e28 <HAL_GPIO_EXTI_Callback+0x7c>) 8006dfa: 681a ldr r2, [r3, #0] 8006dfc: f44f 7384 mov.w r3, #264 ; 0x108 8006e00: 480a ldr r0, [pc, #40] ; (8006e2c <HAL_GPIO_EXTI_Callback+0x80>) 8006e02: f7fe fa2d bl 8005260 <HAL_SPI_TransmitReceive_IT> } } 8006e06: bf00 nop 8006e08: 3708 adds r7, #8 8006e0a: 46bd mov sp, r7 8006e0c: bd80 pop {r7, pc} 8006e0e: bf00 nop 8006e10: 40010c00 .word 0x40010c00 8006e14: 2000079d .word 0x2000079d 8006e18: 2000079e .word 0x2000079e 8006e1c: 20000bc8 .word 0x20000bc8 8006e20: 20000bc0 .word 0x20000bc0 8006e24: 20000bcc .word 0x20000bcc 8006e28: 20000bc4 .word 0x20000bc4 8006e2c: 200004c4 .word 0x200004c4 08006e30 <fillBuffer>: void fillBuffer(uint8_t* buf, uint8_t fill_symbol) { 8006e30: b480 push {r7} 8006e32: b085 sub sp, #20 8006e34: af00 add r7, sp, #0 8006e36: 6078 str r0, [r7, #4] 8006e38: 460b mov r3, r1 8006e3a: 70fb strb r3, [r7, #3] for(int i = 0; i < FRAME_LEN; i++) { 8006e3c: 2300 movs r3, #0 8006e3e: 60fb str r3, [r7, #12] 8006e40: e007 b.n 8006e52 <fillBuffer+0x22> buf[i] = fill_symbol; 8006e42: 68fb ldr r3, [r7, #12] 8006e44: 687a ldr r2, [r7, #4] 8006e46: 4413 add r3, r2 8006e48: 78fa ldrb r2, [r7, #3] 8006e4a: 701a strb r2, [r3, #0] for(int i = 0; i < FRAME_LEN; i++) { 8006e4c: 68fb ldr r3, [r7, #12] 8006e4e: 3301 adds r3, #1 8006e50: 60fb str r3, [r7, #12] 8006e52: 68fb ldr r3, [r7, #12] 8006e54: f5b3 7f84 cmp.w r3, #264 ; 0x108 8006e58: dbf3 blt.n 8006e42 <fillBuffer+0x12> } } 8006e5a: bf00 nop 8006e5c: bf00 nop 8006e5e: 3714 adds r7, #20 8006e60: 46bd mov sp, r7 8006e62: bc80 pop {r7} 8006e64: 4770 bx lr ... 08006e68 <initSPIConnection>: void initSPIConnection() { 8006e68: b580 push {r7, lr} 8006e6a: af00 add r7, sp, #0 spi_state = SPI_MODE_RX; 8006e6c: 4b07 ldr r3, [pc, #28] ; (8006e8c <initSPIConnection+0x24>) 8006e6e: 2200 movs r2, #0 8006e70: 701a strb r2, [r3, #0] switchBuffer(spi_state); 8006e72: 4b06 ldr r3, [pc, #24] ; (8006e8c <initSPIConnection+0x24>) 8006e74: 781b ldrb r3, [r3, #0] 8006e76: 4618 mov r0, r3 8006e78: f000 f844 bl 8006f04 <switchBuffer> fillBuffer(dummy_frame, 0xAA); 8006e7c: 21aa movs r1, #170 ; 0xaa 8006e7e: 4804 ldr r0, [pc, #16] ; (8006e90 <initSPIConnection+0x28>) 8006e80: f7ff ffd6 bl 8006e30 <fillBuffer> initResponseBuffer(); 8006e84: f000 f806 bl 8006e94 <initResponseBuffer> }; 8006e88: bf00 nop 8006e8a: bd80 pop {r7, pc} 8006e8c: 2000079e .word 0x2000079e 8006e90: 200009b0 .word 0x200009b0 08006e94 <initResponseBuffer>: void resetSPIConnection() { initSPIConnection(); response_ready = 0; } void initResponseBuffer() { 8006e94: b580 push {r7, lr} 8006e96: b082 sub sp, #8 8006e98: af00 add r7, sp, #0 wait_response_frame[0] = 0xFA; 8006e9a: 4b19 ldr r3, [pc, #100] ; (8006f00 <initResponseBuffer+0x6c>) 8006e9c: 22fa movs r2, #250 ; 0xfa 8006e9e: 701a strb r2, [r3, #0] wait_response_frame[1] = 0xAF; 8006ea0: 4b17 ldr r3, [pc, #92] ; (8006f00 <initResponseBuffer+0x6c>) 8006ea2: 22af movs r2, #175 ; 0xaf 8006ea4: 705a strb r2, [r3, #1] wait_response_frame[2] = STATE_WAIT; 8006ea6: 4b16 ldr r3, [pc, #88] ; (8006f00 <initResponseBuffer+0x6c>) 8006ea8: 2203 movs r2, #3 8006eaa: 709a strb r2, [r3, #2] wait_response_frame[258] = 0xFF; 8006eac: 4b14 ldr r3, [pc, #80] ; (8006f00 <initResponseBuffer+0x6c>) 8006eae: 22ff movs r2, #255 ; 0xff 8006eb0: f883 2102 strb.w r2, [r3, #258] ; 0x102 wait_response_frame[259] = 0x0D; 8006eb4: 4b12 ldr r3, [pc, #72] ; (8006f00 <initResponseBuffer+0x6c>) 8006eb6: 220d movs r2, #13 8006eb8: f883 2103 strb.w r2, [r3, #259] ; 0x103 // TODO: добавить расчет CRC uint32_t crc = calculateCRC32(wait_response_frame, FRAME_LEN-4); 8006ebc: f44f 7182 mov.w r1, #260 ; 0x104 8006ec0: 480f ldr r0, [pc, #60] ; (8006f00 <initResponseBuffer+0x6c>) 8006ec2: f000 fc21 bl 8007708 <calculateCRC32> 8006ec6: 6078 str r0, [r7, #4] wait_response_frame[260] = (crc >> 24) & 0xFF; 8006ec8: 687b ldr r3, [r7, #4] 8006eca: 0e1b lsrs r3, r3, #24 8006ecc: b2da uxtb r2, r3 8006ece: 4b0c ldr r3, [pc, #48] ; (8006f00 <initResponseBuffer+0x6c>) 8006ed0: f883 2104 strb.w r2, [r3, #260] ; 0x104 wait_response_frame[261] = (crc >> 16) & 0xFF; 8006ed4: 687b ldr r3, [r7, #4] 8006ed6: 0c1b lsrs r3, r3, #16 8006ed8: b2da uxtb r2, r3 8006eda: 4b09 ldr r3, [pc, #36] ; (8006f00 <initResponseBuffer+0x6c>) 8006edc: f883 2105 strb.w r2, [r3, #261] ; 0x105 wait_response_frame[262] = (crc >> 8) & 0xFF; 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: 0a1b lsrs r3, r3, #8 8006ee4: b2da uxtb r2, r3 8006ee6: 4b06 ldr r3, [pc, #24] ; (8006f00 <initResponseBuffer+0x6c>) 8006ee8: f883 2106 strb.w r2, [r3, #262] ; 0x106 wait_response_frame[263] = crc & 0xFF; 8006eec: 687b ldr r3, [r7, #4] 8006eee: b2da uxtb r2, r3 8006ef0: 4b03 ldr r3, [pc, #12] ; (8006f00 <initResponseBuffer+0x6c>) 8006ef2: f883 2107 strb.w r2, [r3, #263] ; 0x107 }; 8006ef6: bf00 nop 8006ef8: 3708 adds r7, #8 8006efa: 46bd mov sp, r7 8006efc: bd80 pop {r7, pc} 8006efe: bf00 nop 8006f00: 20000bcc .word 0x20000bcc 08006f04 <switchBuffer>: void switchBuffer(bool spi_state) { 8006f04: b480 push {r7} 8006f06: b083 sub sp, #12 8006f08: af00 add r7, sp, #0 8006f0a: 4603 mov r3, r0 8006f0c: 71fb strb r3, [r7, #7] if(spi_state == SPI_MODE_TX) { 8006f0e: 79fb ldrb r3, [r7, #7] 8006f10: 2b00 cmp r3, #0 8006f12: d003 beq.n 8006f1c <switchBuffer+0x18> //spi_tx_ptr = &response_frame[0]; spi_rx_ptr = &trash_frame[0]; 8006f14: 4b07 ldr r3, [pc, #28] ; (8006f34 <switchBuffer+0x30>) 8006f16: 4a08 ldr r2, [pc, #32] ; (8006f38 <switchBuffer+0x34>) 8006f18: 601a str r2, [r3, #0] } else { spi_tx_ptr = &dummy_frame[0]; spi_rx_ptr = &response_frame[0]; } }; 8006f1a: e005 b.n 8006f28 <switchBuffer+0x24> spi_tx_ptr = &dummy_frame[0]; 8006f1c: 4b07 ldr r3, [pc, #28] ; (8006f3c <switchBuffer+0x38>) 8006f1e: 4a08 ldr r2, [pc, #32] ; (8006f40 <switchBuffer+0x3c>) 8006f20: 601a str r2, [r3, #0] spi_rx_ptr = &response_frame[0]; 8006f22: 4b04 ldr r3, [pc, #16] ; (8006f34 <switchBuffer+0x30>) 8006f24: 4a07 ldr r2, [pc, #28] ; (8006f44 <switchBuffer+0x40>) 8006f26: 601a str r2, [r3, #0] }; 8006f28: bf00 nop 8006f2a: 370c adds r7, #12 8006f2c: 46bd mov sp, r7 8006f2e: bc80 pop {r7} 8006f30: 4770 bx lr 8006f32: bf00 nop 8006f34: 20000bc4 .word 0x20000bc4 8006f38: 20000ab8 .word 0x20000ab8 8006f3c: 20000bc0 .word 0x20000bc0 8006f40: 200009b0 .word 0x200009b0 8006f44: 200007a0 .word 0x200007a0 08006f48 <HAL_SPI_TxRxCpltCallback>: /* Обработчик прерывания по окончанию передачи/приема всего кадра */ void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { 8006f48: b580 push {r7, lr} 8006f4a: b082 sub sp, #8 8006f4c: af00 add r7, sp, #0 8006f4e: 6078 str r0, [r7, #4] if (hspi->Instance == SPI2) 8006f50: 687b ldr r3, [r7, #4] 8006f52: 681b ldr r3, [r3, #0] 8006f54: 4a11 ldr r2, [pc, #68] ; (8006f9c <HAL_SPI_TxRxCpltCallback+0x54>) 8006f56: 4293 cmp r3, r2 8006f58: d11b bne.n 8006f92 <HAL_SPI_TxRxCpltCallback+0x4a> { if (spi_state == SPI_MODE_TX) { 8006f5a: 4b11 ldr r3, [pc, #68] ; (8006fa0 <HAL_SPI_TxRxCpltCallback+0x58>) 8006f5c: 781b ldrb r3, [r3, #0] 8006f5e: 2b00 cmp r3, #0 8006f60: d003 beq.n 8006f6a <HAL_SPI_TxRxCpltCallback+0x22> // сделать датчик приемником в следующем сеансе spi_state = SPI_MODE_RX; 8006f62: 4b0f ldr r3, [pc, #60] ; (8006fa0 <HAL_SPI_TxRxCpltCallback+0x58>) 8006f64: 2200 movs r2, #0 8006f66: 701a strb r2, [r3, #0] 8006f68: e00e b.n 8006f88 <HAL_SPI_TxRxCpltCallback+0x40> } else { // сделать датчик передатчиком в следующем сеансе spi_state = SPI_MODE_TX; 8006f6a: 4b0d ldr r3, [pc, #52] ; (8006fa0 <HAL_SPI_TxRxCpltCallback+0x58>) 8006f6c: 2201 movs r2, #1 8006f6e: 701a strb r2, [r3, #0] // сохранить полученную команду от мастера в безопасный буфер memcpy(safe_command_frame,response_frame,FRAME_LEN); 8006f70: 4a0c ldr r2, [pc, #48] ; (8006fa4 <HAL_SPI_TxRxCpltCallback+0x5c>) 8006f72: 4b0d ldr r3, [pc, #52] ; (8006fa8 <HAL_SPI_TxRxCpltCallback+0x60>) 8006f74: 4610 mov r0, r2 8006f76: 4619 mov r1, r3 8006f78: f44f 7384 mov.w r3, #264 ; 0x108 8006f7c: 461a mov r2, r3 8006f7e: f000 fd1f bl 80079c0 <memcpy> spi_rx_complete = true; 8006f82: 4b0a ldr r3, [pc, #40] ; (8006fac <HAL_SPI_TxRxCpltCallback+0x64>) 8006f84: 2201 movs r2, #1 8006f86: 701a strb r2, [r3, #0] } switchBuffer(spi_state); 8006f88: 4b05 ldr r3, [pc, #20] ; (8006fa0 <HAL_SPI_TxRxCpltCallback+0x58>) 8006f8a: 781b ldrb r3, [r3, #0] 8006f8c: 4618 mov r0, r3 8006f8e: f7ff ffb9 bl 8006f04 <switchBuffer> } } 8006f92: bf00 nop 8006f94: 3708 adds r7, #8 8006f96: 46bd mov sp, r7 8006f98: bd80 pop {r7, pc} 8006f9a: bf00 nop 8006f9c: 40003800 .word 0x40003800 8006fa0: 2000079e .word 0x2000079e 8006fa4: 200008a8 .word 0x200008a8 8006fa8: 200007a0 .word 0x200007a0 8006fac: 2000079c .word 0x2000079c 08006fb0 <HAL_SPI_ErrorCallback>: void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { 8006fb0: b480 push {r7} 8006fb2: b083 sub sp, #12 8006fb4: af00 add r7, sp, #0 8006fb6: 6078 str r0, [r7, #4] HAL_Delay(1); HAL_SPI_Init(&hspi2); resetSPIConnection(); } */ } 8006fb8: bf00 nop 8006fba: 370c adds r7, #12 8006fbc: 46bd mov sp, r7 8006fbe: bc80 pop {r7} 8006fc0: 4770 bx lr ... 08006fc4 <updateNumAvailableMeasData>: void sendRxCompleteCTRL(); /* реализация функций */ /* Вычисляет количество готовых байт данных измерения в пределах одной страницы флеш-памяти * и обновляет соответствующее поле структуры */ void updateNumAvailableMeasData() { 8006fc4: b480 push {r7} 8006fc6: b083 sub sp, #12 8006fc8: af00 add r7, sp, #0 uint8_t first_elem, curr_page_pos_ptr, curr_page_ptr; // сохранение последнего значения смещения записанных байт в странице curr_page_pos_ptr = page_pos_ptr; 8006fca: 4b23 ldr r3, [pc, #140] ; (8007058 <updateNumAvailableMeasData+0x94>) 8006fcc: 781b ldrb r3, [r3, #0] 8006fce: 71bb strb r3, [r7, #6] // сохранение последнего номера страницы, используемого для записи curr_page_ptr = page_ptr; 8006fd0: 4b22 ldr r3, [pc, #136] ; (800705c <updateNumAvailableMeasData+0x98>) 8006fd2: 881b ldrh r3, [r3, #0] 8006fd4: b29b uxth r3, r3 8006fd6: 717b strb r3, [r7, #5] if (read.cur_page_num == curr_page_ptr && // если указатели записи и чтения на одной странице и совпадают 8006fd8: 4b21 ldr r3, [pc, #132] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8006fda: 681a ldr r2, [r3, #0] 8006fdc: 797b ldrb r3, [r7, #5] 8006fde: 429a cmp r2, r3 8006fe0: d10a bne.n 8006ff8 <updateNumAvailableMeasData+0x34> read.page_offset_read == curr_page_pos_ptr) { 8006fe2: 4b1f ldr r3, [pc, #124] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8006fe4: f993 3004 ldrsb.w r3, [r3, #4] 8006fe8: 461a mov r2, r3 8006fea: 79bb ldrb r3, [r7, #6] if (read.cur_page_num == curr_page_ptr && // если указатели записи и чтения на одной странице и совпадают 8006fec: 429a cmp r2, r3 8006fee: d103 bne.n 8006ff8 <updateNumAvailableMeasData+0x34> read.num_ready_bytes = 0; 8006ff0: 4b1b ldr r3, [pc, #108] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8006ff2: 2200 movs r2, #0 8006ff4: 715a strb r2, [r3, #5] return; 8006ff6: e02b b.n 8007050 <updateNumAvailableMeasData+0x8c> } else if (read.cur_page_num == curr_page_ptr && curr_page_pos_ptr == 0) { 8006ff8: 4b19 ldr r3, [pc, #100] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8006ffa: 681a ldr r2, [r3, #0] 8006ffc: 797b ldrb r3, [r7, #5] 8006ffe: 429a cmp r2, r3 8007000: d106 bne.n 8007010 <updateNumAvailableMeasData+0x4c> 8007002: 79bb ldrb r3, [r7, #6] 8007004: 2b00 cmp r3, #0 8007006: d103 bne.n 8007010 <updateNumAvailableMeasData+0x4c> read.num_ready_bytes = 0; 8007008: 4b15 ldr r3, [pc, #84] ; (8007060 <updateNumAvailableMeasData+0x9c>) 800700a: 2200 movs r2, #0 800700c: 715a strb r2, [r3, #5] return; 800700e: e01f b.n 8007050 <updateNumAvailableMeasData+0x8c> } else if (read.cur_page_num != curr_page_ptr) { // если указатель записи на другой странице 8007010: 4b13 ldr r3, [pc, #76] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8007012: 681a ldr r2, [r3, #0] 8007014: 797b ldrb r3, [r7, #5] 8007016: 429a cmp r2, r3 8007018: d001 beq.n 800701e <updateNumAvailableMeasData+0x5a> // будет выполняться чтение до конца текущей страницы curr_page_pos_ptr = 127; 800701a: 237f movs r3, #127 ; 0x7f 800701c: 71bb strb r3, [r7, #6] } // общий случай: если номер последней считанной страницы совпадает с номером страницы, куда выполнялась запись // определение первого элемента страницы, начиная с которого в странице находятся готовые данные if (read.page_offset_read == -1) { 800701e: 4b10 ldr r3, [pc, #64] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8007020: f993 3004 ldrsb.w r3, [r3, #4] 8007024: f1b3 3fff cmp.w r3, #4294967295 8007028: d102 bne.n 8007030 <updateNumAvailableMeasData+0x6c> first_elem = 0; 800702a: 2300 movs r3, #0 800702c: 71fb strb r3, [r7, #7] 800702e: e006 b.n 800703e <updateNumAvailableMeasData+0x7a> } else { first_elem = (read.page_offset_read + 1) * 2; 8007030: 4b0b ldr r3, [pc, #44] ; (8007060 <updateNumAvailableMeasData+0x9c>) 8007032: f993 3004 ldrsb.w r3, [r3, #4] 8007036: 3301 adds r3, #1 8007038: b2db uxtb r3, r3 800703a: 005b lsls r3, r3, #1 800703c: 71fb strb r3, [r7, #7] } read.num_ready_bytes = (curr_page_pos_ptr * 2) - first_elem; 800703e: 79bb ldrb r3, [r7, #6] 8007040: 005b lsls r3, r3, #1 8007042: b2da uxtb r2, r3 8007044: 79fb ldrb r3, [r7, #7] 8007046: 1ad3 subs r3, r2, r3 8007048: b2da uxtb r2, r3 800704a: 4b05 ldr r3, [pc, #20] ; (8007060 <updateNumAvailableMeasData+0x9c>) 800704c: 715a strb r2, [r3, #5] return; 800704e: bf00 nop } 8007050: 370c adds r7, #12 8007052: 46bd mov sp, r7 8007054: bc80 pop {r7} 8007056: 4770 bx lr 8007058: 2000073e .word 0x2000073e 800705c: 2000073c .word 0x2000073c 8007060: 20000014 .word 0x20000014 08007064 <setFSMProtocolState>: void setFSMProtocolState(uint8_t state) { 8007064: b480 push {r7} 8007066: b083 sub sp, #12 8007068: af00 add r7, sp, #0 800706a: 4603 mov r3, r0 800706c: 71fb strb r3, [r7, #7] FSM_state = state; 800706e: 4a04 ldr r2, [pc, #16] ; (8007080 <setFSMProtocolState+0x1c>) 8007070: 79fb ldrb r3, [r7, #7] 8007072: 7013 strb r3, [r2, #0] } 8007074: bf00 nop 8007076: 370c adds r7, #12 8007078: 46bd mov sp, r7 800707a: bc80 pop {r7} 800707c: 4770 bx lr 800707e: bf00 nop 8007080: 20000ddc .word 0x20000ddc 08007084 <fillDataFrame>: /* Заполняет кадр ответа с данными измерения и уведомляет модуль SPI_connection * о готовности ответа к отправке */ void fillDataFrame() { 8007084: b580 push {r7, lr} 8007086: b082 sub sp, #8 8007088: af00 add r7, sp, #0 // формирование кадра ответа с данными memset(response,0,FRAME_LEN); 800708a: f44f 7284 mov.w r2, #264 ; 0x108 800708e: 2100 movs r1, #0 8007090: 481f ldr r0, [pc, #124] ; (8007110 <fillDataFrame+0x8c>) 8007092: f000 fca3 bl 80079dc <memset> response[0] = 0xFA; 8007096: 4b1e ldr r3, [pc, #120] ; (8007110 <fillDataFrame+0x8c>) 8007098: 22fa movs r2, #250 ; 0xfa 800709a: 701a strb r2, [r3, #0] response[1] = 0xAA; 800709c: 4b1c ldr r3, [pc, #112] ; (8007110 <fillDataFrame+0x8c>) 800709e: 22aa movs r2, #170 ; 0xaa 80070a0: 705a strb r2, [r3, #1] // заполнение поля данных fillDataField(); 80070a2: f000 f83d bl 8007120 <fillDataField> // определение наличия следующих байт данных, для следующего запроса на получение данных updateNumAvailableMeasData(); 80070a6: f7ff ff8d bl 8006fc4 <updateNumAvailableMeasData> response[2] = read.num_ready_bytes; 80070aa: 4b1a ldr r3, [pc, #104] ; (8007114 <fillDataFrame+0x90>) 80070ac: 795a ldrb r2, [r3, #5] 80070ae: 4b18 ldr r3, [pc, #96] ; (8007110 <fillDataFrame+0x8c>) 80070b0: 709a strb r2, [r3, #2] response[258] = 0xFF; 80070b2: 4b17 ldr r3, [pc, #92] ; (8007110 <fillDataFrame+0x8c>) 80070b4: 22ff movs r2, #255 ; 0xff 80070b6: f883 2102 strb.w r2, [r3, #258] ; 0x102 response[259] = 0x0B; 80070ba: 4b15 ldr r3, [pc, #84] ; (8007110 <fillDataFrame+0x8c>) 80070bc: 220b movs r2, #11 80070be: f883 2103 strb.w r2, [r3, #259] ; 0x103 //response[257] = FSM_state; // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 80070c2: f44f 7182 mov.w r1, #260 ; 0x104 80070c6: 4812 ldr r0, [pc, #72] ; (8007110 <fillDataFrame+0x8c>) 80070c8: f000 fb1e bl 8007708 <calculateCRC32> 80070cc: 6078 str r0, [r7, #4] response[260] = (crc >> 24) & 0xFF; 80070ce: 687b ldr r3, [r7, #4] 80070d0: 0e1b lsrs r3, r3, #24 80070d2: b2da uxtb r2, r3 80070d4: 4b0e ldr r3, [pc, #56] ; (8007110 <fillDataFrame+0x8c>) 80070d6: f883 2104 strb.w r2, [r3, #260] ; 0x104 response[261] = (crc >> 16) & 0xFF; 80070da: 687b ldr r3, [r7, #4] 80070dc: 0c1b lsrs r3, r3, #16 80070de: b2da uxtb r2, r3 80070e0: 4b0b ldr r3, [pc, #44] ; (8007110 <fillDataFrame+0x8c>) 80070e2: f883 2105 strb.w r2, [r3, #261] ; 0x105 response[262] = (crc >> 8) & 0xFF; 80070e6: 687b ldr r3, [r7, #4] 80070e8: 0a1b lsrs r3, r3, #8 80070ea: b2da uxtb r2, r3 80070ec: 4b08 ldr r3, [pc, #32] ; (8007110 <fillDataFrame+0x8c>) 80070ee: f883 2106 strb.w r2, [r3, #262] ; 0x106 response[263] = crc & 0xFF; 80070f2: 687b ldr r3, [r7, #4] 80070f4: b2da uxtb r2, r3 80070f6: 4b06 ldr r3, [pc, #24] ; (8007110 <fillDataFrame+0x8c>) 80070f8: f883 2107 strb.w r2, [r3, #263] ; 0x107 // устанавливаем указатель модуля приема/передачи на буфер с подготовленным ответом new_response_frame = response; 80070fc: 4b06 ldr r3, [pc, #24] ; (8007118 <fillDataFrame+0x94>) 80070fe: 4a04 ldr r2, [pc, #16] ; (8007110 <fillDataFrame+0x8c>) 8007100: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 8007102: 4b06 ldr r3, [pc, #24] ; (800711c <fillDataFrame+0x98>) 8007104: 2201 movs r2, #1 8007106: 701a strb r2, [r3, #0] }; 8007108: bf00 nop 800710a: 3708 adds r7, #8 800710c: 46bd mov sp, r7 800710e: bd80 pop {r7, pc} 8007110: 20000cd4 .word 0x20000cd4 8007114: 20000014 .word 0x20000014 8007118: 20000bc8 .word 0x20000bc8 800711c: 2000079d .word 0x2000079d 08007120 <fillDataField>: void fillDataField() { 8007120: b580 push {r7, lr} 8007122: b082 sub sp, #8 8007124: af00 add r7, sp, #0 uint8_t first_elem, last_elem; if (read.num_ready_bytes == 0) { 8007126: 4b3b ldr r3, [pc, #236] ; (8007214 <fillDataField+0xf4>) 8007128: 795b ldrb r3, [r3, #5] 800712a: 2b00 cmp r3, #0 800712c: d06e beq.n 800720c <fillDataField+0xec> return; } // чтение страницы флеш-памяти в буфер с данными HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 800712e: 2201 movs r2, #1 8007130: 2104 movs r1, #4 8007132: 4839 ldr r0, [pc, #228] ; (8007218 <fillDataField+0xf8>) 8007134: f7fc fe43 bl 8003dbe <HAL_GPIO_WritePin> W25_Read_Page(data_buf, read.cur_page_num, 0, w25_info.PageSize); 8007138: 4b36 ldr r3, [pc, #216] ; (8007214 <fillDataField+0xf4>) 800713a: 6819 ldr r1, [r3, #0] 800713c: 4b37 ldr r3, [pc, #220] ; (800721c <fillDataField+0xfc>) 800713e: 881b ldrh r3, [r3, #0] 8007140: 2200 movs r2, #0 8007142: 4837 ldr r0, [pc, #220] ; (8007220 <fillDataField+0x100>) 8007144: f7fb fc3a bl 80029bc <W25_Read_Page> // определение смещения, с которого необходимо добавлять байты в поле данных считанной страницы if (read.page_offset_read == -1) { 8007148: 4b32 ldr r3, [pc, #200] ; (8007214 <fillDataField+0xf4>) 800714a: f993 3004 ldrsb.w r3, [r3, #4] 800714e: f1b3 3fff cmp.w r3, #4294967295 8007152: d102 bne.n 800715a <fillDataField+0x3a> first_elem = 0; 8007154: 2300 movs r3, #0 8007156: 71fb strb r3, [r7, #7] 8007158: e006 b.n 8007168 <fillDataField+0x48> } else { first_elem = (read.page_offset_read + 1) * 2; 800715a: 4b2e ldr r3, [pc, #184] ; (8007214 <fillDataField+0xf4>) 800715c: f993 3004 ldrsb.w r3, [r3, #4] 8007160: 3301 adds r3, #1 8007162: b2db uxtb r3, r3 8007164: 005b lsls r3, r3, #1 8007166: 71fb strb r3, [r7, #7] } // определение последнего номера элемента страницы, до которого необходимо выполнять считывание страницы last_elem = first_elem + read.num_ready_bytes - 1; 8007168: 4b2a ldr r3, [pc, #168] ; (8007214 <fillDataField+0xf4>) 800716a: 795a ldrb r2, [r3, #5] 800716c: 79fb ldrb r3, [r7, #7] 800716e: 4413 add r3, r2 8007170: b2db uxtb r3, r3 8007172: 3b01 subs r3, #1 8007174: 707b strb r3, [r7, #1] for (uint16_t k = 3, i = first_elem; i <= last_elem; i++, k++) { 8007176: 2303 movs r3, #3 8007178: 80bb strh r3, [r7, #4] 800717a: 79fb ldrb r3, [r7, #7] 800717c: 807b strh r3, [r7, #2] 800717e: e00b b.n 8007198 <fillDataField+0x78> response[k] = data_buf[i]; 8007180: 887a ldrh r2, [r7, #2] 8007182: 88bb ldrh r3, [r7, #4] 8007184: 4926 ldr r1, [pc, #152] ; (8007220 <fillDataField+0x100>) 8007186: 5c89 ldrb r1, [r1, r2] 8007188: 4a26 ldr r2, [pc, #152] ; (8007224 <fillDataField+0x104>) 800718a: 54d1 strb r1, [r2, r3] for (uint16_t k = 3, i = first_elem; i <= last_elem; i++, k++) { 800718c: 887b ldrh r3, [r7, #2] 800718e: 3301 adds r3, #1 8007190: 807b strh r3, [r7, #2] 8007192: 88bb ldrh r3, [r7, #4] 8007194: 3301 adds r3, #1 8007196: 80bb strh r3, [r7, #4] 8007198: 787b ldrb r3, [r7, #1] 800719a: b29b uxth r3, r3 800719c: 887a ldrh r2, [r7, #2] 800719e: 429a cmp r2, r3 80071a0: d9ee bls.n 8007180 <fillDataField+0x60> } // обновление номера последнего считанного слова страницы if (read.page_offset_read == -1) { 80071a2: 4b1c ldr r3, [pc, #112] ; (8007214 <fillDataField+0xf4>) 80071a4: f993 3004 ldrsb.w r3, [r3, #4] 80071a8: f1b3 3fff cmp.w r3, #4294967295 80071ac: d109 bne.n 80071c2 <fillDataField+0xa2> read.page_offset_read = (read.num_ready_bytes / 2) - 1; 80071ae: 4b19 ldr r3, [pc, #100] ; (8007214 <fillDataField+0xf4>) 80071b0: 795b ldrb r3, [r3, #5] 80071b2: 085b lsrs r3, r3, #1 80071b4: b2db uxtb r3, r3 80071b6: 3b01 subs r3, #1 80071b8: b2db uxtb r3, r3 80071ba: b25a sxtb r2, r3 80071bc: 4b15 ldr r3, [pc, #84] ; (8007214 <fillDataField+0xf4>) 80071be: 711a strb r2, [r3, #4] 80071c0: e00c b.n 80071dc <fillDataField+0xbc> } else { read.page_offset_read += (read.num_ready_bytes / 2); 80071c2: 4b14 ldr r3, [pc, #80] ; (8007214 <fillDataField+0xf4>) 80071c4: f993 3004 ldrsb.w r3, [r3, #4] 80071c8: b2da uxtb r2, r3 80071ca: 4b12 ldr r3, [pc, #72] ; (8007214 <fillDataField+0xf4>) 80071cc: 795b ldrb r3, [r3, #5] 80071ce: 085b lsrs r3, r3, #1 80071d0: b2db uxtb r3, r3 80071d2: 4413 add r3, r2 80071d4: b2db uxtb r3, r3 80071d6: b25a sxtb r2, r3 80071d8: 4b0e ldr r3, [pc, #56] ; (8007214 <fillDataField+0xf4>) 80071da: 711a strb r2, [r3, #4] } // обновление номера страницы флеш-памяти, которая будет считана в следующий раз если текущая считана полностью if (read.page_offset_read == 126) { 80071dc: 4b0d ldr r3, [pc, #52] ; (8007214 <fillDataField+0xf4>) 80071de: f993 3004 ldrsb.w r3, [r3, #4] 80071e2: 2b7e cmp r3, #126 ; 0x7e 80071e4: d113 bne.n 800720e <fillDataField+0xee> if (read.cur_page_num == LIMIT_FLASH_PAGE_NUM - 1) { // текущая считанная страница последняя во флеш-памяти 80071e6: 4b0b ldr r3, [pc, #44] ; (8007214 <fillDataField+0xf4>) 80071e8: 681b ldr r3, [r3, #0] 80071ea: f64f 72ff movw r2, #65535 ; 0xffff 80071ee: 4293 cmp r3, r2 80071f0: d103 bne.n 80071fa <fillDataField+0xda> read.cur_page_num = 0; 80071f2: 4b08 ldr r3, [pc, #32] ; (8007214 <fillDataField+0xf4>) 80071f4: 2200 movs r2, #0 80071f6: 601a str r2, [r3, #0] 80071f8: e004 b.n 8007204 <fillDataField+0xe4> } else { read.cur_page_num++; 80071fa: 4b06 ldr r3, [pc, #24] ; (8007214 <fillDataField+0xf4>) 80071fc: 681b ldr r3, [r3, #0] 80071fe: 3301 adds r3, #1 8007200: 4a04 ldr r2, [pc, #16] ; (8007214 <fillDataField+0xf4>) 8007202: 6013 str r3, [r2, #0] } // выполняется сброс смещения для чтения, поскольку было прочитано последнее слово страницы флеш-памяти read.page_offset_read = -1; 8007204: 4b03 ldr r3, [pc, #12] ; (8007214 <fillDataField+0xf4>) 8007206: 22ff movs r2, #255 ; 0xff 8007208: 711a strb r2, [r3, #4] 800720a: e000 b.n 800720e <fillDataField+0xee> return; 800720c: bf00 nop } }; 800720e: 3708 adds r7, #8 8007210: 46bd mov sp, r7 8007212: bd80 pop {r7, pc} 8007214: 20000014 .word 0x20000014 8007218: 40010800 .word 0x40010800 800721c: 20000748 .word 0x20000748 8007220: 2000063c .word 0x2000063c 8007224: 20000cd4 .word 0x20000cd4 08007228 <fillResponseFrame>: /* Заполняет кадр ответа и уведомляет модуль SPI_connection о готовности ответа к отправке * Параметр 1: код состояния датчика по протоколу * Параметр 2: код команды, на которую дается ответ */ void fillResponseFrame(uint16_t response_code, uint16_t command_code) { 8007228: b580 push {r7, lr} 800722a: b084 sub sp, #16 800722c: af00 add r7, sp, #0 800722e: 4603 mov r3, r0 8007230: 460a mov r2, r1 8007232: 80fb strh r3, [r7, #6] 8007234: 4613 mov r3, r2 8007236: 80bb strh r3, [r7, #4] // формирование ответа memset(response,0,FRAME_LEN); 8007238: f44f 7284 mov.w r2, #264 ; 0x108 800723c: 2100 movs r1, #0 800723e: 4821 ldr r0, [pc, #132] ; (80072c4 <fillResponseFrame+0x9c>) 8007240: f000 fbcc bl 80079dc <memset> response[0] = 0xFA; 8007244: 4b1f ldr r3, [pc, #124] ; (80072c4 <fillResponseFrame+0x9c>) 8007246: 22fa movs r2, #250 ; 0xfa 8007248: 701a strb r2, [r3, #0] response[1] = 0xAF; 800724a: 4b1e ldr r3, [pc, #120] ; (80072c4 <fillResponseFrame+0x9c>) 800724c: 22af movs r2, #175 ; 0xaf 800724e: 705a strb r2, [r3, #1] response[2] = response_code; 8007250: 88fb ldrh r3, [r7, #6] 8007252: b2da uxtb r2, r3 8007254: 4b1b ldr r3, [pc, #108] ; (80072c4 <fillResponseFrame+0x9c>) 8007256: 709a strb r2, [r3, #2] if (command_code == CMD_STATUS) { 8007258: 88bb ldrh r3, [r7, #4] 800725a: 2ba2 cmp r3, #162 ; 0xa2 800725c: d103 bne.n 8007266 <fillResponseFrame+0x3e> // определение числа готовых данных измерения response[3] = read.num_ready_bytes; 800725e: 4b1a ldr r3, [pc, #104] ; (80072c8 <fillResponseFrame+0xa0>) 8007260: 795a ldrb r2, [r3, #5] 8007262: 4b18 ldr r3, [pc, #96] ; (80072c4 <fillResponseFrame+0x9c>) 8007264: 70da strb r2, [r3, #3] response[254] = read.cur_page_num; response[255] = page_pos_ptr; response[256] = read.page_offset_read; response[257] = FSM_state; */ response[258] = 0xFF; 8007266: 4b17 ldr r3, [pc, #92] ; (80072c4 <fillResponseFrame+0x9c>) 8007268: 22ff movs r2, #255 ; 0xff 800726a: f883 2102 strb.w r2, [r3, #258] ; 0x102 response[259] = 0x0D; 800726e: 4b15 ldr r3, [pc, #84] ; (80072c4 <fillResponseFrame+0x9c>) 8007270: 220d movs r2, #13 8007272: f883 2103 strb.w r2, [r3, #259] ; 0x103 // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 8007276: f44f 7182 mov.w r1, #260 ; 0x104 800727a: 4812 ldr r0, [pc, #72] ; (80072c4 <fillResponseFrame+0x9c>) 800727c: f000 fa44 bl 8007708 <calculateCRC32> 8007280: 60f8 str r0, [r7, #12] response[260] = (crc >> 24) & 0xFF; 8007282: 68fb ldr r3, [r7, #12] 8007284: 0e1b lsrs r3, r3, #24 8007286: b2da uxtb r2, r3 8007288: 4b0e ldr r3, [pc, #56] ; (80072c4 <fillResponseFrame+0x9c>) 800728a: f883 2104 strb.w r2, [r3, #260] ; 0x104 response[261] = (crc >> 16) & 0xFF; 800728e: 68fb ldr r3, [r7, #12] 8007290: 0c1b lsrs r3, r3, #16 8007292: b2da uxtb r2, r3 8007294: 4b0b ldr r3, [pc, #44] ; (80072c4 <fillResponseFrame+0x9c>) 8007296: f883 2105 strb.w r2, [r3, #261] ; 0x105 response[262] = (crc >> 8) & 0xFF; 800729a: 68fb ldr r3, [r7, #12] 800729c: 0a1b lsrs r3, r3, #8 800729e: b2da uxtb r2, r3 80072a0: 4b08 ldr r3, [pc, #32] ; (80072c4 <fillResponseFrame+0x9c>) 80072a2: f883 2106 strb.w r2, [r3, #262] ; 0x106 response[263] = crc & 0xFF; 80072a6: 68fb ldr r3, [r7, #12] 80072a8: b2da uxtb r2, r3 80072aa: 4b06 ldr r3, [pc, #24] ; (80072c4 <fillResponseFrame+0x9c>) 80072ac: f883 2107 strb.w r2, [r3, #263] ; 0x107 // устанавливаем указатель модуля приема/передачи на буфер с подготовленным ответом new_response_frame = response; 80072b0: 4b06 ldr r3, [pc, #24] ; (80072cc <fillResponseFrame+0xa4>) 80072b2: 4a04 ldr r2, [pc, #16] ; (80072c4 <fillResponseFrame+0x9c>) 80072b4: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 80072b6: 4b06 ldr r3, [pc, #24] ; (80072d0 <fillResponseFrame+0xa8>) 80072b8: 2201 movs r2, #1 80072ba: 701a strb r2, [r3, #0] }; 80072bc: bf00 nop 80072be: 3710 adds r7, #16 80072c0: 46bd mov sp, r7 80072c2: bd80 pop {r7, pc} 80072c4: 20000cd4 .word 0x20000cd4 80072c8: 20000014 .word 0x20000014 80072cc: 20000bc8 .word 0x20000bc8 80072d0: 2000079d .word 0x2000079d 080072d4 <sendPreviousResponse>: /* Подготавливает к отправке предыдущий кадр ответа */ void sendPreviousResponse() { 80072d4: b580 push {r7, lr} 80072d6: af00 add r7, sp, #0 // обновление сохраненного ответа updateSavedResponse(response); 80072d8: 4805 ldr r0, [pc, #20] ; (80072f0 <sendPreviousResponse+0x1c>) 80072da: f000 f80f bl 80072fc <updateSavedResponse> // устанавливаем указатель модуля приема/передачи на буфер с прошлым ответом для его передачи new_response_frame = response; 80072de: 4b05 ldr r3, [pc, #20] ; (80072f4 <sendPreviousResponse+0x20>) 80072e0: 4a03 ldr r2, [pc, #12] ; (80072f0 <sendPreviousResponse+0x1c>) 80072e2: 601a str r2, [r3, #0] // сигнализируем модулю приема/передачи SPI о том, что ответ готов response_ready = true; 80072e4: 4b04 ldr r3, [pc, #16] ; (80072f8 <sendPreviousResponse+0x24>) 80072e6: 2201 movs r2, #1 80072e8: 701a strb r2, [r3, #0] return; 80072ea: bf00 nop }; 80072ec: bd80 pop {r7, pc} 80072ee: bf00 nop 80072f0: 20000cd4 .word 0x20000cd4 80072f4: 20000bc8 .word 0x20000bc8 80072f8: 2000079d .word 0x2000079d 080072fc <updateSavedResponse>: void updateSavedResponse(uint8_t* response) { 80072fc: b580 push {r7, lr} 80072fe: b084 sub sp, #16 8007300: af00 add r7, sp, #0 8007302: 6078 str r0, [r7, #4] // определение типа сохраненного кадра ответа if (response[1] == 0xAA) { // сохраненный кадр - кадр ответа с данными (проверка 2-го байта старт-слова) 8007304: 687b ldr r3, [r7, #4] 8007306: 3301 adds r3, #1 8007308: 781b ldrb r3, [r3, #0] 800730a: 2baa cmp r3, #170 ; 0xaa 800730c: d107 bne.n 800731e <updateSavedResponse+0x22> // обновления наличия следующих байт данных, для следующего запроса на получение данных updateNumAvailableMeasData(); 800730e: f7ff fe59 bl 8006fc4 <updateNumAvailableMeasData> response[2] = read.num_ready_bytes; 8007312: 687b ldr r3, [r7, #4] 8007314: 3302 adds r3, #2 8007316: 4a1a ldr r2, [pc, #104] ; (8007380 <updateSavedResponse+0x84>) 8007318: 7952 ldrb r2, [r2, #5] 800731a: 701a strb r2, [r3, #0] 800731c: e00b b.n 8007336 <updateSavedResponse+0x3a> } else { // кадр ответа на команду if (response[2] == CMD_STATUS) { 800731e: 687b ldr r3, [r7, #4] 8007320: 3302 adds r3, #2 8007322: 781b ldrb r3, [r3, #0] 8007324: 2ba2 cmp r3, #162 ; 0xa2 8007326: d106 bne.n 8007336 <updateSavedResponse+0x3a> // обновление признака наличия результатов измерения updateNumAvailableMeasData(); 8007328: f7ff fe4c bl 8006fc4 <updateNumAvailableMeasData> response[3] = read.num_ready_bytes; 800732c: 687b ldr r3, [r7, #4] 800732e: 3303 adds r3, #3 8007330: 4a13 ldr r2, [pc, #76] ; (8007380 <updateSavedResponse+0x84>) 8007332: 7952 ldrb r2, [r2, #5] 8007334: 701a strb r2, [r3, #0] } } // формирование CRC для кадра в порядке MSB uint32_t crc = calculateCRC32(response,FRAME_LEN-4); 8007336: f44f 7182 mov.w r1, #260 ; 0x104 800733a: 6878 ldr r0, [r7, #4] 800733c: f000 f9e4 bl 8007708 <calculateCRC32> 8007340: 60f8 str r0, [r7, #12] response[260] = (crc >> 24) & 0xFF; 8007342: 68fb ldr r3, [r7, #12] 8007344: 0e1a lsrs r2, r3, #24 8007346: 687b ldr r3, [r7, #4] 8007348: f503 7382 add.w r3, r3, #260 ; 0x104 800734c: b2d2 uxtb r2, r2 800734e: 701a strb r2, [r3, #0] response[261] = (crc >> 16) & 0xFF; 8007350: 68fb ldr r3, [r7, #12] 8007352: 0c1a lsrs r2, r3, #16 8007354: 687b ldr r3, [r7, #4] 8007356: f203 1305 addw r3, r3, #261 ; 0x105 800735a: b2d2 uxtb r2, r2 800735c: 701a strb r2, [r3, #0] response[262] = (crc >> 8) & 0xFF; 800735e: 68fb ldr r3, [r7, #12] 8007360: 0a1a lsrs r2, r3, #8 8007362: 687b ldr r3, [r7, #4] 8007364: f503 7383 add.w r3, r3, #262 ; 0x106 8007368: b2d2 uxtb r2, r2 800736a: 701a strb r2, [r3, #0] response[263] = crc & 0xFF; 800736c: 687b ldr r3, [r7, #4] 800736e: f203 1307 addw r3, r3, #263 ; 0x107 8007372: 68fa ldr r2, [r7, #12] 8007374: b2d2 uxtb r2, r2 8007376: 701a strb r2, [r3, #0] return; 8007378: bf00 nop } 800737a: 3710 adds r7, #16 800737c: 46bd mov sp, r7 800737e: bd80 pop {r7, pc} 8007380: 20000014 .word 0x20000014 08007384 <parserFSM>: void parserFSM() { 8007384: b580 push {r7, lr} 8007386: af00 add r7, sp, #0 #ifndef TEST_VER sendRxCompleteCTRL(); 8007388: f000 fa14 bl 80077b4 <sendRxCompleteCTRL> // проверка контрольной суммы if(!checkCRC32(safe_command_frame, FRAME_LEN-4)) { 800738c: f44f 7182 mov.w r1, #260 ; 0x104 8007390: 48ba ldr r0, [pc, #744] ; (800767c <parserFSM+0x2f8>) 8007392: f000 f989 bl 80076a8 <checkCRC32> 8007396: 4603 mov r3, r0 8007398: f083 0301 eor.w r3, r3, #1 800739c: b2db uxtb r3, r3 800739e: 2b00 cmp r3, #0 80073a0: d004 beq.n 80073ac <parserFSM+0x28> // формирование ответа - ошибка CRC fillResponseFrame(CRC_ERROR, 0); 80073a2: 2100 movs r1, #0 80073a4: 20ff movs r0, #255 ; 0xff 80073a6: f7ff ff3f bl 8007228 <fillResponseFrame> return; 80073aa: e17c b.n 80076a6 <parserFSM+0x322> } #endif switch(FSM_state) { 80073ac: 4bb4 ldr r3, [pc, #720] ; (8007680 <parserFSM+0x2fc>) 80073ae: 781b ldrb r3, [r3, #0] 80073b0: 2b05 cmp r3, #5 80073b2: f200 8178 bhi.w 80076a6 <parserFSM+0x322> 80073b6: a201 add r2, pc, #4 ; (adr r2, 80073bc <parserFSM+0x38>) 80073b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80073bc: 080073d5 .word 0x080073d5 80073c0: 08007433 .word 0x08007433 80073c4: 080074af .word 0x080074af 80073c8: 0800753d .word 0x0800753d 80073cc: 080075bd .word 0x080075bd 80073d0: 08007645 .word 0x08007645 case CONNECTED_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 80073d4: 4ba9 ldr r3, [pc, #676] ; (800767c <parserFSM+0x2f8>) 80073d6: 789b ldrb r3, [r3, #2] 80073d8: 2bff cmp r3, #255 ; 0xff 80073da: d026 beq.n 800742a <parserFSM+0xa6> 80073dc: 2bff cmp r3, #255 ; 0xff 80073de: f300 8159 bgt.w 8007694 <parserFSM+0x310> 80073e2: 2ba2 cmp r3, #162 ; 0xa2 80073e4: d002 beq.n 80073ec <parserFSM+0x68> 80073e6: 2ba3 cmp r3, #163 ; 0xa3 80073e8: d01c beq.n 8007424 <parserFSM+0xa0> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 80073ea: e153 b.n 8007694 <parserFSM+0x310> if (sensorSelfCheck()) { // самопроверка датчика выполнилась успешно 80073ec: f000 fa0a bl 8007804 <sensorSelfCheck> 80073f0: 4603 mov r3, r0 80073f2: 2b00 cmp r3, #0 80073f4: d011 beq.n 800741a <parserFSM+0x96> updateNumAvailableMeasData(); 80073f6: f7ff fde5 bl 8006fc4 <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 80073fa: 4ba2 ldr r3, [pc, #648] ; (8007684 <parserFSM+0x300>) 80073fc: 795b ldrb r3, [r3, #5] 80073fe: 2b00 cmp r3, #0 8007400: d003 beq.n 800740a <parserFSM+0x86> setFSMProtocolState(EXCHANGE_STATE); 8007402: 2003 movs r0, #3 8007404: f7ff fe2e bl 8007064 <setFSMProtocolState> 8007408: e002 b.n 8007410 <parserFSM+0x8c> setFSMProtocolState(READY_STATE); 800740a: 2001 movs r0, #1 800740c: f7ff fe2a bl 8007064 <setFSMProtocolState> fillResponseFrame(SENSOR_ID, CMD_STATUS); 8007410: 21a2 movs r1, #162 ; 0xa2 8007412: 202a movs r0, #42 ; 0x2a 8007414: f7ff ff08 bl 8007228 <fillResponseFrame> break; 8007418: e00a b.n 8007430 <parserFSM+0xac> fillResponseFrame(STATE_ERROR, CMD_STATUS); 800741a: 21a2 movs r1, #162 ; 0xa2 800741c: 2008 movs r0, #8 800741e: f7ff ff03 bl 8007228 <fillResponseFrame> break; 8007422: e005 b.n 8007430 <parserFSM+0xac> resetSensor(); 8007424: f000 fa70 bl 8007908 <resetSensor> break; 8007428: e002 b.n 8007430 <parserFSM+0xac> sendPreviousResponse(); 800742a: f7ff ff53 bl 80072d4 <sendPreviousResponse> break; 800742e: bf00 nop break; 8007430: e130 b.n 8007694 <parserFSM+0x310> case READY_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 8007432: 4b92 ldr r3, [pc, #584] ; (800767c <parserFSM+0x2f8>) 8007434: 789b ldrb r3, [r3, #2] 8007436: 2bff cmp r3, #255 ; 0xff 8007438: d035 beq.n 80074a6 <parserFSM+0x122> 800743a: 2bff cmp r3, #255 ; 0xff 800743c: f300 812c bgt.w 8007698 <parserFSM+0x314> 8007440: 2ba4 cmp r3, #164 ; 0xa4 8007442: d026 beq.n 8007492 <parserFSM+0x10e> 8007444: 2ba4 cmp r3, #164 ; 0xa4 8007446: f300 8127 bgt.w 8007698 <parserFSM+0x314> 800744a: 2ba2 cmp r3, #162 ; 0xa2 800744c: d002 beq.n 8007454 <parserFSM+0xd0> 800744e: 2ba3 cmp r3, #163 ; 0xa3 8007450: d01c beq.n 800748c <parserFSM+0x108> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 8007452: e121 b.n 8007698 <parserFSM+0x314> if (sensorSelfCheck()) { // самопроверка датчика выполнилась успешно 8007454: f000 f9d6 bl 8007804 <sensorSelfCheck> 8007458: 4603 mov r3, r0 800745a: 2b00 cmp r3, #0 800745c: d011 beq.n 8007482 <parserFSM+0xfe> updateNumAvailableMeasData(); 800745e: f7ff fdb1 bl 8006fc4 <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8007462: 4b88 ldr r3, [pc, #544] ; (8007684 <parserFSM+0x300>) 8007464: 795b ldrb r3, [r3, #5] 8007466: 2b00 cmp r3, #0 8007468: d003 beq.n 8007472 <parserFSM+0xee> setFSMProtocolState(EXCHANGE_STATE); 800746a: 2003 movs r0, #3 800746c: f7ff fdfa bl 8007064 <setFSMProtocolState> 8007470: e002 b.n 8007478 <parserFSM+0xf4> setFSMProtocolState(READY_STATE); 8007472: 2001 movs r0, #1 8007474: f7ff fdf6 bl 8007064 <setFSMProtocolState> fillResponseFrame(SENSOR_ID, CMD_STATUS); 8007478: 21a2 movs r1, #162 ; 0xa2 800747a: 202a movs r0, #42 ; 0x2a 800747c: f7ff fed4 bl 8007228 <fillResponseFrame> break; 8007480: e014 b.n 80074ac <parserFSM+0x128> fillResponseFrame(STATE_ERROR, CMD_STATUS); 8007482: 21a2 movs r1, #162 ; 0xa2 8007484: 2008 movs r0, #8 8007486: f7ff fecf bl 8007228 <fillResponseFrame> break; 800748a: e00f b.n 80074ac <parserFSM+0x128> resetSensor(); 800748c: f000 fa3c bl 8007908 <resetSensor> break; 8007490: e00c b.n 80074ac <parserFSM+0x128> fillResponseFrame(STATE_START_MEASURE, CMD_START_MEASURE); 8007492: 21a4 movs r1, #164 ; 0xa4 8007494: 2006 movs r0, #6 8007496: f7ff fec7 bl 8007228 <fillResponseFrame> startMeasurement(); 800749a: f000 fa57 bl 800794c <startMeasurement> setFSMProtocolState(MEASUREMENT_STATE); 800749e: 2002 movs r0, #2 80074a0: f7ff fde0 bl 8007064 <setFSMProtocolState> break; 80074a4: e002 b.n 80074ac <parserFSM+0x128> sendPreviousResponse(); 80074a6: f7ff ff15 bl 80072d4 <sendPreviousResponse> break; 80074aa: bf00 nop break; 80074ac: e0f4 b.n 8007698 <parserFSM+0x314> case MEASUREMENT_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 80074ae: 4b73 ldr r3, [pc, #460] ; (800767c <parserFSM+0x2f8>) 80074b0: 789b ldrb r3, [r3, #2] 80074b2: 2ba7 cmp r3, #167 ; 0xa7 80074b4: dc18 bgt.n 80074e8 <parserFSM+0x164> 80074b6: 2ba1 cmp r3, #161 ; 0xa1 80074b8: f2c0 80f0 blt.w 800769c <parserFSM+0x318> 80074bc: 3ba1 subs r3, #161 ; 0xa1 80074be: 2b06 cmp r3, #6 80074c0: f200 80ec bhi.w 800769c <parserFSM+0x318> 80074c4: a201 add r2, pc, #4 ; (adr r2, 80074cc <parserFSM+0x148>) 80074c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80074ca: bf00 nop 80074cc: 080074ef .word 0x080074ef 80074d0: 080074fb .word 0x080074fb 80074d4: 0800751b .word 0x0800751b 80074d8: 0800769d .word 0x0800769d 80074dc: 0800769d .word 0x0800769d 80074e0: 0800769d .word 0x0800769d 80074e4: 08007521 .word 0x08007521 80074e8: 2bff cmp r3, #255 ; 0xff 80074ea: d023 beq.n 8007534 <parserFSM+0x1b0> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 80074ec: e0d6 b.n 800769c <parserFSM+0x318> setFSMProtocolState(MEASUREMENT_EXCHANGE_STATE); 80074ee: 2004 movs r0, #4 80074f0: f7ff fdb8 bl 8007064 <setFSMProtocolState> fillDataFrame(); 80074f4: f7ff fdc6 bl 8007084 <fillDataFrame> break; 80074f8: e01f b.n 800753a <parserFSM+0x1b6> updateNumAvailableMeasData(); 80074fa: f7ff fd63 bl 8006fc4 <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 80074fe: 4b61 ldr r3, [pc, #388] ; (8007684 <parserFSM+0x300>) 8007500: 795b ldrb r3, [r3, #5] 8007502: 2b00 cmp r3, #0 8007504: d004 beq.n 8007510 <parserFSM+0x18c> fillResponseFrame(STATE_READY, CMD_STATUS); 8007506: 21a2 movs r1, #162 ; 0xa2 8007508: 2001 movs r0, #1 800750a: f7ff fe8d bl 8007228 <fillResponseFrame> break; 800750e: e014 b.n 800753a <parserFSM+0x1b6> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 8007510: 21a2 movs r1, #162 ; 0xa2 8007512: 2002 movs r0, #2 8007514: f7ff fe88 bl 8007228 <fillResponseFrame> break; 8007518: e00f b.n 800753a <parserFSM+0x1b6> resetSensor(); 800751a: f000 f9f5 bl 8007908 <resetSensor> break; 800751e: e00c b.n 800753a <parserFSM+0x1b6> stopMeasurement(); 8007520: f000 fa1c bl 800795c <stopMeasurement> fillResponseFrame(STATE_STOP_MEASURE, CMD_STOP_MEASURE); 8007524: 21a7 movs r1, #167 ; 0xa7 8007526: 2007 movs r0, #7 8007528: f7ff fe7e bl 8007228 <fillResponseFrame> setFSMProtocolState(READY_STATE); 800752c: 2001 movs r0, #1 800752e: f7ff fd99 bl 8007064 <setFSMProtocolState> break; 8007532: e002 b.n 800753a <parserFSM+0x1b6> sendPreviousResponse(); 8007534: f7ff fece bl 80072d4 <sendPreviousResponse> break; 8007538: bf00 nop break; 800753a: e0af b.n 800769c <parserFSM+0x318> case EXCHANGE_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 800753c: 4b4f ldr r3, [pc, #316] ; (800767c <parserFSM+0x2f8>) 800753e: 789b ldrb r3, [r3, #2] 8007540: 2ba4 cmp r3, #164 ; 0xa4 8007542: dc11 bgt.n 8007568 <parserFSM+0x1e4> 8007544: 2ba1 cmp r3, #161 ; 0xa1 8007546: f2c0 80ab blt.w 80076a0 <parserFSM+0x31c> 800754a: 3ba1 subs r3, #161 ; 0xa1 800754c: 2b03 cmp r3, #3 800754e: f200 80a7 bhi.w 80076a0 <parserFSM+0x31c> 8007552: a201 add r2, pc, #4 ; (adr r2, 8007558 <parserFSM+0x1d4>) 8007554: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007558: 0800756f .word 0x0800756f 800755c: 08007575 .word 0x08007575 8007560: 0800759b .word 0x0800759b 8007564: 080075a1 .word 0x080075a1 8007568: 2bff cmp r3, #255 ; 0xff 800756a: d023 beq.n 80075b4 <parserFSM+0x230> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 800756c: e098 b.n 80076a0 <parserFSM+0x31c> fillDataFrame(); 800756e: f7ff fd89 bl 8007084 <fillDataFrame> break; 8007572: e022 b.n 80075ba <parserFSM+0x236> updateNumAvailableMeasData(); 8007574: f7ff fd26 bl 8006fc4 <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8007578: 4b42 ldr r3, [pc, #264] ; (8007684 <parserFSM+0x300>) 800757a: 795b ldrb r3, [r3, #5] 800757c: 2b00 cmp r3, #0 800757e: d004 beq.n 800758a <parserFSM+0x206> fillResponseFrame(STATE_READY, CMD_STATUS); 8007580: 21a2 movs r1, #162 ; 0xa2 8007582: 2001 movs r0, #1 8007584: f7ff fe50 bl 8007228 <fillResponseFrame> break; 8007588: e017 b.n 80075ba <parserFSM+0x236> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 800758a: 21a2 movs r1, #162 ; 0xa2 800758c: 2002 movs r0, #2 800758e: f7ff fe4b bl 8007228 <fillResponseFrame> setFSMProtocolState(READY_STATE); 8007592: 2001 movs r0, #1 8007594: f7ff fd66 bl 8007064 <setFSMProtocolState> break; 8007598: e00f b.n 80075ba <parserFSM+0x236> resetSensor(); 800759a: f000 f9b5 bl 8007908 <resetSensor> break; 800759e: e00c b.n 80075ba <parserFSM+0x236> fillResponseFrame(STATE_START_MEASURE, CMD_START_MEASURE); 80075a0: 21a4 movs r1, #164 ; 0xa4 80075a2: 2006 movs r0, #6 80075a4: f7ff fe40 bl 8007228 <fillResponseFrame> startMeasurement(); 80075a8: f000 f9d0 bl 800794c <startMeasurement> setFSMProtocolState(MEASUREMENT_EXCHANGE_STATE); 80075ac: 2004 movs r0, #4 80075ae: f7ff fd59 bl 8007064 <setFSMProtocolState> break; 80075b2: e002 b.n 80075ba <parserFSM+0x236> sendPreviousResponse(); 80075b4: f7ff fe8e bl 80072d4 <sendPreviousResponse> break; 80075b8: bf00 nop break; 80075ba: e071 b.n 80076a0 <parserFSM+0x31c> case MEASUREMENT_EXCHANGE_STATE: // анализ полученной команды switch (safe_command_frame[2]) { 80075bc: 4b2f ldr r3, [pc, #188] ; (800767c <parserFSM+0x2f8>) 80075be: 789b ldrb r3, [r3, #2] 80075c0: 2ba7 cmp r3, #167 ; 0xa7 80075c2: dc15 bgt.n 80075f0 <parserFSM+0x26c> 80075c4: 2ba1 cmp r3, #161 ; 0xa1 80075c6: db6d blt.n 80076a4 <parserFSM+0x320> 80075c8: 3ba1 subs r3, #161 ; 0xa1 80075ca: 2b06 cmp r3, #6 80075cc: d86a bhi.n 80076a4 <parserFSM+0x320> 80075ce: a201 add r2, pc, #4 ; (adr r2, 80075d4 <parserFSM+0x250>) 80075d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80075d4: 080075f7 .word 0x080075f7 80075d8: 080075fd .word 0x080075fd 80075dc: 08007623 .word 0x08007623 80075e0: 080076a5 .word 0x080076a5 80075e4: 080076a5 .word 0x080076a5 80075e8: 080076a5 .word 0x080076a5 80075ec: 08007629 .word 0x08007629 80075f0: 2bff cmp r3, #255 ; 0xff 80075f2: d023 beq.n 800763c <parserFSM+0x2b8> break; case CMD_CRC_ANS_ERR: sendPreviousResponse(); break; } break; 80075f4: e056 b.n 80076a4 <parserFSM+0x320> fillDataFrame(); 80075f6: f7ff fd45 bl 8007084 <fillDataFrame> break; 80075fa: e022 b.n 8007642 <parserFSM+0x2be> updateNumAvailableMeasData(); 80075fc: f7ff fce2 bl 8006fc4 <updateNumAvailableMeasData> if (read.num_ready_bytes != 0) { // данные для передачи уже готовы 8007600: 4b20 ldr r3, [pc, #128] ; (8007684 <parserFSM+0x300>) 8007602: 795b ldrb r3, [r3, #5] 8007604: 2b00 cmp r3, #0 8007606: d004 beq.n 8007612 <parserFSM+0x28e> fillResponseFrame(STATE_READY, CMD_STATUS); 8007608: 21a2 movs r1, #162 ; 0xa2 800760a: 2001 movs r0, #1 800760c: f7ff fe0c bl 8007228 <fillResponseFrame> break; 8007610: e017 b.n 8007642 <parserFSM+0x2be> fillResponseFrame(STATE_NOT_READY, CMD_STATUS); 8007612: 21a2 movs r1, #162 ; 0xa2 8007614: 2002 movs r0, #2 8007616: f7ff fe07 bl 8007228 <fillResponseFrame> setFSMProtocolState(MEASUREMENT_STATE); 800761a: 2002 movs r0, #2 800761c: f7ff fd22 bl 8007064 <setFSMProtocolState> break; 8007620: e00f b.n 8007642 <parserFSM+0x2be> resetSensor(); 8007622: f000 f971 bl 8007908 <resetSensor> break; 8007626: e00c b.n 8007642 <parserFSM+0x2be> stopMeasurement(); 8007628: f000 f998 bl 800795c <stopMeasurement> fillResponseFrame(STATE_STOP_MEASURE, CMD_STOP_MEASURE); 800762c: 21a7 movs r1, #167 ; 0xa7 800762e: 2007 movs r0, #7 8007630: f7ff fdfa bl 8007228 <fillResponseFrame> setFSMProtocolState(EXCHANGE_STATE); 8007634: 2003 movs r0, #3 8007636: f7ff fd15 bl 8007064 <setFSMProtocolState> break; 800763a: e002 b.n 8007642 <parserFSM+0x2be> sendPreviousResponse(); 800763c: f7ff fe4a bl 80072d4 <sendPreviousResponse> break; 8007640: bf00 nop break; 8007642: e02f b.n 80076a4 <parserFSM+0x320> case RESET_STATE: if(safe_command_frame[2] == CMD_STATUS) { 8007644: 4b0d ldr r3, [pc, #52] ; (800767c <parserFSM+0x2f8>) 8007646: 789b ldrb r3, [r3, #2] 8007648: 2ba2 cmp r3, #162 ; 0xa2 800764a: d12c bne.n 80076a6 <parserFSM+0x322> if (reset_ready) { 800764c: 4b0e ldr r3, [pc, #56] ; (8007688 <parserFSM+0x304>) 800764e: 781b ldrb r3, [r3, #0] 8007650: 2b00 cmp r3, #0 8007652: d00f beq.n 8007674 <parserFSM+0x2f0> HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET); 8007654: 2200 movs r2, #0 8007656: 2104 movs r1, #4 8007658: 480c ldr r0, [pc, #48] ; (800768c <parserFSM+0x308>) 800765a: f7fc fbb0 bl 8003dbe <HAL_GPIO_WritePin> fillResponseFrame(STATE_RESET, CMD_RESET); 800765e: 21a3 movs r1, #163 ; 0xa3 8007660: 2005 movs r0, #5 8007662: f7ff fde1 bl 8007228 <fillResponseFrame> setFSMProtocolState(CONNECTED_STATE); 8007666: 2000 movs r0, #0 8007668: f7ff fcfc bl 8007064 <setFSMProtocolState> reset_ready = 0; 800766c: 4b06 ldr r3, [pc, #24] ; (8007688 <parserFSM+0x304>) 800766e: 2200 movs r2, #0 8007670: 701a strb r2, [r3, #0] 8007672: e018 b.n 80076a6 <parserFSM+0x322> } else { response_ready = 0; 8007674: 4b06 ldr r3, [pc, #24] ; (8007690 <parserFSM+0x30c>) 8007676: 2200 movs r2, #0 8007678: 701a strb r2, [r3, #0] 800767a: e014 b.n 80076a6 <parserFSM+0x322> 800767c: 200008a8 .word 0x200008a8 8007680: 20000ddc .word 0x20000ddc 8007684: 20000014 .word 0x20000014 8007688: 20000ddd .word 0x20000ddd 800768c: 40010800 .word 0x40010800 8007690: 2000079d .word 0x2000079d break; 8007694: bf00 nop 8007696: e006 b.n 80076a6 <parserFSM+0x322> break; 8007698: bf00 nop 800769a: e004 b.n 80076a6 <parserFSM+0x322> break; 800769c: bf00 nop 800769e: e002 b.n 80076a6 <parserFSM+0x322> break; 80076a0: bf00 nop 80076a2: e000 b.n 80076a6 <parserFSM+0x322> break; 80076a4: bf00 nop } } } }; 80076a6: bd80 pop {r7, pc} 080076a8 <checkCRC32>: bool checkCRC32(uint8_t* command_frame, uint16_t length) { 80076a8: b580 push {r7, lr} 80076aa: b084 sub sp, #16 80076ac: af00 add r7, sp, #0 80076ae: 6078 str r0, [r7, #4] 80076b0: 460b mov r3, r1 80076b2: 807b strh r3, [r7, #2] // получение CRC полученного кадра uint32_t command_crc = (uint32_t)command_frame[263] | 80076b4: 687b ldr r3, [r7, #4] 80076b6: f203 1307 addw r3, r3, #263 ; 0x107 80076ba: 781b ldrb r3, [r3, #0] 80076bc: 461a mov r2, r3 ((uint32_t)command_frame[262] << 8) | 80076be: 687b ldr r3, [r7, #4] 80076c0: f503 7383 add.w r3, r3, #262 ; 0x106 80076c4: 781b ldrb r3, [r3, #0] 80076c6: 021b lsls r3, r3, #8 uint32_t command_crc = (uint32_t)command_frame[263] | 80076c8: 431a orrs r2, r3 ((uint32_t)command_frame[261] << 16) | 80076ca: 687b ldr r3, [r7, #4] 80076cc: f203 1305 addw r3, r3, #261 ; 0x105 80076d0: 781b ldrb r3, [r3, #0] 80076d2: 041b lsls r3, r3, #16 ((uint32_t)command_frame[262] << 8) | 80076d4: 431a orrs r2, r3 ((uint32_t)command_frame[260] << 24); 80076d6: 687b ldr r3, [r7, #4] 80076d8: f503 7382 add.w r3, r3, #260 ; 0x104 80076dc: 781b ldrb r3, [r3, #0] 80076de: 061b lsls r3, r3, #24 uint32_t command_crc = (uint32_t)command_frame[263] | 80076e0: 4313 orrs r3, r2 80076e2: 60fb str r3, [r7, #12] // расчет ожидаемой CRC для полученного кадра uint32_t calc_crc = calculateCRC32(command_frame, FRAME_LEN-4); 80076e4: f44f 7182 mov.w r1, #260 ; 0x104 80076e8: 6878 ldr r0, [r7, #4] 80076ea: f000 f80d bl 8007708 <calculateCRC32> 80076ee: 60b8 str r0, [r7, #8] // сравнение полученной и ожидаемой CRC if (command_crc != calc_crc) { 80076f0: 68fa ldr r2, [r7, #12] 80076f2: 68bb ldr r3, [r7, #8] 80076f4: 429a cmp r2, r3 80076f6: d001 beq.n 80076fc <checkCRC32+0x54> return false; 80076f8: 2300 movs r3, #0 80076fa: e000 b.n 80076fe <checkCRC32+0x56> } else { return true; 80076fc: 2301 movs r3, #1 } }; 80076fe: 4618 mov r0, r3 8007700: 3710 adds r7, #16 8007702: 46bd mov sp, r7 8007704: bd80 pop {r7, pc} ... 08007708 <calculateCRC32>: uint32_t calculateCRC32(uint8_t* arg,uint16_t length) { 8007708: b480 push {r7} 800770a: b085 sub sp, #20 800770c: af00 add r7, sp, #0 800770e: 6078 str r0, [r7, #4] 8007710: 460b mov r3, r1 8007712: 807b strh r3, [r7, #2] uint32_t crc_f = 0xFFFFFFFF; // Начальное значение CRC 8007714: f04f 33ff mov.w r3, #4294967295 8007718: 60fb str r3, [r7, #12] for (int i=0;i<length;i++) 800771a: 2300 movs r3, #0 800771c: 60bb str r3, [r7, #8] 800771e: e011 b.n 8007744 <calculateCRC32+0x3c> {crc_f=crc32_table[(crc_f ^ arg[i]) & 0xFF] ^ (crc_f >> 8);} 8007720: 68bb ldr r3, [r7, #8] 8007722: 687a ldr r2, [r7, #4] 8007724: 4413 add r3, r2 8007726: 781b ldrb r3, [r3, #0] 8007728: 461a mov r2, r3 800772a: 68fb ldr r3, [r7, #12] 800772c: 4053 eors r3, r2 800772e: b2db uxtb r3, r3 8007730: 4a0a ldr r2, [pc, #40] ; (800775c <calculateCRC32+0x54>) 8007732: f852 2023 ldr.w r2, [r2, r3, lsl #2] 8007736: 68fb ldr r3, [r7, #12] 8007738: 0a1b lsrs r3, r3, #8 800773a: 4053 eors r3, r2 800773c: 60fb str r3, [r7, #12] for (int i=0;i<length;i++) 800773e: 68bb ldr r3, [r7, #8] 8007740: 3301 adds r3, #1 8007742: 60bb str r3, [r7, #8] 8007744: 887b ldrh r3, [r7, #2] 8007746: 68ba ldr r2, [r7, #8] 8007748: 429a cmp r2, r3 800774a: dbe9 blt.n 8007720 <calculateCRC32+0x18> return ~crc_f; 800774c: 68fb ldr r3, [r7, #12] 800774e: 43db mvns r3, r3 } 8007750: 4618 mov r0, r3 8007752: 3714 adds r7, #20 8007754: 46bd mov sp, r7 8007756: bc80 pop {r7} 8007758: 4770 bx lr 800775a: bf00 nop 800775c: 08008658 .word 0x08008658 08007760 <sensorInit>: /* Инициализация датчика при его подключении */ void sensorInit() { 8007760: b580 push {r7, lr} 8007762: af00 add r7, sp, #0 // инициализация флеш-памяти W25_Ini(0); 8007764: 2000 movs r0, #0 8007766: f7fa ff83 bl 8002670 <W25_Ini> // инициализация SPI-соединения initSPIConnection(); 800776a: f7ff fb7d bl 8006e68 <initSPIConnection> // инициализация микросхемы датчика sensorChipInit(); 800776e: f000 f899 bl 80078a4 <sensorChipInit> // включение таймера формирования сигнала CTRL HAL_TIM_OnePulse_Start(&htim2, TIM_CHANNEL_1); 8007772: 2100 movs r1, #0 8007774: 4806 ldr r0, [pc, #24] ; (8007790 <sensorInit+0x30>) 8007776: f7fe fac7 bl 8005d08 <HAL_TIM_OnePulse_Start> // задержка для удержания линии в активном уровне HAL_Delay(1); 800777a: 2001 movs r0, #1 800777c: f7fb f9fc bl 8002b78 <HAL_Delay> // отправка сигнала на CTRL для уведомления мастера о подключении датчика sendInitCTRL(); 8007780: f000 f808 bl 8007794 <sendInitCTRL> // установка состояния датчика "датчик подключен" setFSMProtocolState(CONNECTED_STATE); 8007784: 2000 movs r0, #0 8007786: f7ff fc6d bl 8007064 <setFSMProtocolState> } 800778a: bf00 nop 800778c: bd80 pop {r7, pc} 800778e: bf00 nop 8007790: 2000051c .word 0x2000051c 08007794 <sendInitCTRL>: /* Формирует сигнал CTRL для уведомления мастера о подключении датчика */ void sendInitCTRL() { 8007794: b480 push {r7} 8007796: af00 add r7, sp, #0 __HAL_TIM_ENABLE(&htim2); 8007798: 4b05 ldr r3, [pc, #20] ; (80077b0 <sendInitCTRL+0x1c>) 800779a: 681b ldr r3, [r3, #0] 800779c: 681a ldr r2, [r3, #0] 800779e: 4b04 ldr r3, [pc, #16] ; (80077b0 <sendInitCTRL+0x1c>) 80077a0: 681b ldr r3, [r3, #0] 80077a2: f042 0201 orr.w r2, r2, #1 80077a6: 601a str r2, [r3, #0] return; 80077a8: bf00 nop } 80077aa: 46bd mov sp, r7 80077ac: bc80 pop {r7} 80077ae: 4770 bx lr 80077b0: 2000051c .word 0x2000051c 080077b4 <sendRxCompleteCTRL>: /* Формирует сигнал CTRL для уведомления мастера о получении команды */ void sendRxCompleteCTRL() { 80077b4: b480 push {r7} 80077b6: af00 add r7, sp, #0 __HAL_TIM_ENABLE(&htim2); 80077b8: 4b05 ldr r3, [pc, #20] ; (80077d0 <sendRxCompleteCTRL+0x1c>) 80077ba: 681b ldr r3, [r3, #0] 80077bc: 681a ldr r2, [r3, #0] 80077be: 4b04 ldr r3, [pc, #16] ; (80077d0 <sendRxCompleteCTRL+0x1c>) 80077c0: 681b ldr r3, [r3, #0] 80077c2: f042 0201 orr.w r2, r2, #1 80077c6: 601a str r2, [r3, #0] return; 80077c8: bf00 nop } 80077ca: 46bd mov sp, r7 80077cc: bc80 pop {r7} 80077ce: 4770 bx lr 80077d0: 2000051c .word 0x2000051c 080077d4 <resetFSMProtocol>: void resetFSMProtocol() { 80077d4: b580 push {r7, lr} 80077d6: af00 add r7, sp, #0 setFSMProtocolState(RESET_STATE); 80077d8: 2005 movs r0, #5 80077da: f7ff fc43 bl 8007064 <setFSMProtocolState> read.cur_page_num = 0; 80077de: 4b07 ldr r3, [pc, #28] ; (80077fc <resetFSMProtocol+0x28>) 80077e0: 2200 movs r2, #0 80077e2: 601a str r2, [r3, #0] read.page_offset_read = -1; 80077e4: 4b05 ldr r3, [pc, #20] ; (80077fc <resetFSMProtocol+0x28>) 80077e6: 22ff movs r2, #255 ; 0xff 80077e8: 711a strb r2, [r3, #4] read.num_ready_bytes = 0; 80077ea: 4b04 ldr r3, [pc, #16] ; (80077fc <resetFSMProtocol+0x28>) 80077ec: 2200 movs r2, #0 80077ee: 715a strb r2, [r3, #5] response_ready = 0; 80077f0: 4b03 ldr r3, [pc, #12] ; (8007800 <resetFSMProtocol+0x2c>) 80077f2: 2200 movs r2, #0 80077f4: 701a strb r2, [r3, #0] } 80077f6: bf00 nop 80077f8: bd80 pop {r7, pc} 80077fa: bf00 nop 80077fc: 20000014 .word 0x20000014 8007800: 2000079d .word 0x2000079d 08007804 <sensorSelfCheck>: /* Выполняет проверку работоспособности датчика * Возврат: 1 - датчик работоспособен * 0 - датчик не работоспособен */ uint16_t val1, val2; bool sensorSelfCheck() { 8007804: b580 push {r7, lr} 8007806: af00 add r7, sp, #0 return true; #endif HAL_ADC_Start(&hadc1); 8007808: 4822 ldr r0, [pc, #136] ; (8007894 <sensorSelfCheck+0x90>) 800780a: f7fb fab1 bl 8002d70 <HAL_ADC_Start> if (HAL_ADC_PollForConversion(&hadc1, 300) == HAL_OK) { 800780e: f44f 7196 mov.w r1, #300 ; 0x12c 8007812: 4820 ldr r0, [pc, #128] ; (8007894 <sensorSelfCheck+0x90>) 8007814: f7fb fb86 bl 8002f24 <HAL_ADC_PollForConversion> 8007818: 4603 mov r3, r0 800781a: 2b00 cmp r3, #0 800781c: d106 bne.n 800782c <sensorSelfCheck+0x28> val1 = HAL_ADC_GetValue(&hadc1); 800781e: 481d ldr r0, [pc, #116] ; (8007894 <sensorSelfCheck+0x90>) 8007820: f7fb fd3c bl 800329c <HAL_ADC_GetValue> 8007824: 4603 mov r3, r0 8007826: b29a uxth r2, r3 8007828: 4b1b ldr r3, [pc, #108] ; (8007898 <sensorSelfCheck+0x94>) 800782a: 801a strh r2, [r3, #0] } HAL_ADC_Stop(&hadc1); 800782c: 4819 ldr r0, [pc, #100] ; (8007894 <sensorSelfCheck+0x90>) 800782e: f7fb fb4d bl 8002ecc <HAL_ADC_Stop> if (val1 == 0 || val1 == 4095) { 8007832: 4b19 ldr r3, [pc, #100] ; (8007898 <sensorSelfCheck+0x94>) 8007834: 881b ldrh r3, [r3, #0] 8007836: 2b00 cmp r3, #0 8007838: d005 beq.n 8007846 <sensorSelfCheck+0x42> 800783a: 4b17 ldr r3, [pc, #92] ; (8007898 <sensorSelfCheck+0x94>) 800783c: 881b ldrh r3, [r3, #0] 800783e: f640 72ff movw r2, #4095 ; 0xfff 8007842: 4293 cmp r3, r2 8007844: d101 bne.n 800784a <sensorSelfCheck+0x46> return false; 8007846: 2300 movs r3, #0 8007848: e021 b.n 800788e <sensorSelfCheck+0x8a> } HAL_ADC_Start(&hadc2); 800784a: 4814 ldr r0, [pc, #80] ; (800789c <sensorSelfCheck+0x98>) 800784c: f7fb fa90 bl 8002d70 <HAL_ADC_Start> if (HAL_ADC_PollForConversion(&hadc2, 300) == HAL_OK) { 8007850: f44f 7196 mov.w r1, #300 ; 0x12c 8007854: 4811 ldr r0, [pc, #68] ; (800789c <sensorSelfCheck+0x98>) 8007856: f7fb fb65 bl 8002f24 <HAL_ADC_PollForConversion> 800785a: 4603 mov r3, r0 800785c: 2b00 cmp r3, #0 800785e: d106 bne.n 800786e <sensorSelfCheck+0x6a> val2 = HAL_ADC_GetValue(&hadc2); 8007860: 480e ldr r0, [pc, #56] ; (800789c <sensorSelfCheck+0x98>) 8007862: f7fb fd1b bl 800329c <HAL_ADC_GetValue> 8007866: 4603 mov r3, r0 8007868: b29a uxth r2, r3 800786a: 4b0d ldr r3, [pc, #52] ; (80078a0 <sensorSelfCheck+0x9c>) 800786c: 801a strh r2, [r3, #0] } HAL_ADC_Stop(&hadc2); 800786e: 480b ldr r0, [pc, #44] ; (800789c <sensorSelfCheck+0x98>) 8007870: f7fb fb2c bl 8002ecc <HAL_ADC_Stop> if (val2 == 0 || val2 == 4095) { 8007874: 4b0a ldr r3, [pc, #40] ; (80078a0 <sensorSelfCheck+0x9c>) 8007876: 881b ldrh r3, [r3, #0] 8007878: 2b00 cmp r3, #0 800787a: d005 beq.n 8007888 <sensorSelfCheck+0x84> 800787c: 4b08 ldr r3, [pc, #32] ; (80078a0 <sensorSelfCheck+0x9c>) 800787e: 881b ldrh r3, [r3, #0] 8007880: f640 72ff movw r2, #4095 ; 0xfff 8007884: 4293 cmp r3, r2 8007886: d101 bne.n 800788c <sensorSelfCheck+0x88> return false; 8007888: 2300 movs r3, #0 800788a: e000 b.n 800788e <sensorSelfCheck+0x8a> HAL_ADC_Stop(&hadc2); if (val < 100 || val > 65000) return false; */ return true; 800788c: 2301 movs r3, #1 } 800788e: 4618 mov r0, r3 8007890: bd80 pop {r7, pc} 8007892: bf00 nop 8007894: 2000040c .word 0x2000040c 8007898: 20000dde .word 0x20000dde 800789c: 2000043c .word 0x2000043c 80078a0: 20000de0 .word 0x20000de0 080078a4 <sensorChipInit>: void sensorChipInit() { 80078a4: b580 push {r7, lr} 80078a6: af00 add r7, sp, #0 HAL_ADC_Start(&hadc1); 80078a8: 480c ldr r0, [pc, #48] ; (80078dc <sensorChipInit+0x38>) 80078aa: f7fb fa61 bl 8002d70 <HAL_ADC_Start> HAL_Delay(20); 80078ae: 2014 movs r0, #20 80078b0: f7fb f962 bl 8002b78 <HAL_Delay> HAL_ADC_PollForConversion(&hadc1, 300); 80078b4: f44f 7196 mov.w r1, #300 ; 0x12c 80078b8: 4808 ldr r0, [pc, #32] ; (80078dc <sensorChipInit+0x38>) 80078ba: f7fb fb33 bl 8002f24 <HAL_ADC_PollForConversion> HAL_ADC_Start(&hadc2); 80078be: 4808 ldr r0, [pc, #32] ; (80078e0 <sensorChipInit+0x3c>) 80078c0: f7fb fa56 bl 8002d70 <HAL_ADC_Start> HAL_Delay(20); 80078c4: 2014 movs r0, #20 80078c6: f7fb f957 bl 8002b78 <HAL_Delay> HAL_ADC_PollForConversion(&hadc2, 300); 80078ca: f44f 7196 mov.w r1, #300 ; 0x12c 80078ce: 4804 ldr r0, [pc, #16] ; (80078e0 <sensorChipInit+0x3c>) 80078d0: f7fb fb28 bl 8002f24 <HAL_ADC_PollForConversion> TM_init(); 80078d4: f7f9 fd2a bl 800132c <TM_init> return; 80078d8: bf00 nop } 80078da: bd80 pop {r7, pc} 80078dc: 2000040c .word 0x2000040c 80078e0: 2000043c .word 0x2000043c 080078e4 <resetSensorChip>: void resetSensorChip() { 80078e4: b580 push {r7, lr} 80078e6: af00 add r7, sp, #0 TM_init(); 80078e8: f7f9 fd20 bl 800132c <TM_init> return; 80078ec: bf00 nop } 80078ee: bd80 pop {r7, pc} 080078f0 <stopSensorChip>: void stopSensorChip() { 80078f0: b480 push {r7} 80078f2: af00 add r7, sp, #0 return; 80078f4: bf00 nop } 80078f6: 46bd mov sp, r7 80078f8: bc80 pop {r7} 80078fa: 4770 bx lr 080078fc <enableSensorChip>: void enableSensorChip() { 80078fc: b480 push {r7} 80078fe: af00 add r7, sp, #0 return; 8007900: bf00 nop } 8007902: 46bd mov sp, r7 8007904: bc80 pop {r7} 8007906: 4770 bx lr 08007908 <resetSensor>: /* Выполняет сброс датчика */ void resetSensor() { 8007908: b580 push {r7, lr} 800790a: af00 add r7, sp, #0 stopMeasurement(); 800790c: f000 f826 bl 800795c <stopMeasurement> // сброс cостояния протокола resetFSMProtocol(); 8007910: f7ff ff60 bl 80077d4 <resetFSMProtocol> // сброс переменных page_pos_ptr = 0; 8007914: 4b09 ldr r3, [pc, #36] ; (800793c <resetSensor+0x34>) 8007916: 2200 movs r2, #0 8007918: 701a strb r2, [r3, #0] page_ptr = 0; 800791a: 4b09 ldr r3, [pc, #36] ; (8007940 <resetSensor+0x38>) 800791c: 2200 movs r2, #0 800791e: 801a strh r2, [r3, #0] // сброс микросхемы датчика resetSensorChip(); 8007920: f7ff ffe0 bl 80078e4 <resetSensorChip> // очистка флеш-памяти HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET); 8007924: 2201 movs r2, #1 8007926: 2104 movs r1, #4 8007928: 4806 ldr r0, [pc, #24] ; (8007944 <resetSensor+0x3c>) 800792a: f7fc fa48 bl 8003dbe <HAL_GPIO_WritePin> W25_Erase_Chip(); 800792e: f7fa fdd3 bl 80024d8 <W25_Erase_Chip> reset_ready = true; 8007932: 4b05 ldr r3, [pc, #20] ; (8007948 <resetSensor+0x40>) 8007934: 2201 movs r2, #1 8007936: 701a strb r2, [r3, #0] return; 8007938: bf00 nop } 800793a: bd80 pop {r7, pc} 800793c: 2000073e .word 0x2000073e 8007940: 2000073c .word 0x2000073c 8007944: 40010800 .word 0x40010800 8007948: 20000ddd .word 0x20000ddd 0800794c <startMeasurement>: /* Запуск измерения */ void startMeasurement() { 800794c: b580 push {r7, lr} 800794e: af00 add r7, sp, #0 TM_start(); 8007950: f7f9 fd12 bl 8001378 <TM_start> enableSensorChip(); 8007954: f7ff ffd2 bl 80078fc <enableSensorChip> return; 8007958: bf00 nop } 800795a: bd80 pop {r7, pc} 0800795c <stopMeasurement>: /* Остановка измерения */ void stopMeasurement() { 800795c: b580 push {r7, lr} 800795e: af00 add r7, sp, #0 TM_stop(); 8007960: f7f9 fd1e bl 80013a0 <TM_stop> stopSensorChip(); 8007964: f7ff ffc4 bl 80078f0 <stopSensorChip> return; 8007968: bf00 nop } 800796a: bd80 pop {r7, pc} 0800796c <__errno>: 800796c: 4b01 ldr r3, [pc, #4] ; (8007974 <__errno+0x8>) 800796e: 6818 ldr r0, [r3, #0] 8007970: 4770 bx lr 8007972: bf00 nop 8007974: 2000001c .word 0x2000001c 08007978 <__libc_init_array>: 8007978: b570 push {r4, r5, r6, lr} 800797a: 2600 movs r6, #0 800797c: 4d0c ldr r5, [pc, #48] ; (80079b0 <__libc_init_array+0x38>) 800797e: 4c0d ldr r4, [pc, #52] ; (80079b4 <__libc_init_array+0x3c>) 8007980: 1b64 subs r4, r4, r5 8007982: 10a4 asrs r4, r4, #2 8007984: 42a6 cmp r6, r4 8007986: d109 bne.n 800799c <__libc_init_array+0x24> 8007988: f000 fc9c bl 80082c4 <_init> 800798c: 2600 movs r6, #0 800798e: 4d0a ldr r5, [pc, #40] ; (80079b8 <__libc_init_array+0x40>) 8007990: 4c0a ldr r4, [pc, #40] ; (80079bc <__libc_init_array+0x44>) 8007992: 1b64 subs r4, r4, r5 8007994: 10a4 asrs r4, r4, #2 8007996: 42a6 cmp r6, r4 8007998: d105 bne.n 80079a6 <__libc_init_array+0x2e> 800799a: bd70 pop {r4, r5, r6, pc} 800799c: f855 3b04 ldr.w r3, [r5], #4 80079a0: 4798 blx r3 80079a2: 3601 adds r6, #1 80079a4: e7ee b.n 8007984 <__libc_init_array+0xc> 80079a6: f855 3b04 ldr.w r3, [r5], #4 80079aa: 4798 blx r3 80079ac: 3601 adds r6, #1 80079ae: e7f2 b.n 8007996 <__libc_init_array+0x1e> 80079b0: 08008a8c .word 0x08008a8c 80079b4: 08008a8c .word 0x08008a8c 80079b8: 08008a8c .word 0x08008a8c 80079bc: 08008a90 .word 0x08008a90 080079c0 <memcpy>: 80079c0: 440a add r2, r1 80079c2: 4291 cmp r1, r2 80079c4: f100 33ff add.w r3, r0, #4294967295 80079c8: d100 bne.n 80079cc <memcpy+0xc> 80079ca: 4770 bx lr 80079cc: b510 push {r4, lr} 80079ce: f811 4b01 ldrb.w r4, [r1], #1 80079d2: 4291 cmp r1, r2 80079d4: f803 4f01 strb.w r4, [r3, #1]! 80079d8: d1f9 bne.n 80079ce <memcpy+0xe> 80079da: bd10 pop {r4, pc} 080079dc <memset>: 80079dc: 4603 mov r3, r0 80079de: 4402 add r2, r0 80079e0: 4293 cmp r3, r2 80079e2: d100 bne.n 80079e6 <memset+0xa> 80079e4: 4770 bx lr 80079e6: f803 1b01 strb.w r1, [r3], #1 80079ea: e7f9 b.n 80079e0 <memset+0x4> 080079ec <siprintf>: 80079ec: b40e push {r1, r2, r3} 80079ee: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 80079f2: b500 push {lr} 80079f4: b09c sub sp, #112 ; 0x70 80079f6: ab1d add r3, sp, #116 ; 0x74 80079f8: 9002 str r0, [sp, #8] 80079fa: 9006 str r0, [sp, #24] 80079fc: 9107 str r1, [sp, #28] 80079fe: 9104 str r1, [sp, #16] 8007a00: 4808 ldr r0, [pc, #32] ; (8007a24 <siprintf+0x38>) 8007a02: 4909 ldr r1, [pc, #36] ; (8007a28 <siprintf+0x3c>) 8007a04: f853 2b04 ldr.w r2, [r3], #4 8007a08: 9105 str r1, [sp, #20] 8007a0a: 6800 ldr r0, [r0, #0] 8007a0c: a902 add r1, sp, #8 8007a0e: 9301 str r3, [sp, #4] 8007a10: f000 f868 bl 8007ae4 <_svfiprintf_r> 8007a14: 2200 movs r2, #0 8007a16: 9b02 ldr r3, [sp, #8] 8007a18: 701a strb r2, [r3, #0] 8007a1a: b01c add sp, #112 ; 0x70 8007a1c: f85d eb04 ldr.w lr, [sp], #4 8007a20: b003 add sp, #12 8007a22: 4770 bx lr 8007a24: 2000001c .word 0x2000001c 8007a28: ffff0208 .word 0xffff0208 08007a2c <__ssputs_r>: 8007a2c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8007a30: 688e ldr r6, [r1, #8] 8007a32: 4682 mov sl, r0 8007a34: 429e cmp r6, r3 8007a36: 460c mov r4, r1 8007a38: 4690 mov r8, r2 8007a3a: 461f mov r7, r3 8007a3c: d838 bhi.n 8007ab0 <__ssputs_r+0x84> 8007a3e: 898a ldrh r2, [r1, #12] 8007a40: f412 6f90 tst.w r2, #1152 ; 0x480 8007a44: d032 beq.n 8007aac <__ssputs_r+0x80> 8007a46: 6825 ldr r5, [r4, #0] 8007a48: 6909 ldr r1, [r1, #16] 8007a4a: 3301 adds r3, #1 8007a4c: eba5 0901 sub.w r9, r5, r1 8007a50: 6965 ldr r5, [r4, #20] 8007a52: 444b add r3, r9 8007a54: eb05 0545 add.w r5, r5, r5, lsl #1 8007a58: eb05 75d5 add.w r5, r5, r5, lsr #31 8007a5c: 106d asrs r5, r5, #1 8007a5e: 429d cmp r5, r3 8007a60: bf38 it cc 8007a62: 461d movcc r5, r3 8007a64: 0553 lsls r3, r2, #21 8007a66: d531 bpl.n 8007acc <__ssputs_r+0xa0> 8007a68: 4629 mov r1, r5 8007a6a: f000 fb61 bl 8008130 <_malloc_r> 8007a6e: 4606 mov r6, r0 8007a70: b950 cbnz r0, 8007a88 <__ssputs_r+0x5c> 8007a72: 230c movs r3, #12 8007a74: f04f 30ff mov.w r0, #4294967295 8007a78: f8ca 3000 str.w r3, [sl] 8007a7c: 89a3 ldrh r3, [r4, #12] 8007a7e: f043 0340 orr.w r3, r3, #64 ; 0x40 8007a82: 81a3 strh r3, [r4, #12] 8007a84: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8007a88: 464a mov r2, r9 8007a8a: 6921 ldr r1, [r4, #16] 8007a8c: f7ff ff98 bl 80079c0 <memcpy> 8007a90: 89a3 ldrh r3, [r4, #12] 8007a92: f423 6390 bic.w r3, r3, #1152 ; 0x480 8007a96: f043 0380 orr.w r3, r3, #128 ; 0x80 8007a9a: 81a3 strh r3, [r4, #12] 8007a9c: 6126 str r6, [r4, #16] 8007a9e: 444e add r6, r9 8007aa0: 6026 str r6, [r4, #0] 8007aa2: 463e mov r6, r7 8007aa4: 6165 str r5, [r4, #20] 8007aa6: eba5 0509 sub.w r5, r5, r9 8007aaa: 60a5 str r5, [r4, #8] 8007aac: 42be cmp r6, r7 8007aae: d900 bls.n 8007ab2 <__ssputs_r+0x86> 8007ab0: 463e mov r6, r7 8007ab2: 4632 mov r2, r6 8007ab4: 4641 mov r1, r8 8007ab6: 6820 ldr r0, [r4, #0] 8007ab8: f000 fab8 bl 800802c <memmove> 8007abc: 68a3 ldr r3, [r4, #8] 8007abe: 2000 movs r0, #0 8007ac0: 1b9b subs r3, r3, r6 8007ac2: 60a3 str r3, [r4, #8] 8007ac4: 6823 ldr r3, [r4, #0] 8007ac6: 4433 add r3, r6 8007ac8: 6023 str r3, [r4, #0] 8007aca: e7db b.n 8007a84 <__ssputs_r+0x58> 8007acc: 462a mov r2, r5 8007ace: f000 fba3 bl 8008218 <_realloc_r> 8007ad2: 4606 mov r6, r0 8007ad4: 2800 cmp r0, #0 8007ad6: d1e1 bne.n 8007a9c <__ssputs_r+0x70> 8007ad8: 4650 mov r0, sl 8007ada: 6921 ldr r1, [r4, #16] 8007adc: f000 fac0 bl 8008060 <_free_r> 8007ae0: e7c7 b.n 8007a72 <__ssputs_r+0x46> ... 08007ae4 <_svfiprintf_r>: 8007ae4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007ae8: 4698 mov r8, r3 8007aea: 898b ldrh r3, [r1, #12] 8007aec: 4607 mov r7, r0 8007aee: 061b lsls r3, r3, #24 8007af0: 460d mov r5, r1 8007af2: 4614 mov r4, r2 8007af4: b09d sub sp, #116 ; 0x74 8007af6: d50e bpl.n 8007b16 <_svfiprintf_r+0x32> 8007af8: 690b ldr r3, [r1, #16] 8007afa: b963 cbnz r3, 8007b16 <_svfiprintf_r+0x32> 8007afc: 2140 movs r1, #64 ; 0x40 8007afe: f000 fb17 bl 8008130 <_malloc_r> 8007b02: 6028 str r0, [r5, #0] 8007b04: 6128 str r0, [r5, #16] 8007b06: b920 cbnz r0, 8007b12 <_svfiprintf_r+0x2e> 8007b08: 230c movs r3, #12 8007b0a: 603b str r3, [r7, #0] 8007b0c: f04f 30ff mov.w r0, #4294967295 8007b10: e0d1 b.n 8007cb6 <_svfiprintf_r+0x1d2> 8007b12: 2340 movs r3, #64 ; 0x40 8007b14: 616b str r3, [r5, #20] 8007b16: 2300 movs r3, #0 8007b18: 9309 str r3, [sp, #36] ; 0x24 8007b1a: 2320 movs r3, #32 8007b1c: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8007b20: 2330 movs r3, #48 ; 0x30 8007b22: f04f 0901 mov.w r9, #1 8007b26: f8cd 800c str.w r8, [sp, #12] 8007b2a: f8df 81a4 ldr.w r8, [pc, #420] ; 8007cd0 <_svfiprintf_r+0x1ec> 8007b2e: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8007b32: 4623 mov r3, r4 8007b34: 469a mov sl, r3 8007b36: f813 2b01 ldrb.w r2, [r3], #1 8007b3a: b10a cbz r2, 8007b40 <_svfiprintf_r+0x5c> 8007b3c: 2a25 cmp r2, #37 ; 0x25 8007b3e: d1f9 bne.n 8007b34 <_svfiprintf_r+0x50> 8007b40: ebba 0b04 subs.w fp, sl, r4 8007b44: d00b beq.n 8007b5e <_svfiprintf_r+0x7a> 8007b46: 465b mov r3, fp 8007b48: 4622 mov r2, r4 8007b4a: 4629 mov r1, r5 8007b4c: 4638 mov r0, r7 8007b4e: f7ff ff6d bl 8007a2c <__ssputs_r> 8007b52: 3001 adds r0, #1 8007b54: f000 80aa beq.w 8007cac <_svfiprintf_r+0x1c8> 8007b58: 9a09 ldr r2, [sp, #36] ; 0x24 8007b5a: 445a add r2, fp 8007b5c: 9209 str r2, [sp, #36] ; 0x24 8007b5e: f89a 3000 ldrb.w r3, [sl] 8007b62: 2b00 cmp r3, #0 8007b64: f000 80a2 beq.w 8007cac <_svfiprintf_r+0x1c8> 8007b68: 2300 movs r3, #0 8007b6a: f04f 32ff mov.w r2, #4294967295 8007b6e: e9cd 2305 strd r2, r3, [sp, #20] 8007b72: f10a 0a01 add.w sl, sl, #1 8007b76: 9304 str r3, [sp, #16] 8007b78: 9307 str r3, [sp, #28] 8007b7a: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8007b7e: 931a str r3, [sp, #104] ; 0x68 8007b80: 4654 mov r4, sl 8007b82: 2205 movs r2, #5 8007b84: f814 1b01 ldrb.w r1, [r4], #1 8007b88: 4851 ldr r0, [pc, #324] ; (8007cd0 <_svfiprintf_r+0x1ec>) 8007b8a: f000 fa41 bl 8008010 <memchr> 8007b8e: 9a04 ldr r2, [sp, #16] 8007b90: b9d8 cbnz r0, 8007bca <_svfiprintf_r+0xe6> 8007b92: 06d0 lsls r0, r2, #27 8007b94: bf44 itt mi 8007b96: 2320 movmi r3, #32 8007b98: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8007b9c: 0711 lsls r1, r2, #28 8007b9e: bf44 itt mi 8007ba0: 232b movmi r3, #43 ; 0x2b 8007ba2: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8007ba6: f89a 3000 ldrb.w r3, [sl] 8007baa: 2b2a cmp r3, #42 ; 0x2a 8007bac: d015 beq.n 8007bda <_svfiprintf_r+0xf6> 8007bae: 4654 mov r4, sl 8007bb0: 2000 movs r0, #0 8007bb2: f04f 0c0a mov.w ip, #10 8007bb6: 9a07 ldr r2, [sp, #28] 8007bb8: 4621 mov r1, r4 8007bba: f811 3b01 ldrb.w r3, [r1], #1 8007bbe: 3b30 subs r3, #48 ; 0x30 8007bc0: 2b09 cmp r3, #9 8007bc2: d94e bls.n 8007c62 <_svfiprintf_r+0x17e> 8007bc4: b1b0 cbz r0, 8007bf4 <_svfiprintf_r+0x110> 8007bc6: 9207 str r2, [sp, #28] 8007bc8: e014 b.n 8007bf4 <_svfiprintf_r+0x110> 8007bca: eba0 0308 sub.w r3, r0, r8 8007bce: fa09 f303 lsl.w r3, r9, r3 8007bd2: 4313 orrs r3, r2 8007bd4: 46a2 mov sl, r4 8007bd6: 9304 str r3, [sp, #16] 8007bd8: e7d2 b.n 8007b80 <_svfiprintf_r+0x9c> 8007bda: 9b03 ldr r3, [sp, #12] 8007bdc: 1d19 adds r1, r3, #4 8007bde: 681b ldr r3, [r3, #0] 8007be0: 9103 str r1, [sp, #12] 8007be2: 2b00 cmp r3, #0 8007be4: bfbb ittet lt 8007be6: 425b neglt r3, r3 8007be8: f042 0202 orrlt.w r2, r2, #2 8007bec: 9307 strge r3, [sp, #28] 8007bee: 9307 strlt r3, [sp, #28] 8007bf0: bfb8 it lt 8007bf2: 9204 strlt r2, [sp, #16] 8007bf4: 7823 ldrb r3, [r4, #0] 8007bf6: 2b2e cmp r3, #46 ; 0x2e 8007bf8: d10c bne.n 8007c14 <_svfiprintf_r+0x130> 8007bfa: 7863 ldrb r3, [r4, #1] 8007bfc: 2b2a cmp r3, #42 ; 0x2a 8007bfe: d135 bne.n 8007c6c <_svfiprintf_r+0x188> 8007c00: 9b03 ldr r3, [sp, #12] 8007c02: 3402 adds r4, #2 8007c04: 1d1a adds r2, r3, #4 8007c06: 681b ldr r3, [r3, #0] 8007c08: 9203 str r2, [sp, #12] 8007c0a: 2b00 cmp r3, #0 8007c0c: bfb8 it lt 8007c0e: f04f 33ff movlt.w r3, #4294967295 8007c12: 9305 str r3, [sp, #20] 8007c14: f8df a0bc ldr.w sl, [pc, #188] ; 8007cd4 <_svfiprintf_r+0x1f0> 8007c18: 2203 movs r2, #3 8007c1a: 4650 mov r0, sl 8007c1c: 7821 ldrb r1, [r4, #0] 8007c1e: f000 f9f7 bl 8008010 <memchr> 8007c22: b140 cbz r0, 8007c36 <_svfiprintf_r+0x152> 8007c24: 2340 movs r3, #64 ; 0x40 8007c26: eba0 000a sub.w r0, r0, sl 8007c2a: fa03 f000 lsl.w r0, r3, r0 8007c2e: 9b04 ldr r3, [sp, #16] 8007c30: 3401 adds r4, #1 8007c32: 4303 orrs r3, r0 8007c34: 9304 str r3, [sp, #16] 8007c36: f814 1b01 ldrb.w r1, [r4], #1 8007c3a: 2206 movs r2, #6 8007c3c: 4826 ldr r0, [pc, #152] ; (8007cd8 <_svfiprintf_r+0x1f4>) 8007c3e: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8007c42: f000 f9e5 bl 8008010 <memchr> 8007c46: 2800 cmp r0, #0 8007c48: d038 beq.n 8007cbc <_svfiprintf_r+0x1d8> 8007c4a: 4b24 ldr r3, [pc, #144] ; (8007cdc <_svfiprintf_r+0x1f8>) 8007c4c: bb1b cbnz r3, 8007c96 <_svfiprintf_r+0x1b2> 8007c4e: 9b03 ldr r3, [sp, #12] 8007c50: 3307 adds r3, #7 8007c52: f023 0307 bic.w r3, r3, #7 8007c56: 3308 adds r3, #8 8007c58: 9303 str r3, [sp, #12] 8007c5a: 9b09 ldr r3, [sp, #36] ; 0x24 8007c5c: 4433 add r3, r6 8007c5e: 9309 str r3, [sp, #36] ; 0x24 8007c60: e767 b.n 8007b32 <_svfiprintf_r+0x4e> 8007c62: 460c mov r4, r1 8007c64: 2001 movs r0, #1 8007c66: fb0c 3202 mla r2, ip, r2, r3 8007c6a: e7a5 b.n 8007bb8 <_svfiprintf_r+0xd4> 8007c6c: 2300 movs r3, #0 8007c6e: f04f 0c0a mov.w ip, #10 8007c72: 4619 mov r1, r3 8007c74: 3401 adds r4, #1 8007c76: 9305 str r3, [sp, #20] 8007c78: 4620 mov r0, r4 8007c7a: f810 2b01 ldrb.w r2, [r0], #1 8007c7e: 3a30 subs r2, #48 ; 0x30 8007c80: 2a09 cmp r2, #9 8007c82: d903 bls.n 8007c8c <_svfiprintf_r+0x1a8> 8007c84: 2b00 cmp r3, #0 8007c86: d0c5 beq.n 8007c14 <_svfiprintf_r+0x130> 8007c88: 9105 str r1, [sp, #20] 8007c8a: e7c3 b.n 8007c14 <_svfiprintf_r+0x130> 8007c8c: 4604 mov r4, r0 8007c8e: 2301 movs r3, #1 8007c90: fb0c 2101 mla r1, ip, r1, r2 8007c94: e7f0 b.n 8007c78 <_svfiprintf_r+0x194> 8007c96: ab03 add r3, sp, #12 8007c98: 9300 str r3, [sp, #0] 8007c9a: 462a mov r2, r5 8007c9c: 4638 mov r0, r7 8007c9e: 4b10 ldr r3, [pc, #64] ; (8007ce0 <_svfiprintf_r+0x1fc>) 8007ca0: a904 add r1, sp, #16 8007ca2: f3af 8000 nop.w 8007ca6: 1c42 adds r2, r0, #1 8007ca8: 4606 mov r6, r0 8007caa: d1d6 bne.n 8007c5a <_svfiprintf_r+0x176> 8007cac: 89ab ldrh r3, [r5, #12] 8007cae: 065b lsls r3, r3, #25 8007cb0: f53f af2c bmi.w 8007b0c <_svfiprintf_r+0x28> 8007cb4: 9809 ldr r0, [sp, #36] ; 0x24 8007cb6: b01d add sp, #116 ; 0x74 8007cb8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8007cbc: ab03 add r3, sp, #12 8007cbe: 9300 str r3, [sp, #0] 8007cc0: 462a mov r2, r5 8007cc2: 4638 mov r0, r7 8007cc4: 4b06 ldr r3, [pc, #24] ; (8007ce0 <_svfiprintf_r+0x1fc>) 8007cc6: a904 add r1, sp, #16 8007cc8: f000 f87c bl 8007dc4 <_printf_i> 8007ccc: e7eb b.n 8007ca6 <_svfiprintf_r+0x1c2> 8007cce: bf00 nop 8007cd0: 08008a58 .word 0x08008a58 8007cd4: 08008a5e .word 0x08008a5e 8007cd8: 08008a62 .word 0x08008a62 8007cdc: 00000000 .word 0x00000000 8007ce0: 08007a2d .word 0x08007a2d 08007ce4 <_printf_common>: 8007ce4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8007ce8: 4616 mov r6, r2 8007cea: 4699 mov r9, r3 8007cec: 688a ldr r2, [r1, #8] 8007cee: 690b ldr r3, [r1, #16] 8007cf0: 4607 mov r7, r0 8007cf2: 4293 cmp r3, r2 8007cf4: bfb8 it lt 8007cf6: 4613 movlt r3, r2 8007cf8: 6033 str r3, [r6, #0] 8007cfa: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8007cfe: 460c mov r4, r1 8007d00: f8dd 8020 ldr.w r8, [sp, #32] 8007d04: b10a cbz r2, 8007d0a <_printf_common+0x26> 8007d06: 3301 adds r3, #1 8007d08: 6033 str r3, [r6, #0] 8007d0a: 6823 ldr r3, [r4, #0] 8007d0c: 0699 lsls r1, r3, #26 8007d0e: bf42 ittt mi 8007d10: 6833 ldrmi r3, [r6, #0] 8007d12: 3302 addmi r3, #2 8007d14: 6033 strmi r3, [r6, #0] 8007d16: 6825 ldr r5, [r4, #0] 8007d18: f015 0506 ands.w r5, r5, #6 8007d1c: d106 bne.n 8007d2c <_printf_common+0x48> 8007d1e: f104 0a19 add.w sl, r4, #25 8007d22: 68e3 ldr r3, [r4, #12] 8007d24: 6832 ldr r2, [r6, #0] 8007d26: 1a9b subs r3, r3, r2 8007d28: 42ab cmp r3, r5 8007d2a: dc28 bgt.n 8007d7e <_printf_common+0x9a> 8007d2c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8007d30: 1e13 subs r3, r2, #0 8007d32: 6822 ldr r2, [r4, #0] 8007d34: bf18 it ne 8007d36: 2301 movne r3, #1 8007d38: 0692 lsls r2, r2, #26 8007d3a: d42d bmi.n 8007d98 <_printf_common+0xb4> 8007d3c: 4649 mov r1, r9 8007d3e: 4638 mov r0, r7 8007d40: f104 0243 add.w r2, r4, #67 ; 0x43 8007d44: 47c0 blx r8 8007d46: 3001 adds r0, #1 8007d48: d020 beq.n 8007d8c <_printf_common+0xa8> 8007d4a: 6823 ldr r3, [r4, #0] 8007d4c: 68e5 ldr r5, [r4, #12] 8007d4e: f003 0306 and.w r3, r3, #6 8007d52: 2b04 cmp r3, #4 8007d54: bf18 it ne 8007d56: 2500 movne r5, #0 8007d58: 6832 ldr r2, [r6, #0] 8007d5a: f04f 0600 mov.w r6, #0 8007d5e: 68a3 ldr r3, [r4, #8] 8007d60: bf08 it eq 8007d62: 1aad subeq r5, r5, r2 8007d64: 6922 ldr r2, [r4, #16] 8007d66: bf08 it eq 8007d68: ea25 75e5 biceq.w r5, r5, r5, asr #31 8007d6c: 4293 cmp r3, r2 8007d6e: bfc4 itt gt 8007d70: 1a9b subgt r3, r3, r2 8007d72: 18ed addgt r5, r5, r3 8007d74: 341a adds r4, #26 8007d76: 42b5 cmp r5, r6 8007d78: d11a bne.n 8007db0 <_printf_common+0xcc> 8007d7a: 2000 movs r0, #0 8007d7c: e008 b.n 8007d90 <_printf_common+0xac> 8007d7e: 2301 movs r3, #1 8007d80: 4652 mov r2, sl 8007d82: 4649 mov r1, r9 8007d84: 4638 mov r0, r7 8007d86: 47c0 blx r8 8007d88: 3001 adds r0, #1 8007d8a: d103 bne.n 8007d94 <_printf_common+0xb0> 8007d8c: f04f 30ff mov.w r0, #4294967295 8007d90: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8007d94: 3501 adds r5, #1 8007d96: e7c4 b.n 8007d22 <_printf_common+0x3e> 8007d98: 2030 movs r0, #48 ; 0x30 8007d9a: 18e1 adds r1, r4, r3 8007d9c: f881 0043 strb.w r0, [r1, #67] ; 0x43 8007da0: 1c5a adds r2, r3, #1 8007da2: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8007da6: 4422 add r2, r4 8007da8: 3302 adds r3, #2 8007daa: f882 1043 strb.w r1, [r2, #67] ; 0x43 8007dae: e7c5 b.n 8007d3c <_printf_common+0x58> 8007db0: 2301 movs r3, #1 8007db2: 4622 mov r2, r4 8007db4: 4649 mov r1, r9 8007db6: 4638 mov r0, r7 8007db8: 47c0 blx r8 8007dba: 3001 adds r0, #1 8007dbc: d0e6 beq.n 8007d8c <_printf_common+0xa8> 8007dbe: 3601 adds r6, #1 8007dc0: e7d9 b.n 8007d76 <_printf_common+0x92> ... 08007dc4 <_printf_i>: 8007dc4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8007dc8: 7e0f ldrb r7, [r1, #24] 8007dca: 4691 mov r9, r2 8007dcc: 2f78 cmp r7, #120 ; 0x78 8007dce: 4680 mov r8, r0 8007dd0: 460c mov r4, r1 8007dd2: 469a mov sl, r3 8007dd4: 9d0c ldr r5, [sp, #48] ; 0x30 8007dd6: f101 0243 add.w r2, r1, #67 ; 0x43 8007dda: d807 bhi.n 8007dec <_printf_i+0x28> 8007ddc: 2f62 cmp r7, #98 ; 0x62 8007dde: d80a bhi.n 8007df6 <_printf_i+0x32> 8007de0: 2f00 cmp r7, #0 8007de2: f000 80d9 beq.w 8007f98 <_printf_i+0x1d4> 8007de6: 2f58 cmp r7, #88 ; 0x58 8007de8: f000 80a4 beq.w 8007f34 <_printf_i+0x170> 8007dec: f104 0542 add.w r5, r4, #66 ; 0x42 8007df0: f884 7042 strb.w r7, [r4, #66] ; 0x42 8007df4: e03a b.n 8007e6c <_printf_i+0xa8> 8007df6: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8007dfa: 2b15 cmp r3, #21 8007dfc: d8f6 bhi.n 8007dec <_printf_i+0x28> 8007dfe: a101 add r1, pc, #4 ; (adr r1, 8007e04 <_printf_i+0x40>) 8007e00: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8007e04: 08007e5d .word 0x08007e5d 8007e08: 08007e71 .word 0x08007e71 8007e0c: 08007ded .word 0x08007ded 8007e10: 08007ded .word 0x08007ded 8007e14: 08007ded .word 0x08007ded 8007e18: 08007ded .word 0x08007ded 8007e1c: 08007e71 .word 0x08007e71 8007e20: 08007ded .word 0x08007ded 8007e24: 08007ded .word 0x08007ded 8007e28: 08007ded .word 0x08007ded 8007e2c: 08007ded .word 0x08007ded 8007e30: 08007f7f .word 0x08007f7f 8007e34: 08007ea1 .word 0x08007ea1 8007e38: 08007f61 .word 0x08007f61 8007e3c: 08007ded .word 0x08007ded 8007e40: 08007ded .word 0x08007ded 8007e44: 08007fa1 .word 0x08007fa1 8007e48: 08007ded .word 0x08007ded 8007e4c: 08007ea1 .word 0x08007ea1 8007e50: 08007ded .word 0x08007ded 8007e54: 08007ded .word 0x08007ded 8007e58: 08007f69 .word 0x08007f69 8007e5c: 682b ldr r3, [r5, #0] 8007e5e: 1d1a adds r2, r3, #4 8007e60: 681b ldr r3, [r3, #0] 8007e62: 602a str r2, [r5, #0] 8007e64: f104 0542 add.w r5, r4, #66 ; 0x42 8007e68: f884 3042 strb.w r3, [r4, #66] ; 0x42 8007e6c: 2301 movs r3, #1 8007e6e: e0a4 b.n 8007fba <_printf_i+0x1f6> 8007e70: 6820 ldr r0, [r4, #0] 8007e72: 6829 ldr r1, [r5, #0] 8007e74: 0606 lsls r6, r0, #24 8007e76: f101 0304 add.w r3, r1, #4 8007e7a: d50a bpl.n 8007e92 <_printf_i+0xce> 8007e7c: 680e ldr r6, [r1, #0] 8007e7e: 602b str r3, [r5, #0] 8007e80: 2e00 cmp r6, #0 8007e82: da03 bge.n 8007e8c <_printf_i+0xc8> 8007e84: 232d movs r3, #45 ; 0x2d 8007e86: 4276 negs r6, r6 8007e88: f884 3043 strb.w r3, [r4, #67] ; 0x43 8007e8c: 230a movs r3, #10 8007e8e: 485e ldr r0, [pc, #376] ; (8008008 <_printf_i+0x244>) 8007e90: e019 b.n 8007ec6 <_printf_i+0x102> 8007e92: 680e ldr r6, [r1, #0] 8007e94: f010 0f40 tst.w r0, #64 ; 0x40 8007e98: 602b str r3, [r5, #0] 8007e9a: bf18 it ne 8007e9c: b236 sxthne r6, r6 8007e9e: e7ef b.n 8007e80 <_printf_i+0xbc> 8007ea0: 682b ldr r3, [r5, #0] 8007ea2: 6820 ldr r0, [r4, #0] 8007ea4: 1d19 adds r1, r3, #4 8007ea6: 6029 str r1, [r5, #0] 8007ea8: 0601 lsls r1, r0, #24 8007eaa: d501 bpl.n 8007eb0 <_printf_i+0xec> 8007eac: 681e ldr r6, [r3, #0] 8007eae: e002 b.n 8007eb6 <_printf_i+0xf2> 8007eb0: 0646 lsls r6, r0, #25 8007eb2: d5fb bpl.n 8007eac <_printf_i+0xe8> 8007eb4: 881e ldrh r6, [r3, #0] 8007eb6: 2f6f cmp r7, #111 ; 0x6f 8007eb8: bf0c ite eq 8007eba: 2308 moveq r3, #8 8007ebc: 230a movne r3, #10 8007ebe: 4852 ldr r0, [pc, #328] ; (8008008 <_printf_i+0x244>) 8007ec0: 2100 movs r1, #0 8007ec2: f884 1043 strb.w r1, [r4, #67] ; 0x43 8007ec6: 6865 ldr r5, [r4, #4] 8007ec8: 2d00 cmp r5, #0 8007eca: bfa8 it ge 8007ecc: 6821 ldrge r1, [r4, #0] 8007ece: 60a5 str r5, [r4, #8] 8007ed0: bfa4 itt ge 8007ed2: f021 0104 bicge.w r1, r1, #4 8007ed6: 6021 strge r1, [r4, #0] 8007ed8: b90e cbnz r6, 8007ede <_printf_i+0x11a> 8007eda: 2d00 cmp r5, #0 8007edc: d04d beq.n 8007f7a <_printf_i+0x1b6> 8007ede: 4615 mov r5, r2 8007ee0: fbb6 f1f3 udiv r1, r6, r3 8007ee4: fb03 6711 mls r7, r3, r1, r6 8007ee8: 5dc7 ldrb r7, [r0, r7] 8007eea: f805 7d01 strb.w r7, [r5, #-1]! 8007eee: 4637 mov r7, r6 8007ef0: 42bb cmp r3, r7 8007ef2: 460e mov r6, r1 8007ef4: d9f4 bls.n 8007ee0 <_printf_i+0x11c> 8007ef6: 2b08 cmp r3, #8 8007ef8: d10b bne.n 8007f12 <_printf_i+0x14e> 8007efa: 6823 ldr r3, [r4, #0] 8007efc: 07de lsls r6, r3, #31 8007efe: d508 bpl.n 8007f12 <_printf_i+0x14e> 8007f00: 6923 ldr r3, [r4, #16] 8007f02: 6861 ldr r1, [r4, #4] 8007f04: 4299 cmp r1, r3 8007f06: bfde ittt le 8007f08: 2330 movle r3, #48 ; 0x30 8007f0a: f805 3c01 strble.w r3, [r5, #-1] 8007f0e: f105 35ff addle.w r5, r5, #4294967295 8007f12: 1b52 subs r2, r2, r5 8007f14: 6122 str r2, [r4, #16] 8007f16: 464b mov r3, r9 8007f18: 4621 mov r1, r4 8007f1a: 4640 mov r0, r8 8007f1c: f8cd a000 str.w sl, [sp] 8007f20: aa03 add r2, sp, #12 8007f22: f7ff fedf bl 8007ce4 <_printf_common> 8007f26: 3001 adds r0, #1 8007f28: d14c bne.n 8007fc4 <_printf_i+0x200> 8007f2a: f04f 30ff mov.w r0, #4294967295 8007f2e: b004 add sp, #16 8007f30: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8007f34: 4834 ldr r0, [pc, #208] ; (8008008 <_printf_i+0x244>) 8007f36: f881 7045 strb.w r7, [r1, #69] ; 0x45 8007f3a: 6829 ldr r1, [r5, #0] 8007f3c: 6823 ldr r3, [r4, #0] 8007f3e: f851 6b04 ldr.w r6, [r1], #4 8007f42: 6029 str r1, [r5, #0] 8007f44: 061d lsls r5, r3, #24 8007f46: d514 bpl.n 8007f72 <_printf_i+0x1ae> 8007f48: 07df lsls r7, r3, #31 8007f4a: bf44 itt mi 8007f4c: f043 0320 orrmi.w r3, r3, #32 8007f50: 6023 strmi r3, [r4, #0] 8007f52: b91e cbnz r6, 8007f5c <_printf_i+0x198> 8007f54: 6823 ldr r3, [r4, #0] 8007f56: f023 0320 bic.w r3, r3, #32 8007f5a: 6023 str r3, [r4, #0] 8007f5c: 2310 movs r3, #16 8007f5e: e7af b.n 8007ec0 <_printf_i+0xfc> 8007f60: 6823 ldr r3, [r4, #0] 8007f62: f043 0320 orr.w r3, r3, #32 8007f66: 6023 str r3, [r4, #0] 8007f68: 2378 movs r3, #120 ; 0x78 8007f6a: 4828 ldr r0, [pc, #160] ; (800800c <_printf_i+0x248>) 8007f6c: f884 3045 strb.w r3, [r4, #69] ; 0x45 8007f70: e7e3 b.n 8007f3a <_printf_i+0x176> 8007f72: 0659 lsls r1, r3, #25 8007f74: bf48 it mi 8007f76: b2b6 uxthmi r6, r6 8007f78: e7e6 b.n 8007f48 <_printf_i+0x184> 8007f7a: 4615 mov r5, r2 8007f7c: e7bb b.n 8007ef6 <_printf_i+0x132> 8007f7e: 682b ldr r3, [r5, #0] 8007f80: 6826 ldr r6, [r4, #0] 8007f82: 1d18 adds r0, r3, #4 8007f84: 6961 ldr r1, [r4, #20] 8007f86: 6028 str r0, [r5, #0] 8007f88: 0635 lsls r5, r6, #24 8007f8a: 681b ldr r3, [r3, #0] 8007f8c: d501 bpl.n 8007f92 <_printf_i+0x1ce> 8007f8e: 6019 str r1, [r3, #0] 8007f90: e002 b.n 8007f98 <_printf_i+0x1d4> 8007f92: 0670 lsls r0, r6, #25 8007f94: d5fb bpl.n 8007f8e <_printf_i+0x1ca> 8007f96: 8019 strh r1, [r3, #0] 8007f98: 2300 movs r3, #0 8007f9a: 4615 mov r5, r2 8007f9c: 6123 str r3, [r4, #16] 8007f9e: e7ba b.n 8007f16 <_printf_i+0x152> 8007fa0: 682b ldr r3, [r5, #0] 8007fa2: 2100 movs r1, #0 8007fa4: 1d1a adds r2, r3, #4 8007fa6: 602a str r2, [r5, #0] 8007fa8: 681d ldr r5, [r3, #0] 8007faa: 6862 ldr r2, [r4, #4] 8007fac: 4628 mov r0, r5 8007fae: f000 f82f bl 8008010 <memchr> 8007fb2: b108 cbz r0, 8007fb8 <_printf_i+0x1f4> 8007fb4: 1b40 subs r0, r0, r5 8007fb6: 6060 str r0, [r4, #4] 8007fb8: 6863 ldr r3, [r4, #4] 8007fba: 6123 str r3, [r4, #16] 8007fbc: 2300 movs r3, #0 8007fbe: f884 3043 strb.w r3, [r4, #67] ; 0x43 8007fc2: e7a8 b.n 8007f16 <_printf_i+0x152> 8007fc4: 462a mov r2, r5 8007fc6: 4649 mov r1, r9 8007fc8: 4640 mov r0, r8 8007fca: 6923 ldr r3, [r4, #16] 8007fcc: 47d0 blx sl 8007fce: 3001 adds r0, #1 8007fd0: d0ab beq.n 8007f2a <_printf_i+0x166> 8007fd2: 6823 ldr r3, [r4, #0] 8007fd4: 079b lsls r3, r3, #30 8007fd6: d413 bmi.n 8008000 <_printf_i+0x23c> 8007fd8: 68e0 ldr r0, [r4, #12] 8007fda: 9b03 ldr r3, [sp, #12] 8007fdc: 4298 cmp r0, r3 8007fde: bfb8 it lt 8007fe0: 4618 movlt r0, r3 8007fe2: e7a4 b.n 8007f2e <_printf_i+0x16a> 8007fe4: 2301 movs r3, #1 8007fe6: 4632 mov r2, r6 8007fe8: 4649 mov r1, r9 8007fea: 4640 mov r0, r8 8007fec: 47d0 blx sl 8007fee: 3001 adds r0, #1 8007ff0: d09b beq.n 8007f2a <_printf_i+0x166> 8007ff2: 3501 adds r5, #1 8007ff4: 68e3 ldr r3, [r4, #12] 8007ff6: 9903 ldr r1, [sp, #12] 8007ff8: 1a5b subs r3, r3, r1 8007ffa: 42ab cmp r3, r5 8007ffc: dcf2 bgt.n 8007fe4 <_printf_i+0x220> 8007ffe: e7eb b.n 8007fd8 <_printf_i+0x214> 8008000: 2500 movs r5, #0 8008002: f104 0619 add.w r6, r4, #25 8008006: e7f5 b.n 8007ff4 <_printf_i+0x230> 8008008: 08008a69 .word 0x08008a69 800800c: 08008a7a .word 0x08008a7a 08008010 <memchr>: 8008010: 4603 mov r3, r0 8008012: b510 push {r4, lr} 8008014: b2c9 uxtb r1, r1 8008016: 4402 add r2, r0 8008018: 4293 cmp r3, r2 800801a: 4618 mov r0, r3 800801c: d101 bne.n 8008022 <memchr+0x12> 800801e: 2000 movs r0, #0 8008020: e003 b.n 800802a <memchr+0x1a> 8008022: 7804 ldrb r4, [r0, #0] 8008024: 3301 adds r3, #1 8008026: 428c cmp r4, r1 8008028: d1f6 bne.n 8008018 <memchr+0x8> 800802a: bd10 pop {r4, pc} 0800802c <memmove>: 800802c: 4288 cmp r0, r1 800802e: b510 push {r4, lr} 8008030: eb01 0402 add.w r4, r1, r2 8008034: d902 bls.n 800803c <memmove+0x10> 8008036: 4284 cmp r4, r0 8008038: 4623 mov r3, r4 800803a: d807 bhi.n 800804c <memmove+0x20> 800803c: 1e43 subs r3, r0, #1 800803e: 42a1 cmp r1, r4 8008040: d008 beq.n 8008054 <memmove+0x28> 8008042: f811 2b01 ldrb.w r2, [r1], #1 8008046: f803 2f01 strb.w r2, [r3, #1]! 800804a: e7f8 b.n 800803e <memmove+0x12> 800804c: 4601 mov r1, r0 800804e: 4402 add r2, r0 8008050: 428a cmp r2, r1 8008052: d100 bne.n 8008056 <memmove+0x2a> 8008054: bd10 pop {r4, pc} 8008056: f813 4d01 ldrb.w r4, [r3, #-1]! 800805a: f802 4d01 strb.w r4, [r2, #-1]! 800805e: e7f7 b.n 8008050 <memmove+0x24> 08008060 <_free_r>: 8008060: b538 push {r3, r4, r5, lr} 8008062: 4605 mov r5, r0 8008064: 2900 cmp r1, #0 8008066: d040 beq.n 80080ea <_free_r+0x8a> 8008068: f851 3c04 ldr.w r3, [r1, #-4] 800806c: 1f0c subs r4, r1, #4 800806e: 2b00 cmp r3, #0 8008070: bfb8 it lt 8008072: 18e4 addlt r4, r4, r3 8008074: f000 f910 bl 8008298 <__malloc_lock> 8008078: 4a1c ldr r2, [pc, #112] ; (80080ec <_free_r+0x8c>) 800807a: 6813 ldr r3, [r2, #0] 800807c: b933 cbnz r3, 800808c <_free_r+0x2c> 800807e: 6063 str r3, [r4, #4] 8008080: 6014 str r4, [r2, #0] 8008082: 4628 mov r0, r5 8008084: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8008088: f000 b90c b.w 80082a4 <__malloc_unlock> 800808c: 42a3 cmp r3, r4 800808e: d908 bls.n 80080a2 <_free_r+0x42> 8008090: 6820 ldr r0, [r4, #0] 8008092: 1821 adds r1, r4, r0 8008094: 428b cmp r3, r1 8008096: bf01 itttt eq 8008098: 6819 ldreq r1, [r3, #0] 800809a: 685b ldreq r3, [r3, #4] 800809c: 1809 addeq r1, r1, r0 800809e: 6021 streq r1, [r4, #0] 80080a0: e7ed b.n 800807e <_free_r+0x1e> 80080a2: 461a mov r2, r3 80080a4: 685b ldr r3, [r3, #4] 80080a6: b10b cbz r3, 80080ac <_free_r+0x4c> 80080a8: 42a3 cmp r3, r4 80080aa: d9fa bls.n 80080a2 <_free_r+0x42> 80080ac: 6811 ldr r1, [r2, #0] 80080ae: 1850 adds r0, r2, r1 80080b0: 42a0 cmp r0, r4 80080b2: d10b bne.n 80080cc <_free_r+0x6c> 80080b4: 6820 ldr r0, [r4, #0] 80080b6: 4401 add r1, r0 80080b8: 1850 adds r0, r2, r1 80080ba: 4283 cmp r3, r0 80080bc: 6011 str r1, [r2, #0] 80080be: d1e0 bne.n 8008082 <_free_r+0x22> 80080c0: 6818 ldr r0, [r3, #0] 80080c2: 685b ldr r3, [r3, #4] 80080c4: 4401 add r1, r0 80080c6: 6011 str r1, [r2, #0] 80080c8: 6053 str r3, [r2, #4] 80080ca: e7da b.n 8008082 <_free_r+0x22> 80080cc: d902 bls.n 80080d4 <_free_r+0x74> 80080ce: 230c movs r3, #12 80080d0: 602b str r3, [r5, #0] 80080d2: e7d6 b.n 8008082 <_free_r+0x22> 80080d4: 6820 ldr r0, [r4, #0] 80080d6: 1821 adds r1, r4, r0 80080d8: 428b cmp r3, r1 80080da: bf01 itttt eq 80080dc: 6819 ldreq r1, [r3, #0] 80080de: 685b ldreq r3, [r3, #4] 80080e0: 1809 addeq r1, r1, r0 80080e2: 6021 streq r1, [r4, #0] 80080e4: 6063 str r3, [r4, #4] 80080e6: 6054 str r4, [r2, #4] 80080e8: e7cb b.n 8008082 <_free_r+0x22> 80080ea: bd38 pop {r3, r4, r5, pc} 80080ec: 20000de4 .word 0x20000de4 080080f0 <sbrk_aligned>: 80080f0: b570 push {r4, r5, r6, lr} 80080f2: 4e0e ldr r6, [pc, #56] ; (800812c <sbrk_aligned+0x3c>) 80080f4: 460c mov r4, r1 80080f6: 6831 ldr r1, [r6, #0] 80080f8: 4605 mov r5, r0 80080fa: b911 cbnz r1, 8008102 <sbrk_aligned+0x12> 80080fc: f000 f8bc bl 8008278 <_sbrk_r> 8008100: 6030 str r0, [r6, #0] 8008102: 4621 mov r1, r4 8008104: 4628 mov r0, r5 8008106: f000 f8b7 bl 8008278 <_sbrk_r> 800810a: 1c43 adds r3, r0, #1 800810c: d00a beq.n 8008124 <sbrk_aligned+0x34> 800810e: 1cc4 adds r4, r0, #3 8008110: f024 0403 bic.w r4, r4, #3 8008114: 42a0 cmp r0, r4 8008116: d007 beq.n 8008128 <sbrk_aligned+0x38> 8008118: 1a21 subs r1, r4, r0 800811a: 4628 mov r0, r5 800811c: f000 f8ac bl 8008278 <_sbrk_r> 8008120: 3001 adds r0, #1 8008122: d101 bne.n 8008128 <sbrk_aligned+0x38> 8008124: f04f 34ff mov.w r4, #4294967295 8008128: 4620 mov r0, r4 800812a: bd70 pop {r4, r5, r6, pc} 800812c: 20000de8 .word 0x20000de8 08008130 <_malloc_r>: 8008130: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8008134: 1ccd adds r5, r1, #3 8008136: f025 0503 bic.w r5, r5, #3 800813a: 3508 adds r5, #8 800813c: 2d0c cmp r5, #12 800813e: bf38 it cc 8008140: 250c movcc r5, #12 8008142: 2d00 cmp r5, #0 8008144: 4607 mov r7, r0 8008146: db01 blt.n 800814c <_malloc_r+0x1c> 8008148: 42a9 cmp r1, r5 800814a: d905 bls.n 8008158 <_malloc_r+0x28> 800814c: 230c movs r3, #12 800814e: 2600 movs r6, #0 8008150: 603b str r3, [r7, #0] 8008152: 4630 mov r0, r6 8008154: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8008158: 4e2e ldr r6, [pc, #184] ; (8008214 <_malloc_r+0xe4>) 800815a: f000 f89d bl 8008298 <__malloc_lock> 800815e: 6833 ldr r3, [r6, #0] 8008160: 461c mov r4, r3 8008162: bb34 cbnz r4, 80081b2 <_malloc_r+0x82> 8008164: 4629 mov r1, r5 8008166: 4638 mov r0, r7 8008168: f7ff ffc2 bl 80080f0 <sbrk_aligned> 800816c: 1c43 adds r3, r0, #1 800816e: 4604 mov r4, r0 8008170: d14d bne.n 800820e <_malloc_r+0xde> 8008172: 6834 ldr r4, [r6, #0] 8008174: 4626 mov r6, r4 8008176: 2e00 cmp r6, #0 8008178: d140 bne.n 80081fc <_malloc_r+0xcc> 800817a: 6823 ldr r3, [r4, #0] 800817c: 4631 mov r1, r6 800817e: 4638 mov r0, r7 8008180: eb04 0803 add.w r8, r4, r3 8008184: f000 f878 bl 8008278 <_sbrk_r> 8008188: 4580 cmp r8, r0 800818a: d13a bne.n 8008202 <_malloc_r+0xd2> 800818c: 6821 ldr r1, [r4, #0] 800818e: 3503 adds r5, #3 8008190: 1a6d subs r5, r5, r1 8008192: f025 0503 bic.w r5, r5, #3 8008196: 3508 adds r5, #8 8008198: 2d0c cmp r5, #12 800819a: bf38 it cc 800819c: 250c movcc r5, #12 800819e: 4638 mov r0, r7 80081a0: 4629 mov r1, r5 80081a2: f7ff ffa5 bl 80080f0 <sbrk_aligned> 80081a6: 3001 adds r0, #1 80081a8: d02b beq.n 8008202 <_malloc_r+0xd2> 80081aa: 6823 ldr r3, [r4, #0] 80081ac: 442b add r3, r5 80081ae: 6023 str r3, [r4, #0] 80081b0: e00e b.n 80081d0 <_malloc_r+0xa0> 80081b2: 6822 ldr r2, [r4, #0] 80081b4: 1b52 subs r2, r2, r5 80081b6: d41e bmi.n 80081f6 <_malloc_r+0xc6> 80081b8: 2a0b cmp r2, #11 80081ba: d916 bls.n 80081ea <_malloc_r+0xba> 80081bc: 1961 adds r1, r4, r5 80081be: 42a3 cmp r3, r4 80081c0: 6025 str r5, [r4, #0] 80081c2: bf18 it ne 80081c4: 6059 strne r1, [r3, #4] 80081c6: 6863 ldr r3, [r4, #4] 80081c8: bf08 it eq 80081ca: 6031 streq r1, [r6, #0] 80081cc: 5162 str r2, [r4, r5] 80081ce: 604b str r3, [r1, #4] 80081d0: 4638 mov r0, r7 80081d2: f104 060b add.w r6, r4, #11 80081d6: f000 f865 bl 80082a4 <__malloc_unlock> 80081da: f026 0607 bic.w r6, r6, #7 80081de: 1d23 adds r3, r4, #4 80081e0: 1af2 subs r2, r6, r3 80081e2: d0b6 beq.n 8008152 <_malloc_r+0x22> 80081e4: 1b9b subs r3, r3, r6 80081e6: 50a3 str r3, [r4, r2] 80081e8: e7b3 b.n 8008152 <_malloc_r+0x22> 80081ea: 6862 ldr r2, [r4, #4] 80081ec: 42a3 cmp r3, r4 80081ee: bf0c ite eq 80081f0: 6032 streq r2, [r6, #0] 80081f2: 605a strne r2, [r3, #4] 80081f4: e7ec b.n 80081d0 <_malloc_r+0xa0> 80081f6: 4623 mov r3, r4 80081f8: 6864 ldr r4, [r4, #4] 80081fa: e7b2 b.n 8008162 <_malloc_r+0x32> 80081fc: 4634 mov r4, r6 80081fe: 6876 ldr r6, [r6, #4] 8008200: e7b9 b.n 8008176 <_malloc_r+0x46> 8008202: 230c movs r3, #12 8008204: 4638 mov r0, r7 8008206: 603b str r3, [r7, #0] 8008208: f000 f84c bl 80082a4 <__malloc_unlock> 800820c: e7a1 b.n 8008152 <_malloc_r+0x22> 800820e: 6025 str r5, [r4, #0] 8008210: e7de b.n 80081d0 <_malloc_r+0xa0> 8008212: bf00 nop 8008214: 20000de4 .word 0x20000de4 08008218 <_realloc_r>: 8008218: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800821c: 4680 mov r8, r0 800821e: 4614 mov r4, r2 8008220: 460e mov r6, r1 8008222: b921 cbnz r1, 800822e <_realloc_r+0x16> 8008224: 4611 mov r1, r2 8008226: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800822a: f7ff bf81 b.w 8008130 <_malloc_r> 800822e: b92a cbnz r2, 800823c <_realloc_r+0x24> 8008230: f7ff ff16 bl 8008060 <_free_r> 8008234: 4625 mov r5, r4 8008236: 4628 mov r0, r5 8008238: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800823c: f000 f838 bl 80082b0 <_malloc_usable_size_r> 8008240: 4284 cmp r4, r0 8008242: 4607 mov r7, r0 8008244: d802 bhi.n 800824c <_realloc_r+0x34> 8008246: ebb4 0f50 cmp.w r4, r0, lsr #1 800824a: d812 bhi.n 8008272 <_realloc_r+0x5a> 800824c: 4621 mov r1, r4 800824e: 4640 mov r0, r8 8008250: f7ff ff6e bl 8008130 <_malloc_r> 8008254: 4605 mov r5, r0 8008256: 2800 cmp r0, #0 8008258: d0ed beq.n 8008236 <_realloc_r+0x1e> 800825a: 42bc cmp r4, r7 800825c: 4622 mov r2, r4 800825e: 4631 mov r1, r6 8008260: bf28 it cs 8008262: 463a movcs r2, r7 8008264: f7ff fbac bl 80079c0 <memcpy> 8008268: 4631 mov r1, r6 800826a: 4640 mov r0, r8 800826c: f7ff fef8 bl 8008060 <_free_r> 8008270: e7e1 b.n 8008236 <_realloc_r+0x1e> 8008272: 4635 mov r5, r6 8008274: e7df b.n 8008236 <_realloc_r+0x1e> ... 08008278 <_sbrk_r>: 8008278: b538 push {r3, r4, r5, lr} 800827a: 2300 movs r3, #0 800827c: 4d05 ldr r5, [pc, #20] ; (8008294 <_sbrk_r+0x1c>) 800827e: 4604 mov r4, r0 8008280: 4608 mov r0, r1 8008282: 602b str r3, [r5, #0] 8008284: f7fa f810 bl 80022a8 <_sbrk> 8008288: 1c43 adds r3, r0, #1 800828a: d102 bne.n 8008292 <_sbrk_r+0x1a> 800828c: 682b ldr r3, [r5, #0] 800828e: b103 cbz r3, 8008292 <_sbrk_r+0x1a> 8008290: 6023 str r3, [r4, #0] 8008292: bd38 pop {r3, r4, r5, pc} 8008294: 20000dec .word 0x20000dec 08008298 <__malloc_lock>: 8008298: 4801 ldr r0, [pc, #4] ; (80082a0 <__malloc_lock+0x8>) 800829a: f000 b811 b.w 80082c0 <__retarget_lock_acquire_recursive> 800829e: bf00 nop 80082a0: 20000df0 .word 0x20000df0 080082a4 <__malloc_unlock>: 80082a4: 4801 ldr r0, [pc, #4] ; (80082ac <__malloc_unlock+0x8>) 80082a6: f000 b80c b.w 80082c2 <__retarget_lock_release_recursive> 80082aa: bf00 nop 80082ac: 20000df0 .word 0x20000df0 080082b0 <_malloc_usable_size_r>: 80082b0: f851 3c04 ldr.w r3, [r1, #-4] 80082b4: 1f18 subs r0, r3, #4 80082b6: 2b00 cmp r3, #0 80082b8: bfbc itt lt 80082ba: 580b ldrlt r3, [r1, r0] 80082bc: 18c0 addlt r0, r0, r3 80082be: 4770 bx lr 080082c0 <__retarget_lock_acquire_recursive>: 80082c0: 4770 bx lr 080082c2 <__retarget_lock_release_recursive>: 80082c2: 4770 bx lr 080082c4 <_init>: 80082c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80082c6: bf00 nop 80082c8: bcf8 pop {r3, r4, r5, r6, r7} 80082ca: bc08 pop {r3} 80082cc: 469e mov lr, r3 80082ce: 4770 bx lr 080082d0 <_fini>: 80082d0: b5f8 push {r3, r4, r5, r6, r7, lr} 80082d2: bf00 nop 80082d4: bcf8 pop {r3, r4, r5, r6, r7} 80082d6: bc08 pop {r3} 80082d8: 469e mov lr, r3 80082da: 4770 bx lr