llvm-project

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; RUN: opt %loadNPMPolly -polly-vectorizer=stripmine -polly-isl-arg=--no-schedule-serialize-sccs -polly-tiling=0 '-passes=print<polly-opt-isl>' -disable-output < %s | FileCheck %s
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; isl_schedule_node_band_sink may sink into multiple children.
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; https://llvm.org/PR52637
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%struct.v4l2_sliced_vbi_data = type { [48 x i8] }
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define void @vivid_vbi_gen_sliced() {
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entry:
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  br label %for.body
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for.body:                                         ; preds = %vivid_vbi_gen_teletext.exit, %entry
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  %i.015 = phi i32 [ 0, %entry ], [ %inc, %vivid_vbi_gen_teletext.exit ]
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  %data0.014 = phi ptr [ null, %entry ], [ %incdec.ptr, %vivid_vbi_gen_teletext.exit ]
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  %arrayidx.i = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 0, i32 0, i32 6
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  %0 = load i8, ptr %arrayidx.i, align 1
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  store i8 %0, ptr %data0.014, align 1
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  br label %for.body.for.body_crit_edge.i
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for.body.for.body_crit_edge.i:                    ; preds = %for.body.for.body_crit_edge.i, %for.body
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  %inc10.i13 = phi i32 [ 1, %for.body ], [ %inc10.i, %for.body.for.body_crit_edge.i ]
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  %arrayidx2.phi.trans.insert.i = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 0, i32 0, i32 %inc10.i13
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  store i8 0, ptr %arrayidx2.phi.trans.insert.i, align 1
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  %inc10.i = add nuw nsw i32 %inc10.i13, 1
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  %exitcond.not.i = icmp eq i32 %inc10.i13, 42
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  br i1 %exitcond.not.i, label %vivid_vbi_gen_teletext.exit, label %for.body.for.body_crit_edge.i
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vivid_vbi_gen_teletext.exit:                      ; preds = %for.body.for.body_crit_edge.i
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  %incdec.ptr = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 1
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  %inc = add nuw nsw i32 %i.015, 1
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  %exitcond.not = icmp eq i32 %i.015, 1
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  br i1 %exitcond.not, label %for.end, label %for.body
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for.end:                                          ; preds = %vivid_vbi_gen_teletext.exit
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  ret void
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}
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; CHECK: schedule:
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; CHECK:   schedule:
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; CHECK:     mark: "SIMD"
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; CHECK:       schedule:
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; CHECK:     mark: "SIMD"
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; CHECK:       schedule:
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