llvm-project

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//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Common/AssemblerUtils.h"
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#include "LlvmState.h"
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#include "MCInstrDescView.h"
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#include "ParallelSnippetGenerator.h"
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#include "RegisterAliasing.h"
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#include "SerialSnippetGenerator.h"
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#include "TestBase.h"
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#include "X86InstrInfo.h"
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#include "llvm/ADT/SetOperations.h"
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#include <unordered_set>
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namespace llvm {
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namespace exegesis {
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void InitializeX86ExegesisTarget();
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namespace {
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using testing::AnyOf;
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using testing::ElementsAre;
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using testing::Gt;
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using testing::HasSubstr;
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using testing::IsEmpty;
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using testing::Not;
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using testing::SizeIs;
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MATCHER(IsInvalid, "") { return !arg.isValid(); }
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MATCHER(IsReg, "") { return arg.isReg(); }
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template <typename SnippetGeneratorT>
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class X86SnippetGeneratorTest : public X86TestBase {
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protected:
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  X86SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()),
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	                      InstrInfo(State.getInstrInfo()) {}
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  std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
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    randomGenerator().seed(0); // Initialize seed.
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    const Instruction &Instr = State.getIC().getInstr(Opcode);
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    auto CodeTemplateOrError = Generator.generateCodeTemplates(
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        &Instr, State.getRATC().emptyRegisters());
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    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
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    return std::move(CodeTemplateOrError.get());
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  }
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  SnippetGeneratorT Generator;
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  const MCInstrInfo &InstrInfo;
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};
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using X86SerialSnippetGeneratorTest = X86SnippetGeneratorTest<SerialSnippetGenerator>;
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using X86ParallelSnippetGeneratorTest =
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    X86SnippetGeneratorTest<ParallelSnippetGenerator>;
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TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
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  // - ADC16i16
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  // - Op0 Explicit Use Immediate
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  // - Op1 Implicit Def Reg(AX)
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  // - Op2 Implicit Def Reg(EFLAGS)
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  // - Op3 Implicit Use Reg(AX)
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  // - Op4 Implicit Use Reg(EFLAGS)
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  // - Var0 [Op0]
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  // - hasAliasingImplicitRegisters (execution is always serial)
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::ADC16i16;
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  EXPECT_THAT(InstrInfo.get(Opcode).implicit_defs()[0], X86::AX);
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  EXPECT_THAT(InstrInfo.get(Opcode).implicit_defs()[1], X86::EFLAGS);
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  EXPECT_THAT(InstrInfo.get(Opcode).implicit_uses()[0], X86::AX);
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  EXPECT_THAT(InstrInfo.get(Opcode).implicit_uses()[1], X86::EFLAGS);
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(1));
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  const auto &CT = CodeTemplates[0];
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  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
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  ASSERT_THAT(CT.Instructions, SizeIs(1));
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  const InstructionTemplate &IT = CT.Instructions[0];
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  EXPECT_THAT(IT.getOpcode(), Opcode);
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  ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
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  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
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}
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TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
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  // - ADD16ri
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  // - Op0 Explicit Def RegClass(GR16)
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  // - Op1 Explicit Use RegClass(GR16) TiedToOp0
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  // - Op2 Explicit Use Immediate
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  // - Op3 Implicit Def Reg(EFLAGS)
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  // - Var0 [Op0,Op1]
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  // - Var1 [Op2]
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  // - hasTiedRegisters (execution is always serial)
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::ADD16ri;
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  EXPECT_THAT(InstrInfo.get(Opcode).implicit_defs()[0], X86::EFLAGS);
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(1));
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  const auto &CT = CodeTemplates[0];
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  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
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  ASSERT_THAT(CT.Instructions, SizeIs(1));
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  const InstructionTemplate &IT = CT.Instructions[0];
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  EXPECT_THAT(IT.getOpcode(), Opcode);
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  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
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  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
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}
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TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
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  // - VXORPSrr
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  // - Op0 Explicit Def RegClass(VR128)
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  // - Op1 Explicit Use RegClass(VR128)
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  // - Op2 Explicit Use RegClass(VR128)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  // - Var2 [Op2]
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::VXORPSrr;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(1));
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  const auto &CT = CodeTemplates[0];
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  EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
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  ASSERT_THAT(CT.Instructions, SizeIs(1));
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  const InstructionTemplate &IT = CT.Instructions[0];
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  EXPECT_THAT(IT.getOpcode(), Opcode);
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  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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  EXPECT_THAT(IT.getVariableValues(),
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              AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
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                    ElementsAre(IsReg(), IsReg(), IsInvalid())))
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      << "Op0 is either set to Op1 or to Op2";
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}
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TEST_F(X86SerialSnippetGeneratorTest,
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       ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
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  // - VXORPSrr
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  // - Op0 Explicit Def RegClass(VR128)
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  // - Op1 Explicit Use RegClass(VR128)
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  // - Op2 Explicit Use RegClass(VR128)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  // - Var2 [Op2]
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::VXORPSrr;
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  randomGenerator().seed(0); // Initialize seed.
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  const Instruction &Instr = State.getIC().getInstr(Opcode);
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  auto AllRegisters = State.getRATC().emptyRegisters();
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  AllRegisters.flip();
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  auto Error =
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      Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
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  EXPECT_TRUE((bool)Error);
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  consumeError(std::move(Error));
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}
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TEST_F(X86SerialSnippetGeneratorTest,
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       ImplicitSelfDependencyThroughExplicitRegsForbidAlmostAll) {
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  // - VXORPSrr
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  // - Op0 Explicit Def RegClass(VR128)
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  // - Op1 Explicit Use RegClass(VR128)
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  // - Op2 Explicit Use RegClass(VR128)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  // - Var2 [Op2]
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::VXORPSrr;
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  randomGenerator().seed(0); // Initialize seed.
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  const Instruction &Instr = State.getIC().getInstr(Opcode);
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  auto ForbiddenRegisters = State.getRATC().emptyRegisters();
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  ForbiddenRegisters.flip();
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  ForbiddenRegisters.reset(X86::XMM0);
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  auto Error = Generator.generateCodeTemplates(&Instr, ForbiddenRegisters);
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  EXPECT_FALSE((bool)Error.takeError());
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  auto CodeTemplates = std::move(Error.get());
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  ASSERT_THAT(CodeTemplates, SizeIs(Gt(0U))) << "Templates are available";
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
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    ASSERT_THAT(CT.Instructions, SizeIs(1));
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    const InstructionTemplate &IT = CT.Instructions[0];
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    EXPECT_THAT(IT.getOpcode(), Opcode);
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    ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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    for (const auto &Var : IT.getVariableValues()) {
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      if (Var.isReg()) {
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        EXPECT_FALSE(ForbiddenRegisters[Var.getReg()]);
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      }
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    }
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  }
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}
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TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
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  // - CMP64rr
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  // - Op0 Explicit Use RegClass(GR64)
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  // - Op1 Explicit Use RegClass(GR64)
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  // - Op2 Implicit Def Reg(EFLAGS)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  const unsigned Opcode = X86::CMP64rr;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
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    ASSERT_THAT(CT.Instructions, SizeIs(2));
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    const InstructionTemplate &IT = CT.Instructions[0];
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    EXPECT_THAT(IT.getOpcode(), Opcode);
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    ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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    EXPECT_THAT(IT.getVariableValues(),
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                AnyOf(ElementsAre(IsReg(), IsInvalid()),
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                      ElementsAre(IsInvalid(), IsReg())));
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    EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
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    // TODO: check that the two instructions alias each other.
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  }
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}
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TEST_F(X86SerialSnippetGeneratorTest, LAHF) {
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  // - LAHF
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  // - Op0 Implicit Def Reg(AH)
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  // - Op1 Implicit Use Reg(EFLAGS)
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  const unsigned Opcode = X86::LAHF;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
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    ASSERT_THAT(CT.Instructions, SizeIs(2));
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    const InstructionTemplate &IT = CT.Instructions[0];
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    EXPECT_THAT(IT.getOpcode(), Opcode);
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    ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
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  }
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}
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TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
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  // - VCVTUSI642SDZrrb_Int
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  // - Op0 Explicit Def RegClass(VR128X)
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  // - Op1 Explicit Use RegClass(VR128X)
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  // - Op2 Explicit Use STATIC_ROUNDING
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  // - Op2 Explicit Use RegClass(GR64)
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  // - Op4 Implicit Use Reg(MXSCR)
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  const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
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  const Instruction &Instr = State.getIC().getInstr(Opcode);
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  std::vector<BenchmarkCode> Configs;
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  auto Error = Generator.generateConfigurations(
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      &Instr, Configs, State.getRATC().emptyRegisters());
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  ASSERT_FALSE(Error);
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  ASSERT_THAT(Configs, SizeIs(1));
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  const BenchmarkCode &BC = Configs[0];
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  ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
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  ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
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}
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TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
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  // - CDQ
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  // - Op0 Implicit Def Reg(EAX)
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  // - Op1 Implicit Def Reg(EDX)
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  // - Op2 Implicit Use Reg(EAX)
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  // - hasAliasingImplicitRegisters (execution is always serial)
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::CDQ;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(1));
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  const auto &CT = CodeTemplates[0];
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  EXPECT_THAT(CT.Info, HasSubstr("serial"));
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  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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  ASSERT_THAT(CT.Instructions, SizeIs(1));
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  const InstructionTemplate &IT = CT.Instructions[0];
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  EXPECT_THAT(IT.getOpcode(), Opcode);
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  ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
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}
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TEST_F(X86ParallelSnippetGeneratorTest, ReadAfterWrite_CMOV32rr) {
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  // CMOV32rr has tied variables, we enumerate the possible values to execute
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  // as many in parallel as possible.
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  // - CMOV32rr
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  // - Op0 Explicit Def RegClass(GR32)
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  // - Op1 Explicit Use RegClass(GR32) TiedToOp0
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  // - Op2 Explicit Use RegClass(GR32)
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  // - Op3 Explicit Use Immediate
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  // - Op3 Implicit Use Reg(EFLAGS)
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  // - Var0 [Op0,Op1]
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  // - Var1 [Op2]
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  // - hasTiedRegisters (execution is always serial)
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::CMOV32rr;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(2));
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Info, HasSubstr("avoiding Read-After-Write issue"));
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    EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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    ASSERT_GT(CT.Instructions.size(), 1U);
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    std::unordered_set<unsigned> AllDefRegisters;
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    std::unordered_set<unsigned> AllUseRegisters;
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    for (const auto &IT : CT.Instructions) {
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      ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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      AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
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      AllUseRegisters.insert(IT.getVariableValues()[1].getReg());
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    }
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    EXPECT_THAT(AllDefRegisters, SizeIs(CT.Instructions.size()))
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        << "Each instruction writes to a different register";
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    EXPECT_THAT(AllUseRegisters, Not(IsEmpty()))
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        << "In total, some other registers are used";
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    auto AllDefAndUseRegs = AllUseRegisters;
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    llvm::set_intersect(AllDefAndUseRegs, AllDefRegisters); // A := A ^ B
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    EXPECT_THAT(AllDefAndUseRegs, IsEmpty())
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        << "No instruction uses any register defined by any of the "
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           "instructions";
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  }
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}
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TEST_F(X86ParallelSnippetGeneratorTest, ReadAfterWrite_VFMADD132PDr) {
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  // VFMADD132PDr has tied variables, we enumerate the possible values
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  // to execute as many in parallel as possible.
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  // - VFMADD132PDr
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  // - Op0 Explicit Def RegClass(XMM)
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  // - Op1 Explicit Use RegClass(XMM) TiedToOp0
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  // - Op2 Explicit Use RegClass(XMM)
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  // - Op3 Explicit Use RegClass(XMM)
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  // - Var0 [Op0,Op1]
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  // - Var1 [Op2]
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  // - Var2 [Op3]
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  // - hasTiedRegisters (execution is always serial)
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::VFMADD132PDr;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(3));
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Info, HasSubstr("avoiding Read-After-Write issue"));
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    EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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    ASSERT_GT(CT.Instructions.size(), 1U);
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    std::unordered_set<unsigned> AllDefRegisters;
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    std::unordered_set<unsigned> AllUseRegisters;
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    for (const auto &IT : CT.Instructions) {
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      ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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      AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
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      AllUseRegisters.insert(IT.getVariableValues()[1].getReg());
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      AllUseRegisters.insert(IT.getVariableValues()[2].getReg());
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    }
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    EXPECT_THAT(AllDefRegisters, SizeIs(CT.Instructions.size()))
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        << "Each instruction writes to a different register";
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    EXPECT_THAT(AllUseRegisters, Not(IsEmpty()))
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        << "In total, some other registers are used";
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    auto AllDefAndUseRegs = AllUseRegisters;
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    llvm::set_intersect(AllDefAndUseRegs, AllDefRegisters); // A := A ^ B
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    EXPECT_THAT(AllDefAndUseRegs, IsEmpty())
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        << "No instruction uses any register defined by any of the "
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           "instructions";
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  }
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}
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TEST_F(X86ParallelSnippetGeneratorTest, NoTiedVariables) {
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  // CMOV_GR32 has no tied variables, we make sure def and use are different
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  // from each other.
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  // - CMOV_GR32
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  // - Op0 Explicit Def RegClass(GR32)
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  // - Op1 Explicit Use RegClass(GR32)
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  // - Op2 Explicit Use RegClass(GR32)
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  // - Op3 Explicit Use Immediate
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  // - Op4 Implicit Use Reg(EFLAGS)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  // - Var2 [Op2]
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  // - Var3 [Op3]
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::CMOV_GR32;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(2));
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
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    EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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    ASSERT_THAT(CT.Instructions, SizeIs(1));
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    const InstructionTemplate &IT = CT.Instructions[0];
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    EXPECT_THAT(IT.getOpcode(), Opcode);
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    ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
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    EXPECT_THAT(IT.getVariableValues()[0].getReg(),
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                Not(IT.getVariableValues()[1].getReg()))
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        << "Def is different from first Use";
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    EXPECT_THAT(IT.getVariableValues()[0].getReg(),
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                Not(IT.getVariableValues()[2].getReg()))
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        << "Def is different from second Use";
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    EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
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  }
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}
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TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) {
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  // Mov32rm reads from memory.
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  // - MOV32rm
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  // - Op0 Explicit Def RegClass(GR32)
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  // - Op1 Explicit Use Memory RegClass(GR8)
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  // - Op2 Explicit Use Memory
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  // - Op3 Explicit Use Memory RegClass(GRH8)
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  // - Op4 Explicit Use Memory
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  // - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
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  // - Var0 [Op0]
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  // - Var1 [Op1]
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  // - Var2 [Op2]
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  // - Var3 [Op3]
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  // - Var4 [Op4]
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  // - Var5 [Op5]
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  // - hasMemoryOperands
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  // - hasAliasingRegisters
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  const unsigned Opcode = X86::MOV32rm;
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  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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  ASSERT_THAT(CodeTemplates, SizeIs(1));
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  for (const auto &CT : CodeTemplates) {
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    EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
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    EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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    ASSERT_THAT(CT.Instructions,
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                SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
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    const InstructionTemplate &IT = CT.Instructions[0];
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    EXPECT_THAT(IT.getOpcode(), Opcode);
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    ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
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    EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
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    EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
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    EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
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    EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
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  }
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}
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TEST_F(X86ParallelSnippetGeneratorTest, MOV16ms) {
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  const unsigned Opcode = X86::MOV16ms;
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  const Instruction &Instr = State.getIC().getInstr(Opcode);
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  std::vector<BenchmarkCode> Benchmarks;
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  auto Err = Generator.generateConfigurations(&Instr, Benchmarks,
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                                              State.getRATC().emptyRegisters());
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  EXPECT_TRUE((bool)Err);
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  EXPECT_THAT(toString(std::move(Err)),
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              testing::HasSubstr("no available registers"));
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}
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TEST_F(X86ParallelSnippetGeneratorTest,
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       AvoidSerializingThroughImplicitRegisters) {
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  // MULX32rr implicitly uses EDX. We should not select that register to avoid
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  // serialization.
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  const unsigned Opcode = X86::MULX32rr;
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  randomGenerator().seed(0); // Initialize seed.
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  const Instruction &Instr = State.getIC().getInstr(Opcode);
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  // Forbid all registers but RDX/EDX/DX/DH/DL. The only option would be to
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  // choose that register, but that would serialize the instruction, so we
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  // should be returning an error.
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  auto AllRegisters = State.getRATC().emptyRegisters();
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  AllRegisters.flip();
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  AllRegisters.reset(X86::RDX);
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  AllRegisters.reset(X86::EDX);
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  AllRegisters.reset(X86::DX);
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  AllRegisters.reset(X86::DH);
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  AllRegisters.reset(X86::DL);
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  auto Err = Generator.generateCodeTemplates(&Instr, AllRegisters);
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  EXPECT_FALSE((bool)Err);
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  EXPECT_THAT(toString(Err.takeError()),
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              testing::HasSubstr("Failed to produce any snippet"));
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}
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class X86FakeSnippetGenerator : public SnippetGenerator {
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public:
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  X86FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
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      : SnippetGenerator(State, Opts) {}
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  const Instruction &getInstr(unsigned Opcode) {
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    return State.getIC().getInstr(Opcode);
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  }
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  InstructionTemplate getInstructionTemplate(unsigned Opcode) {
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    return {&getInstr(Opcode)};
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  }
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private:
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  Expected<std::vector<CodeTemplate>>
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  generateCodeTemplates(InstructionTemplate, const BitVector &) const override {
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    return make_error<StringError>("not implemented", inconvertibleErrorCode());
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  }
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};
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using X86FakeSnippetGeneratorTest = X86SnippetGeneratorTest<X86FakeSnippetGenerator>;
476

477
testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
478
                                                        APInt Value) {
479
  return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
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                        testing::Field(&RegisterValue::Value, Value));
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}
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TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) {
484
  // MOVSB writes to scratch memory register.
485
  // - MOVSB
486
  // - Op0 Explicit Use Memory RegClass(GR8)
487
  // - Op1 Explicit Use Memory RegClass(GR8)
488
  // - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
489
  // - Op3 Implicit Def Reg(EDI)
490
  // - Op4 Implicit Def Reg(ESI)
491
  // - Op5 Implicit Use Reg(EDI)
492
  // - Op6 Implicit Use Reg(ESI)
493
  // - Op7 Implicit Use Reg(DF)
494
  // - Var0 [Op0]
495
  // - Var1 [Op1]
496
  // - Var2 [Op2]
497
  // - hasMemoryOperands
498
  // - hasAliasingImplicitRegisters (execution is always serial)
499
  // - hasAliasingRegisters
500
  const unsigned Opcode = X86::MOVSB;
501
  const Instruction &Instr = State.getIC().getInstr(Opcode);
502
  std::vector<BenchmarkCode> Benchmarks;
503
  auto Error = Generator.generateConfigurations(
504
      &Instr, Benchmarks, State.getRATC().emptyRegisters());
505
  EXPECT_TRUE((bool)Error);
506
  consumeError(std::move(Error));
507
}
508

509
TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
510
  // ADD16ri:
511
  // explicit def 0       : reg RegClass=GR16
512
  // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
513
  // explicit use 2       : imm
514
  // implicit def         : EFLAGS
515
  InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
516
  IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
517
  std::vector<InstructionTemplate> Snippet;
518
  Snippet.push_back(std::move(IT));
519
  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
520
  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
521
}
522

523
TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
524
  // ADD64rr:
525
  //  mov64ri rax, 42
526
  //  add64rr rax, rax, rbx
527
  // -> only rbx needs defining.
528
  std::vector<InstructionTemplate> Snippet;
529
  {
530
    InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
531
    Mov.getValueFor(Mov.getInstr().Variables[0]) =
532
        MCOperand::createReg(X86::RAX);
533
    Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
534
    Snippet.push_back(std::move(Mov));
535
  }
536
  {
537
    InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
538
    Add.getValueFor(Add.getInstr().Variables[0]) =
539
        MCOperand::createReg(X86::RAX);
540
    Add.getValueFor(Add.getInstr().Variables[1]) =
541
        MCOperand::createReg(X86::RBX);
542
    Snippet.push_back(std::move(Add));
543
  }
544

545
  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
546
  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
547
}
548

549
} // namespace
550
} // namespace exegesis
551
} // namespace llvm
552