llvm-project

uniform-regions.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-- -S -o - -structurizecfg -structurizecfg-skip-uniform-regions -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s
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define amdgpu_cs void @uniform(i32 inreg %v) {
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; CHECK-LABEL: @uniform(
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; CHECK-NEXT:  entry:
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; CHECK-NEXT:    [[CC:%.*]] = icmp eq i32 [[V:%.*]], 0
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; CHECK-NEXT:    br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]], !structurizecfg.uniform !0
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; CHECK:       if:
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; CHECK-NEXT:    br label [[END]], !structurizecfg.uniform !0
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; CHECK:       end:
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; CHECK-NEXT:    ret void
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;
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entry:
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  %cc = icmp eq i32 %v, 0
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  br i1 %cc, label %if, label %end
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if:
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  br label %end
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end:
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  ret void
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}
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define amdgpu_cs void @nonuniform(ptr addrspace(4) %ptr) {
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; CHECK-LABEL: @nonuniform(
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; CHECK-NEXT:  entry:
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; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
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; CHECK:       for.body:
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; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[FLOW:%.*]] ]
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; CHECK-NEXT:    [[CC:%.*]] = icmp ult i32 [[I]], 4
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; CHECK-NEXT:    br i1 [[CC]], label [[MID_LOOP:%.*]], label [[FLOW]]
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; CHECK:       mid.loop:
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; CHECK-NEXT:    [[V:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT:    [[CC2:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT:    br i1 [[CC2]], label [[END_LOOP:%.*]], label [[FLOW1:%.*]]
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; CHECK:       Flow:
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; CHECK-NEXT:    [[TMP0]] = phi i32 [ [[TMP2:%.*]], [[FLOW1]] ], [ undef, [[FOR_BODY]] ]
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; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ [[TMP3:%.*]], [[FLOW1]] ], [ true, [[FOR_BODY]] ]
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; CHECK-NEXT:    br i1 [[TMP1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
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; CHECK:       end.loop:
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; CHECK-NEXT:    [[I_INC:%.*]] = add i32 [[I]], 1
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; CHECK-NEXT:    br label [[FLOW1]]
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; CHECK:       Flow1:
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; CHECK-NEXT:    [[TMP2]] = phi i32 [ [[I_INC]], [[END_LOOP]] ], [ undef, [[MID_LOOP]] ]
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; CHECK-NEXT:    [[TMP3]] = phi i1 [ false, [[END_LOOP]] ], [ true, [[MID_LOOP]] ]
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; CHECK-NEXT:    br label [[FLOW]]
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; CHECK:       for.end:
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; CHECK-NEXT:    br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK:       if:
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; CHECK-NEXT:    br label [[END]]
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; CHECK:       end:
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; CHECK-NEXT:    ret void
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;
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entry:
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  br label %for.body
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for.body:
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  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
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  %cc = icmp ult i32 %i, 4
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  br i1 %cc, label %mid.loop, label %for.end
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mid.loop:
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  %v = call i32 @llvm.amdgcn.workitem.id.x()
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  %cc2 = icmp eq i32 %v, 0
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  br i1 %cc2, label %end.loop, label %for.end
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end.loop:
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  %i.inc = add i32 %i, 1
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  br label %for.body
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for.end:
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  br i1 %cc, label %if, label %end
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if:
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  br label %end
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end:
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  ret void
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}
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define amdgpu_cs void @uniform_branch_to_nonuniform_subregions(ptr addrspace(4) %ptr, i32 inreg %data) {
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; CHECK-LABEL: @uniform_branch_to_nonuniform_subregions(
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; CHECK-NEXT:  entry:
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; CHECK-NEXT:    [[C:%.*]] = icmp eq i32 [[DATA:%.*]], 42
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; CHECK-NEXT:    br i1 [[C]], label [[UNIFORM_FOR_BODY:%.*]], label [[FOR_BODY:%.*]], !structurizecfg.uniform !0
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; CHECK:       for.body:
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; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[FLOW1:%.*]] ]
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; CHECK-NEXT:    [[CC:%.*]] = icmp ult i32 [[I]], 4
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; CHECK-NEXT:    br i1 [[CC]], label [[MID_LOOP:%.*]], label [[FLOW1]]
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; CHECK:       mid.loop:
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; CHECK-NEXT:    [[V:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT:    [[CC2:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT:    br i1 [[CC2]], label [[END_LOOP:%.*]], label [[FLOW2:%.*]]
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; CHECK:       Flow1:
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; CHECK-NEXT:    [[TMP0]] = phi i32 [ [[TMP2:%.*]], [[FLOW2]] ], [ undef, [[FOR_BODY]] ]
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; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ [[TMP3:%.*]], [[FLOW2]] ], [ true, [[FOR_BODY]] ]
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; CHECK-NEXT:    br i1 [[TMP1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
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; CHECK:       end.loop:
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; CHECK-NEXT:    [[I_INC:%.*]] = add i32 [[I]], 1
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; CHECK-NEXT:    br label [[FLOW2]]
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; CHECK:       Flow2:
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; CHECK-NEXT:    [[TMP2]] = phi i32 [ [[I_INC]], [[END_LOOP]] ], [ undef, [[MID_LOOP]] ]
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; CHECK-NEXT:    [[TMP3]] = phi i1 [ false, [[END_LOOP]] ], [ true, [[MID_LOOP]] ]
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; CHECK-NEXT:    br label [[FLOW1]]
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; CHECK:       for.end:
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; CHECK-NEXT:    br i1 [[CC]], label [[IF:%.*]], label [[FLOW:%.*]]
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; CHECK:       if:
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; CHECK-NEXT:    br label [[FLOW]]
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; CHECK:       uniform.for.body:
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; CHECK-NEXT:    [[UNIFORM_I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP4:%.*]], [[FLOW4:%.*]] ]
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; CHECK-NEXT:    [[UNIFORM_CC:%.*]] = icmp ult i32 [[UNIFORM_I]], 4
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; CHECK-NEXT:    br i1 [[UNIFORM_CC]], label [[UNIFORM_MID_LOOP:%.*]], label [[FLOW4]]
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; CHECK:       uniform.mid.loop:
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; CHECK-NEXT:    [[UNIFORM_V:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT:    [[UNIFORM_CC2:%.*]] = icmp eq i32 [[UNIFORM_V]], 0
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; CHECK-NEXT:    br i1 [[UNIFORM_CC2]], label [[UNIFORM_END_LOOP:%.*]], label [[FLOW5:%.*]]
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; CHECK:       Flow4:
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; CHECK-NEXT:    [[TMP4]] = phi i32 [ [[TMP6:%.*]], [[FLOW5]] ], [ undef, [[UNIFORM_FOR_BODY]] ]
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; CHECK-NEXT:    [[TMP5:%.*]] = phi i1 [ [[TMP7:%.*]], [[FLOW5]] ], [ true, [[UNIFORM_FOR_BODY]] ]
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; CHECK-NEXT:    br i1 [[TMP5]], label [[UNIFORM_FOR_END:%.*]], label [[UNIFORM_FOR_BODY]]
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; CHECK:       uniform.end.loop:
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; CHECK-NEXT:    [[UNIFORM_I_INC:%.*]] = add i32 [[UNIFORM_I]], 1
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; CHECK-NEXT:    br label [[FLOW5]]
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; CHECK:       Flow5:
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; CHECK-NEXT:    [[TMP6]] = phi i32 [ [[UNIFORM_I_INC]], [[UNIFORM_END_LOOP]] ], [ undef, [[UNIFORM_MID_LOOP]] ]
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; CHECK-NEXT:    [[TMP7]] = phi i1 [ false, [[UNIFORM_END_LOOP]] ], [ true, [[UNIFORM_MID_LOOP]] ]
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; CHECK-NEXT:    br label [[FLOW4]]
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; CHECK:       uniform.for.end:
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; CHECK-NEXT:    br i1 [[UNIFORM_CC]], label [[UNIFORM_IF:%.*]], label [[FLOW3:%.*]]
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; CHECK:       uniform.if:
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; CHECK-NEXT:    br label [[FLOW3]]
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; CHECK:       Flow:
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; CHECK-NEXT:    br label [[END:%.*]]
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; CHECK:       Flow3:
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; CHECK-NEXT:    br label [[END]]
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; CHECK:       end:
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; CHECK-NEXT:    ret void
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;
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entry:
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  %c = icmp eq i32 %data, 42
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  br i1 %c, label %uniform.for.body, label %for.body
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for.body:
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  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
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  %cc = icmp ult i32 %i, 4
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  br i1 %cc, label %mid.loop, label %for.end
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mid.loop:
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  %v = call i32 @llvm.amdgcn.workitem.id.x()
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  %cc2 = icmp eq i32 %v, 0
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  br i1 %cc2, label %end.loop, label %for.end
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end.loop:
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  %i.inc = add i32 %i, 1
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  br label %for.body
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for.end:
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  br i1 %cc, label %if, label %end
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if:
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  br label %end
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uniform.for.body:
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  %uniform.i = phi i32 [0, %entry], [%uniform.i.inc, %uniform.end.loop]
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  %uniform.cc = icmp ult i32 %uniform.i, 4
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  br i1 %uniform.cc, label %uniform.mid.loop, label %uniform.for.end
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uniform.mid.loop:
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  %uniform.v = call i32 @llvm.amdgcn.workitem.id.x()
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  %uniform.cc2 = icmp eq i32 %uniform.v, 0
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  br i1 %uniform.cc2, label %uniform.end.loop, label %uniform.for.end
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uniform.end.loop:
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  %uniform.i.inc = add i32 %uniform.i, 1
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  br label %uniform.for.body
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uniform.for.end:
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  br i1 %uniform.cc, label %uniform.if, label %end
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uniform.if:
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  br label %end
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end:
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  ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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