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scalable-vectors.ll 
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
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; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
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; This test checks that SROA runs mem2reg on scalable vectors.
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define <vscale x 16 x i1> @alloca_nxv16i1(<vscale x 16 x i1> %pg) {
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; CHECK-LABEL: @alloca_nxv16i1(
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; CHECK-NEXT:    ret <vscale x 16 x i1> [[PG:%.*]]
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;
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  %pg.addr = alloca <vscale x 16 x i1>
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  store <vscale x 16 x i1> %pg, ptr %pg.addr
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  %1 = load <vscale x 16 x i1>, ptr %pg.addr
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  ret <vscale x 16 x i1> %1
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}
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define <vscale x 16 x i8> @alloca_nxv16i8(<vscale x 16 x i8> %vec) {
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; CHECK-LABEL: @alloca_nxv16i8(
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; CHECK-NEXT:    ret <vscale x 16 x i8> [[VEC:%.*]]
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;
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  %vec.addr = alloca <vscale x 16 x i8>
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  store <vscale x 16 x i8> %vec, ptr %vec.addr
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  %1 = load <vscale x 16 x i8>, ptr %vec.addr
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  ret <vscale x 16 x i8> %1
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}
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; Test scalable alloca that can't be promoted. Mem2Reg only considers
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; non-volatile loads and stores for promotion.
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define <vscale x 16 x i8> @unpromotable_alloca(<vscale x 16 x i8> %vec) {
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; CHECK-LABEL: @unpromotable_alloca(
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; CHECK-NEXT:    [[VEC_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
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; CHECK-NEXT:    store volatile <vscale x 16 x i8> [[VEC:%.*]], ptr [[VEC_ADDR]], align 16
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; CHECK-NEXT:    [[TMP1:%.*]] = load volatile <vscale x 16 x i8>, ptr [[VEC_ADDR]], align 16
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; CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
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;
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  %vec.addr = alloca <vscale x 16 x i8>
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  store volatile <vscale x 16 x i8> %vec, ptr %vec.addr
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  %1 = load volatile <vscale x 16 x i8>, ptr %vec.addr
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  ret <vscale x 16 x i8> %1
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}
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; Test we bail out when using an alloca of a fixed-length vector (VLS) that was
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; bitcasted to a scalable vector.
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define <vscale x 4 x i32> @cast_alloca_to_svint32_t(<vscale x 4 x i32> %type.coerce) {
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; CHECK-LABEL: @cast_alloca_to_svint32_t(
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; CHECK-NEXT:    [[TYPE:%.*]] = alloca <16 x i32>, align 64
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; CHECK-NEXT:    [[TYPE_ADDR:%.*]] = alloca <16 x i32>, align 64
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; CHECK-NEXT:    store <vscale x 4 x i32> [[TYPE_COERCE:%.*]], ptr [[TYPE]], align 16
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; CHECK-NEXT:    [[TYPE1:%.*]] = load <16 x i32>, ptr [[TYPE]], align 64
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; CHECK-NEXT:    store <16 x i32> [[TYPE1]], ptr [[TYPE_ADDR]], align 64
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; CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i32>, ptr [[TYPE_ADDR]], align 64
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; CHECK-NEXT:    [[TMP2:%.*]] = load <vscale x 4 x i32>, ptr [[TYPE_ADDR]], align 16
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; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
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;
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  %type = alloca <16 x i32>
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  %type.addr = alloca <16 x i32>
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  store <vscale x 4 x i32> %type.coerce, ptr %type
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  %type1 = load <16 x i32>, ptr %type
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  store <16 x i32> %type1, ptr %type.addr
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  %1 = load <16 x i32>, ptr %type.addr
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  %2 = load <vscale x 4 x i32>, ptr %type.addr
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  ret <vscale x 4 x i32> %2
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}
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; When casting from VLA to VLS via memory check we bail out when producing a
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; GEP where the element type is a scalable vector.
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define <vscale x 4 x i32> @cast_alloca_from_svint32_t() {
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; CHECK-LABEL: @cast_alloca_from_svint32_t(
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; CHECK-NEXT:    [[RETVAL_COERCE:%.*]] = alloca <vscale x 4 x i32>, align 16
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; CHECK-NEXT:    store <16 x i32> undef, ptr [[RETVAL_COERCE]], align 16
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; CHECK-NEXT:    [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[RETVAL_COERCE]], align 16
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; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
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;
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  %retval = alloca <16 x i32>
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  %retval.coerce = alloca <vscale x 4 x i32>
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  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %retval.coerce, ptr align 16 %retval, i64 64, i1 false)
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  %1 = load <vscale x 4 x i32>, ptr %retval.coerce
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  ret <vscale x 4 x i32> %1
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}
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; Test we bail out when using an alloca of a fixed-length vector (VLS) that was
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; bitcasted to a scalable vector.
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define void @select_load_alloca_to_svdouble_t() {
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; CHECK-LABEL: @select_load_alloca_to_svdouble_t(
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; CHECK-NEXT:    [[Z:%.*]] = alloca <16 x half>, align 32
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; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 0, 0
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; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], ptr [[Z]], ptr null
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; CHECK-NEXT:    [[VAL:%.*]] = load <vscale x 2 x double>, ptr [[COND]], align 16
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; CHECK-NEXT:    ret void
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;
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  %z = alloca <16 x half>
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  %cmp = icmp eq i32 0, 0
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  %cond = select i1 %cmp, ptr %z, ptr null
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  %val = load <vscale x 2 x double>, ptr %cond, align 16
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  ret void
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}
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define void @select_store_alloca_to_svdouble_t(<vscale x 2 x double> %val) {
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; CHECK-LABEL: @select_store_alloca_to_svdouble_t(
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; CHECK-NEXT:    [[Z:%.*]] = alloca <16 x half>, align 32
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; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 0, 0
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; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], ptr [[Z]], ptr null
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; CHECK-NEXT:    store <vscale x 2 x double> [[VAL:%.*]], ptr [[COND]], align 16
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; CHECK-NEXT:    ret void
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;
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  %z = alloca <16 x half>
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  %cmp = icmp eq i32 0, 0
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  %cond = select i1 %cmp, ptr %z, ptr null
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  store <vscale x 2 x double> %val, ptr %cond, align 16
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  ret void
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}
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declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK-MODIFY-CFG: {{.*}}
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; CHECK-PRESERVE-CFG: {{.*}}
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