llvm-project

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This file is a partial list of people who have contributed to the LLVM
2
project. If you have contributed a patch or made some other contribution to
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LLVM, please submit a patch to this file to add yourself, and it will be
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done!
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The list is sorted by surname and formatted to allow easy grepping and
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beautification by scripts.  The fields are: name (N), email (E), web-address
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(W), PGP key ID and fingerprint (P), description (D), snail-mail address
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(S), and (I) IRC handle.
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N: Vikram Adve
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E: vadve@cs.uiuc.edu
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W: http://www.cs.uiuc.edu/~vadve/
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D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
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N: Owen Anderson
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E: resistor@mac.com
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D: LCSSA pass and related LoopUnswitch work
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D: GVNPRE pass, DataLayout refactoring, random improvements
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N: Henrik Bach
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D: MingW Win32 API portability layer
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N: Aaron Ballman
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E: aaron@aaronballman.com
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D: Clang frontend, frontend attributes, Windows support, general bug fixing
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I: AaronBallman
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N: Alexey Bataev
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E: a.bataev@outlook.com
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D: Clang frontend, OpenMP in clang, SLP vectorizer, Loop vectorizer, InstCombine
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I: ABataev
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N: Nate Begeman
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E: natebegeman@mac.com
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D: PowerPC backend developer
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D: Target-independent code generator and analysis improvements
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N: Daniel Berlin
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E: dberlin@dberlin.org
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D: ET-Forest implementation.
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D: Sparse bitmap
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N: Geoff Berry
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E: gberry@codeaurora.org
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E: gcb@acm.org
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D: AArch64 backend improvements
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D: Added EarlyCSE MemorySSA support
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D: CodeGen improvements
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N: David Blaikie
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E: dblaikie@gmail.com
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D: General bug fixing/fit & finish, mostly in Clang
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N: Neil Booth
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E: neil@daikokuya.co.uk
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D: APFloat implementation.
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N: Alex Bradbury
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E: asb@igalia.com
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D: RISC-V backend
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N: Misha Brukman
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E: brukman+llvm@uiuc.edu
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W: http://misha.brukman.net
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D: Portions of X86 and Sparc JIT compilers, PowerPC backend
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D: Incremental bitcode loader
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N: Cameron Buschardt
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E: buschard@uiuc.edu
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D: The `mem2reg' pass - promotes values stored in memory to registers
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N: Brendon Cahoon
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E: bcahoon@codeaurora.org
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D: Loop unrolling with run-time trip counts.
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N: Chandler Carruth
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E: chandlerc@gmail.com
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E: chandlerc@google.com
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D: Hashing algorithms and interfaces
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D: Inline cost analysis
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D: Machine block placement pass
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D: SROA
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N: Casey Carter
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E: ccarter@uiuc.edu
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D: Fixes to the Reassociation pass, various improvement patches
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N: Evan Cheng
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E: evan.cheng@apple.com
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D: ARM and X86 backends
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D: Instruction scheduler improvements
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D: Register allocator improvements
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D: Loop optimizer improvements
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D: Target-independent code generator improvements
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N: Dan Villiom Podlaski Christiansen
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E: danchr@gmail.com
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E: danchr@cs.au.dk
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W: http://villiom.dk
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D: LLVM Makefile improvements
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D: Clang diagnostic & driver tweaks
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S: Aarhus, Denmark
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N: Jeff Cohen
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E: jeffc@jolt-lang.org
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W: http://jolt-lang.org
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D: Native Win32 API portability layer
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N: John T. Criswell
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E: criswell@uiuc.edu
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D: Original Autoconf support, documentation improvements, bug fixes
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N: Anshuman Dasgupta
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E: adasgupt@codeaurora.org
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D: Deterministic finite automaton based infrastructure for VLIW packetization
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N: Stefanus Du Toit
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E: stefanus.du.toit@intel.com
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D: Bug fixes and minor improvements
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N: Rafael Avila de Espindola
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E: rafael@espindo.la
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D: MC and LLD work
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N: Dave Estes
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E: cestes@codeaurora.org
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D: AArch64 machine description for Cortex-A53
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N: Alkis Evlogimenos
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E: alkis@evlogimenos.com
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D: Linear scan register allocator, many codegen improvements, Java frontend
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N: Hal Finkel
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E: hfinkel@anl.gov
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D: Basic-block autovectorization, PowerPC backend improvements
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N: Eric Fiselier
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E: eric@efcs.ca
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D: LIT patches and documentation
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N: Ryan Flynn
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E: pizza@parseerror.com
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D: Miscellaneous bug fixes
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N: Brian Gaeke
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E: gaeke@uiuc.edu
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W: http://www.students.uiuc.edu/~gaeke/
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D: Portions of X86 static and JIT compilers; initial SparcV8 backend
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D: Dynamic trace optimizer
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D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
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N: Nicolas Geoffray
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E: nicolas.geoffray@lip6.fr
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W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
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D: PPC backend fixes for Linux
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N: Louis Gerbarg
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E: lgg@apple.com
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D: Portions of the PowerPC backend
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N: Saem Ghani
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E: saemghani@gmail.com
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D: Callgraph class cleanups
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N: Mikhail Glushenkov
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E: foldr@codedgers.com
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D: Author of llvmc2
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N: Dan Gohman
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E: llvm@sunfishcode.online
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D: Miscellaneous bug fixes
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D: WebAssembly Backend
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N: Renato Golin
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E: rengolin@systemcall.eu
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E: rengolin@gmail.com
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D: ARM/AArch64 back-end improvements
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D: Loop Vectorizer improvements
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D: Regression and Test Suite improvements
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D: Linux compatibility (GNU, musl, etc)
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D: Initial Linux kernel / Android support effort
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I: rengolin
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N: David Goodwin
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E: david@goodwinz.net
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D: Thumb-2 code generator
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N: David Greene
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E: greened@obbligato.org
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D: Miscellaneous bug fixes
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D: Register allocation refactoring
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N: Gabor Greif
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E: ggreif@gmail.com
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D: Improvements for space efficiency
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N: James Grosbach
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E: grosbach@apple.com
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I: grosbach
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D: SjLj exception handling support
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D: General fixes and improvements for the ARM back-end
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D: MCJIT
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D: ARM integrated assembler and assembly parser
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D: Led effort for the backend formerly known as ARM64
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N: Lang Hames
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E: lhames@gmail.com
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D: PBQP-based register allocator
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N: Gordon Henriksen
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E: gordonhenriksen@mac.com
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D: Pluggable GC support
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D: C interface
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D: Ocaml bindings
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N: Raul Fernandes Herbster
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E: raul@dsc.ufcg.edu.br
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D: JIT support for ARM
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N: Paolo Invernizzi
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E: arathorn@fastwebnet.it
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D: Visual C++ compatibility fixes
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N: Patrick Jenkins
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E: patjenk@wam.umd.edu
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D: Nightly Tester
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N: Tony(Yanjun) Jiang
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E: jtony@ca.ibm.com
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D: PowerPC Backend Developer
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D: Improvements to the PPC backend and miscellaneous bug fixes
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N: Dale Johannesen
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E: dalej@apple.com
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D: ARM constant islands improvements
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D: Tail merging improvements
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D: Rewrite X87 back end
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D: Use APFloat for floating point constants widely throughout compiler
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D: Implement X87 long double
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N: Brad Jones
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E: kungfoomaster@nondot.org
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D: Support for packed types
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N: Rod Kay
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E: rkay@auroraux.org
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D: Author of LLVM Ada bindings
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N: Erich Keane
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E: erich.keane@intel.com
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D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.
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I: ErichKeane
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N: Eric Kidd
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W: http://randomhacks.net/
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D: llvm-config script
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N: Anton Korobeynikov
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E: anton at korobeynikov dot info
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D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
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D: x86/linux PIC codegen, aliases, regparm/visibility attributes
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D: Switch lowering refactoring
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N: Sumant Kowshik
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E: kowshik@uiuc.edu
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D: Author of the original C backend
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269
N: Benjamin Kramer
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E: benny.kra@gmail.com
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D: Miscellaneous bug fixes
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N: Michael Kuperstein
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E: mkuper@google.com
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D: Loop Vectorizer
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N: Sundeep Kushwaha
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E: sundeepk@codeaurora.org
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D: Implemented DFA-based target independent VLIW packetizer
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N: Christopher Lamb
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E: christopher.lamb@gmail.com
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D: aligned load/store support, parts of noalias and restrict support
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D: vreg subreg infrastructure, X86 codegen improvements based on subregs
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D: address spaces
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N: Jim Laskey
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E: jlaskey@apple.com
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D: Improvements to the PPC backend, instruction scheduling
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D: Debug and Dwarf implementation
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D: Auto upgrade mangler
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D: llvm-gcc4 svn wrangler
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N: Chris Lattner
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E: sabre@nondot.org
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W: http://nondot.org/~sabre/
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D: Primary architect of LLVM
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N: Tanya Lattner (Tanya Brethour)
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E: tonic@nondot.org
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W: http://nondot.org/~tonic/
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D: The initial llvm-ar tool, converted regression testsuite to dejagnu
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D: Modulo scheduling in the SparcV9 backend
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D: Release manager (1.7+)
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N: Sylvestre Ledru
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E: sylvestre@debian.org
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W: http://sylvestre.ledru.info/
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W: https://apt.llvm.org/
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D: Debian and Ubuntu packaging
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D: Continuous integration with jenkins
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N: Andrew Lenharth
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E: alenhar2@cs.uiuc.edu
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W: http://www.lenharth.org/~andrewl/
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D: Alpha backend
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D: Sampling based profiling
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N: Nick Lewycky
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E: nicholas@mxc.ca
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D: PredicateSimplifier pass
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N: Tony Linthicum, et. al.
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E: tlinth@codeaurora.org
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D: Backend for Qualcomm's Hexagon VLIW processor.
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N: Bruno Cardoso Lopes
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E: bruno.cardoso@gmail.com
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I: bruno
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W: http://brunocardoso.cc
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D: Mips backend
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D: Random ARM integrated assembler and assembly parser improvements
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D: General X86 AVX1 support
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N: Weining Lu
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E: luweining@loongson.cn
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D: LoongArch backend
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N: Duraid Madina
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E: duraid@octopus.com.au
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W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
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D: IA64 backend, BigBlock register allocator
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N: John McCall
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E: rjmccall@apple.com
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D: Clang semantic analysis and IR generation
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N: Michael McCracken
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E: michael.mccracken@gmail.com
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D: Line number support for llvmgcc
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352
N: Fanbo Meng
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E: fanbo.meng@ibm.com
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D: z/OS support
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N: Vladimir Merzliakov
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E: wanderer@rsu.ru
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D: Test suite fixes for FreeBSD
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N: Scott Michel
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E: scottm@aero.org
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D: Added STI Cell SPU backend.
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N: Kai Nacke
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E: kai@redstar.de
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D: Support for implicit TLS model used with MS VC runtime
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D: Dumping of Win64 EH structures
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N: Takumi Nakamura
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I: chapuni
371
E: geek4civic@gmail.com
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E: chapuni@hf.rim.or.jp
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D: Maintaining the Git monorepo
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W: https://github.com/llvm-project/
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S: Ebina, Japan
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377
N: Edward O'Callaghan
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E: eocallaghan@auroraux.org
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W: http://www.auroraux.org
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D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
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D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
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D: and error clean ups.
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384
N: Morten Ofstad
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E: morten@hue.no
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D: Visual C++ compatibility fixes
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N: Jakob Stoklund Olesen
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E: stoklund@2pi.dk
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D: Machine code verifier
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D: Blackfin backend
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D: Fast register allocator
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D: Greedy register allocator
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395
N: Richard Osborne
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E: richard@xmos.com
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D: XCore backend
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399
N: Piotr Padlewski
400
E: piotr.padlewski@gmail.com
401
D: !invariant.group metadata and other intrinsics for devirtualization in clang
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403
N: Devang Patel
404
E: dpatel@apple.com
405
D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
406
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
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D: Optimizer improvements, Loop Index Split
408

409
N: Ana Pazos
410
E: apazos@codeaurora.org
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D: Fixes and improvements to the AArch64 backend
412

413
N: Wesley Peck
414
E: peckw@wesleypeck.com
415
W: http://wesleypeck.com/
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D: MicroBlaze backend
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418
N: Francois Pichet
419
E: pichet2000@gmail.com
420
D: MSVC support
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422
N: Simon Pilgrim
423
E: llvm-dev@redking.me.uk
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D: X86 backend, Selection DAG, Scheduler Models and Cost Tables.
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426
N: Adrian Prantl
427
E: aprantl@apple.com
428
D: Debug Information
429

430
N: Vladimir Prus
431
W: http://vladimir_prus.blogspot.com
432
E: ghost@cs.msu.su
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D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
434

435
N: QIU Chaofan
436
E: qiucofan@cn.ibm.com
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D: PowerPC Backend Developer
438

439
N: Kalle Raiskila
440
E: kalle.rasikila@nokia.com
441
D: Some bugfixes to CellSPU
442

443
N: Xerxes Ranby
444
E: xerxes@zafena.se
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D: Cmake dependency chain and various bug fixes
446

447
N: Alex Rosenberg
448
E: alexr@leftfield.org
449
I: arosenberg
450
D: ARM calling conventions rewrite, hard float support
451

452
N: Chad Rosier
453
E: mcrosier@codeaurora.org
454
I: mcrosier
455
D: AArch64 fast instruction selection pass
456
D: Fixes and improvements to the ARM fast-isel pass
457
D: Fixes and improvements to the AArch64 backend
458

459
N: Nadav Rotem
460
E: nadav.rotem@me.com
461
D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer
462

463
N: Roman Samoilov
464
E: roman@codedgers.com
465
D: MSIL backend
466

467
N: Duncan Sands
468
E: baldrick@free.fr
469
I: baldrick
470
D: Ada support in llvm-gcc
471
D: Dragonegg plugin
472
D: Exception handling improvements
473
D: Type legalizer rewrite
474

475
N: Ruchira Sasanka
476
E: sasanka@uiuc.edu
477
D: Graph coloring register allocator for the Sparc64 backend
478

479
N: Alina Sbirlea
480
E: alina.sbirlea@gmail.com
481
D: MemorySSA, BatchAA, misc loop and new pass manager work.
482

483
N: Arnold Schwaighofer
484
E: arnold.schwaighofer@gmail.com
485
D: Tail call optimization for the x86 backend
486

487
N: Shantonu Sen
488
E: ssen@apple.com
489
D: Miscellaneous bug fixes
490

491
N: Anand Shukla
492
E: ashukla@cs.uiuc.edu
493
D: The `paths' pass
494

495
N: Michael J. Spencer
496
E: bigcheesegs@gmail.com
497
D: Shepherding Windows COFF support into MC.
498
D: Lots of Windows stuff.
499

500
N: Reid Spencer
501
E: rspencer@reidspencer.com
502
W: http://reidspencer.com/
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D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
504

505
N: Abhina Sreeskantharajan
506
E: Abhina.Sreeskantharajan@ibm.com
507
D: z/OS support
508

509
N: Alp Toker
510
E: alp@nuanti.com
511
W: http://atoker.com/
512
D: C++ frontend next generation standards implementation
513

514
N: Craig Topper
515
E: craig.topper@gmail.com
516
D: X86 codegen and disassembler improvements. AVX2 support.
517

518
N: Edwin Torok
519
E: edwintorok@gmail.com
520
D: Miscellaneous bug fixes
521

522
N: Adam Treat
523
E: manyoso@yahoo.com
524
D: C++ bugs filed, and C++ front-end bug fixes.
525

526
N: Andrew Trick
527
E: atrick@apple.com
528
D: Instruction Scheduling, ...
529

530
N: Lauro Ramos Venancio
531
E: lauro.venancio@indt.org.br
532
D: ARM backend improvements
533
D: Thread Local Storage implementation
534

535
N: Phoebe Wang
536
E: phoebe.wang@intel.com
537
D: X86 bug fixes and new instruction support.
538

539
N: Bill Wendling
540
I: wendling
541
E: isanbard@gmail.com
542
D: Release manager, IR Linker, LTO.
543
D: Bunches of stuff.
544

545
N: Bob Wilson
546
E: bob.wilson@acm.org
547
D: Advanced SIMD (NEON) support in the ARM backend.
548

549
N: QingShan Zhang
550
N: steven.zhang
551
E: zhangqingshan.zll@bytedance.com
552

553
N: Li Jia He
554
E: hljhehlj@cn.ibm.com
555
D: PowerPC Backend Developer
556

557
N: Zi Xuan Wu
558
N: Zeson
559
E: zixuan.wu@linux.alibaba.com
560

561
N: Kang Zhang
562
E: shkzhang@cn.ibm.com
563
D: PowerPC Backend Developer
564

565
N: Zheng Chen
566
E: czhengsz@cn.ibm.com
567
D: PowerPC Backend Developer
568

569
N: Djordje Todorovic
570
E: djordje.todorovic@rt-rk.com
571
D: Debug Information
572

573
N: Biplob Mishra
574
E: biplmish@in.ibm.com
575
D: PowerPC Analysis
576