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* Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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#include "precompiled.hpp"
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#include "gc/shared/barrierSet.hpp"
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#include "gc/shared/c2/barrierSetC2.hpp"
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#include "gc/shared/collectedHeap.hpp"
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#include "memory/universe.hpp"
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#include "oops/compressedOops.hpp"
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#include "opto/machnode.hpp"
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#include "opto/output.hpp"
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#include "opto/regalloc.hpp"
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#include "utilities/vmError.hpp"
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//=============================================================================
37
// Return the value requested
38
// result register lookup, corresponding to int_format
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int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
40
return (int)ra_->get_encode(node);
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// input register lookup, corresponding to ext_format
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int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
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return (int)(ra_->get_encode(node->in(idx)));
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intptr_t MachOper::constant() const { return 0x00; }
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relocInfo::relocType MachOper::constant_reloc() const { return relocInfo::none; }
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jdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; }
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jfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; }
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jlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; }
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TypeOopPtr *MachOper::oop() const { return nullptr; }
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int MachOper::ccode() const { return 0x00; }
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// A zero, default, indicates this value is not needed.
54
// May need to lookup the base register, as done in int_ and ext_format
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int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::scale() const { return 0x00; }
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int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::constant_disp() const { return 0; }
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int MachOper::base_position() const { return -1; } // no base input
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int MachOper::index_position() const { return -1; } // no index input
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// Check for PC-Relative displacement
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relocInfo::relocType MachOper::disp_reloc() const { return relocInfo::none; }
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Label* MachOper::label() const { ShouldNotReachHere(); return 0; }
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intptr_t MachOper::method() const { ShouldNotReachHere(); return 0; }
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//------------------------------negate-----------------------------------------
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// Negate conditional branches. Error for non-branch operands
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void MachOper::negate() {
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//-----------------------------type--------------------------------------------
76
const Type *MachOper::type() const {
80
//------------------------------in_RegMask-------------------------------------
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const RegMask *MachOper::in_RegMask(int index) const {
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//------------------------------dump_spec--------------------------------------
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// Print any per-operand special info
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void MachOper::dump_spec(outputStream *st) const { }
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//------------------------------hash-------------------------------------------
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// Print any per-operand special info
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uint MachOper::hash() const {
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//------------------------------cmp--------------------------------------------
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// Print any per-operand special info
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bool MachOper::cmp( const MachOper &oper ) const {
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return opcode() == oper.opcode();
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//------------------------------hash-------------------------------------------
107
// Print any per-operand special info
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uint labelOper::hash() const {
112
//------------------------------cmp--------------------------------------------
113
// Print any per-operand special info
114
bool labelOper::cmp( const MachOper &oper ) const {
115
return (opcode() == oper.opcode()) && (_label == oper.label());
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//------------------------------hash-------------------------------------------
119
// Print any per-operand special info
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uint methodOper::hash() const {
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return (uint)_method;
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//------------------------------cmp--------------------------------------------
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// Print any per-operand special info
126
bool methodOper::cmp( const MachOper &oper ) const {
127
return (opcode() == oper.opcode()) && (_method == oper.method());
131
//=============================================================================
132
//------------------------------MachNode---------------------------------------
134
//------------------------------emit-------------------------------------------
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void MachNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
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tty->print("missing MachNode emit function: ");
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//---------------------------postalloc_expand----------------------------------
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// Expand node after register allocation.
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void MachNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {}
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//------------------------------size-------------------------------------------
148
// Size of instruction in bytes
149
uint MachNode::size(PhaseRegAlloc *ra_) const {
150
// If a virtual was not defined for this specific instruction,
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// Call the helper which finds the size by emitting the bits.
152
return MachNode::emit_size(ra_);
155
//------------------------------size-------------------------------------------
156
// Helper function that computes size by emitting code
157
uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
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// Emit into a trash buffer and count bytes emitted.
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assert(ra_ == ra_->C->regalloc(), "sanity");
160
return ra_->C->output()->scratch_emit_size(this);
165
//------------------------------hash-------------------------------------------
166
uint MachNode::hash() const {
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uint no = num_opnds();
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for( uint i=0; i<no; i++ )
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sum += _opnds[i]->hash();
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return sum+Node::hash();
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//-----------------------------cmp---------------------------------------------
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bool MachNode::cmp( const Node &node ) const {
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MachNode& n = *((Node&)node).as_Mach();
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uint no = num_opnds();
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if( no != n.num_opnds() ) return false;
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if( rule() != n.rule() ) return false;
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for( uint i=0; i<no; i++ ) // All operands must match
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if( !_opnds[i]->cmp( *n._opnds[i] ) )
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return false; // mis-matched operands
183
return true; // match
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void MachNode::fill_new_machnode(MachNode* node) const {
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// New node must use same node index
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// Copy machine-independent inputs
190
for (uint j = 0; j < req(); j++) {
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node->add_req(in(j));
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// Copy my operands, except for cisc position
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int nopnds = num_opnds();
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assert(node->num_opnds() == (uint)nopnds, "Must have same number of operands");
196
MachOper** to = node->_opnds;
197
for (int i = 0; i < nopnds; i++) {
198
if (i != cisc_operand()) {
199
to[i] = _opnds[i]->clone();
202
// Do not increment node index counter, since node reuses my index
203
Compile* C = Compile::current();
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C->set_unique(C->unique() - 1);
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// Return an equivalent instruction using memory for cisc_operand position
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MachNode *MachNode::cisc_version(int offset) {
213
void MachNode::use_cisc_RegMask() {
214
ShouldNotReachHere();
218
//-----------------------------in_RegMask--------------------------------------
219
const RegMask &MachNode::in_RegMask( uint idx ) const {
220
uint numopnds = num_opnds(); // Virtual call for number of operands
221
uint skipped = oper_input_base(); // Sum of leaves skipped so far
222
if( idx < skipped ) {
223
assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
224
assert( idx == 1, "expected base ptr here" );
225
// debug info can be anywhere
226
return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
228
uint opcnt = 1; // First operand
229
uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
230
while( idx >= skipped+num_edges ) {
231
skipped += num_edges;
232
opcnt++; // Bump operand count
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assert( opcnt < numopnds, "Accessing non-existent operand" );
234
num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
237
const RegMask *rm = cisc_RegMask();
238
if( rm == nullptr || (int)opcnt != cisc_operand() ) {
239
rm = _opnds[opcnt]->in_RegMask(idx-skipped);
244
//-----------------------------memory_inputs--------------------------------
245
const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
246
const MachOper* oper = memory_operand();
248
if (oper == (MachOper*)-1) {
250
index = NodeSentinel;
254
if (oper != nullptr) {
255
// It has a unique memory operand. Find its index.
256
int oper_idx = num_opnds();
257
while (--oper_idx >= 0) {
258
if (_opnds[oper_idx] == oper) break;
260
int oper_pos = operand_index(oper_idx);
261
int base_pos = oper->base_position();
263
base = _in[oper_pos+base_pos];
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int index_pos = oper->index_position();
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if (index_pos >= 0) {
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index = _in[oper_pos+index_pos];
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//-----------------------------get_base_and_disp----------------------------
276
const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
278
// Find the memory inputs using our helper function
281
const MachOper* oper = memory_inputs(base, index);
283
if (oper == nullptr) {
284
// Base has been set to null
286
} else if (oper == (MachOper*)-1) {
287
// Base has been set to NodeSentinel
288
// There is not a unique memory use here. We will fall to AliasIdxBot.
289
offset = Type::OffsetBot;
291
// Base may be null, even if offset turns out to be != 0
293
intptr_t disp = oper->constant_disp();
294
int scale = oper->scale();
295
// Now we have collected every part of the ADLC MEMORY_INTER.
296
// See if it adds up to a base + offset.
297
if (index != nullptr) {
298
const Type* t_index = index->bottom_type();
299
if (t_index->isa_narrowoop() || t_index->isa_narrowklass()) { // EncodeN, LoadN, LoadConN, LoadNKlass,
300
// EncodeNKlass, LoadConNklass.
301
// Memory references through narrow oops have a
302
// funny base so grab the type from the index:
303
// [R12 + narrow_oop_reg<<3 + offset]
304
assert(base == nullptr, "Memory references through narrow oops have no base");
306
adr_type = t_index->make_ptr()->add_offset(offset);
308
} else if (!index->is_Con()) {
309
disp = Type::OffsetBot;
310
} else if (disp != Type::OffsetBot) {
311
const TypeX* ti = t_index->isa_intptr_t();
313
disp = Type::OffsetBot; // a random constant??
315
disp += ti->get_con() << scale;
321
// In x86_32.ad, indOffset32X uses base==RegI and disp==RegP,
322
// this will prevent alias analysis without the following support:
323
// Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
324
// Add the offset determined by the "base", or use Type::OffsetBot.
325
if( adr_type == TYPE_PTR_SENTINAL ) {
326
const TypePtr *t_disp = oper->disp_as_type(); // only not null for indOffset32X
327
if (t_disp != nullptr) {
328
offset = Type::OffsetBot;
329
const Type* t_base = base->bottom_type();
330
if (t_base->isa_intptr_t()) {
331
const TypeX *t_offset = t_base->is_intptr_t();
332
if( t_offset->is_con() ) {
333
offset = t_offset->get_con();
336
adr_type = t_disp->add_offset(offset);
337
} else if( base == nullptr && offset != 0 && offset != Type::OffsetBot ) {
338
// Use ideal type if it is oop ptr.
339
const TypePtr *tp = oper->type()->isa_ptr();
351
//---------------------------------adr_type---------------------------------
352
const class TypePtr *MachNode::adr_type() const {
354
const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
355
const Node *base = get_base_and_disp(offset, adr_type);
356
if( adr_type != TYPE_PTR_SENTINAL ) {
357
return adr_type; // get_base_and_disp has the answer
361
if (base != nullptr && base->is_Mach() && base->as_Mach()->ideal_Opcode() == Op_VerifyVectorAlignment) {
362
// For VerifyVectorAlignment we just pass the type through
363
return base->bottom_type()->is_ptr();
367
// Direct addressing modes have no base node, simply an indirect
368
// offset, which is always to raw memory.
369
// %%%%% Someday we'd like to allow constant oop offsets which
370
// would let Intel load from static globals in 1 instruction.
371
// Currently Intel requires 2 instructions and a register temp.
372
if (base == nullptr) {
373
// null base, zero offset means no memory at all (a null pointer!)
377
// null base, any offset means any pointer whatever
378
if (offset == Type::OffsetBot) {
379
return TypePtr::BOTTOM;
381
// %%% make offset be intptr_t
382
assert(!Universe::heap()->is_in(cast_to_oop(offset)), "must be a raw ptr");
383
return TypeRawPtr::BOTTOM;
386
// base of -1 with no particular offset means all of memory
387
if (base == NodeSentinel) return TypePtr::BOTTOM;
389
const Type* t = base->bottom_type();
390
if (t->isa_narrowoop() && CompressedOops::shift() == 0) {
391
// 32-bit unscaled narrow oop can be the base of any address expression
394
if (t->isa_narrowklass() && CompressedKlassPointers::shift() == 0) {
395
// 32-bit unscaled narrow oop can be the base of any address expression
399
if (t->isa_intptr_t() &&
401
// AArch64 supports the addressing mode:
402
// [base, 0], in which [base] is converted from a long value
405
offset != Type::OffsetBot) {
406
// We cannot assert that the offset does not look oop-ish here.
407
// Depending on the heap layout the cardmark base could land
408
// inside some oopish region. It definitely does for Win2K.
409
// The sum of cardmark-base plus shift-by-9-oop lands outside
410
// the oop-ish area but we can't assert for that statically.
411
return TypeRawPtr::BOTTOM;
414
const TypePtr *tp = t->isa_ptr();
416
// be conservative if we do not recognize the type
418
assert(false, "this path may produce not optimal code");
419
return TypePtr::BOTTOM;
421
assert(tp->base() != Type::AnyPtr, "not a bare pointer");
423
return tp->add_offset(offset);
427
//-----------------------------operand_index---------------------------------
428
int MachNode::operand_index(uint operand) const {
429
if (operand < 1) return -1;
430
assert(operand < num_opnds(), "oob");
431
if (_opnds[operand]->num_edges() == 0) return -1;
433
uint skipped = oper_input_base(); // Sum of leaves skipped so far
434
for (uint opcnt = 1; opcnt < operand; opcnt++) {
435
uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
436
skipped += num_edges;
441
int MachNode::operand_index(const MachOper *oper) const {
442
uint skipped = oper_input_base(); // Sum of leaves skipped so far
444
for (opcnt = 1; opcnt < num_opnds(); opcnt++) {
445
if (_opnds[opcnt] == oper) break;
446
uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
447
skipped += num_edges;
449
if (_opnds[opcnt] != oper) return -1;
453
int MachNode::operand_index(Node* def) const {
454
uint skipped = oper_input_base(); // Sum of leaves skipped so far
455
for (uint opcnt = 1; opcnt < num_opnds(); opcnt++) {
456
uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
457
for (uint i = 0; i < num_edges; i++) {
458
if (in(skipped + i) == def) {
462
skipped += num_edges;
467
//------------------------------peephole---------------------------------------
468
// Apply peephole rule(s) to this instruction
469
int MachNode::peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_) {
473
//------------------------------add_case_label---------------------------------
474
// Adds the label for the case
475
void MachNode::add_case_label( int index_num, Label* blockLabel) {
479
//------------------------------method_set-------------------------------------
480
// Set the absolute address of a method
481
void MachNode::method_set( intptr_t addr ) {
485
//------------------------------rematerialize----------------------------------
486
bool MachNode::rematerialize() const {
487
// Temps are always rematerializable
488
if (is_MachTemp()) return true;
490
uint r = rule(); // Match rule
491
if (r < Matcher::_begin_rematerialize ||
492
r >= Matcher::_end_rematerialize) {
496
// For 2-address instructions, the input live range is also the output
497
// live range. Remateralizing does not make progress on the that live range.
498
if (two_adr()) return false;
500
// Check for rematerializing float constants, or not
501
if (!Matcher::rematerialize_float_constants) {
502
int op = ideal_Opcode();
503
if (op == Op_ConF || op == Op_ConD) {
508
// Defining flags - can't spill these! Must remateralize.
509
if (ideal_reg() == Op_RegFlags) {
513
// Stretching lots of inputs - don't do it.
514
// A MachContant has the last input being the constant base
515
if (req() > (is_MachConstant() ? 3U : 2U)) {
519
if (req() >= 2 && in(1) && in(1)->ideal_reg() == Op_RegFlags) {
520
// In(1) will be rematerialized, too.
521
// Stretching lots of inputs - don't do it.
522
if (in(1)->req() > (in(1)->is_MachConstant() ? 3U : 2U)) {
527
// Don't remateralize somebody with bound inputs - it stretches a
528
// fixed register lifetime.
529
uint idx = oper_input_base();
531
const RegMask &rm = in_RegMask(idx);
532
if (rm.is_NotEmpty() && rm.is_bound(ideal_reg())) {
541
//------------------------------dump_spec--------------------------------------
542
// Print any per-operand special info
543
void MachNode::dump_spec(outputStream *st) const {
544
uint cnt = num_opnds();
545
for( uint i=0; i<cnt; i++ ) {
546
if (_opnds[i] != nullptr) {
547
_opnds[i]->dump_spec(st);
552
const TypePtr *t = adr_type();
554
Compile* C = Compile::current();
555
if( C->alias_type(t)->is_volatile() )
556
st->print(" Volatile!");
558
if (barrier_data() != 0) {
559
st->print(" barrier(");
560
BarrierSet::barrier_set()->barrier_set_c2()->dump_barrier_data(this, st);
565
//------------------------------dump_format------------------------------------
567
void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
568
format(ra, st); // access to virtual
572
//=============================================================================
574
void MachTypeNode::dump_spec(outputStream *st) const {
575
MachNode::dump_spec(st);
576
if (_bottom_type != nullptr) {
577
_bottom_type->dump_on(st);
585
//=============================================================================
586
int MachConstantNode::constant_offset() {
587
// Bind the offset lazily.
588
if (_constant.offset() == -1) {
589
ConstantTable& constant_table = Compile::current()->output()->constant_table();
590
int offset = constant_table.find_offset(_constant);
591
// If called from Compile::scratch_emit_size return the
592
// pre-calculated offset.
593
// NOTE: If the AD file does some table base offset optimizations
594
// later the AD file needs to take care of this fact.
595
if (Compile::current()->output()->in_scratch_emit_size()) {
596
return constant_table.calculate_table_base_offset() + offset;
598
_constant.set_offset(constant_table.table_base_offset() + offset);
600
return _constant.offset();
603
int MachConstantNode::constant_offset_unchecked() const {
604
return _constant.offset();
607
//=============================================================================
609
void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
610
int reg = ra_->get_reg_first(in(1)->in(_vidx));
611
st->print("%s %s", Name(), Matcher::regName[reg]);
615
void MachNullCheckNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
616
// only emits entries in the null-pointer exception handler table
618
void MachNullCheckNode::label_set(Label* label, uint block_num) {
621
void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
625
const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
626
if( idx == 0 ) return RegMask::Empty;
627
else return in(1)->as_Mach()->out_RegMask();
630
//=============================================================================
631
const Type *MachProjNode::bottom_type() const {
632
if( _ideal_reg == fat_proj ) return Type::BOTTOM;
633
// Try the normal mechanism first
634
const Type *t = in(0)->bottom_type();
635
if( t->base() == Type::Tuple ) {
636
const TypeTuple *tt = t->is_tuple();
637
if (_con < tt->cnt())
638
return tt->field_at(_con);
640
// Else use generic type from ideal register set
641
assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
642
return Type::mreg2type[_ideal_reg];
645
const TypePtr *MachProjNode::adr_type() const {
646
if (bottom_type() == Type::MEMORY) {
647
// in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
649
if (ctrl == nullptr) return nullptr; // node is dead
650
const TypePtr* adr_type = ctrl->adr_type();
652
if (!VMError::is_error_reported() && !Node::in_dump())
653
assert(adr_type != nullptr, "source must have adr_type");
657
assert(bottom_type()->base() != Type::Memory, "no other memories?");
662
void MachProjNode::dump_spec(outputStream *st) const {
663
ProjNode::dump_spec(st);
664
switch (_ideal_reg) {
665
case unmatched_proj: st->print("/unmatched"); break;
666
case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(st); break;
671
//=============================================================================
673
void MachIfNode::dump_spec(outputStream *st) const {
674
st->print("P=%f, C=%f",_prob, _fcnt);
678
//=============================================================================
679
uint MachReturnNode::size_of() const { return sizeof(*this); }
681
//------------------------------Registers--------------------------------------
682
const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
686
const TypePtr *MachReturnNode::adr_type() const {
687
// most returns and calls are assumed to consume & modify all of memory
688
// the matcher will copy non-wide adr_types from ideal originals
692
//=============================================================================
693
const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
695
//------------------------------Registers--------------------------------------
696
const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
697
// Values in the domain use the users calling convention, embodied in the
698
// _in_rms array of RegMasks.
699
if( idx < TypeFunc::Parms ) return _in_rms[idx];
701
if (idx == TypeFunc::Parms &&
702
ideal_Opcode() == Op_SafePoint) {
703
return MachNode::in_RegMask(idx);
706
// Values outside the domain represent debug info
707
assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
708
return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
712
//=============================================================================
714
bool MachCallNode::cmp( const Node &n ) const
715
{ return _tf == ((MachCallNode&)n)._tf; }
716
const Type *MachCallNode::bottom_type() const { return tf()->range(); }
717
const Type* MachCallNode::Value(PhaseGVN* phase) const { return tf()->range(); }
720
void MachCallNode::dump_spec(outputStream *st) const {
722
if (tf() != nullptr) tf()->dump_on(st);
723
if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
724
if (jvms() != nullptr) jvms()->dump_spec(st);
729
bool MachCallNode::return_value_is_used() const {
730
if (tf()->range()->cnt() == TypeFunc::Parms) {
735
// find the projection corresponding to the return value
736
for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
737
Node *use = fast_out(i);
738
if (!use->is_Proj()) continue;
739
if (use->as_Proj()->_con == TypeFunc::Parms) {
747
// Similar to cousin class CallNode::returns_pointer
748
// Because this is used in deoptimization, we want the type info, not the data
749
// flow info; the interpreter will "use" things that are dead to the optimizer.
750
bool MachCallNode::returns_pointer() const {
751
const TypeTuple *r = tf()->range();
752
return (r->cnt() > TypeFunc::Parms &&
753
r->field_at(TypeFunc::Parms)->isa_ptr());
756
//------------------------------Registers--------------------------------------
757
const RegMask &MachCallNode::in_RegMask(uint idx) const {
758
// Values in the domain use the users calling convention, embodied in the
759
// _in_rms array of RegMasks.
760
if (idx < tf()->domain()->cnt()) {
763
if (idx == mach_constant_base_node_input()) {
764
return MachConstantBaseNode::static_out_RegMask();
766
// Values outside the domain represent debug info
767
return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
770
//=============================================================================
771
uint MachCallJavaNode::size_of() const { return sizeof(*this); }
772
bool MachCallJavaNode::cmp( const Node &n ) const {
773
MachCallJavaNode &call = (MachCallJavaNode&)n;
774
return MachCallNode::cmp(call) && _method->equals(call._method) &&
775
_override_symbolic_info == call._override_symbolic_info;
778
void MachCallJavaNode::dump_spec(outputStream *st) const {
779
if (_method_handle_invoke)
780
st->print("MethodHandle ");
782
_method->print_short_name(st);
785
MachCallNode::dump_spec(st);
789
//------------------------------Registers--------------------------------------
790
const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
791
// Values in the domain use the users calling convention, embodied in the
792
// _in_rms array of RegMasks.
793
if (idx < tf()->domain()->cnt()) {
796
if (idx == mach_constant_base_node_input()) {
797
return MachConstantBaseNode::static_out_RegMask();
799
// Values outside the domain represent debug info
800
Matcher* m = Compile::current()->matcher();
801
// If this call is a MethodHandle invoke we have to use a different
802
// debugmask which does not include the register we use to save the
803
// SP over MH invokes.
804
RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
805
return *debugmask[in(idx)->ideal_reg()];
808
//=============================================================================
809
uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
810
bool MachCallStaticJavaNode::cmp( const Node &n ) const {
811
MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
812
return MachCallJavaNode::cmp(call) && _name == call._name;
815
//----------------------------uncommon_trap_request----------------------------
816
// If this is an uncommon trap, return the request code, else zero.
817
int MachCallStaticJavaNode::uncommon_trap_request() const {
818
if (_name != nullptr && !strcmp(_name, "uncommon_trap")) {
819
return CallStaticJavaNode::extract_uncommon_trap_request(this);
825
// Helper for summarizing uncommon_trap arguments.
826
void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
827
int trap_req = uncommon_trap_request();
831
Deoptimization::format_trap_request(buf, sizeof(buf),
836
void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
837
st->print("Static ");
838
if (_name != nullptr) {
839
st->print("wrapper for: %s", _name );
843
MachCallJavaNode::dump_spec(st);
847
//=============================================================================
849
void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
850
st->print("Dynamic ");
851
MachCallJavaNode::dump_spec(st);
854
//=============================================================================
855
uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
856
bool MachCallRuntimeNode::cmp( const Node &n ) const {
857
MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
858
return MachCallNode::cmp(call) && !strcmp(_name,call._name);
861
void MachCallRuntimeNode::dump_spec(outputStream *st) const {
862
st->print("%s ",_name);
863
MachCallNode::dump_spec(st);
866
//=============================================================================
867
// A shared JVMState for all HaltNodes. Indicates the start of debug info
868
// is at TypeFunc::Parms. Only required for SOE register spill handling -
869
// to indicate where the stack-slot-only debug info inputs begin.
870
// There is no other JVM state needed here.
871
JVMState jvms_for_throw(0);
872
JVMState *MachHaltNode::jvms() const {
873
return &jvms_for_throw;
876
uint MachMemBarNode::size_of() const { return sizeof(*this); }
878
const TypePtr *MachMemBarNode::adr_type() const {
883
//=============================================================================
885
void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
886
st->print("B%d", _block_num);
890
//=============================================================================
892
void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
893
st->print(INTPTR_FORMAT, _method);