25
#include "precompiled.hpp"
26
#include "asm/macroAssembler.hpp"
27
#include "asm/macroAssembler.inline.hpp"
28
#include "classfile/vmIntrinsics.hpp"
29
#include "code/codeBlob.hpp"
30
#include "compiler/compilerDefinitions.inline.hpp"
32
#include "logging/log.hpp"
33
#include "logging/logStream.hpp"
34
#include "memory/resourceArea.hpp"
35
#include "memory/universe.hpp"
36
#include "runtime/globals_extension.hpp"
37
#include "runtime/java.hpp"
38
#include "runtime/os.inline.hpp"
39
#include "runtime/stubCodeGenerator.hpp"
40
#include "runtime/vm_version.hpp"
41
#include "utilities/checkedCast.hpp"
42
#include "utilities/powerOfTwo.hpp"
43
#include "utilities/virtualizationSupport.hpp"
46
int VM_Version::_model;
47
int VM_Version::_stepping;
48
bool VM_Version::_has_intel_jcc_erratum;
49
VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
51
#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
52
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
53
#undef DECLARE_CPU_FEATURE_FLAG
56
address VM_Version::_cpuinfo_segv_addr = 0;
58
address VM_Version::_cpuinfo_cont_addr = 0;
60
address VM_Version::_cpuinfo_segv_addr_apx = 0;
62
address VM_Version::_cpuinfo_cont_addr_apx = 0;
64
static BufferBlob* stub_blob;
65
static const int stub_size = 2000;
68
typedef void (*get_cpu_info_stub_t)(void*);
69
typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
70
typedef void (*clear_apx_test_state_t)(void);
72
static get_cpu_info_stub_t get_cpu_info_stub = nullptr;
73
static detect_virt_stub_t detect_virt_stub = nullptr;
74
static clear_apx_test_state_t clear_apx_test_state_stub = nullptr;
78
bool VM_Version::supports_clflush() {
88
assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
93
#define CPUID_STANDARD_FN 0x0
94
#define CPUID_STANDARD_FN_1 0x1
95
#define CPUID_STANDARD_FN_4 0x4
96
#define CPUID_STANDARD_FN_B 0xb
98
#define CPUID_EXTENDED_FN 0x80000000
99
#define CPUID_EXTENDED_FN_1 0x80000001
100
#define CPUID_EXTENDED_FN_2 0x80000002
101
#define CPUID_EXTENDED_FN_3 0x80000003
102
#define CPUID_EXTENDED_FN_4 0x80000004
103
#define CPUID_EXTENDED_FN_7 0x80000007
104
#define CPUID_EXTENDED_FN_8 0x80000008
106
class VM_Version_StubGenerator: public StubCodeGenerator {
109
VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
112
address clear_apx_test_state() {
114
address start = __ pc();
119
bool save_apx = UseAPX;
120
VM_Version::set_apx_cpuFeatures();
126
VM_Version::clean_cpuFeatures();
132
address generate_get_cpu_info() {
134
const uint32_t HS_EFL_AC = 0x40000;
135
const uint32_t HS_EFL_ID = 0x200000;
137
const int CPU_FAMILY_SHIFT = 8;
138
const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
139
const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
140
bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
142
Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
143
Label sef_cpuid, sefsl1_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7;
144
Label ext_cpuid8, done, wrapup, vector_save_restore, apx_save_restore_warning;
145
Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
147
StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
150
address start = __ pc();
159
__ mov(rbp, c_rarg0);
161
__ movptr(rbp, Address(rsp, 8));
172
__ xorl(rax, HS_EFL_AC);
178
__ jccb(Assembler::notEqual, detect_486);
180
__ movl(rax, CPU_FAMILY_386);
181
__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
190
__ xorl(rax, HS_EFL_ID);
196
__ jccb(Assembler::notEqual, detect_586);
199
__ movl(rax, CPU_FAMILY_486);
200
__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
210
__ jcc(Assembler::equal, cpu486);
213
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
214
__ movl(Address(rsi, 0), rax);
215
__ movl(Address(rsi, 4), rbx);
216
__ movl(Address(rsi, 8), rcx);
217
__ movl(Address(rsi,12), rdx);
220
__ jccb(Assembler::belowEqual, std_cpuid4);
229
__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
230
__ movl(Address(rsi, 0), rax);
231
__ movl(Address(rsi, 4), rbx);
232
__ movl(Address(rsi, 8), rcx);
233
__ movl(Address(rsi,12), rdx);
241
__ andl(rax, 0xffff);
243
__ jccb(Assembler::equal, std_cpuid4);
245
__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
246
__ movl(Address(rsi, 0), rax);
247
__ movl(Address(rsi, 4), rbx);
248
__ movl(Address(rsi, 8), rcx);
249
__ movl(Address(rsi,12), rdx);
257
__ andl(rax, 0xffff);
259
__ jccb(Assembler::equal, std_cpuid4);
261
__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
262
__ movl(Address(rsi, 0), rax);
263
__ movl(Address(rsi, 4), rbx);
264
__ movl(Address(rsi, 8), rcx);
265
__ movl(Address(rsi,12), rdx);
272
__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
273
__ jccb(Assembler::greater, std_cpuid1);
281
__ jccb(Assembler::equal, std_cpuid1);
283
__ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
284
__ movl(Address(rsi, 0), rax);
285
__ movl(Address(rsi, 4), rbx);
286
__ movl(Address(rsi, 8), rcx);
287
__ movl(Address(rsi,12), rdx);
295
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
296
__ movl(Address(rsi, 0), rax);
297
__ movl(Address(rsi, 4), rbx);
298
__ movl(Address(rsi, 8), rcx);
299
__ movl(Address(rsi,12), rdx);
305
__ andl(rcx, 0x18000000);
306
__ cmpl(rcx, 0x18000000);
307
__ jccb(Assembler::notEqual, sef_cpuid);
314
__ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
315
__ movl(Address(rsi, 0), rax);
316
__ movl(Address(rsi, 4), rdx);
323
__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
324
__ jccb(Assembler::greater, ext_cpuid);
328
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
329
__ movl(Address(rsi, 0), rax);
330
__ movl(Address(rsi, 4), rbx);
331
__ movl(Address(rsi, 8), rcx);
332
__ movl(Address(rsi, 12), rdx);
337
__ bind(sefsl1_cpuid);
341
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sefsl1_cpuid7_offset())));
342
__ movl(Address(rsi, 0), rax);
343
__ movl(Address(rsi, 4), rdx);
349
__ movl(rax, 0x80000000);
351
__ cmpl(rax, 0x80000000);
352
__ jcc(Assembler::belowEqual, done);
353
__ cmpl(rax, 0x80000004);
354
__ jcc(Assembler::belowEqual, ext_cpuid1);
355
__ cmpl(rax, 0x80000006);
356
__ jccb(Assembler::belowEqual, ext_cpuid5);
357
__ cmpl(rax, 0x80000007);
358
__ jccb(Assembler::belowEqual, ext_cpuid7);
359
__ cmpl(rax, 0x80000008);
360
__ jccb(Assembler::belowEqual, ext_cpuid8);
361
__ cmpl(rax, 0x8000001E);
362
__ jccb(Assembler::below, ext_cpuid8);
366
__ movl(rax, 0x8000001E);
368
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
369
__ movl(Address(rsi, 0), rax);
370
__ movl(Address(rsi, 4), rbx);
371
__ movl(Address(rsi, 8), rcx);
372
__ movl(Address(rsi,12), rdx);
378
__ movl(rax, 0x80000008);
380
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
381
__ movl(Address(rsi, 0), rax);
382
__ movl(Address(rsi, 4), rbx);
383
__ movl(Address(rsi, 8), rcx);
384
__ movl(Address(rsi,12), rdx);
390
__ movl(rax, 0x80000007);
392
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
393
__ movl(Address(rsi, 0), rax);
394
__ movl(Address(rsi, 4), rbx);
395
__ movl(Address(rsi, 8), rcx);
396
__ movl(Address(rsi,12), rdx);
402
__ movl(rax, 0x80000005);
404
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
405
__ movl(Address(rsi, 0), rax);
406
__ movl(Address(rsi, 4), rbx);
407
__ movl(Address(rsi, 8), rcx);
408
__ movl(Address(rsi,12), rdx);
414
__ movl(rax, 0x80000001);
416
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
417
__ movl(Address(rsi, 0), rax);
418
__ movl(Address(rsi, 4), rbx);
419
__ movl(Address(rsi, 8), rcx);
420
__ movl(Address(rsi,12), rdx);
429
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sefsl1_cpuid7_offset())));
430
__ movl(rax, 0x200000);
431
__ andl(rax, Address(rsi, 4));
432
__ cmpl(rax, 0x200000);
433
__ jcc(Assembler::notEqual, vector_save_restore);
435
__ movl(rax, 0x80000);
436
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
437
__ cmpl(rax, 0x80000);
438
__ jcc(Assembler::notEqual, vector_save_restore);
440
bool save_apx = UseAPX;
441
VM_Version::set_apx_cpuFeatures();
443
__ mov64(r16, VM_Version::egpr_test_value());
444
__ mov64(r31, VM_Version::egpr_test_value());
446
VM_Version::set_cpuinfo_segv_addr_apx(__ pc());
448
__ movl(rax, Address(rsi, 0));
450
VM_Version::set_cpuinfo_cont_addr_apx(__ pc());
451
__ lea(rsi, Address(rbp, in_bytes(VM_Version::apx_save_offset())));
452
__ movq(Address(rsi, 0), r16);
453
__ movq(Address(rsi, 8), r31);
457
__ bind(vector_save_restore);
462
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
463
__ movl(rcx, 0x18000000);
464
__ andl(rcx, Address(rsi, 8));
465
__ cmpl(rcx, 0x18000000);
466
__ jccb(Assembler::notEqual, done);
469
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
471
__ jccb(Assembler::equal, start_simd_check);
477
__ bind(start_simd_check);
484
int saved_useavx = UseAVX;
485
int saved_usesse = UseSSE;
490
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
491
__ movl(rax, 0x10000);
492
__ andl(rax, Address(rsi, 4));
493
__ cmpl(rax, 0x10000);
494
__ jccb(Assembler::notEqual, legacy_setup);
499
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
501
__ jccb(Assembler::notEqual, legacy_setup);
503
if (FLAG_IS_DEFAULT(UseAVX)) {
504
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
505
__ movl(rax, Address(rsi, 0));
506
__ cmpl(rax, 0x50654);
507
__ jcc(Assembler::equal, legacy_setup);
510
VM_Version::set_evex_cpuFeatures();
517
__ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
520
__ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
522
__ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
527
__ movl(rcx, VM_Version::ymm_test_value());
529
__ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
530
__ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
532
__ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
533
__ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
535
VM_Version::clean_cpuFeatures();
536
__ jmp(save_restore_except);
539
__ bind(legacy_setup);
541
VM_Version::set_avx_cpuFeatures();
546
__ vmovdqu(Address(rsp, 0), xmm7);
549
__ vmovdqu(Address(rsp, 0), xmm8);
551
__ vmovdqu(Address(rsp, 0), xmm15);
556
__ movl(rcx, VM_Version::ymm_test_value());
559
__ pshufd(xmm0, xmm0, 0x00);
560
__ vinsertf128_high(xmm0, xmm0);
561
__ vmovdqu(xmm7, xmm0);
563
__ vmovdqu(xmm8, xmm0);
564
__ vmovdqu(xmm15, xmm0);
566
VM_Version::clean_cpuFeatures();
568
__ bind(save_restore_except);
570
VM_Version::set_cpuinfo_segv_addr(__ pc());
572
__ movl(rax, Address(rsi, 0));
574
VM_Version::set_cpuinfo_cont_addr(__ pc());
580
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
581
__ movl(rax, 0x10000);
582
__ andl(rax, Address(rsi, 4));
583
__ cmpl(rax, 0x10000);
584
__ jcc(Assembler::notEqual, legacy_save_restore);
589
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
591
__ jcc(Assembler::notEqual, legacy_save_restore);
593
if (FLAG_IS_DEFAULT(UseAVX)) {
594
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
595
__ movl(rax, Address(rsi, 0));
596
__ cmpl(rax, 0x50654);
597
__ jcc(Assembler::equal, legacy_save_restore);
600
VM_Version::set_evex_cpuFeatures();
603
__ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
604
__ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
605
__ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
607
__ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
608
__ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
613
__ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
615
__ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
618
__ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
621
generate_vzeroupper(wrapup);
622
VM_Version::clean_cpuFeatures();
623
UseAVX = saved_useavx;
624
UseSSE = saved_usesse;
628
__ bind(legacy_save_restore);
630
VM_Version::set_avx_cpuFeatures();
633
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
634
__ vmovdqu(Address(rsi, 0), xmm0);
635
__ vmovdqu(Address(rsi, 32), xmm7);
637
__ vmovdqu(Address(rsi, 64), xmm8);
638
__ vmovdqu(Address(rsi, 96), xmm15);
643
__ vmovdqu(xmm15, Address(rsp, 0));
645
__ vmovdqu(xmm8, Address(rsp, 0));
648
__ vmovdqu(xmm7, Address(rsp, 0));
652
generate_vzeroupper(wrapup);
653
VM_Version::clean_cpuFeatures();
654
UseAVX = saved_useavx;
655
UseSSE = saved_usesse;
668
void generate_vzeroupper(Label& L_wrapup) {
670
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
671
__ cmpl(Address(rsi, 4), 0x756e6547);
672
__ jcc(Assembler::notEqual, L_wrapup);
673
__ movl(rcx, 0x0FFF0FF0);
674
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
675
__ andl(rcx, Address(rsi, 0));
676
__ cmpl(rcx, 0x00050670);
677
__ jcc(Assembler::equal, L_wrapup);
678
__ cmpl(rcx, 0x00080650);
679
__ jcc(Assembler::equal, L_wrapup);
683
__ vzeroupper_uncached();
686
address generate_detect_virt() {
687
StubCodeMark mark(this, "VM_Version", "detect_virt_stub");
690
address start = __ pc();
698
__ mov(rax, c_rarg0);
699
__ mov(rsi, c_rarg1);
701
__ movptr(rax, Address(rsp, 16));
702
__ movptr(rsi, Address(rsp, 20));
708
__ movl(Address(rsi, 0), rax);
709
__ movl(Address(rsi, 4), rbx);
710
__ movl(Address(rsi, 8), rcx);
711
__ movl(Address(rsi, 12), rdx);
725
address generate_getCPUIDBrandString(void) {
727
const uint32_t HS_EFL_AC = 0x40000;
728
const uint32_t HS_EFL_ID = 0x200000;
730
const int CPU_FAMILY_SHIFT = 8;
731
const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
732
const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
734
Label detect_486, cpu486, detect_586, done, ext_cpuid;
736
StubCodeMark mark(this, "VM_Version", "getCPUIDNameInfo_stub");
739
address start = __ pc();
748
__ mov(rbp, c_rarg0);
750
__ movptr(rbp, Address(rsp, 8));
761
__ xorl(rax, HS_EFL_AC);
767
__ jccb(Assembler::notEqual, detect_486);
769
__ movl(rax, CPU_FAMILY_386);
778
__ xorl(rax, HS_EFL_ID);
784
__ jccb(Assembler::notEqual, detect_586);
787
__ movl(rax, CPU_FAMILY_486);
797
__ jcc(Assembler::equal, cpu486);
805
__ movl(rax, CPUID_EXTENDED_FN);
807
__ cmpl(rax, CPUID_EXTENDED_FN_4);
808
__ jcc(Assembler::below, done);
813
__ movl(rax, CPUID_EXTENDED_FN_2);
815
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_0_offset())));
816
__ movl(Address(rsi, 0), rax);
817
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_1_offset())));
818
__ movl(Address(rsi, 0), rbx);
819
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_2_offset())));
820
__ movl(Address(rsi, 0), rcx);
821
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_3_offset())));
822
__ movl(Address(rsi,0), rdx);
827
__ movl(rax, CPUID_EXTENDED_FN_3);
829
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_4_offset())));
830
__ movl(Address(rsi, 0), rax);
831
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_5_offset())));
832
__ movl(Address(rsi, 0), rbx);
833
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_6_offset())));
834
__ movl(Address(rsi, 0), rcx);
835
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_7_offset())));
836
__ movl(Address(rsi,0), rdx);
841
__ movl(rax, CPUID_EXTENDED_FN_4);
843
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_8_offset())));
844
__ movl(Address(rsi, 0), rax);
845
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_9_offset())));
846
__ movl(Address(rsi, 0), rbx);
847
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_10_offset())));
848
__ movl(Address(rsi, 0), rcx);
849
__ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_11_offset())));
850
__ movl(Address(rsi,0), rdx);
868
void VM_Version::get_processor_features() {
874
_logical_processors_per_package = 1;
876
_L1_data_cache_line_size = 16;
880
get_cpu_info_stub(&_cpuid_info);
882
assert_is_initialized();
883
_cpu = extended_cpu_family();
884
_model = extended_cpu_model();
885
_stepping = cpu_stepping();
887
if (cpu_family() > 4) {
888
_features = _cpuid_info.feature_flags();
889
_cpu_features = _features;
892
_logical_processors_per_package = logical_processor_count();
893
_L1_data_cache_line_size = L1_line_size();
897
_supports_atomic_getset4 = true;
898
_supports_atomic_getadd4 = true;
899
LP64_ONLY(_supports_atomic_getset8 = true);
900
LP64_ONLY(_supports_atomic_getadd8 = true);
904
if (!VM_Version::supports_sse2()) {
905
vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
908
if (UseSSE < 2) UseSSE = 2;
920
guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
922
guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
929
if (os::supports_map_sync()) {
932
_data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
937
if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && cpu_family() == 6 &&
938
(_model == 0x97 || _model == 0xAA || _model == 0xAC || _model == 0xAF)) {
939
FLAG_SET_DEFAULT(EnableX86ECoreOpts, true);
943
_features &= ~CPU_SSE4_1;
944
_features &= ~CPU_SSE4_2;
948
_features &= ~CPU_SSE3;
949
_features &= ~CPU_SSSE3;
950
_features &= ~CPU_SSE4A;
954
_features &= ~CPU_SSE2;
957
_features &= ~CPU_SSE;
960
if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
967
int use_sse_limit = 0;
969
if (UseSSE > 3 && supports_sse4_1()) {
971
} else if (UseSSE > 2 && supports_sse3()) {
973
} else if (UseSSE > 1 && supports_sse2()) {
975
} else if (UseSSE > 0 && supports_sse()) {
981
if (FLAG_IS_DEFAULT(UseSSE)) {
982
FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
983
} else if (UseSSE > use_sse_limit) {
984
warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", UseSSE, use_sse_limit);
985
FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
989
int use_avx_limit = 0;
994
} else if (UseAVX > 2 && supports_evex()) {
996
} else if (UseAVX > 1 && supports_avx2()) {
998
} else if (UseAVX > 0 && supports_avx()) {
1004
if (FLAG_IS_DEFAULT(UseAVX)) {
1006
if (use_avx_limit > 2 && is_intel_skylake() && _stepping < 5) {
1007
FLAG_SET_DEFAULT(UseAVX, 2);
1009
FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
1013
if (UseAVX > use_avx_limit) {
1015
warning("UseAVX=%d requires UseSSE=4, setting it to UseAVX=0", UseAVX);
1017
warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", UseAVX, use_avx_limit);
1019
FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
1023
_features &= ~CPU_AVX512F;
1024
_features &= ~CPU_AVX512DQ;
1025
_features &= ~CPU_AVX512CD;
1026
_features &= ~CPU_AVX512BW;
1027
_features &= ~CPU_AVX512VL;
1028
_features &= ~CPU_AVX512_VPOPCNTDQ;
1029
_features &= ~CPU_AVX512_VPCLMULQDQ;
1030
_features &= ~CPU_AVX512_VAES;
1031
_features &= ~CPU_AVX512_VNNI;
1032
_features &= ~CPU_AVX512_VBMI;
1033
_features &= ~CPU_AVX512_VBMI2;
1034
_features &= ~CPU_AVX512_BITALG;
1035
_features &= ~CPU_AVX512_IFMA;
1036
_features &= ~CPU_APX_F;
1040
bool apx_supported = os_supports_apx_egprs() && supports_apx_f() && supports_avx512vl();
1041
if (UseAPX && !apx_supported) {
1042
warning("UseAPX is not supported on this CPU, setting it to false");
1043
FLAG_SET_DEFAULT(UseAPX, false);
1044
} else if (FLAG_IS_DEFAULT(UseAPX)) {
1045
FLAG_SET_DEFAULT(UseAPX, apx_supported ? true : false);
1049
_features &= ~CPU_AVX2;
1050
_features &= ~CPU_AVX_IFMA;
1054
_features &= ~CPU_AVX;
1055
_features &= ~CPU_VZEROUPPER;
1056
_features &= ~CPU_F16C;
1059
if (logical_processors_per_package() == 1) {
1061
_features &= ~CPU_HT;
1065
if (is_knights_family()) {
1066
_features &= ~CPU_VZEROUPPER;
1067
_features &= ~CPU_AVX512BW;
1068
_features &= ~CPU_AVX512VL;
1069
_features &= ~CPU_AVX512DQ;
1070
_features &= ~CPU_AVX512_VNNI;
1071
_features &= ~CPU_AVX512_VAES;
1072
_features &= ~CPU_AVX512_VPOPCNTDQ;
1073
_features &= ~CPU_AVX512_VPCLMULQDQ;
1074
_features &= ~CPU_AVX512_VBMI;
1075
_features &= ~CPU_AVX512_VBMI2;
1076
_features &= ~CPU_CLWB;
1077
_features &= ~CPU_FLUSHOPT;
1078
_features &= ~CPU_GFNI;
1079
_features &= ~CPU_AVX512_BITALG;
1080
_features &= ~CPU_AVX512_IFMA;
1081
_features &= ~CPU_AVX_IFMA;
1085
if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
1086
_has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
1088
_has_intel_jcc_erratum = IntelJccErratumMitigation;
1092
int res = jio_snprintf(
1094
"(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x",
1095
cores_per_cpu(), threads_per_core(),
1096
cpu_family(), _model, _stepping, os::cpu_microcode_revision());
1097
assert(res > 0, "not enough temporary space allocated");
1098
insert_features_names(buf + res, sizeof(buf) - res, _features_names);
1100
_features_string = os::strdup(buf);
1103
if (supports_aes()) {
1104
if (FLAG_IS_DEFAULT(UseAES)) {
1105
FLAG_SET_DEFAULT(UseAES, true);
1108
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1109
warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
1111
FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1114
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1115
FLAG_SET_DEFAULT(UseAESIntrinsics, true);
1120
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1121
warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
1123
FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1127
if (!UseAESIntrinsics) {
1128
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1129
warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
1130
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1133
if (supports_sse4_1()) {
1134
if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1135
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
1140
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1141
warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
1143
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1148
} else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
1149
if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
1150
warning("AES instructions are not available on this CPU");
1151
FLAG_SET_DEFAULT(UseAES, false);
1153
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1154
warning("AES intrinsics are not available on this CPU");
1155
FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1157
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1158
warning("AES-CTR intrinsics are not available on this CPU");
1159
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1164
if (supports_clmul()) {
1165
if (FLAG_IS_DEFAULT(UseCLMUL)) {
1168
} else if (UseCLMUL) {
1169
if (!FLAG_IS_DEFAULT(UseCLMUL))
1170
warning("CLMUL instructions not available on this CPU (AVX may also be required)");
1171
FLAG_SET_DEFAULT(UseCLMUL, false);
1174
if (UseCLMUL && (UseSSE > 2)) {
1175
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
1176
UseCRC32Intrinsics = true;
1178
} else if (UseCRC32Intrinsics) {
1179
if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
1180
warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
1181
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
1185
if (supports_avx2()) {
1186
if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
1187
UseAdler32Intrinsics = true;
1189
} else if (UseAdler32Intrinsics) {
1190
if (!FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
1191
warning("Adler32 Intrinsics requires avx2 instructions (not available on this CPU)");
1193
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
1196
if (UseAdler32Intrinsics) {
1197
warning("Adler32Intrinsics not available on this CPU.");
1198
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
1202
if (supports_sse4_2() && supports_clmul()) {
1203
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
1204
UseCRC32CIntrinsics = true;
1206
} else if (UseCRC32CIntrinsics) {
1207
if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
1208
warning("CRC32C intrinsics are not available on this CPU");
1210
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
1214
if (UseCLMUL && (UseSSE > 2)) {
1215
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
1216
UseGHASHIntrinsics = true;
1218
} else if (UseGHASHIntrinsics) {
1219
if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
1220
warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
1221
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
1231
if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
1232
UseChaCha20Intrinsics = true;
1234
} else if (UseChaCha20Intrinsics) {
1235
if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
1236
warning("ChaCha20 intrinsic requires AVX instructions");
1238
FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
1242
if (UseChaCha20Intrinsics) {
1243
warning("ChaCha20 intrinsics are not available on this CPU.");
1244
FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
1250
if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
1251
UseBASE64Intrinsics = true;
1253
} else if (UseBASE64Intrinsics) {
1254
if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
1255
warning("Base64 intrinsic requires EVEX instructions on this CPU");
1256
FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
1259
if (supports_fma() && UseSSE >= 2) {
1260
if (FLAG_IS_DEFAULT(UseFMA)) {
1263
} else if (UseFMA) {
1264
warning("FMA instructions are not available on this CPU");
1265
FLAG_SET_DEFAULT(UseFMA, false);
1268
if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
1269
UseMD5Intrinsics = true;
1272
if (supports_sha() LP64_ONLY(|| (supports_avx2() && supports_bmi2()))) {
1273
if (FLAG_IS_DEFAULT(UseSHA)) {
1276
} else if (UseSHA) {
1277
warning("SHA instructions are not available on this CPU");
1278
FLAG_SET_DEFAULT(UseSHA, false);
1281
if (supports_sha() && supports_sse4_1() && UseSHA) {
1282
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
1283
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
1285
} else if (UseSHA1Intrinsics) {
1286
warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
1287
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
1290
if (supports_sse4_1() && UseSHA) {
1291
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
1292
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
1294
} else if (UseSHA256Intrinsics) {
1295
warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
1296
FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
1301
if (UseSHA && supports_avx2() && supports_bmi2()) {
1302
if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1303
FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1307
if (UseSHA512Intrinsics) {
1308
warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1309
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1312
if (UseSHA3Intrinsics) {
1313
warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
1314
FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
1317
if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
1318
FLAG_SET_DEFAULT(UseSHA, false);
1322
if (UseFPUForSpilling) {
1325
FLAG_SET_DEFAULT(UseFPUForSpilling, false);
1330
#if COMPILER2_OR_JVMCI
1331
int max_vector_size = 0;
1335
max_vector_size = 0;
1336
} else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1338
max_vector_size = 16;
1339
} else if (UseAVX == 1 || UseAVX == 2) {
1341
max_vector_size = 32;
1342
} else if (UseAVX > 2) {
1344
max_vector_size = 64;
1348
int min_vector_size = 4;
1350
int min_vector_size = 0;
1353
if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1354
if (MaxVectorSize < min_vector_size) {
1355
warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1356
FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1358
if (MaxVectorSize > max_vector_size) {
1359
warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1360
FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1362
if (!is_power_of_2(MaxVectorSize)) {
1363
warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1364
FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1368
FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1371
#if defined(COMPILER2) && defined(ASSERT)
1372
if (MaxVectorSize > 0) {
1373
if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1374
tty->print_cr("State of YMM registers after signal handle:");
1375
int nreg = 2 LP64_ONLY(+2);
1376
const char* ymm_name[4] = {"0", "7", "8", "15"};
1377
for (int i = 0; i < nreg; i++) {
1378
tty->print("YMM%s:", ymm_name[i]);
1379
for (int j = 7; j >=0; j--) {
1380
tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1389
if ((supports_avx512ifma() && supports_avx512vlbw()) || supports_avxifma()) {
1390
if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
1391
FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
1395
if (UsePoly1305Intrinsics) {
1396
warning("Intrinsics for Poly1305 crypto hash functions not available on this CPU.");
1397
FLAG_SET_DEFAULT(UsePoly1305Intrinsics, false);
1401
if (supports_avx512ifma() && supports_avx512vlbw()) {
1402
if (FLAG_IS_DEFAULT(UseIntPolyIntrinsics)) {
1403
FLAG_SET_DEFAULT(UseIntPolyIntrinsics, true);
1407
if (UseIntPolyIntrinsics) {
1408
warning("Intrinsics for Polynomial crypto functions not available on this CPU.");
1409
FLAG_SET_DEFAULT(UseIntPolyIntrinsics, false);
1413
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1414
UseMultiplyToLenIntrinsic = true;
1416
if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1417
UseSquareToLenIntrinsic = true;
1419
if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1420
UseMulAddIntrinsic = true;
1422
if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1423
UseMontgomeryMultiplyIntrinsic = true;
1425
if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1426
UseMontgomerySquareIntrinsic = true;
1429
if (UseMultiplyToLenIntrinsic) {
1430
if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1431
warning("multiplyToLen intrinsic is not available in 32-bit VM");
1433
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1435
if (UseMontgomeryMultiplyIntrinsic) {
1436
if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1437
warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1439
FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1441
if (UseMontgomerySquareIntrinsic) {
1442
if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1443
warning("montgomerySquare intrinsic is not available in 32-bit VM");
1445
FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1447
if (UseSquareToLenIntrinsic) {
1448
if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1449
warning("squareToLen intrinsic is not available in 32-bit VM");
1451
FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1453
if (UseMulAddIntrinsic) {
1454
if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1455
warning("mulAdd intrinsic is not available in 32-bit VM");
1457
FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1472
if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1473
UseStoreImmI16 = false;
1475
if ((cpu_family() == 6) || (cpu_family() == 7)) {
1476
if (FLAG_IS_DEFAULT(UseAddressNop)) {
1478
UseAddressNop = true;
1481
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1482
UseXmmLoadAndClearUpper = true;
1484
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1485
if (supports_sse3()) {
1486
UseXmmRegToRegMoveAll = true;
1488
UseXmmRegToRegMoveAll = false;
1491
if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) {
1493
if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1505
if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1506
UseXMMForArrayCopy = true;
1508
if (supports_sse4_2()) {
1509
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1510
UseUnalignedLoadStores = true;
1513
if (supports_sse4_2()) {
1514
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1515
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1518
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1519
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1521
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1525
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1526
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1530
if (is_amd_family()) {
1531
if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1533
UseAddressNop = true;
1535
if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1537
UseNewLongLShift = true;
1539
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1540
if (supports_sse4a()) {
1541
UseXmmLoadAndClearUpper = true;
1543
UseXmmLoadAndClearUpper = false;
1546
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1547
if (supports_sse4a()) {
1548
UseXmmRegToRegMoveAll = true;
1550
UseXmmRegToRegMoveAll = false;
1553
if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1554
if (supports_sse4a()) {
1560
if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1561
if (supports_sse4a()) {
1567
if (supports_sse4_2()) {
1568
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1569
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1572
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1573
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1575
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1579
if (cpu_family() == 0x15) {
1581
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1582
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1585
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1586
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1589
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1590
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1592
if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1593
FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1598
if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1600
FLAG_SET_DEFAULT(MaxVectorSize, 16);
1605
if (cpu_family() >= 0x17) {
1608
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1609
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1611
if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1612
FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1615
if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1616
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1623
if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1624
UseStoreImmI16 = false;
1626
if (cpu_family() == 6 || cpu_family() == 15) {
1627
if (FLAG_IS_DEFAULT(UseAddressNop)) {
1629
UseAddressNop = true;
1632
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1633
UseXmmLoadAndClearUpper = true;
1635
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1636
if (supports_sse3()) {
1637
UseXmmRegToRegMoveAll = true;
1639
UseXmmRegToRegMoveAll = false;
1642
if (cpu_family() == 6 && supports_sse3()) {
1644
if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1657
if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1658
UseXMMForArrayCopy = true;
1660
if ((supports_sse4_2() && supports_ht()) || supports_avx()) {
1661
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1662
UseUnalignedLoadStores = true;
1665
if (supports_sse4_2()) {
1666
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1667
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1670
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1671
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1673
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1676
if (is_atom_family() || is_knights_family()) {
1678
if (FLAG_IS_DEFAULT(OptoScheduling)) {
1679
OptoScheduling = true;
1682
if (supports_sse4_2()) {
1683
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1684
UseUnalignedLoadStores = true;
1687
if (FLAG_IS_DEFAULT(UseIncDec)) {
1688
FLAG_SET_DEFAULT(UseIncDec, false);
1691
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1692
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1696
if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) ||
1697
(!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) &&
1698
ArrayOperationPartialInlineSize != 0 &&
1699
ArrayOperationPartialInlineSize != 16 &&
1700
ArrayOperationPartialInlineSize != 32 &&
1701
ArrayOperationPartialInlineSize != 64)) {
1702
int inline_size = 0;
1703
if (MaxVectorSize >= 64 && AVX3Threshold == 0) {
1705
} else if (MaxVectorSize >= 32) {
1707
} else if (MaxVectorSize >= 16) {
1710
if(!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
1711
warning("Setting ArrayOperationPartialInlineSize as %d", inline_size);
1713
ArrayOperationPartialInlineSize = inline_size;
1716
if (ArrayOperationPartialInlineSize > MaxVectorSize) {
1717
ArrayOperationPartialInlineSize = MaxVectorSize >= 16 ? MaxVectorSize : 0;
1718
if (ArrayOperationPartialInlineSize) {
1719
warning("Setting ArrayOperationPartialInlineSize as MaxVectorSize" INTX_FORMAT ")", MaxVectorSize);
1721
warning("Setting ArrayOperationPartialInlineSize as " INTX_FORMAT, ArrayOperationPartialInlineSize);
1729
if (FLAG_IS_DEFAULT(OptimizeFill)) {
1730
if (MaxVectorSize < 32 || !VM_Version::supports_avx512vlbw()) {
1731
OptimizeFill = false;
1737
if (UseSSE42Intrinsics) {
1738
if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1739
UseVectorizedMismatchIntrinsic = true;
1741
} else if (UseVectorizedMismatchIntrinsic) {
1742
if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1743
warning("vectorizedMismatch intrinsics are not available on this CPU");
1744
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1747
FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
1748
} else if (UseVectorizedHashCodeIntrinsic) {
1749
if (!FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic))
1750
warning("vectorizedHashCode intrinsics are not available on this CPU");
1751
FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, false);
1754
if (UseVectorizedMismatchIntrinsic) {
1755
if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1756
warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1758
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1760
if (UseVectorizedHashCodeIntrinsic) {
1761
if (!FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
1762
warning("vectorizedHashCode intrinsic is not available in 32-bit VM");
1764
FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, false);
1769
if (supports_lzcnt()) {
1770
if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1771
UseCountLeadingZerosInstruction = true;
1773
} else if (UseCountLeadingZerosInstruction) {
1774
warning("lzcnt instruction is not available on this CPU");
1775
FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1779
if (supports_bmi1()) {
1781
if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1782
if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1784
UseCountTrailingZerosInstruction = false;
1786
UseCountTrailingZerosInstruction = true;
1789
} else if (UseCountTrailingZerosInstruction) {
1790
warning("tzcnt instruction is not available on this CPU");
1791
FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1796
if (supports_bmi1() && supports_avx()) {
1797
if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1798
UseBMI1Instructions = true;
1800
} else if (UseBMI1Instructions) {
1801
warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1802
FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1805
if (supports_bmi2() && supports_avx()) {
1806
if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1807
UseBMI2Instructions = true;
1809
} else if (UseBMI2Instructions) {
1810
warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1811
FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1815
if (supports_popcnt()) {
1816
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1817
UsePopCountInstruction = true;
1819
} else if (UsePopCountInstruction) {
1820
warning("POPCNT instruction is not available on this CPU");
1821
FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1825
if (supports_erms()) {
1826
if (FLAG_IS_DEFAULT(UseFastStosb)) {
1827
UseFastStosb = true;
1829
} else if (UseFastStosb) {
1830
warning("fast-string operations are not available on this CPU");
1831
FLAG_SET_DEFAULT(UseFastStosb, false);
1836
if (is_amd() && cpu_family() >= 0x19) {
1837
if (FLAG_IS_DEFAULT(UseFastStosb)) {
1838
UseFastStosb = false;
1843
if (is_intel() && MaxVectorSize > 16) {
1844
if (FLAG_IS_DEFAULT(UseFastStosb)) {
1845
UseFastStosb = false;
1851
if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1852
if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1853
UseXMMForObjInit = true;
1855
} else if (UseXMMForObjInit) {
1856
warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1857
FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1861
if (FLAG_IS_DEFAULT(AlignVector)) {
1863
AlignVector = !UseUnalignedLoadStores;
1867
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1868
if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1869
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1870
} else if (!supports_sse() && supports_3dnow_prefetch()) {
1871
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1876
int cache_line_size = checked_cast<int>(prefetch_data_size());
1877
if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1878
(cache_line_size > AllocatePrefetchStepSize)) {
1879
FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1882
if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1883
assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1884
if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1885
warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1887
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1890
if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1891
bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1892
FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1895
if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1896
if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1897
supports_sse4_2() && supports_ht()) {
1898
FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1901
if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1902
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1907
if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1909
if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1910
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1928
if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1929
FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1931
if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1932
FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1936
if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1937
(cache_line_size > ContendedPaddingWidth))
1938
ContendedPaddingWidth = cache_line_size;
1941
if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1942
FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1946
if (log_is_enabled(Info, os, cpu)) {
1947
LogStream ls(Log(os, cpu)::info());
1948
outputStream* log = &ls;
1949
log->print_cr("Logical CPUs per core: %u",
1950
logical_processors_per_package());
1951
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1952
log->print("UseSSE=%d", UseSSE);
1954
log->print(" UseAVX=%d", UseAVX);
1957
log->print(" UseAES=1");
1960
if (MaxVectorSize > 0) {
1961
log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1965
log->print("Allocation");
1966
if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1967
log->print_cr(": no prefetching");
1969
log->print(" prefetching: ");
1970
if (UseSSE == 0 && supports_3dnow_prefetch()) {
1971
log->print("PREFETCHW");
1972
} else if (UseSSE >= 1) {
1973
if (AllocatePrefetchInstr == 0) {
1974
log->print("PREFETCHNTA");
1975
} else if (AllocatePrefetchInstr == 1) {
1976
log->print("PREFETCHT0");
1977
} else if (AllocatePrefetchInstr == 2) {
1978
log->print("PREFETCHT2");
1979
} else if (AllocatePrefetchInstr == 3) {
1980
log->print("PREFETCHW");
1983
if (AllocatePrefetchLines > 1) {
1984
log->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
1986
log->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
1990
if (PrefetchCopyIntervalInBytes > 0) {
1991
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1993
if (PrefetchScanIntervalInBytes > 0) {
1994
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1996
if (ContendedPaddingWidth > 0) {
1997
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
2001
if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
2002
FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
2004
if (FLAG_IS_DEFAULT(UseCopySignIntrinsic)) {
2005
FLAG_SET_DEFAULT(UseCopySignIntrinsic, true);
2009
void VM_Version::print_platform_virtualization_info(outputStream* st) {
2010
VirtualizationType vrt = VM_Version::get_detected_virtualization();
2011
if (vrt == XenHVM) {
2012
st->print_cr("Xen hardware-assisted virtualization detected");
2013
} else if (vrt == KVM) {
2014
st->print_cr("KVM virtualization detected");
2015
} else if (vrt == VMWare) {
2016
st->print_cr("VMWare virtualization detected");
2017
VirtualizationSupport::print_virtualization_info(st);
2018
} else if (vrt == HyperV) {
2019
st->print_cr("Hyper-V virtualization detected");
2020
} else if (vrt == HyperVRole) {
2021
st->print_cr("Hyper-V role detected");
2025
bool VM_Version::compute_has_intel_jcc_erratum() {
2026
if (!is_intel_family_core()) {
2043
return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xC;
2048
return _stepping == 0x3;
2056
return _stepping == 0x4 || _stepping == 0x7;
2060
return _stepping == 0x3;
2076
return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xD;
2083
return _stepping == 0x0;
2086
return _stepping == 0xA;
2107
void VM_Version::check_virtualizations() {
2108
uint32_t registers[4] = {0};
2109
char signature[13] = {0};
2114
for (int leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
2115
detect_virt_stub(leaf, registers);
2116
memcpy(signature, ®isters[1], 12);
2118
if (strncmp("VMwareVMware", signature, 12) == 0) {
2119
Abstract_VM_Version::_detected_virtualization = VMWare;
2121
VirtualizationSupport::initialize();
2122
} else if (strncmp("Microsoft Hv", signature, 12) == 0) {
2123
Abstract_VM_Version::_detected_virtualization = HyperV;
2128
detect_virt_stub(0x40000007, registers);
2129
if ((registers[0] != 0x0) ||
2130
(registers[1] != 0x0) ||
2131
(registers[2] != 0x0) ||
2132
(registers[3] != 0x0)) {
2133
Abstract_VM_Version::_detected_virtualization = HyperVRole;
2136
} else if (strncmp("KVMKVMKVM", signature, 9) == 0) {
2137
Abstract_VM_Version::_detected_virtualization = KVM;
2138
} else if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
2139
Abstract_VM_Version::_detected_virtualization = XenHVM;
2146
bool VM_Version::is_default_intel_cascade_lake() {
2147
return FLAG_IS_DEFAULT(UseAVX) &&
2148
FLAG_IS_DEFAULT(MaxVectorSize) &&
2150
is_intel_cascade_lake();
2154
bool VM_Version::is_intel_cascade_lake() {
2155
return is_intel_skylake() && _stepping >= 5;
2163
int VM_Version::avx3_threshold() {
2164
return (is_intel_family_core() &&
2165
supports_serialize() &&
2166
FLAG_IS_DEFAULT(AVX3Threshold)) ? 0 : AVX3Threshold;
2170
void VM_Version::clear_apx_test_state() {
2171
clear_apx_test_state_stub();
2175
static bool _vm_version_initialized = false;
2177
void VM_Version::initialize() {
2180
stub_blob = BufferBlob::create("VM_Version stub", stub_size);
2181
if (stub_blob == nullptr) {
2182
vm_exit_during_initialization("Unable to allocate stub for VM_Version");
2184
CodeBuffer c(stub_blob);
2185
VM_Version_StubGenerator g(&c);
2187
get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
2188
g.generate_get_cpu_info());
2189
detect_virt_stub = CAST_TO_FN_PTR(detect_virt_stub_t,
2190
g.generate_detect_virt());
2193
clear_apx_test_state_stub = CAST_TO_FN_PTR(clear_apx_test_state_t,
2194
g.clear_apx_test_state());
2196
get_processor_features();
2198
LP64_ONLY(Assembler::precompute_instructions();)
2200
if (VM_Version::supports_hv()) {
2201
check_virtualizations();
2203
_vm_version_initialized = true;
2207
CPU_FAMILY_8086_8088 = 0,
2208
CPU_FAMILY_INTEL_286 = 2,
2209
CPU_FAMILY_INTEL_386 = 3,
2210
CPU_FAMILY_INTEL_486 = 4,
2211
CPU_FAMILY_PENTIUM = 5,
2212
CPU_FAMILY_PENTIUMPRO = 6,
2213
CPU_FAMILY_PENTIUM_4 = 0xF
2217
RDTSCP_FLAG = 0x08000000,
2218
INTEL64_FLAG = 0x20000000
2219
} _featureExtendedEdxFlag;
2222
FPU_FLAG = 0x00000001,
2223
VME_FLAG = 0x00000002,
2224
DE_FLAG = 0x00000004,
2225
PSE_FLAG = 0x00000008,
2226
TSC_FLAG = 0x00000010,
2227
MSR_FLAG = 0x00000020,
2228
PAE_FLAG = 0x00000040,
2229
MCE_FLAG = 0x00000080,
2230
CX8_FLAG = 0x00000100,
2231
APIC_FLAG = 0x00000200,
2232
SEP_FLAG = 0x00000800,
2233
MTRR_FLAG = 0x00001000,
2234
PGE_FLAG = 0x00002000,
2235
MCA_FLAG = 0x00004000,
2236
CMOV_FLAG = 0x00008000,
2237
PAT_FLAG = 0x00010000,
2238
PSE36_FLAG = 0x00020000,
2239
PSNUM_FLAG = 0x00040000,
2240
CLFLUSH_FLAG = 0x00080000,
2241
DTS_FLAG = 0x00200000,
2242
ACPI_FLAG = 0x00400000,
2243
MMX_FLAG = 0x00800000,
2244
FXSR_FLAG = 0x01000000,
2245
SSE_FLAG = 0x02000000,
2246
SSE2_FLAG = 0x04000000,
2247
SS_FLAG = 0x08000000,
2248
HTT_FLAG = 0x10000000,
2249
TM_FLAG = 0x20000000
2252
static BufferBlob* cpuid_brand_string_stub_blob;
2253
static const int cpuid_brand_string_stub_size = 550;
2256
typedef void (*getCPUIDBrandString_stub_t)(void*);
2259
static getCPUIDBrandString_stub_t getCPUIDBrandString_stub = nullptr;
2263
ExtendedFamilyIdLength_INTEL = 16,
2264
ExtendedFamilyIdLength_AMD = 24
2267
const size_t VENDOR_LENGTH = 13;
2268
const size_t CPU_EBS_MAX_LENGTH = (3 * 4 * 4 + 1);
2269
static char* _cpu_brand_string = nullptr;
2270
static int64_t _max_qualified_cpu_frequency = 0;
2272
static int _no_of_threads = 0;
2273
static int _no_of_cores = 0;
2275
const char* const _family_id_intel[ExtendedFamilyIdLength_INTEL] = {
2294
const char* const _family_id_amd[ExtendedFamilyIdLength_AMD] = {
2311
"Opteron QC/Phenom",
2322
const char* const _model_id_pentium_pro[] = {
2326
"Pentium II model 3",
2328
"Pentium II model 5/Xeon/Celeron",
2330
"Pentium III/Pentium III Xeon",
2331
"Pentium III/Pentium III Xeon",
2332
"Pentium M model 9",
2333
"Pentium III, model A",
2334
"Pentium III, model B",
2336
"Pentium M model D",
2399
const char* const _brand_id[] = {
2401
"Celeron processor",
2402
"Pentium III processor",
2403
"Intel Pentium III Xeon processor",
2408
"Intel Pentium 4 processor",
2413
const char* const _feature_edx_id[] = {
2415
"Virtual Mode Extensions",
2416
"Debugging Extensions",
2417
"Page Size Extensions",
2418
"Time Stamp Counter",
2419
"Model Specific Registers",
2420
"Physical Address Extension",
2421
"Machine Check Exceptions",
2422
"CMPXCHG8B Instruction",
2426
"Memory Type Range Registers",
2427
"Page Global Enable",
2428
"Machine Check Architecture",
2429
"Conditional Mov Instruction",
2430
"Page Attribute Table",
2431
"36-bit Page Size Extension",
2432
"Processor Serial Number",
2433
"CLFLUSH Instruction",
2435
"Debug Trace Store feature",
2436
"ACPI registers in MSR space",
2437
"Intel Architecture MMX Technology",
2438
"Fast Float Point Save and Restore",
2439
"Streaming SIMD extensions",
2440
"Streaming SIMD extensions 2",
2445
"Pending Break Enable"
2448
const char* const _feature_extended_edx_id[] = {
2469
"Execute Disable Bit",
2478
"Intel 64 Architecture",
2483
const char* const _feature_ecx_id[] = {
2484
"Streaming SIMD Extensions 3",
2487
"MONITOR/MWAIT instructions",
2488
"CPL Qualified Debug Store",
2489
"Virtual Machine Extensions",
2490
"Safer Mode Extensions",
2491
"Enhanced Intel SpeedStep technology",
2492
"Thermal Monitor 2",
2493
"Supplemental Streaming SIMD Extensions 3",
2496
"Fused Multiply-Add",
2498
"xTPR Update Control",
2499
"Perfmon and Debug Capability",
2501
"Process-context identifiers",
2502
"Direct Cache Access",
2503
"Streaming SIMD extensions 4.1",
2504
"Streaming SIMD extensions 4.2",
2507
"Popcount instruction",
2518
const char* const _feature_extended_ecx_id[] = {
2519
"LAHF/SAHF instruction support",
2520
"Core multi-processor legacy mode",
2524
"Advanced Bit Manipulations: LZCNT",
2525
"SSE4A: MOVNTSS, MOVNTSD, EXTRQ, INSERTQ",
2526
"Misaligned SSE mode",
2553
void VM_Version::initialize_tsc(void) {
2556
cpuid_brand_string_stub_blob = BufferBlob::create("getCPUIDBrandString_stub", cpuid_brand_string_stub_size);
2557
if (cpuid_brand_string_stub_blob == nullptr) {
2558
vm_exit_during_initialization("Unable to allocate getCPUIDBrandString_stub");
2560
CodeBuffer c(cpuid_brand_string_stub_blob);
2561
VM_Version_StubGenerator g(&c);
2562
getCPUIDBrandString_stub = CAST_TO_FN_PTR(getCPUIDBrandString_stub_t,
2563
g.generate_getCPUIDBrandString());
2566
const char* VM_Version::cpu_model_description(void) {
2567
uint32_t cpu_family = extended_cpu_family();
2568
uint32_t cpu_model = extended_cpu_model();
2569
const char* model = nullptr;
2571
if (cpu_family == CPU_FAMILY_PENTIUMPRO) {
2572
for (uint32_t i = 0; i <= cpu_model; i++) {
2573
model = _model_id_pentium_pro[i];
2574
if (model == nullptr) {
2582
const char* VM_Version::cpu_brand_string(void) {
2583
if (_cpu_brand_string == nullptr) {
2584
_cpu_brand_string = NEW_C_HEAP_ARRAY_RETURN_NULL(char, CPU_EBS_MAX_LENGTH, mtInternal);
2585
if (nullptr == _cpu_brand_string) {
2588
int ret_val = cpu_extended_brand_string(_cpu_brand_string, CPU_EBS_MAX_LENGTH);
2589
if (ret_val != OS_OK) {
2590
FREE_C_HEAP_ARRAY(char, _cpu_brand_string);
2591
_cpu_brand_string = nullptr;
2594
return _cpu_brand_string;
2597
const char* VM_Version::cpu_brand(void) {
2598
const char* brand = nullptr;
2600
if ((_cpuid_info.std_cpuid1_ebx.value & 0xFF) > 0) {
2601
int brand_num = _cpuid_info.std_cpuid1_ebx.value & 0xFF;
2602
brand = _brand_id[0];
2603
for (int i = 0; brand != nullptr && i <= brand_num; i += 1) {
2604
brand = _brand_id[i];
2610
bool VM_Version::cpu_is_em64t(void) {
2611
return ((_cpuid_info.ext_cpuid1_edx.value & INTEL64_FLAG) == INTEL64_FLAG);
2614
bool VM_Version::is_netburst(void) {
2615
return (is_intel() && (extended_cpu_family() == CPU_FAMILY_PENTIUM_4));
2618
bool VM_Version::supports_tscinv_ext(void) {
2619
if (!supports_tscinv_bit()) {
2628
return !is_amd_Barcelona();
2638
void VM_Version::resolve_cpu_information_details(void) {
2651
_no_of_threads = os::processor_count();
2654
int threads_per_package = threads_per_core() * cores_per_cpu();
2657
_no_of_sockets = _no_of_threads / threads_per_package;
2662
if (0 == _no_of_sockets) {
2667
_no_of_cores = cores_per_cpu() * _no_of_sockets;
2671
const char* VM_Version::cpu_family_description(void) {
2672
int cpu_family_id = extended_cpu_family();
2674
if (cpu_family_id < ExtendedFamilyIdLength_AMD) {
2675
return _family_id_amd[cpu_family_id];
2679
if (cpu_family_id == CPU_FAMILY_PENTIUMPRO) {
2680
return cpu_model_description();
2682
if (cpu_family_id < ExtendedFamilyIdLength_INTEL) {
2683
return _family_id_intel[cpu_family_id];
2689
return "Unknown x86";
2692
int VM_Version::cpu_type_description(char* const buf, size_t buf_len) {
2693
assert(buf != nullptr, "buffer is null!");
2694
assert(buf_len >= CPU_TYPE_DESC_BUF_SIZE, "buffer len should at least be == CPU_TYPE_DESC_BUF_SIZE!");
2696
const char* cpu_type = nullptr;
2697
const char* x64 = nullptr;
2701
x64 = cpu_is_em64t() ? " Intel64" : "";
2702
} else if (is_amd()) {
2704
x64 = cpu_is_em64t() ? " AMD64" : "";
2705
} else if (is_hygon()) {
2707
x64 = cpu_is_em64t() ? " AMD64" : "";
2709
cpu_type = "Unknown x86";
2710
x64 = cpu_is_em64t() ? " x86_64" : "";
2713
jio_snprintf(buf, buf_len, "%s %s%s SSE SSE2%s%s%s%s%s%s%s%s",
2715
cpu_family_description(),
2716
supports_ht() ? " (HT)" : "",
2717
supports_sse3() ? " SSE3" : "",
2718
supports_ssse3() ? " SSSE3" : "",
2719
supports_sse4_1() ? " SSE4.1" : "",
2720
supports_sse4_2() ? " SSE4.2" : "",
2721
supports_sse4a() ? " SSE4A" : "",
2722
is_netburst() ? " Netburst" : "",
2723
is_intel_family_core() ? " Core" : "",
2729
int VM_Version::cpu_extended_brand_string(char* const buf, size_t buf_len) {
2730
assert(buf != nullptr, "buffer is null!");
2731
assert(buf_len >= CPU_EBS_MAX_LENGTH, "buffer len should at least be == CPU_EBS_MAX_LENGTH!");
2732
assert(getCPUIDBrandString_stub != nullptr, "not initialized");
2735
getCPUIDBrandString_stub(&_cpuid_info);
2738
*((uint32_t*) &buf[0]) = _cpuid_info.proc_name_0;
2739
*((uint32_t*) &buf[4]) = _cpuid_info.proc_name_1;
2740
*((uint32_t*) &buf[8]) = _cpuid_info.proc_name_2;
2741
*((uint32_t*) &buf[12]) = _cpuid_info.proc_name_3;
2742
*((uint32_t*) &buf[16]) = _cpuid_info.proc_name_4;
2743
*((uint32_t*) &buf[20]) = _cpuid_info.proc_name_5;
2744
*((uint32_t*) &buf[24]) = _cpuid_info.proc_name_6;
2745
*((uint32_t*) &buf[28]) = _cpuid_info.proc_name_7;
2746
*((uint32_t*) &buf[32]) = _cpuid_info.proc_name_8;
2747
*((uint32_t*) &buf[36]) = _cpuid_info.proc_name_9;
2748
*((uint32_t*) &buf[40]) = _cpuid_info.proc_name_10;
2749
*((uint32_t*) &buf[44]) = _cpuid_info.proc_name_11;
2754
size_t VM_Version::cpu_write_support_string(char* const buf, size_t buf_len) {
2755
guarantee(buf != nullptr, "buffer is null!");
2756
guarantee(buf_len > 0, "buffer len not enough!");
2758
unsigned int flag = 0;
2759
unsigned int fi = 0;
2761
const char* prefix = "";
2763
#define WRITE_TO_BUF(string) \
2765
int res = jio_snprintf(&buf[written], buf_len - written, "%s%s", prefix, string); \
2767
return buf_len - 1; \
2770
if (prefix[0] == '\0') { \
2775
for (flag = 1, fi = 0; flag <= 0x20000000 ; flag <<= 1, fi++) {
2776
if (flag == HTT_FLAG && (((_cpuid_info.std_cpuid1_ebx.value >> 16) & 0xff) <= 1)) {
2778
} else if (flag == SEP_FLAG && (cpu_family() == CPU_FAMILY_PENTIUMPRO && ((_cpuid_info.std_cpuid1_eax.value & 0xff) < 0x33))) {
2781
if ((_cpuid_info.std_cpuid1_edx.value & flag) && strlen(_feature_edx_id[fi]) > 0) {
2782
WRITE_TO_BUF(_feature_edx_id[fi]);
2786
for (flag = 1, fi = 0; flag <= 0x20000000; flag <<= 1, fi++) {
2787
if ((_cpuid_info.std_cpuid1_ecx.value & flag) && strlen(_feature_ecx_id[fi]) > 0) {
2788
WRITE_TO_BUF(_feature_ecx_id[fi]);
2792
for (flag = 1, fi = 0; flag <= 0x20000000 ; flag <<= 1, fi++) {
2793
if ((_cpuid_info.ext_cpuid1_ecx.value & flag) && strlen(_feature_extended_ecx_id[fi]) > 0) {
2794
WRITE_TO_BUF(_feature_extended_ecx_id[fi]);
2798
for (flag = 1, fi = 0; flag <= 0x20000000; flag <<= 1, fi++) {
2799
if ((_cpuid_info.ext_cpuid1_edx.value & flag) && strlen(_feature_extended_edx_id[fi]) > 0) {
2800
WRITE_TO_BUF(_feature_extended_edx_id[fi]);
2804
if (supports_tscinv_bit()) {
2805
WRITE_TO_BUF("Invariant TSC");
2815
int VM_Version::cpu_detailed_description(char* const buf, size_t buf_len) {
2816
assert(buf != nullptr, "buffer is null!");
2817
assert(buf_len >= CPU_DETAILED_DESC_BUF_SIZE, "buffer len should at least be == CPU_DETAILED_DESC_BUF_SIZE!");
2819
static const char* unknown = "<unknown>";
2820
char vendor_id[VENDOR_LENGTH];
2821
const char* family = nullptr;
2822
const char* model = nullptr;
2823
const char* brand = nullptr;
2826
family = cpu_family_description();
2827
if (family == nullptr) {
2831
model = cpu_model_description();
2832
if (model == nullptr) {
2836
brand = cpu_brand_string();
2838
if (brand == nullptr) {
2839
brand = cpu_brand();
2840
if (brand == nullptr) {
2845
*((uint32_t*) &vendor_id[0]) = _cpuid_info.std_vendor_name_0;
2846
*((uint32_t*) &vendor_id[4]) = _cpuid_info.std_vendor_name_2;
2847
*((uint32_t*) &vendor_id[8]) = _cpuid_info.std_vendor_name_1;
2848
vendor_id[VENDOR_LENGTH-1] = '\0';
2850
outputLen = jio_snprintf(buf, buf_len, "Brand: %s, Vendor: %s\n"
2851
"Family: %s (0x%x), Model: %s (0x%x), Stepping: 0x%x\n"
2852
"Ext. family: 0x%x, Ext. model: 0x%x, Type: 0x%x, Signature: 0x%8.8x\n"
2853
"Features: ebx: 0x%8.8x, ecx: 0x%8.8x, edx: 0x%8.8x\n"
2854
"Ext. features: eax: 0x%8.8x, ebx: 0x%8.8x, ecx: 0x%8.8x, edx: 0x%8.8x\n"
2859
extended_cpu_family(),
2861
extended_cpu_model(),
2863
_cpuid_info.std_cpuid1_eax.bits.ext_family,
2864
_cpuid_info.std_cpuid1_eax.bits.ext_model,
2865
_cpuid_info.std_cpuid1_eax.bits.proc_type,
2866
_cpuid_info.std_cpuid1_eax.value,
2867
_cpuid_info.std_cpuid1_ebx.value,
2868
_cpuid_info.std_cpuid1_ecx.value,
2869
_cpuid_info.std_cpuid1_edx.value,
2870
_cpuid_info.ext_cpuid1_eax,
2871
_cpuid_info.ext_cpuid1_ebx,
2872
_cpuid_info.ext_cpuid1_ecx,
2873
_cpuid_info.ext_cpuid1_edx);
2875
if (outputLen < 0 || (size_t) outputLen >= buf_len - 1) {
2876
if (buf_len > 0) { buf[buf_len-1] = '\0'; }
2880
cpu_write_support_string(&buf[outputLen], buf_len - outputLen);
2887
void VM_Version::initialize_cpu_information() {
2888
assert(_vm_version_initialized, "should have initialized VM_Version long ago");
2889
assert(!_initialized, "shouldn't be initialized yet");
2890
resolve_cpu_information_details();
2893
cpu_type_description(_cpu_name, CPU_TYPE_DESC_BUF_SIZE);
2894
cpu_detailed_description(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE);
2895
_initialized = true;
2907
int64_t VM_Version::max_qualified_cpu_freq_from_brand_string(void) {
2908
const char* const brand_string = cpu_brand_string();
2909
if (brand_string == nullptr) {
2912
const int64_t MEGA = 1000000;
2913
int64_t multiplier = 0;
2914
int64_t frequency = 0;
2918
for (; idx < 48-2; ++idx) {
2921
if (brand_string[idx+1] == 'H' && brand_string[idx+2] == 'z') {
2922
if (brand_string[idx] == 'M') {
2924
} else if (brand_string[idx] == 'G') {
2925
multiplier = MEGA * 1000;
2926
} else if (brand_string[idx] == 'T') {
2927
multiplier = MEGA * MEGA;
2932
if (multiplier > 0) {
2934
if (brand_string[idx-3] == '.') {
2935
frequency = (brand_string[idx-4] - '0') * multiplier;
2936
frequency += (brand_string[idx-2] - '0') * multiplier / 10;
2937
frequency += (brand_string[idx-1] - '0') * multiplier / 100;
2939
frequency = (brand_string[idx-4] - '0') * 1000;
2940
frequency += (brand_string[idx-3] - '0') * 100;
2941
frequency += (brand_string[idx-2] - '0') * 10;
2942
frequency += (brand_string[idx-1] - '0');
2943
frequency *= multiplier;
2950
int64_t VM_Version::maximum_qualified_cpu_frequency(void) {
2951
if (_max_qualified_cpu_frequency == 0) {
2952
_max_qualified_cpu_frequency = max_qualified_cpu_freq_from_brand_string();
2954
return _max_qualified_cpu_frequency;
2957
uint64_t VM_Version::CpuidInfo::feature_flags() const {
2958
uint64_t result = 0;
2959
if (std_cpuid1_edx.bits.cmpxchg8 != 0)
2961
if (std_cpuid1_edx.bits.cmov != 0)
2963
if (std_cpuid1_edx.bits.clflush != 0)
2964
result |= CPU_FLUSH;
2969
assert ((result & CPU_FLUSH) != 0, "clflush should be available");
2971
if (std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
2972
ext_cpuid1_edx.bits.fxsr != 0))
2975
if (threads_per_core() > 1)
2977
if (std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
2978
ext_cpuid1_edx.bits.mmx != 0))
2980
if (std_cpuid1_edx.bits.sse != 0)
2982
if (std_cpuid1_edx.bits.sse2 != 0)
2984
if (std_cpuid1_ecx.bits.sse3 != 0)
2986
if (std_cpuid1_ecx.bits.ssse3 != 0)
2987
result |= CPU_SSSE3;
2988
if (std_cpuid1_ecx.bits.sse4_1 != 0)
2989
result |= CPU_SSE4_1;
2990
if (std_cpuid1_ecx.bits.sse4_2 != 0)
2991
result |= CPU_SSE4_2;
2992
if (std_cpuid1_ecx.bits.popcnt != 0)
2993
result |= CPU_POPCNT;
2994
if (sefsl1_cpuid7_edx.bits.apx_f != 0 &&
2995
xem_xcr0_eax.bits.apx_f != 0) {
2996
result |= CPU_APX_F;
2998
if (std_cpuid1_ecx.bits.avx != 0 &&
2999
std_cpuid1_ecx.bits.osxsave != 0 &&
3000
xem_xcr0_eax.bits.sse != 0 &&
3001
xem_xcr0_eax.bits.ymm != 0) {
3003
result |= CPU_VZEROUPPER;
3004
if (std_cpuid1_ecx.bits.f16c != 0)
3006
if (sef_cpuid7_ebx.bits.avx2 != 0) {
3008
if (sefsl1_cpuid7_eax.bits.avx_ifma != 0)
3009
result |= CPU_AVX_IFMA;
3011
if (sef_cpuid7_ecx.bits.gfni != 0)
3013
if (sef_cpuid7_ebx.bits.avx512f != 0 &&
3014
xem_xcr0_eax.bits.opmask != 0 &&
3015
xem_xcr0_eax.bits.zmm512 != 0 &&
3016
xem_xcr0_eax.bits.zmm32 != 0) {
3017
result |= CPU_AVX512F;
3018
if (sef_cpuid7_ebx.bits.avx512cd != 0)
3019
result |= CPU_AVX512CD;
3020
if (sef_cpuid7_ebx.bits.avx512dq != 0)
3021
result |= CPU_AVX512DQ;
3022
if (sef_cpuid7_ebx.bits.avx512ifma != 0)
3023
result |= CPU_AVX512_IFMA;
3024
if (sef_cpuid7_ebx.bits.avx512pf != 0)
3025
result |= CPU_AVX512PF;
3026
if (sef_cpuid7_ebx.bits.avx512er != 0)
3027
result |= CPU_AVX512ER;
3028
if (sef_cpuid7_ebx.bits.avx512bw != 0)
3029
result |= CPU_AVX512BW;
3030
if (sef_cpuid7_ebx.bits.avx512vl != 0)
3031
result |= CPU_AVX512VL;
3032
if (sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
3033
result |= CPU_AVX512_VPOPCNTDQ;
3034
if (sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0)
3035
result |= CPU_AVX512_VPCLMULQDQ;
3036
if (sef_cpuid7_ecx.bits.vaes != 0)
3037
result |= CPU_AVX512_VAES;
3038
if (sef_cpuid7_ecx.bits.avx512_vnni != 0)
3039
result |= CPU_AVX512_VNNI;
3040
if (sef_cpuid7_ecx.bits.avx512_bitalg != 0)
3041
result |= CPU_AVX512_BITALG;
3042
if (sef_cpuid7_ecx.bits.avx512_vbmi != 0)
3043
result |= CPU_AVX512_VBMI;
3044
if (sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
3045
result |= CPU_AVX512_VBMI2;
3048
if (std_cpuid1_ecx.bits.hv != 0)
3050
if (sef_cpuid7_ebx.bits.bmi1 != 0)
3052
if (std_cpuid1_edx.bits.tsc != 0)
3054
if (ext_cpuid7_edx.bits.tsc_invariance != 0)
3055
result |= CPU_TSCINV_BIT;
3056
if (std_cpuid1_ecx.bits.aes != 0)
3058
if (sef_cpuid7_ebx.bits.erms != 0)
3060
if (sef_cpuid7_edx.bits.fast_short_rep_mov != 0)
3062
if (std_cpuid1_ecx.bits.clmul != 0)
3063
result |= CPU_CLMUL;
3064
if (sef_cpuid7_ebx.bits.rtm != 0)
3066
if (sef_cpuid7_ebx.bits.adx != 0)
3068
if (sef_cpuid7_ebx.bits.bmi2 != 0)
3070
if (sef_cpuid7_ebx.bits.sha != 0)
3072
if (std_cpuid1_ecx.bits.fma != 0)
3074
if (sef_cpuid7_ebx.bits.clflushopt != 0)
3075
result |= CPU_FLUSHOPT;
3076
if (ext_cpuid1_edx.bits.rdtscp != 0)
3077
result |= CPU_RDTSCP;
3078
if (sef_cpuid7_ecx.bits.rdpid != 0)
3079
result |= CPU_RDPID;
3082
if (is_amd_family()) {
3083
if ((ext_cpuid1_edx.bits.tdnow != 0) ||
3084
(ext_cpuid1_ecx.bits.prefetchw != 0))
3085
result |= CPU_3DNOW_PREFETCH;
3086
if (ext_cpuid1_ecx.bits.lzcnt != 0)
3087
result |= CPU_LZCNT;
3088
if (ext_cpuid1_ecx.bits.sse4a != 0)
3089
result |= CPU_SSE4A;
3094
if (ext_cpuid1_ecx.bits.lzcnt != 0) {
3095
result |= CPU_LZCNT;
3097
if (ext_cpuid1_ecx.bits.prefetchw != 0) {
3098
result |= CPU_3DNOW_PREFETCH;
3100
if (sef_cpuid7_ebx.bits.clwb != 0) {
3103
if (sef_cpuid7_edx.bits.serialize != 0)
3104
result |= CPU_SERIALIZE;
3109
if (ext_cpuid1_ecx.bits.lzcnt != 0) {
3110
result |= CPU_LZCNT;
3112
if (ext_cpuid1_ecx.bits.prefetchw != 0) {
3113
result |= CPU_3DNOW_PREFETCH;
3118
if (sef_cpuid7_ecx.bits.pku != 0) {
3121
if (sef_cpuid7_ecx.bits.ospke != 0) {
3122
result |= CPU_OSPKE;
3126
if (sef_cpuid7_ecx.bits.cet_ss != 0) {
3127
result |= CPU_CET_SS;
3129
if (sef_cpuid7_edx.bits.cet_ibt != 0) {
3130
result |= CPU_CET_IBT;
3134
if (supports_tscinv_bit() &&
3135
((is_amd_family() && !is_amd_Barcelona()) ||
3136
is_intel_tsc_synched_at_init())) {
3137
result |= CPU_TSCINV;
3143
bool VM_Version::os_supports_avx_vectors() {
3144
bool retVal = false;
3145
int nreg = 2 LP64_ONLY(+2);
3146
if (supports_evex()) {
3150
for (int i = 0; i < 16 * nreg; i++) {
3151
if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
3156
} else if (supports_avx()) {
3160
for (int i = 0; i < 8 * nreg; i++) {
3161
if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
3167
if (retVal == false) {
3171
for (int i = 0; i < 16 * nreg; i++) {
3172
if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
3182
bool VM_Version::os_supports_apx_egprs() {
3183
if (!supports_apx_f()) {
3188
#if !defined(PRODUCT)
3189
if (_cpuid_info.apx_save[0] != egpr_test_value() ||
3190
_cpuid_info.apx_save[1] != egpr_test_value()) {
3199
uint VM_Version::cores_per_cpu() {
3202
bool supports_topology = supports_processor_topology();
3203
if (supports_topology) {
3204
result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
3205
_cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
3207
if (!supports_topology || result == 0) {
3208
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
3210
} else if (is_amd_family()) {
3211
result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
3212
} else if (is_zx()) {
3213
bool supports_topology = supports_processor_topology();
3214
if (supports_topology) {
3215
result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
3216
_cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
3218
if (!supports_topology || result == 0) {
3219
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
3225
uint VM_Version::threads_per_core() {
3227
if (is_intel() && supports_processor_topology()) {
3228
result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
3229
} else if (is_zx() && supports_processor_topology()) {
3230
result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
3231
} else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
3232
if (cpu_family() >= 0x17) {
3233
result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
3235
result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
3239
return (result == 0 ? 1 : result);
3242
uint VM_Version::L1_line_size() {
3245
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
3246
} else if (is_amd_family()) {
3247
result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
3248
} else if (is_zx()) {
3249
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
3256
bool VM_Version::is_intel_tsc_synched_at_init() {
3257
if (is_intel_family_core()) {
3258
uint32_t ext_model = extended_cpu_model();
3259
if (ext_model == CPU_MODEL_NEHALEM_EP ||
3260
ext_model == CPU_MODEL_WESTMERE_EP ||
3261
ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
3262
ext_model == CPU_MODEL_IVYBRIDGE_EP) {
3274
int VM_Version::allocate_prefetch_distance(bool use_watermark_prefetch) {
3290
if (is_amd_family()) {
3291
if (supports_sse2()) {
3297
if (supports_sse3() && cpu_family() == 6) {
3298
if (supports_sse4_2() && supports_ht()) {
3300
} else if (use_watermark_prefetch) {
3308
if (supports_sse2()) {
3309
if (cpu_family() == 6) {
3320
bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) {
3321
assert(id != vmIntrinsics::_none, "must be a VM intrinsic");
3323
case vmIntrinsics::_floatToFloat16:
3324
case vmIntrinsics::_float16ToFloat:
3325
if (!supports_float16()) {