jdk

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/*
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 * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "c1/c1_FrameMap.hpp"
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#include "c1/c1_LIR.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "vmreg_x86.inline.hpp"
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const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
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LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
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  LIR_Opr opr = LIR_OprFact::illegalOpr;
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  VMReg r_1 = reg->first();
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  VMReg r_2 = reg->second();
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  if (r_1->is_stack()) {
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    // Convert stack slot to an SP offset
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    // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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    // so we must add it in here.
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    int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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    opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
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  } else if (r_1->is_Register()) {
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    Register reg = r_1->as_Register();
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    if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
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      Register reg2 = r_2->as_Register();
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#ifdef _LP64
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      assert(reg2 == reg, "must be same register");
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      opr = as_long_opr(reg);
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#else
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      opr = as_long_opr(reg2, reg);
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#endif // _LP64
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    } else if (is_reference_type(type)) {
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      opr = as_oop_opr(reg);
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    } else if (type == T_METADATA) {
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      opr = as_metadata_opr(reg);
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    } else if (type == T_ADDRESS) {
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      opr = as_address_opr(reg);
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    } else {
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      opr = as_opr(reg);
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    }
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  } else if (r_1->is_FloatRegister()) {
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    assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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    int num = r_1->as_FloatRegister()->encoding();
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    if (type == T_FLOAT) {
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      opr = LIR_OprFact::single_fpu(num);
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    } else {
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      opr = LIR_OprFact::double_fpu(num);
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    }
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  } else if (r_1->is_XMMRegister()) {
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    assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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    int num = r_1->as_XMMRegister()->encoding();
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    if (type == T_FLOAT) {
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      opr = LIR_OprFact::single_xmm(num);
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    } else {
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      opr = LIR_OprFact::double_xmm(num);
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    }
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  } else {
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    ShouldNotReachHere();
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  }
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  return opr;
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}
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LIR_Opr FrameMap::rsi_opr;
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LIR_Opr FrameMap::rdi_opr;
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LIR_Opr FrameMap::rbx_opr;
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LIR_Opr FrameMap::rax_opr;
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LIR_Opr FrameMap::rdx_opr;
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LIR_Opr FrameMap::rcx_opr;
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LIR_Opr FrameMap::rsp_opr;
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LIR_Opr FrameMap::rbp_opr;
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LIR_Opr FrameMap::receiver_opr;
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LIR_Opr FrameMap::rsi_oop_opr;
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LIR_Opr FrameMap::rdi_oop_opr;
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LIR_Opr FrameMap::rbx_oop_opr;
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LIR_Opr FrameMap::rax_oop_opr;
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LIR_Opr FrameMap::rdx_oop_opr;
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LIR_Opr FrameMap::rcx_oop_opr;
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LIR_Opr FrameMap::rsi_metadata_opr;
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LIR_Opr FrameMap::rdi_metadata_opr;
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LIR_Opr FrameMap::rbx_metadata_opr;
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LIR_Opr FrameMap::rax_metadata_opr;
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LIR_Opr FrameMap::rdx_metadata_opr;
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LIR_Opr FrameMap::rcx_metadata_opr;
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LIR_Opr FrameMap::long0_opr;
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LIR_Opr FrameMap::long1_opr;
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LIR_Opr FrameMap::fpu0_float_opr;
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LIR_Opr FrameMap::fpu0_double_opr;
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LIR_Opr FrameMap::xmm0_float_opr;
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LIR_Opr FrameMap::xmm0_double_opr;
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#ifdef _LP64
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LIR_Opr  FrameMap::r8_opr;
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LIR_Opr  FrameMap::r9_opr;
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LIR_Opr FrameMap::r10_opr;
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LIR_Opr FrameMap::r11_opr;
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LIR_Opr FrameMap::r12_opr;
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LIR_Opr FrameMap::r13_opr;
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LIR_Opr FrameMap::r14_opr;
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LIR_Opr FrameMap::r15_opr;
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// r10 and r15 can never contain oops since they aren't available to
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// the allocator
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LIR_Opr  FrameMap::r8_oop_opr;
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LIR_Opr  FrameMap::r9_oop_opr;
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LIR_Opr FrameMap::r11_oop_opr;
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LIR_Opr FrameMap::r12_oop_opr;
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LIR_Opr FrameMap::r13_oop_opr;
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LIR_Opr FrameMap::r14_oop_opr;
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LIR_Opr  FrameMap::r8_metadata_opr;
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LIR_Opr  FrameMap::r9_metadata_opr;
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LIR_Opr FrameMap::r11_metadata_opr;
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LIR_Opr FrameMap::r12_metadata_opr;
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LIR_Opr FrameMap::r13_metadata_opr;
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LIR_Opr FrameMap::r14_metadata_opr;
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#endif // _LP64
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LIR_Opr FrameMap::_caller_save_cpu_regs[] = {};
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LIR_Opr FrameMap::_caller_save_fpu_regs[] = {};
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LIR_Opr FrameMap::_caller_save_xmm_regs[] = {};
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XMMRegister FrameMap::_xmm_regs[] = {};
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XMMRegister FrameMap::nr2xmmreg(int rnr) {
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  assert(_init_done, "tables not initialized");
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  return _xmm_regs[rnr];
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}
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//--------------------------------------------------------
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//               FrameMap
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//--------------------------------------------------------
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void FrameMap::initialize() {
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  assert(!_init_done, "once");
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  assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
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  map_register(0, rsi);  rsi_opr = LIR_OprFact::single_cpu(0);
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  map_register(1, rdi);  rdi_opr = LIR_OprFact::single_cpu(1);
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  map_register(2, rbx);  rbx_opr = LIR_OprFact::single_cpu(2);
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  map_register(3, rax);  rax_opr = LIR_OprFact::single_cpu(3);
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  map_register(4, rdx);  rdx_opr = LIR_OprFact::single_cpu(4);
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  map_register(5, rcx);  rcx_opr = LIR_OprFact::single_cpu(5);
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#ifndef _LP64
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  // The unallocatable registers are at the end
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  map_register(6, rsp);
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  map_register(7, rbp);
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#else
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  map_register( 6, r8);    r8_opr = LIR_OprFact::single_cpu(6);
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  map_register( 7, r9);    r9_opr = LIR_OprFact::single_cpu(7);
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  map_register( 8, r11);  r11_opr = LIR_OprFact::single_cpu(8);
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  map_register( 9, r13);  r13_opr = LIR_OprFact::single_cpu(9);
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  map_register(10, r14);  r14_opr = LIR_OprFact::single_cpu(10);
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  // r12 is allocated conditionally. With compressed oops it holds
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  // the heapbase value and is not visible to the allocator.
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  map_register(11, r12);  r12_opr = LIR_OprFact::single_cpu(11);
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  // The unallocatable registers are at the end
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  map_register(12, r10);  r10_opr = LIR_OprFact::single_cpu(12);
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  map_register(13, r15);  r15_opr = LIR_OprFact::single_cpu(13);
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  map_register(14, rsp);
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  map_register(15, rbp);
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#endif // _LP64
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#ifdef _LP64
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  long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
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  long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
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#else
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  long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
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  long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
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#endif // _LP64
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  fpu0_float_opr   = LIR_OprFact::single_fpu(0);
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  fpu0_double_opr  = LIR_OprFact::double_fpu(0);
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  xmm0_float_opr   = LIR_OprFact::single_xmm(0);
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  xmm0_double_opr  = LIR_OprFact::double_xmm(0);
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  _caller_save_cpu_regs[0] = rsi_opr;
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  _caller_save_cpu_regs[1] = rdi_opr;
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  _caller_save_cpu_regs[2] = rbx_opr;
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  _caller_save_cpu_regs[3] = rax_opr;
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  _caller_save_cpu_regs[4] = rdx_opr;
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  _caller_save_cpu_regs[5] = rcx_opr;
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#ifdef _LP64
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  _caller_save_cpu_regs[6]  = r8_opr;
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  _caller_save_cpu_regs[7]  = r9_opr;
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  _caller_save_cpu_regs[8]  = r11_opr;
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  _caller_save_cpu_regs[9]  = r13_opr;
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  _caller_save_cpu_regs[10] = r14_opr;
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  _caller_save_cpu_regs[11] = r12_opr;
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#endif // _LP64
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  _xmm_regs[0] = xmm0;
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  _xmm_regs[1] = xmm1;
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  _xmm_regs[2] = xmm2;
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  _xmm_regs[3] = xmm3;
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  _xmm_regs[4] = xmm4;
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  _xmm_regs[5] = xmm5;
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  _xmm_regs[6] = xmm6;
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  _xmm_regs[7] = xmm7;
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#ifdef _LP64
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  _xmm_regs[8]   = xmm8;
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  _xmm_regs[9]   = xmm9;
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  _xmm_regs[10]  = xmm10;
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  _xmm_regs[11]  = xmm11;
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  _xmm_regs[12]  = xmm12;
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  _xmm_regs[13]  = xmm13;
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  _xmm_regs[14]  = xmm14;
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  _xmm_regs[15]  = xmm15;
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  _xmm_regs[16]  = xmm16;
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  _xmm_regs[17]  = xmm17;
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  _xmm_regs[18]  = xmm18;
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  _xmm_regs[19]  = xmm19;
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  _xmm_regs[20]  = xmm20;
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  _xmm_regs[21]  = xmm21;
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  _xmm_regs[22]  = xmm22;
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  _xmm_regs[23]  = xmm23;
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  _xmm_regs[24]  = xmm24;
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  _xmm_regs[25]  = xmm25;
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  _xmm_regs[26]  = xmm26;
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  _xmm_regs[27]  = xmm27;
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  _xmm_regs[28]  = xmm28;
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  _xmm_regs[29]  = xmm29;
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  _xmm_regs[30]  = xmm30;
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  _xmm_regs[31]  = xmm31;
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#endif // _LP64
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  for (int i = 0; i < 8; i++) {
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    _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
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  }
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  int num_caller_save_xmm_regs = get_num_caller_save_xmms();
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  for (int i = 0; i < num_caller_save_xmm_regs; i++) {
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    _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
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  }
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  _init_done = true;
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  rsi_oop_opr = as_oop_opr(rsi);
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  rdi_oop_opr = as_oop_opr(rdi);
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  rbx_oop_opr = as_oop_opr(rbx);
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  rax_oop_opr = as_oop_opr(rax);
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  rdx_oop_opr = as_oop_opr(rdx);
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  rcx_oop_opr = as_oop_opr(rcx);
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  rsi_metadata_opr = as_metadata_opr(rsi);
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  rdi_metadata_opr = as_metadata_opr(rdi);
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  rbx_metadata_opr = as_metadata_opr(rbx);
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  rax_metadata_opr = as_metadata_opr(rax);
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  rdx_metadata_opr = as_metadata_opr(rdx);
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  rcx_metadata_opr = as_metadata_opr(rcx);
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  rsp_opr = as_pointer_opr(rsp);
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  rbp_opr = as_pointer_opr(rbp);
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#ifdef _LP64
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  r8_oop_opr = as_oop_opr(r8);
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  r9_oop_opr = as_oop_opr(r9);
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  r11_oop_opr = as_oop_opr(r11);
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  r12_oop_opr = as_oop_opr(r12);
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  r13_oop_opr = as_oop_opr(r13);
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  r14_oop_opr = as_oop_opr(r14);
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  r8_metadata_opr = as_metadata_opr(r8);
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  r9_metadata_opr = as_metadata_opr(r9);
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  r11_metadata_opr = as_metadata_opr(r11);
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  r12_metadata_opr = as_metadata_opr(r12);
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  r13_metadata_opr = as_metadata_opr(r13);
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  r14_metadata_opr = as_metadata_opr(r14);
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#endif // _LP64
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  VMRegPair regs;
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  BasicType sig_bt = T_OBJECT;
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  SharedRuntime::java_calling_convention(&sig_bt, &regs, 1);
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  receiver_opr = as_oop_opr(regs.first()->as_Register());
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}
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Address FrameMap::make_new_address(ByteSize sp_offset) const {
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  // for rbp, based address use this:
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  // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
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  return Address(rsp, in_bytes(sp_offset));
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}
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// ----------------mapping-----------------------
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// all mapping is based on rbp, addressing, except for simple leaf methods where we access
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// the locals rsp based (and no frame is built)
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// Frame for simple leaf methods (quick entries)
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//
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//   +----------+
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//   | ret addr |   <- TOS
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//   +----------+
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//   | args     |
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//   | ......   |
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// Frame for standard methods
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//
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//   | .........|  <- TOS
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//   | locals   |
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//   +----------+
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//   | old rbp,  |  <- EBP
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//   +----------+
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//   | ret addr |
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//   +----------+
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//   |  args    |
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//   | .........|
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// For OopMaps, map a local variable or spill index to an VMRegImpl name.
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// This is the offset from sp() in the frame of the slot for the index,
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// skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
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//
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//           framesize +
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//           stack0         stack0          0  <- VMReg
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//             |              | <registers> |
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//  ...........|..............|.............|
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//      0 1 2 3 x x 4 5 6 ... |                <- local indices
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//      ^           ^        sp()                 ( x x indicate link
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//      |           |                               and return addr)
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//  arguments   non-argument locals
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VMReg FrameMap::fpu_regname (int n) {
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  // Return the OptoReg name for the fpu stack slot "n"
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  // A spilled fpu stack slot comprises to two single-word OptoReg's.
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  return as_FloatRegister(n)->as_VMReg();
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}
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LIR_Opr FrameMap::stack_pointer() {
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  return FrameMap::rsp_opr;
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}
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// JSR 292
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// On x86, there is no need to save the SP, because neither
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// method handle intrinsics, nor compiled lambda forms modify it.
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LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
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  return LIR_OprFact::illegalOpr;
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}
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bool FrameMap::validate_frame() {
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  return true;
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}
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