3
// If you somehow want to use the signal names from the Gekkio study (https://github.com/Gekkio/gb-research/tree/main/sm83-cpu-core)
5
// The file is named with the prefix `_` so that it is parsed first when the mask of the files to be added is set to `*.v`.
13
`define WRITEBACK_N CLK5
14
`define WRITEBACK_P CLK6
15
`define WRITEBACK_EXT CLK7
16
`define MCLK_PULSE_N CLK8
17
`define MCLK_PULSE_P CLK9
21
`define s1_op_ld_nn_a_s010 d[0]
22
`define s1_op_ld_a_nn_s010 d[1]
23
`define s1_op_ld_a_nn_s011 d[2]
24
`define s1_op_alu8 d[3]
25
`define s1_op_jp_cc_sx01 d[4]
26
`define s1_op_call_cc_sx01 d[5]
27
`define s1_op_ret_cc_sx00 d[6]
28
`define s1_op_jr_cc_sx00 d[7]
29
`define s1_op_ldh_a_x d[8]
30
`define s1_op_call_any_s000 d[9]
31
`define s1_op_call_any_s001 d[10]
32
`define s1_op_call_any_s010 d[11]
33
`define s1_op_call_any_s011 d[12]
34
`define s1_op_call_any_s100 d[13]
35
`define s1_op_ld_x_n d[14]
36
`define s1_op_ld_x_n_sx00 d[15]
37
`define s1_op_ld_r_n_sx01 d[16]
38
`define s1_op_s110 d[17]
39
`define s1_op_s111 d[18]
40
`define s1_op_jr_any_sx01 d[19]
41
`define s1_op_jr_any_sx00 d[20]
42
`define s1_op_add_sp_e_s010 d[21]
43
`define s1_op_ld_hl_sp_sx10 d[22]
44
`define s1_cb_res_r_sx00 d[23]
45
`define s1_cb_res_hl_sx01 d[24]
46
`define s1_op_rotate_a d[25]
47
`define s1_op_ld_a_rr_sx01 d[26]
48
`define s1_cb_bit d[27]
49
`define s1_op_ld_rr_a_sx00 d[28]
50
`define s1_op_ld_a_rr_sx00 d[29]
51
`define s1_op_ldh_c_a_sx00 d[30]
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`define s1_op_ldh_n_a_sx00 d[31]
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`define s1_op_ldh_n_a_sx01 d[32]
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`define s1_op_ld_r_hl_sx00 d[33]
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`define s1_op_alu_misc_s0xx d[34]
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`define s1_op_add_hl_sxx0 d[35]
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`define s1_op_dec_rr_sx00 d[36]
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`define s1_op_inc_rr_sx00 d[37]
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`define s1_op_push_sx01 d[38]
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`define s1_op_push_sx00 d[39]
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`define s1_op_ld_r_r_s0xx d[40]
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`define s1_op_40_to_7f d[41]
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`define s1_cb_00_to_3f d[42]
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`define s1_op_jp_any_sx00 d[43]
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`define s1_op_jp_any_sx01 d[44]
66
`define s1_op_jp_any_sx10 d[45]
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`define s1_op_add_hl_sx01 d[46]
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`define s1_op_ld_hl_n_sx01 d[47]
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// [!] d48, 49 are skipped
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`define s1_op_push_sx10 d[50]
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`define s1_op_pop_sx00 d[51]
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`define s1_op_pop_sx01 d[52]
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`define s1_op_add_sp_s001 d[53]
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`define s1_op_ld_hl_sp_sx01 d[54]
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`define s1_cb_set_r_sx00 d[55]
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`define s1_cb_set_hl_sx01 d[56]
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`define s1_cb_set_res_hl_sx00 d[57]
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`define s1_op_pop_sx10 d[58]
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`define s1_op_ldh_a_n_sx01 d[59]
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`define s1_op_ld_nn_sp_s010 d[60]
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`define s1_op_ld_nn_sp_s000 d[61]
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`define s1_op_ld_sp_hl_sx00 d[62]
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`define s1_op_add_sp_e_s000 d[63]
84
`define s1_op_add_sp_e_s011 d[64]
85
`define s1_op_ld_hl_sp_sx00 d[65]
86
`define s1_op_ld_nn_sp_s011 d[66]
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`define s1_op_ld_nn_sp_s001 d[67]
88
`define s1_op_ld_hl_r_sx00 d[68]
89
`define s1_op_incdec8_hl_sx00 d[69]
90
`define s1_op_incdec8_hl_sx01 d[70]
91
`define s1_op_ldh_a_c_sx00 d[71]
92
`define s1_op_ldh_a_n_sx00 d[72]
93
`define s1_op_rst_sx01 d[73]
94
`define s1_op_rst_sx00 d[74]
95
`define s1_int_s101 d[75]
96
`define s1_int_s100 d[76]
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`define s1_int_s000 d[77]
98
`define s1_op_80_to_bf_reg_s0xx d[78]
99
`define s1_op_ret_reti_sx00 d[79]
100
`define s1_op_ret_cc_sx01 d[80]
101
`define s1_op_jp_hl_s0xx d[81]
102
`define s1_op_ret_any_reti_s010 d[82]
103
`define s1_op_ret_any_reti_s011 d[83]
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`define s1_op_ld_hlinc_sx00 d[84]
105
`define s1_op_ld_hldec_sx00 d[85]
106
`define s1_op_ld_rr_sx00 d[86]
107
`define s1_op_ld_rr_sx01 d[87]
108
`define s1_op_ld_rr_sx10 d[88]
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`define s1_op_incdec8_s0xx d[89]
110
`define s1_op_alu_hl_sx00 d[90]
111
`define s1_op_alu_n_sx00 d[91]
112
`define s1_op_rst_sx10 d[92]
113
`define s1_int_s110 d[93]
114
`define s1_cb_r_s0xx d[94]
115
`define s1_cb_hl_sx00 d[95]
116
`define s1_cb_bit_hl_sx01 d[96]
117
`define s1_cb_notbit_hl_sx01 d[97]
118
`define s1_op_incdec8 d[98]
119
`define s1_op_di_ei_s0xx d[99]
120
`define s1_op_halt_s0xx d[100]
121
`define s1_op_nop_stop_s0xx d[101]
122
`define s1_op_cb_s0xx d[102]
123
`define s1_op_jr_any_sx10 d[103]
124
`define s1_op_ea_fa_s000 d[104]
125
`define s1_op_ea_fa_s001 d[105]
130
`define s2_cc_check w[0]
131
`define s2_oe_wzreg_to_idu w[1]
132
`define s2_op_jr_any_sx10 w[2]
133
`define s2_op_alu8 w[3]
134
`define s2_op_ld_abs_a_data_cycle w[4]
135
`define s2_op_ld_a_abs_data_cycle w[5]
138
`define s2_op_jr_any_sx01 w[8]
139
`define s2_op_sp_e_sx10 w[9]
140
`define s2_alu_res w[10]
141
`define s2_addr_valid w[11]
142
`define s2_cb_bit w[12]
143
`define s2_op_ld_abs_rr_sx00 w[13]
144
`define s2_op_ldh_any_a_data_cycle w[14]
145
`define s2_op_add_hl_sxx0 w[15]
146
`define s2_op_incdec_rr w[16]
147
`define s2_op_ldh_imm_sx01 w[17]
148
// gekkio order: org w20 -> org w18 -> org w19
149
`define s2_state0_next w[20]
150
`define s2_data_fetch_cycle w[18]
151
`define s2_op_add_hl_sx01 w[19]
153
`define s2_op_push_sx10 w[21]
154
`define s2_addr_hl w[22]
155
`define s2_op_sp_e_s001 w[23]
156
`define s2_alu_set w[24]
157
`define s2_addr_pc w[25]
159
`define s2_op_ld_nn_sp_s01x w[27]
160
`define s2_oe_pchreg_to_pbus w[28]
161
`define s2_op_ldh_c_sx00 w[29]
162
`define s2_stackop w[30]
163
`define s2_idu_inc w[31]
164
`define s2_state2_next w[32]
165
`define s2_state1_next w[33]
166
`define s2_oe_pclreg_to_pbus w[34]
167
`define s2_idu_dec w[35]
168
`define s2_oe_wzreg_to_pcreg w[36]
169
`define s2_op_incdec8 w[37]
170
`define s2_allow_r8_write w[38]
175
`define s3_alu_rotate_shift_left x[0]
176
`define s3_alu_rotate_shift_right x[1]
177
`define s3_alu_set_or x[2]
178
`define s3_alu_sum x[3]
179
`define s3_alu_logic_or x[4]
180
`define s3_alu_rlc x[5]
181
`define s3_alu_rl x[6]
182
`define s3_alu_rrc x[7]
183
`define s3_alu_rr x[8]
184
`define s3_alu_sra x[9]
185
`define s3_alu_sum_pos_hf_cf x[10]
186
`define s3_alu_sum_neg_cf x[11]
187
`define s3_alu_sum_neg_hf_nf x[12]
188
`define s3_regpair_wren x[13]
189
`define s3_alu_to_reg x[14]
190
`define s3_oe_rbus_to_pbus x[15]
191
`define s3_alu_swap x[16]
192
`define s3_cb_20_to_3f x[17]
193
`define s3_alu_xor x[18]
194
`define s3_alu_logic_and x[19]
195
`define s3_rotate x[20]
196
`define s3_alu_ccf_scf x[21]
197
`define s3_alu_daa x[22]
198
`define s3_alu_add_adc x[23]
199
`define s3_alu_sub_sbc x[24]
200
`define s3_alu_b_complement x[25]
201
`define s3_alu_cpl x[26]
202
`define s3_alu_cp x[27]
203
`define s3_wren_cf x[28]
204
`define s3_wren_hf_nf_zf x[29]
205
`define s3_op_add_sp_e_sx10 x[30]
206
`define s3_op_add_sp_e_s001 x[31]
207
`define s3_op_alu_misc_a x[32]
208
`define s3_op_dec8 x[33]
209
`define s3_alu_reg_to_rbus x[34]
210
`define s3_oe_areg_to_rbus x[35]
211
`define s3_cb_wren_r x[36]
212
`define s3_oe_alu_to_pbus x[37]
213
`define s3_wren_a x[38]
214
`define s3_wren_h x[39]
215
`define s3_wren_l x[40]
216
`define s3_op_reti_s011 x[41]
217
`define s3_oe_hlreg_to_idu x[42]
218
`define s3_oe_hreg_to_rbus x[43]
219
`define s3_oe_lreg_to_rbus x[44]
220
`define s3_oe_dereg_to_idu x[45]
221
`define s3_oe_dreg_to_rbus x[46]
222
`define s3_oe_ereg_to_rbus x[47]
223
`define s3_wren_d x[48]
224
`define s3_wren_b x[49]
225
`define s3_wren_e x[50]
226
`define s3_wren_c x[51]
227
`define s3_oe_bcreg_to_idu x[52]
228
`define s3_oe_breg_to_rbus x[53]
229
`define s3_oe_creg_to_rbus x[54]
230
`define s3_oe_idu_to_uhlbus x[55]
231
`define s3_oe_wzreg_to_uhlbus x[56]
232
`define s3_oe_ubus_to_uhlbus x[57]
233
`define s3_oe_zreg_to_rbus x[58]
234
`define s3_wren_w x[59]
235
`define s3_wren_z x[60]
236
`define s3_wren_sp x[61]
237
`define s3_oe_idu_to_spreg x[62]
238
`define s3_oe_wzreg_to_spreg x[63]
239
`define s3_op_ld_hl_sp_e_s010 x[64]
240
`define s3_oe_spreg_to_idu x[65]
241
`define s3_op_ld_hl_sp_e_s001 x[66]
242
`define s3_oe_idu_to_pcreg x[67]
243
`define s3_wren_pc x[68]
245
module org_to_gekkio (d, w, x, stage1, stage2, stage3);
252
// @gekkio: lsb first
253
output [103:0] stage1; // d[48,49,106] -- ignored
254
output [37:0] stage2; // w[7,39,40] -- ignored
255
output [68:0] stage3; // 1=1
257
// Also: org order: w[20] -> w[18] -> w[19] (w20 is crooked in topo)
258
// gekkio order: org w20 -> org w18 -> org w19
260
for (i=0; i<=47; i=i+1) begin
261
assign stage1[103-i] = d[i];
263
for (i=50; i<106; i=i+1) begin
264
assign stage1[(103+2)-i] = d[i]; // +2 skipped
267
for (i=0; i<=6; i=i+1) begin
268
assign stage2[37-i] = w[i];
270
for (i=8; i<18; i=i+1) begin
271
assign stage2[(37+1)-i] = w[i]; // +1 skipped
274
assign stage2[(37+1) - 18] = w[20];
275
assign stage2[(37+1) - 19] = w[18];
276
assign stage2[(37+1) - 20] = w[19];
277
for (i=21; i<39; i=i+1) begin
278
assign stage2[(37+1)-i] = w[i]; // +1 skipped
281
for (i=0; i<=68; i=i+1) begin
282
assign stage3[68-i] = x[i];
285
endmodule // org_to_gekkio