dmgcpu

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// Elements of standard schematics ("kinda cells") used in the sequencer. Moved separately.
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// Module Definitions [It is possible to wrap here on your primitives]
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`timescale 1ns/1ns
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// This module is essentially used to generate the #MREQ signal. Very cleverly twisted combined logic.
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module seq_mreq ( a, b, c, d, x );
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	input a;
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	input b;	
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	input c;
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	input d;
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	output x;
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	assign x = d ? ~((~a & c) | ~(a|b)) : 1'b1;
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endmodule // seq_mreq
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// Regular posedge DFF (dual rails)
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module seq_dff_posedge_comp ( d, clk, cclk, q );
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	input d;	
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	input clk;
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	input cclk;
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	output q;
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	reg val;
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	initial val = 1'bx;
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	always @(posedge clk) begin
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		val <= d;
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	end
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	assign q = val;
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endmodule // seq_dff_posedge_comp
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module seq_not ( a, x );
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	input a;
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	output x;
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	assign x = ~a;
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endmodule // seq_not
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module seq_nor3 ( a, b, c, x );
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	input a;
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	input b;
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	input c;
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	output x;
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	assign x = ~(a|b|c);
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endmodule // seq_nor3
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module seq_nor ( a, b, x );
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	input a;
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	input b;
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	output x;
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	assign x = ~(a|b);
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endmodule // seq_nor
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module seq_aoi_31 ( a0, a1, a2, b, x );
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	input a0;
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	input a1;
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	input a2;
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	input b;
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	output x;
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	assign x = ~( (a0&a1&a2) | b);
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endmodule // seq_aoi_31
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module seq_oai_21 ( a0, a1, b, x );
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	input a0;	
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	input a1;
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	input b;	
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	output x;
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	assign x = ~( (a0|a1) & b );
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endmodule // seq_oai_21
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// This is essentially the same rs_latch, but with the inputs rearranged.
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module seq_rs_latch2 ( nr, s, q );
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	input nr;
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	input s;
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	output q;
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	reg val;
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	// Let's lower the difficulty level and use 0 here instead of `x`.
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	initial val = 1'b0;
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	// The module design is such that reset overrides set if both are set at the same time.
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	always @(*) begin
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		if (~nr)
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			val = 1'b0;
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		else if (s)
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			val = 1'b1;
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	end
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	assign q = val;
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endmodule // seq_rs_latch2
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// rs_latch
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module seq_rs_latch ( nr, s, q );
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	input nr;
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	input s;
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	output q;
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	reg val;
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	// Let's lower the difficulty level and use 0 here instead of `x`.
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	initial val = 1'b0;
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	// The module design is such that reset overrides set if both are set at the same time.
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	always @(*) begin
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		if (~nr)
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			val = 1'b0;
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		else if (s)
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			val = 1'b1;
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	end
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	assign q = val;
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endmodule // seq_rs_latch
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module seq_latchr_comp ( q, d, res, clk, cclk, ld, nld);
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	output q;
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	input d;
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	input res;
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	input clk;
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	input cclk;
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	input ld;
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	input nld;
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	reg val_in;
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	reg val_out;
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	initial val_in = 1'bx;
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	initial val_out = 1'bx;
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	always @(*) begin
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		if (clk && ld)
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			val_in = d;
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		if (res)
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			val_in = 1'b0;
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	end
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	always @(negedge ld) begin
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		val_out <= val_in;
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	end
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	assign q = val_out;
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endmodule // seq_latchr_comp
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module seq_nand ( a, b, x );
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	input a;
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	input b;
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	output x;
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	assign x = ~(a&b);
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endmodule // seq_nand
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module seq_nand3 ( a, b, c, x );
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	input a;
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	input b;
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	input c;
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	output x;
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	assign x = ~(a&b&c);
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endmodule // seq_nand3
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module seq_nor4 ( a, b, c, d, x );
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	input a;
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	input b;
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	input c;
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	input d;
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	output x;
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	assign x = ~(a|b|c|d);
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endmodule // seq_nor4
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module seq_aoi_21 ( a0, a1, b, x );
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	input a0;
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	input a1;
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	input b;
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	output x;
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	assign x = ~( (a0&a1) | b);
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endmodule // seq_aoi_21
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// Regular transparent latch (dual rails)
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module seq_latch_comp ( d, clk, cclk, nq );
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	input d;
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	input clk;
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	input cclk;
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	output nq;
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	reg val;
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	initial val = 1'b0;
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	always @(*) begin
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		if (clk)
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			val = d;
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	end
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	assign nq = ~val;
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endmodule // seq_latch_comp
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module seq_aoi_22_dyn ( clk, a0, a1, b0, b1, x );
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	input clk;
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	input a0;
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	input a1;
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	input b0;
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	input b1;
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	output x;
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	assign x = clk ? ~( (a0&a1) | (b0&b1) ) : 1'b1;
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endmodule // seq_aoi_22_dyn
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module seq_aoi_221_dyn ( clk, a0, a1, b0, b1, c, x );
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	input clk;
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	input a0;
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	input a1;
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	input b0;
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	input b1;
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	input c;
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	output x;
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	assign x = clk ? ~( (a0&a1) | (b0&b1) | c) : ~c;
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endmodule // seq_aoi_221_dyn
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