dmgcpu

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`timescale 1ns/1ns
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module Bottom ( CLK2, CLK4, CLK5, CLK6, CLK7, DL, DV, bc, bq4, bq5, bq7, Temp_C, Temp_H, Temp_N, Temp_Z, alu, Res, IR, d, w, x, 
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	SYNC_RES, TTB1, TTB2, TTB3, BUS_DISABLE, bro, A );
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	input CLK2;
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	input CLK4;
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	input CLK5;
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	input CLK6;
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	input CLK7; 
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	inout [7:0] DL;			// Internal databus
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	output [7:0] DV;		// ALU Operand2
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	input [5:0] bc;
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	output bq4;
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	output bq5;
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	output bq7;
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	output Temp_C;		// Flag C from temp Z register
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	output Temp_H;		// Flag H from temp Z register
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	output Temp_N;		// Flag N from temp Z register
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	output Temp_Z;			// Flag Z from temp Z register  / zbus msb
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	output [7:0] alu; 		// ALU Operand1
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	input [7:0] Res;		// ALU Result
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	output [7:0] IR;		// Current opcode
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	input [106:0] d;		// Decoder1 output
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	input [40:0] w;			// Decoder2 output
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	input [68:0] x;			// Decoder3 output
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	input SYNC_RES;
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	input TTB1;				// 1: Perform pairwise increment/decrement (simultaneously for two 8-bit IncDec halves)
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	input TTB2;				// 1: Perform decrement
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	input TTB3;				// 1: Perform increment
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	input BUS_DISABLE;			// 1: Bus disable
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	input [7:3] bro; 		// IRQ Logic interrupt address
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	output [15:0] A;		// External core address bus
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	// Internal bottom buses
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	wire [7:0] abus;
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	wire [7:0] bbus;
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	wire [7:0] cbus;
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	wire [7:0] dbus;
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	wire [7:0] ebus;
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	wire [7:0] fbus;
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	wire [7:0] zbus;
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	wire [7:0] wbus;
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	wire [7:0] adl;
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	wire [7:0] adh;
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	wire [7:0] Aout;	// Reg A out to bq Logic
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	// Implementation
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	BusPrecharge precharge (
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		.CLK2(CLK2),
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		.DL(DL),
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		.abus(abus),
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		.bbus(bbus),
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		.cbus(cbus),
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		.dbus(dbus) );
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	BottomLeftLogic bottom_left (
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		.CLK2(CLK2),
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		.bc(bc),
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		.bq4(bq4),
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		.bq5(bq5),
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		.bq7(bq7),
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		.Aout(Aout),
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		.abus(abus),
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		.bbus(bbus),
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		.alu(alu),
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		.DV(DV) );
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	RegsBuses regs (
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		.CLK5(CLK5),
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		.CLK6(CLK6),
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		.w(w),
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		.x(x),
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		.DL(DL),
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		.IR(IR),
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		.abus(abus),
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		.bbus(bbus),
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		.cbus(cbus),
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		.dbus(dbus),
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		.ebus(ebus),
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		.fbus(fbus),
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		.Aout(Aout) );
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	TempRegsBuses temp_regs (
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		.CLK4(CLK4),
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		.CLK5(CLK5),
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		.CLK6(CLK6),
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		.d60(`s1_op_ld_nn_sp_s010),
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		.w(w),
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		.x(x),
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		.DL(DL),
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		.bbus(bbus),
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		.cbus(cbus),
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		.dbus(dbus),
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		.ebus(ebus),
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		.fbus(fbus),
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		.zbus(zbus),
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		.wbus(wbus),
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		.Res(Res),
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		.adl(adl),
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		.adh(adh) );
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	SP sp (
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		.CLK5(CLK5),
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		.CLK6(CLK6),
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		.CLK7(CLK7),
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		.IR4(IR[4]),
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		.IR5(IR[5]),
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		.d60(`s1_op_ld_nn_sp_s010),
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		.d66(`s1_op_ld_nn_sp_s011),
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		.w(w),
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		.x(x),
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		.DL(DL),
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		.abus(abus),
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		.bbus(bbus),
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		.cbus(cbus),
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		.dbus(dbus),
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		.zbus(zbus),
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		.wbus(wbus),
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		.adl(adl),
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		.adh(adh) );
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	PC pc (
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		.CLK5(CLK5),
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		.CLK6(CLK6),
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		.CLK7(CLK7),
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		.d92(`s1_op_rst_sx10),
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		.w(w),
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		.x(x),
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		.DL(DL),
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		.abus(abus),
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		.cbus(cbus),
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		.dbus(dbus),
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		.zbus(zbus),
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		.wbus(wbus),
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		.adl(adl),
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		.adh(adh),
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		.IR(IR),
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		.bro(bro),
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		.SYNC_RES(SYNC_RES) );
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	IncDec incdec (
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		.CLK4(CLK4),
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		.TTB1(TTB1),
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		.TTB2(TTB2),
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		.TTB3(TTB3),
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		.BUS_DISABLE(BUS_DISABLE),
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		.cbus(cbus),
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		.dbus(dbus),
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		.adl(adl),
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		.adh(adh),
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		.AddrBus(A) );
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	assign Temp_C = zbus[4];
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	assign Temp_H = zbus[5];
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	assign Temp_N = zbus[6];
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	assign Temp_Z = zbus[7];
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endmodule // Bottom
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module BusPrecharge ( CLK2, DL, abus, bbus, cbus, dbus );
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	input CLK2;
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	output [7:0] DL;
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	output [7:0] abus;
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	output [7:0] bbus;
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	output [7:0] cbus;
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	output [7:0] dbus;
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	assign   DL = CLK2 ? 8'bzzzzzzzz : 8'b11111111;
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	assign abus = CLK2 ? 8'bzzzzzzzz : 8'b11111111;
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	assign bbus = CLK2 ? 8'bzzzzzzzz : 8'b11111111;
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	assign cbus = CLK2 ? 8'bzzzzzzzz : 8'b11111111;
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	assign dbus = CLK2 ? 8'bzzzzzzzz : 8'b11111111;
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endmodule // BusPrecharge
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// It is very difficult to put this circuit into any category. It belongs to both ALU and registers at the same time, and is generally at the bottom. So it's going to stay here untouched for now.
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module BottomLeftLogic ( CLK2, bc, bq4, bq5, bq7, Aout, abus, bbus, alu, DV );
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	input CLK2;
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	input [5:0] bc;
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	output bq4;
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	output bq5;
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	output bq7;
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	input [7:0] Aout; 		// Current value of the `A` register  (directly from the register bits output)
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	input [7:0] abus; 		// ⚠️ inverse hold (active low)
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	input [7:0] bbus; 		// ⚠️ inverse hold (active low)
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	output [7:0] alu; 		// abus -> ALU Operand 1
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	output [7:0] DV; 		// bbus -> ALU Operand 2
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	wire [7:0] abq; 	// abus Bus keepers outputs
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	wire [7:0] bbq; 	// bbus Bus keepers outputs
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	assign bq4 = Aout[1] | Aout[2] | Aout[3];
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	assign bq5 = Aout[5] | Aout[6] | Aout[7];
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	assign bq7 = Aout[4] & Aout[7];
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	// This requires transparent latches, since nobody could set up a abus/bbus. On the actual circuit, they are also present as a memory on the `not` gate.
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	BusKeeper abus_keepers [7:0] ( .d(abus), .q(abq) );
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	BusKeeper bbus_keepers [7:0] ( .d(bbus), .q(bbq) );
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	// TODO: wtf is this at all?
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	assign DV[0] = ~(CLK2 ? (bbq[0] & ~bc[4]) : 1'b1);
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	assign DV[1] = ~(CLK2 ? (bbq[1] & ~bc[4]) : 1'b1);
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	assign DV[2] = ~(CLK2 ? (bbq[2] & ~bc[4]) : 1'b1);
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	assign DV[3] = ~(CLK2 ? (bbq[3] & ~bc[4]) : 1'b1);
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	assign DV[4] = ~(CLK2 ? (bbq[4] & ~(bc[4] | (bc[0] & bc[1])) ) : 1'b1);
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	assign DV[5] = ~(CLK2 ? (bbq[5] & ~(bc[4] | (bc[0] & bc[5])) ) : 1'b1);
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	assign DV[6] = ~(CLK2 ? (bbq[6] & ~(bc[4] | (bc[0] & bc[2])) ) : 1'b1);
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	assign DV[7] = ~(CLK2 ? (bbq[7] & ~(bc[4] | (bc[0] & bc[3])) ) : 1'b1);
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	assign alu = ~abq;
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	// I decided to put the bc0/bc4 generation in the ALU, so that the bc signals would be made as output from the ALU (for beauty).
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endmodule // BottomLeftLogic
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