dmgcpu

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`timescale 1ns/1ns
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module ALU ( CLK2, CLK4, CLK5, CLK6, CLK7, DV, Res, AllZeros, d42, d58, w, x, bc, alu, bq4, bq5, bq7, ALU_to_Thingy,
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	Temp_C, Temp_H, Temp_N, Temp_Z, ALU_Out1, IR, nIR );
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	input CLK2;
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	input CLK4;			// Used as LoadEnable for ALU_to_bot latch.
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	input CLK5;
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	input CLK6;
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	input CLK7;
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	input [7:0] DV; 		// ALU Operand2
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	output [7:0] Res; 		// ALU Result
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	input AllZeros;			// Res == 0
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	input d42; 			// Gekkio: s1_cb_00_to_3f
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	input d58; 			// Gekkio: s1_op_pop_sx10
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	input [40:0] w;		// Decoder2 outputs
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	input [68:0] x;		// Decoder3 outputs
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	output [5:0] bc;
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	input [7:0] alu;		// ALU Operand1
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	input bq4;
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	input bq5;
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	input bq7;
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	output ALU_to_Thingy; 		// ALU Carry Out
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	input Temp_C;		// Flag C from temp Z register  (zbus[4])
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	input Temp_H;		// Flag H from temp Z register  (zbus[5])
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	input Temp_N;		// Flag N from temp Z register    (zbus[6])
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	input Temp_Z;			// Flag Z from temp Z register / zbus msb  (zbus[7])
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	output ALU_Out1;
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	input [7:0] IR;
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	input [5:0] nIR;
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	// Internal wires
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	wire [7:0] e;		// Operand1 processing results for SET/RES opcodes; module2 e in
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	wire [7:0] f;		// module2 f out; Optionaly complemented Operand2
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	wire [7:0] ca; 		// Shifter (comb1-3) out  (active-low)
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	wire [7:0] bx;		// module2 x out
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	wire [7:0] bm;		// module2 m out (G-terms)
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	wire [7:0] bh;		// module2 h out (P-terms)
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	wire [7:0] logic_op;		// module2 w out; The result of the logical operation AND/OR/permutation of Operand2 bits.
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	wire [7:0] ao; 		// G/P ands outputs to module6  (logic xor)
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	wire [7:1] na; 		// CLA Carry outputs; CLA nots outputs to module6
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	wire [7:0] q; 		// CLA carry complement outputs (bits 0-3: topologicaly left, bits 4-7: topologicaly right)
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	wire [5:0] nbc; 	// #bc
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	wire [13:0] azo;	// Random logic results
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	wire ALU_to_top; 		// Carry In
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	wire ALU_L0; 		// ~Carry7
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	wire ALU_L3; 		// ~Carry4
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	wire ALU_L5; 		// Carry4
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	wire ALU_to_bot;		// Derived from zbus[7] .  As a result of the optimization and transposition of the `bc` derivation circuit, the signal became internal.
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	// Top part (CLA + Sum)
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	module6 Sums [7:0] (
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		.a({na[7:1],ALU_to_top}),
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		.b(ao),
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		.c({8{`s3_alu_xor}}),
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		.d({8{`s3_alu_sum}}),
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		.e(logic_op),
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		.x(Res) );
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	assign ALU_L0 = ~ALU_to_Thingy;  		// ~cout
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	assign ALU_L3 = ~na[4]; 			// ~half cout
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	assign ALU_L5 = na[4]; 				// half cout
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	assign {ALU_to_Thingy, na[7:1]} = ~q;
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	assign ao = bh & bx; 		// ands
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	module5 cla_low ( .m(bm[3:0]), .h(bh[3:0]), .c(ALU_to_top), .q(q[3:0]) );
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	module5 cla_high ( .m(bm[7:4]), .h(bh[7:4]), .c(na[4]), .q(q[7:4]) );
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	// Middle part
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	module2 GP_Terms [7:0] (
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		.a(ca), 
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		.b({8{`s3_alu_logic_and}}), 
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		.c({8{`s3_alu_logic_or}}), 
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		.e(e), 
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		.f(f), 
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		.g({8{`s3_alu_b_complement}}), 
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		.h(bh), 
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		.k(DV), 
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		.m(bm), 
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		.x(bx), 
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		.w(logic_op) );
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	// Shifter
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	Comb3 bit_lsb ( .clk(CLK2), .x(ca[0]), .a({`s3_alu_rlc,DV[7]}), .b({`s3_alu_rotate_shift_right,DV[1]}), .c({`s3_alu_swap,DV[4]}), .d({`s3_alu_rl,bc[1]}) );
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	Comb2 bits_mid [6:1] ( .clk({6{CLK2}}), .x(ca[6:1]), 
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		.a({{`s3_alu_rotate_shift_left,DV[5]},{`s3_alu_rotate_shift_left,DV[4]},{`s3_alu_rotate_shift_left,DV[3]},{`s3_alu_rotate_shift_left,DV[2]},{`s3_alu_rotate_shift_left,DV[1]},{`s3_alu_rotate_shift_left,DV[0]}}), 
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		.b({{`s3_alu_rotate_shift_right,DV[7]},{`s3_alu_rotate_shift_right,DV[6]},{`s3_alu_rotate_shift_right,DV[5]},{`s3_alu_rotate_shift_right,DV[4]},{`s3_alu_rotate_shift_right,DV[3]},{`s3_alu_rotate_shift_right,DV[2]}}), 
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		.c({{`s3_alu_swap,DV[2]},{`s3_alu_swap,DV[1]},{`s3_alu_swap,DV[0]},{`s3_alu_swap,DV[7]},{`s3_alu_swap,DV[6]},{`s3_alu_swap,DV[5]}}) );
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	Comb1 bit_msb ( .clk(CLK2), .x(ca[7]), .a({`s3_alu_rotate_shift_left,DV[6]}), .b({`s3_alu_rr,bc[1]}), .c({`s3_alu_sra,DV[7]}), .d({`s3_alu_rrc,DV[0]}), .e({`s3_alu_swap,DV[3]}) );
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	// Random logic (large spaghetti at the bottom)
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	LargeComb1 rand_logic (
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		.CLK2(CLK2),
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		.CLK6(CLK6),
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		.CLK7(CLK7),
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		.Temp_Z(Temp_Z),
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		.AllZeros(AllZeros),
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		.d42(d42),
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		.d58(d58),
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		.w(w),
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		.x(x),
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		.alu(alu),
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		.IR(IR),
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		.nIR(nIR),
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		.f(f),
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		.bc(bc),
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		.nbc(nbc),
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		.ALU_to_Thingy(ALU_to_Thingy),
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		.ALU_L0(ALU_L0),
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		.Temp_H(Temp_H),
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		.Temp_C(Temp_C),
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		.ALU_L3(ALU_L3),
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		.Temp_N(Temp_N),
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		.ALU_L5(ALU_L5),
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		.bq4(bq4),
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		.bq5(bq5),
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		.bq7(bq7),
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		.azo(azo) );
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	// Flags (part of the circuit below spaghetti, some FF and domino inverters)
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	assign e = ~{azo[10],azo[9],azo[8],azo[6],azo[5],azo[4],azo[3],azo[0]};
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	assign ALU_to_top = ~azo[13];
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	assign ALU_Out1 = ~azo[11];
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	bc bc5 ( .nd(azo[1]), .CLK(CLK6), .CCLK(CLK5), .Load(`s3_wren_hf_nf_zf), .q(bc[5]), .nq(nbc[5]) ); 			// Flag H
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	bc bc1 ( .nd(azo[2]), .CLK(CLK6), .CCLK(CLK5), .Load(`s3_wren_cf), .q(bc[1]), .nq(nbc[1]) ); 			// Flag C
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	bc bc2 ( .nd(azo[7]), .CLK(CLK6), .CCLK(CLK5), .Load(`s3_wren_hf_nf_zf), .q(bc[2]), .nq(nbc[2]) );  		// Flag N
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	bc bc3 ( .nd(azo[12]), .CLK(CLK6), .CCLK(CLK5), .Load(`s3_wren_hf_nf_zf), .q(bc[3]), .nq(nbc[3]) ); 	// Flag Z
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	ALU_to_bot_latch zbus_msb ( .d( Temp_Z /* =zbus[7] */ ), .CLK(CLK6), .CCLK(CLK5), .Load(CLK4), .q(ALU_to_bot) ); 			// zbus msb latch
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	// Regarding "bc". I tend to think that even though bc0/bc4 is at the bottom, it is still part of the ALU.
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	// Moved this circuit in my HDL inside the ALU instead of at the bottom. Then wire [5:0] bc; will become output.
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	assign bc[0] = (IR[4] & IR[5] & `s2_op_push_sx10);
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	assign bc[4] = ALU_to_bot & `s2_op_sp_e_sx10;
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	assign nbc[0] = ~bc[0];
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	assign nbc[4] = ~bc[4];
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endmodule // ALU
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// Carry lookahead generator
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module module5 ( m, h, c, q );
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	input [3:0] m; 		// G
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	input [3:0] h;		// P
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	input c;			// CarryIn
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	/* verilator lint_off UNOPTFLAT */
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	output [3:0] q; 	// C1...C4  (inverted)
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	assign q[0] = ~(m[0] | (h[0] & c)); 		// ~Carry1 out
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	assign q[1] = ~(m[1] | (h[1] & ~q[0]));		// ~Carry2 out
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	assign q[2] = ~(m[2] | (h[2] & ~q[1]));		// ~Carry3 out
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	assign q[3] = ~(m[3] | (h[3] & ~q[2]));		// ~Carry4 out
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endmodule // module5
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// Sums block
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module module6 ( a, b, c, d, e, x );
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	input a;
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	input b;
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	input c; 			// x18 (s3_alu_xor)
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	input d; 			// x3 (s3_alu_sum)
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	input e; 			// The result of the logical operation AND/OR/permutation of Operand2 bits.
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	output x;
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	assign x = ( (b & c) | ((a ^ b) & d) | (e) );
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endmodule // module6
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// G/P Terms Product.
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// The module "hybridizes" the computation of G/P terms by reusing them for logical AND/OR operations. It also contains a Shifter result bypass.
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module module2 ( a, b, c, e, f, g, h, k, m, x, w );
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	input a; 		// Result of permutation(shift/rotate/swap) of Operand2 bits; [!] active low input
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	input b;  			// x19 (s3_alu_logic_and)
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	input c; 			// x4 (s3_alu_logic_or)
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	input e; 		// Large Comb results; Result of executing SET/RES opcodes for operand1
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	output f; 		// To Large Comb NAND trees; Operand2 optionally complemented
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	input g; 		// x25 (s3_alu_b_complement)
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	output h; 		// To CLA Generator (P-terms)
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	input k; 		// Operand2: DV[n]
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	output m; 		// To CLA Generator (G-terms)
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	output x; 		// To ands near CLA
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	output w; 		// To Sums; The result of the logical operation AND/OR/permutation of Operand2 bits.
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	// Missing transparent DLatch that stores the result of the shifter (permutation result). This DLatch is critically needed, for example, when shifting DV to the left, in this case the following will happen (get ready, it's complicated):
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	// The dynamic comb of shifter during CLK2 pre-charges the output to 1 - this will be the complement of the result of the shifter bit (i.e. - 0). At the same time, the s3_alu_rotate_shift_left command does not multiplex the output of the dynamic comb for lsb in any way;
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	// Therefore, the output for lsb will be 0 (or rather the complementary value of 1 pre-charge, which is what is stored on the DLatch).
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	wire shift_res_q;  		// <-- active low
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	BusKeeper perm_ff (.d(a), .q(shift_res_q) );
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	assign f = k ^ g;
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	assign h = e | f;
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	assign x = ~(e & f);
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	assign m = ~x;
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	assign w = ~(shift_res_q & (~(b&m)) & (~(c&h))); 		// or simply 3-OR, if you demorganize the operation.
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endmodule // module2
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// AOI-22222 dynamic (5 ANDs to OR Inverted)
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module Comb1 ( clk, x, a, b, c, d, e );
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	input clk;
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	output x;
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	input [1:0] a;
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	input [1:0] b;
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	input [1:0] c;
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	input [1:0] d;
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	input [1:0] e;
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	assign x = clk ? ~((a[0]&a[1]) | (b[0]&b[1]) | (c[0]&c[1]) | (d[0]&d[1]) | (e[0]&e[1])) : 1'b1;
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endmodule // Comb1
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// AOI-222 dynamic (3 ANDs to OR Inverted)
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module Comb2 ( clk, x, a, b, c );
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	input clk;
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	output x;
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	input [1:0] a;
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	input [1:0] b;
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	input [1:0] c;
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	assign x = clk ? ~((a[0]&a[1]) | (b[0]&b[1]) | (c[0]&c[1]) ) : 1'b1;
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endmodule // Comb2
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// AOI-2222 dynamic (4 ANDs to OR Inverted)
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module Comb3 ( clk, x, a, b, c, d );
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	input clk;
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	output x;
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	input [1:0] a;
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	input [1:0] b;
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	input [1:0] c;
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	input [1:0] d;
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	assign x = clk ? ~((a[0]&a[1]) | (b[0]&b[1]) | (c[0]&c[1]) | (d[0]&d[1]) ) : 1'b1;
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endmodule // Comb3
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// Random logic
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module LargeComb1 ( CLK2, CLK6, CLK7, Temp_Z, AllZeros, d42, d58, w, x, alu, IR, nIR, f, bc, nbc, ALU_to_Thingy, ALU_L0, Temp_H, Temp_C, ALU_L3, Temp_N, ALU_L5, bq4, bq5, bq7, azo );
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	input CLK2;
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	input CLK6;
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	input CLK7;
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	input Temp_Z;
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	input AllZeros;
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	input d42;
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	input d58;
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	input [40:0] w;
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	input [68:0] x;
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	input [7:0] alu;
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	input [7:0] IR;
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	input [5:0] nIR;
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	input [7:0] f;
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	input [5:0] bc;
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	input [5:0] nbc;
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	input ALU_to_Thingy;
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	input ALU_L0;
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	input Temp_H;
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	input Temp_C;
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	input ALU_L3;
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	input Temp_N;
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	input ALU_L5;
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	input bq4;
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	input bq5;
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	input bq7;
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	output [13:0] azo; 		// "azo" means absolutely nothing, just the name of the random logic results
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	wire [13:0] azo_latched; 		// Inputs to DLatch from dynamic logic
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	wire [13:0] az;		// random logic results (non-dynamic)
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	// ALU Trees (by hand); Tree numbering is topological (how they are arranged on the chip)
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	// Random logic in SM83 is organized in such a way that all related calculations are performed in one place (topologically). On the one hand it is very convenient (the logic is isolated), on the other hand it turns out to be a very confusing doshirak.
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	// ALU trees 0,3-6,8-10 are responsible for preprocessing operand 1 for SET/RES opcodes (CB table) as well as DAA (decimal correction)
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	// Because of the topological numbering of the trees, they don't go in order, which is a bit ugly.
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	// ALU tree 11 deals with code checking for conditional instructions (NZ/Z/NC/C)
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	assign az[0] = ~( alu[0] | (`s2_alu_set&nIR[3]&nIR[4]&nIR[5]) | (`s2_alu_res&(IR[3]|IR[4]|IR[5])) );
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	assign az[1] = ~( (ALU_L5&((nIR[0]&`s2_op_incdec8)|`s3_alu_sum_pos_hf_cf)) | (ALU_L3&`s3_alu_sum_neg_hf_nf) | `s3_alu_cpl | `s2_cb_bit | `s3_alu_logic_and | (Temp_H&d58) );
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	assign az[2] = ~( (f[0]&`s3_alu_rotate_shift_right) | (Temp_C&d58) | (nbc[1]&IR[3]&`s3_alu_ccf_scf) | (`s3_alu_ccf_scf&nIR[3]) | (`s3_alu_sum_pos_hf_cf&ALU_to_Thingy) | (`s3_alu_daa&(bc[1]|(nbc[2]&ALU_to_Thingy))) | (bc[1]&`s3_alu_cpl) | (f[7]&`s3_alu_rotate_shift_left) | (ALU_L0&`s3_alu_sum_neg_cf) );
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	assign az[3] = ~( alu[1] | (`s2_alu_set&IR[3]&nIR[4]&nIR[5]) | (`s2_alu_res&(nIR[3]|IR[4]|IR[5])) | (`s3_alu_daa&(bc[5]|(nbc[2]&bq4))) );
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	assign az[4] = ~( alu[2] | (`s2_alu_set&nIR[3]&IR[4]&nIR[5]) | (`s2_alu_res&(IR[3]|nIR[4]|IR[5])) | (`s3_alu_daa&nbc[2]&(bq4|bc[5])) );
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	assign az[5] = ~( alu[3] | (`s2_alu_set&IR[3]&IR[4]&nIR[5]) | (`s2_alu_res&(nIR[3]|nIR[4]|IR[5])) | (`s3_alu_daa&bc[2]&bc[5]) );
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	assign az[6] = ~( alu[4] | (`s2_alu_set&nIR[3]&nIR[4]&IR[5]) | (`s2_alu_res&(IR[3]|IR[4]|nIR[5])) | (`s3_alu_daa&bc[2]&bc[5]) );
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	assign az[7] = ~( (bc[2]&`s3_alu_daa) | `s3_alu_sum_neg_hf_nf | `s3_alu_cpl | (Temp_N&d58) );
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	assign az[8] = ~( alu[5] | (`s2_alu_set&IR[3]&nIR[4]&IR[5]) | (`s2_alu_res&(nIR[3]|IR[4]|nIR[5])) | (bc[2]&`s3_alu_daa&((bc[1]&nbc[5])|(nbc[1]&bc[5]))) | (nbc[2]&`s3_alu_daa&((bq5)|(bc[1])|(bq4&bq7))) );
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	assign az[9] = ~( alu[6] | (`s2_alu_set&nIR[3]&IR[4]&IR[5]) | (`s2_alu_res&(IR[3]|nIR[4]|nIR[5])) | (bc[2]&`s3_alu_daa&(nbc[1]&bc[5])) | (nbc[2]&`s3_alu_daa&((bq4&bq7)|(bc[1])|(bq5))) );
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	assign az[10] = ~( alu[7] | (`s2_alu_set&IR[3]&IR[4]&IR[5]) | (`s2_alu_res&(nIR[3]|nIR[4]|nIR[5])) | (bc[2]&`s3_alu_daa&(bc[1]|bc[5])) );
301
	assign az[11] = ~( 
302
		`s2_cc_check & (              // inverted condition check
303
			(nIR[3]&nIR[4] & bc[3]) | // 00 | Z
304
			( IR[3]&nIR[4] &nbc[3]) | // 10 | NZ
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			(nIR[3]& IR[4] & bc[1]) | // 01 | C
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			( IR[3]& IR[4] &nbc[1])   // 11 | NC
307
		));
308
	assign az[12] = ~(
309
		(f[0]&`s2_cb_bit&nIR[3]&nIR[4]&nIR[5]) |
310
		(f[1]&`s2_cb_bit&IR[3]&nIR[4]&nIR[5]) |
311
		(f[2]&`s2_cb_bit&nIR[3]&IR[4]&nIR[5]) |
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		(f[3]&`s2_cb_bit&IR[3]&IR[4]&nIR[5]) |
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		(f[4]&`s2_cb_bit&nIR[3]&nIR[4]&IR[5]) |
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		(f[5]&`s2_cb_bit&IR[3]&nIR[4]&IR[5]) |
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		(f[6]&`s2_cb_bit&nIR[3]&IR[4]&IR[5]) |
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		(f[7]&`s2_cb_bit&IR[3]&IR[4]&IR[5]) |
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		(AllZeros&(d42|`s2_op_alu8|`s2_op_incdec8|`s3_alu_daa)) | (d58&Temp_Z) | (bc[3]&(`s3_alu_cpl|`s2_op_add_hl_sxx0|`s3_alu_ccf_scf|`s2_op_add_hl_sx01)) );
318
	assign az[13] = ~( `s3_alu_cp | (`s2_op_incdec8&nIR[0]) | (`s2_op_sp_e_sx10&bc[1]) | (`s3_alu_sub_sbc&(nIR[3]|nbc[1])) | (`s2_op_add_hl_sx01&bc[1]) | (`s3_alu_add_adc&IR[3]) );
319

320
	// Dynamic part
321

322
	assign azo_latched[0] = CLK2 ? az[0] : 1'bz;
323
	assign azo_latched[1] = CLK7 ? (CLK6 ? az[1] : 1'bz) : 1'bz;		// -> bc5   -- Flag H
324
	assign azo_latched[2] = CLK7 ? (CLK6 ? az[2] : 1'bz) : 1'bz;		// -> bc1   -- Flag C
325
	assign azo_latched[3] = CLK2 ? az[3] : 1'bz;
326
	assign azo_latched[4] = CLK2 ? az[4] : 1'bz;
327
	assign azo_latched[5] = CLK2 ? az[5] : 1'bz;
328
	assign azo_latched[6] = CLK2 ? az[6] : 1'bz;
329
	assign azo_latched[7] = CLK7 ? (CLK6 ? az[7] : 1'bz) : 1'bz;		// -> bc2   -- Flag N
330
	assign azo_latched[8] = CLK2 ? az[8] : 1'bz;
331
	assign azo_latched[9] = CLK2 ? az[9] : 1'bz;
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	assign azo_latched[10] = CLK2 ? az[10] : 1'bz;
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	assign azo_latched[11] = CLK7 ? (CLK6 ? az[11] : 1'bz) : 1'bz; 		// -> ALU_Out1  -- Skip branch
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	assign azo_latched[12] = CLK7 ? (CLK6 ? az[12] : 1'bz) : 1'bz;		// -> bc3   -- Flag Z
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	assign azo_latched[13] = CLK2 ? az[13] : 1'bz;		// -> ALU_to_top aka CarryIn
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	// Transparent DLatch is required at least for asymmetric dynamic logic (which uses CLK7/CLK6, i.e. for flags and cc_check);
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	// The others don't require DLatch, but are made for unification.
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	// The use of asymmetric CLK is obviously related to the peculiarities of overlapped instruction execution in SM83  (CLK6 = writeback; CLK7 = writeback_ext)
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	BusKeeper latched_results [13:0] ( .d(azo_latched), .q(azo) );
341

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endmodule // LargeComb1
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// This latch is used to hold flags (bc3=Z / bc2=N / bc5=H / bc1=C); The silly name `bc` is just from the early stages of research
345
module bc ( nd, CLK, CCLK, Load, q, nq );
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	input nd; 
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	input CLK; 
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	input CCLK; 
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	input Load; 
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	output q;
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	output nq;
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	reg val_in;
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	reg val_out;
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	initial val_in = 1'b0;
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	initial val_out = 1'b0;
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359
	always @(*) begin
360
		if (CLK && Load)
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			val_in = ~nd;
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	end
363

364
	always @(negedge Load) begin
365
		val_out <= val_in;
366
	end
367

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	assign q = val_out;
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	assign nq = ~q;
370

371
endmodule // bc
372

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// This latch exists in a single instance and is used to hold the zbus msb (ie - sign)
374
module ALU_to_bot_latch ( d, CLK, CCLK, Load, q );
375

376
	input d; 
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	input CLK; 
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	input CCLK; 
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	input Load; 
380
	output q;
381

382
	reg val_in;
383
	reg val_out;
384
	initial val_in = 1'b0;
385
	initial val_out = 1'b0;
386

387
	always @(*) begin
388
		if (CLK && Load)
389
			val_in = d;
390
	end
391

392
	always @(negedge Load) begin
393
		val_out <= val_in;
394
	end
395

396
	assign q = val_out;
397

398
endmodule // ALU_to_bot_latch
399