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MukPlis
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src/SW_LOG.vhd
228 строк
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AndreyM
TU good variant
29 мар 2026, 10:04
29 мар 2026, 10:04
0abc2b4
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------------------------------------------------------------------------------- -- -- Title : SW_LOG -- Design : MukOtl -- Author : ������������ Windows -- Company : 1 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity SW_LOG is port( CLK : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0); WR_LO : in std_logic; -- WR20 ������ LO RD_LO : in std_logic; WR_CMOP : in std_logic; -- WR20 ������ CMOP_OUT RD_CMOP : in std_logic; RD_BUF_IN : in std_logic; RD_BUF_TTL : in std_logic; CMOP_IN1 : in std_logic; CMOP_IN2 : in std_logic; CMOP_IN3 : in std_logic; TTL_IN1 : in std_logic; TTL_IN2 : in std_logic; TTL_IN3 : in std_logic; IN1P : in std_logic; IN2P : in std_logic; IN3P : in std_logic; IN1M : in std_logic; IN2M : in std_logic; IN3M : in std_logic; U_IN : in std_logic_vector(12 downto 1); LO_OUT : out std_logic_vector(4 downto 1); CMOP_OUT : out std_logic_vector(6 downto 1); U_OUT : out std_logic_vector(12 downto 1); OUT_TST : out std_logic_vector(12 downto 1); TU : in std_logic; TU_SL : in std_logic ); end SW_LOG; architecture SW_LOG of SW_LOG is signal buf_inp : std_logic_vector(3 downto 1); signal buf_inm : std_logic_vector(3 downto 1); signal buf_cmop_in : std_logic_vector(3 downto 1); signal buf_ttl_in : std_logic_vector(3 downto 1); signal rg_cmop_out : std_logic_vector(6 downto 1):="000000"; signal rg_lo : std_logic_vector(4 downto 1):="0000"; signal buf_u : std_logic; signal OUT1 : std_logic; -- signal OUT2 : std_logic; -- signal OUT3 : std_logic; -- signal OUT4 : std_logic; -- signal OUT5 : std_logic; -- signal OUT6 : std_logic; -- signal OUT7 : std_logic; -- signal OUT8 : std_logic; -- signal OUT9 : std_logic; -- signal OUT10 : std_logic; -- signal OUT11 : std_logic; -- signal OUT12 : std_logic; -- signal OUT13 : std_logic; -- signal OUT14 : std_logic; -- signal OUT15 : std_logic; -- signal OUT16 : std_logic; -- signal OUT17 : std_logic; -- signal OUT18 : std_logic; -- signal OUT19 : std_logic; -- signal OUT20 : std_logic; -- signal OUT21 : std_logic; -- signal OUT22 : std_logic; -- signal OUT23 : std_logic; -- signal OUT24 : std_logic; -- --signal IN1_P : std_logic; -- --signal IN2_P : std_logic; -- --signal IN3_P : std_logic; -- -- --signal IN1_M : std_logic; -- --signal IN2_M : std_logic; -- --signal IN3_M : std_logic; -- ---- Component declarations ----- component ID7 port( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic; Q4 : out std_logic; Q5 : out std_logic; Q6 : out std_logic; Q7 : out std_logic ); end component; begin D1_inst : ID7 port map ( A0=>rg_lo(1), A1=>rg_lo(2), A2=>rg_lo(3), Q0=>OUT1, Q1=>OUT2, Q2=>OUT3, Q3=>OUT4, Q4=>OUT5, Q5=>OUT6, Q6=>OUT7, Q7=>OUT8 ); D2_inst : ID7 port map ( A0=>rg_lo(1), A1=>rg_lo(2), A2=>rg_lo(3), Q0=>OUT9, Q1=>OUT10, Q2=>OUT11, Q3=>OUT12, Q4=>OUT13, Q5=>OUT14, Q6=>OUT15, Q7=>OUT16 ); D3_inst : ID7 port map ( A0=>rg_lo(1), A1=>rg_lo(2), A2=>rg_lo(3), Q0=>OUT17, Q1=>OUT18, Q2=>OUT19, Q3=>OUT20, Q4=>OUT21, Q5=>OUT22, Q6=>OUT23, Q7=>OUT24 ); WR_LO_PROC: process (CLK) begin if rising_edge(CLK) then if WR_LO='1' then rg_lo<= D(4 downto 1); end if; end if; end process WR_LO_PROC; WR_CMOP_PROC: process (CLK) begin if rising_edge(CLK) then if WR_CMOP='1' then rg_cmop_out<= D(6 downto 1); end if; end if; end process WR_CMOP_PROC; buf_u<= U_IN(1) or U_IN(2) or U_IN(3) or U_IN(4) or U_IN(5) or U_IN(6) or U_IN(7) or U_IN(8) or U_IN(9) or U_IN(10) or U_IN(11) or U_IN(12); buf_inp(1)<=not IN1P when TU_SL='0' else OUT13; buf_inp(2)<=not IN2P when TU_SL='0' else OUT14; buf_inp(3)<=not IN3P when TU_SL='0' else OUT15; buf_inm(1)<=not IN1M when TU_SL='0' else OUT16; buf_inm(2)<=not IN2M when TU_SL='0' else OUT17; buf_inm(3)<=not IN3M when TU_SL='0' else OUT18; buf_cmop_in( 1)<=not CMOP_IN1 when TU_SL='0' else OUT19; -- 2 buf_cmop_in( 2)<=not CMOP_IN2 when TU_SL='0' else OUT20; -- 3 buf_cmop_in( 3)<=not CMOP_IN3 when TU_SL='0' else OUT21; -- 4 buf_ttl_in( 1)<=not TTL_IN1 when TU_SL='0' else OUT22; buf_ttl_in( 2)<=not TTL_IN2 when TU_SL='0' else OUT23; buf_ttl_in( 3)<= TTL_IN3 when TU_SL='0' else buf_u; Q(7 downto 0)<="000" & rg_lo & '0' when RD_LO='1' else '0' & rg_cmop_out & '0' when RD_CMOP='1' else buf_inm & '0' & buf_inp & '0' when RD_BUF_IN='1' else buf_cmop_in & '0' & buf_ttl_in & '0' when RD_BUF_TTL='1' else "ZZZZZZZZ"; OUT_TST<= OUT12 & OUT11 & OUT10 & OUT9 & OUT8 & OUT7 & OUT6 & OUT5 & OUT4 & OUT3 & OUT2 & OUT1; LO_OUT<=not rg_lo; CMOP_OUT<=not rg_cmop_out; U_OUT<=not U_IN; end SW_LOG;