src/RG_LED.vhd - master - m59/McoPlis

src/RG_LED.vhd
65 строк2 KB
AndreyM
DDC ok
14 мар 2026, 17:52
14 мар 2026, 17:525f9af40
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;


entity RG_LED is
Port ( 
	CLK 	: in  std_logic;
	D 		: in  std_logic_vector(4 downto 0); 
	Q 		: out std_logic_vector(4 downto 0);
	WR_LED	: in  std_logic;
	WR_AVAR	: in  std_logic;
	RD_LED	: in  std_logic;
	RD_AVAR	: in  std_logic;
	TU		: in  std_logic;											-- ��������� ������ ZD
	ZD_LED	: in  std_logic;											-- ��������� ������ ZD
	OG_LED	: in  std_logic;											-- ��������� ������ OD 
	HL4_R	: out  std_logic;  											-- avar �����
	HL4_G	: out  std_logic;											-- norma �����
	HL5_R	: out  std_logic;											-- ��������� ������ UPR_MOD(Decod_led_r)
	HL5_G	: out  std_logic;											-- ��������� ������ ZD(Decod_led_g)
	HL6		: out  std_logic;
	HL7		: out  std_logic;
	HL8		: out  std_logic;
	HL9		: out  std_logic;
	HL10	: out  std_logic
 );
end RG_LED;

architecture Bev of RG_LED is

signal rg_avar_norm	: std_logic_vector(3 downto 0):=(others => '0');	-- �������� �������
signal rg_led		: std_logic_vector(4 downto 0):=(others => '0');	-- �������� �������

begin 
	
WR_PROC: process (CLK)
begin
  if rising_edge(CLK) then
	  
	if WR_LED='1' then	  
		rg_led(4 downto 0)<= D(4 downto 0);
	end if;	
	  
	if WR_AVAR='1' then	  
		rg_avar_norm(3 downto 0)<= D(3 downto 0);
	end if;		  
	
  end if;  
end process WR_PROC;    
	
Q(4 downto 0)<='0' & rg_avar_norm when RD_AVAR='1' else rg_led(4 downto 0) when RD_LED='1' else "ZZZZZ";	
	
HL4_R<=rg_avar_norm(0);
HL4_G<=rg_avar_norm(1);
HL5_R<=rg_avar_norm(2);
HL5_G<=rg_avar_norm(3);
HL6<=rg_led(0);
HL7<=rg_led(1);
HL8<=rg_led(2);
HL9<=rg_led(3);
HL10<=rg_led(4);

end Bev;