cubefs

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// Copyright 2014 The Go Authors.  All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package x86asm
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import (
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	"fmt"
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	"strings"
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)
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// IntelSyntax returns the Intel assembler syntax for the instruction, as defined by Intel's XED tool.
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func IntelSyntax(inst Inst, pc uint64, symname SymLookup) string {
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	if symname == nil {
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		symname = func(uint64) (string, uint64) { return "", 0 }
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	}
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18
	var iargs []Arg
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	for _, a := range inst.Args {
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		if a == nil {
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			break
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		}
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		iargs = append(iargs, a)
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	}
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26
	switch inst.Op {
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	case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, LOOPNE, JCXZ, JECXZ, JRCXZ, LOOP, LOOPE, MOV, XLATB:
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		if inst.Op == MOV && (inst.Opcode>>16)&0xFFFC != 0x0F20 {
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			break
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		}
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		for i, p := range inst.Prefix {
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			if p&0xFF == PrefixAddrSize {
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				inst.Prefix[i] &^= PrefixImplicit
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			}
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		}
36
	}
37

38
	switch inst.Op {
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	case MOV:
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		dst, _ := inst.Args[0].(Reg)
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		src, _ := inst.Args[1].(Reg)
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		if ES <= dst && dst <= GS && EAX <= src && src <= R15L {
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			src -= EAX - AX
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			iargs[1] = src
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		}
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		if ES <= dst && dst <= GS && RAX <= src && src <= R15 {
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			src -= RAX - AX
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			iargs[1] = src
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		}
50

51
		if inst.Opcode>>24&^3 == 0xA0 {
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			for i, p := range inst.Prefix {
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				if p&0xFF == PrefixAddrSize {
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					inst.Prefix[i] |= PrefixImplicit
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				}
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			}
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		}
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	}
59

60
	switch inst.Op {
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	case AAM, AAD:
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		if imm, ok := iargs[0].(Imm); ok {
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			if inst.DataSize == 32 {
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				iargs[0] = Imm(uint32(int8(imm)))
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			} else if inst.DataSize == 16 {
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				iargs[0] = Imm(uint16(int8(imm)))
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			}
68
		}
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70
	case PUSH:
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		if imm, ok := iargs[0].(Imm); ok {
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			iargs[0] = Imm(uint32(imm))
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		}
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	}
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76
	for _, p := range inst.Prefix {
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		if p&PrefixImplicit != 0 {
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			for j, pj := range inst.Prefix {
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				if pj&0xFF == p&0xFF {
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					inst.Prefix[j] |= PrefixImplicit
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				}
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			}
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		}
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	}
85

86
	if inst.Op != 0 {
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		for i, p := range inst.Prefix {
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			switch p &^ PrefixIgnored {
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			case PrefixData16, PrefixData32, PrefixCS, PrefixDS, PrefixES, PrefixSS:
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				inst.Prefix[i] |= PrefixImplicit
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			}
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			if p.IsREX() {
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				inst.Prefix[i] |= PrefixImplicit
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			}
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			if p.IsVEX() {
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				if p == PrefixVEX3Bytes {
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					inst.Prefix[i+2] |= PrefixImplicit
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				}
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				inst.Prefix[i] |= PrefixImplicit
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				inst.Prefix[i+1] |= PrefixImplicit
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			}
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		}
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	}
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105
	if isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ {
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		for i, p := range inst.Prefix {
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			if p == PrefixPT || p == PrefixPN {
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				inst.Prefix[i] |= PrefixImplicit
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			}
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		}
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	}
112

113
	switch inst.Op {
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	case AAA, AAS, CBW, CDQE, CLC, CLD, CLI, CLTS, CMC, CPUID, CQO, CWD, DAA, DAS,
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		FDECSTP, FINCSTP, FNCLEX, FNINIT, FNOP, FWAIT, HLT,
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		ICEBP, INSB, INSD, INSW, INT, INTO, INVD, IRET, IRETQ,
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		LAHF, LEAVE, LRET, MONITOR, MWAIT, NOP, OUTSB, OUTSD, OUTSW,
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		PAUSE, POPA, POPF, POPFQ, PUSHA, PUSHF, PUSHFQ,
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		RDMSR, RDPMC, RDTSC, RDTSCP, RET, RSM,
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		SAHF, STC, STD, STI, SYSENTER, SYSEXIT, SYSRET,
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		UD2, WBINVD, WRMSR, XEND, XLATB, XTEST:
122

123
		if inst.Op == NOP && inst.Opcode>>24 != 0x90 {
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			break
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		}
126
		if inst.Op == RET && inst.Opcode>>24 != 0xC3 {
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			break
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		}
129
		if inst.Op == INT && inst.Opcode>>24 != 0xCC {
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			break
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		}
132
		if inst.Op == LRET && inst.Opcode>>24 != 0xcb {
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			break
134
		}
135
		for i, p := range inst.Prefix {
136
			if p&0xFF == PrefixDataSize {
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				inst.Prefix[i] &^= PrefixImplicit | PrefixIgnored
138
			}
139
		}
140

141
	case 0:
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		// ok
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	}
144

145
	switch inst.Op {
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	case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, MONITOR, MWAIT, XLATB:
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		iargs = nil
148

149
	case STOSB, STOSW, STOSD, STOSQ:
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		iargs = iargs[:1]
151

152
	case LODSB, LODSW, LODSD, LODSQ, SCASB, SCASW, SCASD, SCASQ:
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		iargs = iargs[1:]
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	}
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156
	const (
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		haveData16 = 1 << iota
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		haveData32
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		haveAddr16
160
		haveAddr32
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		haveXacquire
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		haveXrelease
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		haveLock
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		haveHintTaken
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		haveHintNotTaken
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		haveBnd
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	)
168
	var prefixBits uint32
169
	prefix := ""
170
	for _, p := range inst.Prefix {
171
		if p == 0 {
172
			break
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		}
174
		if p&0xFF == 0xF3 {
175
			prefixBits &^= haveBnd
176
		}
177
		if p&(PrefixImplicit|PrefixIgnored) != 0 {
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			continue
179
		}
180
		switch p {
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		default:
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			prefix += strings.ToLower(p.String()) + " "
183
		case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
184
			if inst.Op == 0 {
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				prefix += strings.ToLower(p.String()) + " "
186
			}
187
		case PrefixREPN:
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			prefix += "repne "
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		case PrefixLOCK:
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			prefixBits |= haveLock
191
		case PrefixData16, PrefixDataSize:
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			prefixBits |= haveData16
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		case PrefixData32:
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			prefixBits |= haveData32
195
		case PrefixAddrSize, PrefixAddr16:
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			prefixBits |= haveAddr16
197
		case PrefixAddr32:
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			prefixBits |= haveAddr32
199
		case PrefixXACQUIRE:
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			prefixBits |= haveXacquire
201
		case PrefixXRELEASE:
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			prefixBits |= haveXrelease
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		case PrefixPT:
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			prefixBits |= haveHintTaken
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		case PrefixPN:
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			prefixBits |= haveHintNotTaken
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		case PrefixBND:
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			prefixBits |= haveBnd
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		}
210
	}
211
	switch inst.Op {
212
	case JMP:
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		if inst.Opcode>>24 == 0xEB {
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			prefixBits &^= haveBnd
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		}
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	case RET, LRET:
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		prefixBits &^= haveData16 | haveData32
218
	}
219

220
	if prefixBits&haveXacquire != 0 {
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		prefix += "xacquire "
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	}
223
	if prefixBits&haveXrelease != 0 {
224
		prefix += "xrelease "
225
	}
226
	if prefixBits&haveLock != 0 {
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		prefix += "lock "
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	}
229
	if prefixBits&haveBnd != 0 {
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		prefix += "bnd "
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	}
232
	if prefixBits&haveHintTaken != 0 {
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		prefix += "hint-taken "
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	}
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	if prefixBits&haveHintNotTaken != 0 {
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		prefix += "hint-not-taken "
237
	}
238
	if prefixBits&haveAddr16 != 0 {
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		prefix += "addr16 "
240
	}
241
	if prefixBits&haveAddr32 != 0 {
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		prefix += "addr32 "
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	}
244
	if prefixBits&haveData16 != 0 {
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		prefix += "data16 "
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	}
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	if prefixBits&haveData32 != 0 {
248
		prefix += "data32 "
249
	}
250

251
	if inst.Op == 0 {
252
		if prefix == "" {
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			return "<no instruction>"
254
		}
255
		return prefix[:len(prefix)-1]
256
	}
257

258
	var args []string
259
	for _, a := range iargs {
260
		if a == nil {
261
			break
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		}
263
		args = append(args, intelArg(&inst, pc, symname, a))
264
	}
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266
	var op string
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	switch inst.Op {
268
	case NOP:
269
		if inst.Opcode>>24 == 0x0F {
270
			if inst.DataSize == 16 {
271
				args = append(args, "ax")
272
			} else {
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				args = append(args, "eax")
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			}
275
		}
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277
	case BLENDVPD, BLENDVPS, PBLENDVB:
278
		args = args[:2]
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280
	case INT:
281
		if inst.Opcode>>24 == 0xCC {
282
			args = nil
283
			op = "int3"
284
		}
285

286
	case LCALL, LJMP:
287
		if len(args) == 2 {
288
			args[0], args[1] = args[1], args[0]
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		}
290

291
	case FCHS, FABS, FTST, FLDPI, FLDL2E, FLDLG2, F2XM1, FXAM, FLD1, FLDL2T, FSQRT, FRNDINT, FCOS, FSIN:
292
		if len(args) == 0 {
293
			args = append(args, "st0")
294
		}
295

296
	case FPTAN, FSINCOS, FUCOMPP, FCOMPP, FYL2X, FPATAN, FXTRACT, FPREM1, FPREM, FYL2XP1, FSCALE:
297
		if len(args) == 0 {
298
			args = []string{"st0", "st1"}
299
		}
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301
	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
302
		if len(args) == 1 {
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			args = append(args, "st0")
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		}
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	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
307
		if len(args) == 1 {
308
			args = []string{"st0", args[0]}
309
		}
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311
	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
312
	FixSegment:
313
		for i := len(inst.Prefix) - 1; i >= 0; i-- {
314
			p := inst.Prefix[i] & 0xFF
315
			switch p {
316
			case PrefixCS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
317
				if inst.Mode != 64 || p == PrefixFS || p == PrefixGS {
318
					args = append(args, strings.ToLower((inst.Prefix[i] & 0xFF).String()))
319
					break FixSegment
320
				}
321
			case PrefixDS:
322
				if inst.Mode != 64 {
323
					break FixSegment
324
				}
325
			}
326
		}
327
	}
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329
	if op == "" {
330
		op = intelOp[inst.Op]
331
	}
332
	if op == "" {
333
		op = strings.ToLower(inst.Op.String())
334
	}
335
	if args != nil {
336
		op += " " + strings.Join(args, ", ")
337
	}
338
	return prefix + op
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}
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341
func intelArg(inst *Inst, pc uint64, symname SymLookup, arg Arg) string {
342
	switch a := arg.(type) {
343
	case Imm:
344
		if s, base := symname(uint64(a)); s != "" {
345
			suffix := ""
346
			if uint64(a) != base {
347
				suffix = fmt.Sprintf("%+d", uint64(a)-base)
348
			}
349
			return fmt.Sprintf("$%s%s", s, suffix)
350
		}
351
		if inst.Mode == 32 {
352
			return fmt.Sprintf("%#x", uint32(a))
353
		}
354
		if Imm(int32(a)) == a {
355
			return fmt.Sprintf("%#x", int64(a))
356
		}
357
		return fmt.Sprintf("%#x", uint64(a))
358
	case Mem:
359
		if a.Base == EIP {
360
			a.Base = RIP
361
		}
362
		prefix := ""
363
		switch inst.MemBytes {
364
		case 1:
365
			prefix = "byte "
366
		case 2:
367
			prefix = "word "
368
		case 4:
369
			prefix = "dword "
370
		case 8:
371
			prefix = "qword "
372
		case 16:
373
			prefix = "xmmword "
374
		case 32:
375
			prefix = "ymmword "
376
		}
377
		switch inst.Op {
378
		case INVLPG:
379
			prefix = "byte "
380
		case STOSB, MOVSB, CMPSB, LODSB, SCASB:
381
			prefix = "byte "
382
		case STOSW, MOVSW, CMPSW, LODSW, SCASW:
383
			prefix = "word "
384
		case STOSD, MOVSD, CMPSD, LODSD, SCASD:
385
			prefix = "dword "
386
		case STOSQ, MOVSQ, CMPSQ, LODSQ, SCASQ:
387
			prefix = "qword "
388
		case LAR:
389
			prefix = "word "
390
		case BOUND:
391
			if inst.Mode == 32 {
392
				prefix = "qword "
393
			} else {
394
				prefix = "dword "
395
			}
396
		case PREFETCHW, PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, CLFLUSH:
397
			prefix = "zmmword "
398
		}
399
		switch inst.Op {
400
		case MOVSB, MOVSW, MOVSD, MOVSQ, CMPSB, CMPSW, CMPSD, CMPSQ, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ, LODSB, LODSW, LODSD, LODSQ:
401
			switch a.Base {
402
			case DI, EDI, RDI:
403
				if a.Segment == ES {
404
					a.Segment = 0
405
				}
406
			case SI, ESI, RSI:
407
				if a.Segment == DS {
408
					a.Segment = 0
409
				}
410
			}
411
		case LEA:
412
			a.Segment = 0
413
		default:
414
			switch a.Base {
415
			case SP, ESP, RSP, BP, EBP, RBP:
416
				if a.Segment == SS {
417
					a.Segment = 0
418
				}
419
			default:
420
				if a.Segment == DS {
421
					a.Segment = 0
422
				}
423
			}
424
		}
425

426
		if inst.Mode == 64 && a.Segment != FS && a.Segment != GS {
427
			a.Segment = 0
428
		}
429

430
		prefix += "ptr "
431
		if s, disp := memArgToSymbol(a, pc, inst.Len, symname); s != "" {
432
			suffix := ""
433
			if disp != 0 {
434
				suffix = fmt.Sprintf("%+d", disp)
435
			}
436
			return prefix + fmt.Sprintf("[%s%s]", s, suffix)
437
		}
438
		if a.Segment != 0 {
439
			prefix += strings.ToLower(a.Segment.String()) + ":"
440
		}
441
		prefix += "["
442
		if a.Base != 0 {
443
			prefix += intelArg(inst, pc, symname, a.Base)
444
		}
445
		if a.Scale != 0 && a.Index != 0 {
446
			if a.Base != 0 {
447
				prefix += "+"
448
			}
449
			prefix += fmt.Sprintf("%s*%d", intelArg(inst, pc, symname, a.Index), a.Scale)
450
		}
451
		if a.Disp != 0 {
452
			if prefix[len(prefix)-1] == '[' && (a.Disp >= 0 || int64(int32(a.Disp)) != a.Disp) {
453
				prefix += fmt.Sprintf("%#x", uint64(a.Disp))
454
			} else {
455
				prefix += fmt.Sprintf("%+#x", a.Disp)
456
			}
457
		}
458
		prefix += "]"
459
		return prefix
460
	case Rel:
461
		if pc == 0 {
462
			return fmt.Sprintf(".%+#x", int64(a))
463
		} else {
464
			addr := pc + uint64(inst.Len) + uint64(a)
465
			if s, base := symname(addr); s != "" && addr == base {
466
				return fmt.Sprintf("%s", s)
467
			} else {
468
				addr := pc + uint64(inst.Len) + uint64(a)
469
				return fmt.Sprintf("%#x", addr)
470
			}
471
		}
472
	case Reg:
473
		if int(a) < len(intelReg) && intelReg[a] != "" {
474
			switch inst.Op {
475
			case VMOVDQA, VMOVDQU, VMOVNTDQA, VMOVNTDQ:
476
				return strings.Replace(intelReg[a], "xmm", "ymm", -1)
477
			default:
478
				return intelReg[a]
479
			}
480
		}
481
	}
482
	return strings.ToLower(arg.String())
483
}
484

485
var intelOp = map[Op]string{
486
	JAE:       "jnb",
487
	JA:        "jnbe",
488
	JGE:       "jnl",
489
	JNE:       "jnz",
490
	JG:        "jnle",
491
	JE:        "jz",
492
	SETAE:     "setnb",
493
	SETA:      "setnbe",
494
	SETGE:     "setnl",
495
	SETNE:     "setnz",
496
	SETG:      "setnle",
497
	SETE:      "setz",
498
	CMOVAE:    "cmovnb",
499
	CMOVA:     "cmovnbe",
500
	CMOVGE:    "cmovnl",
501
	CMOVNE:    "cmovnz",
502
	CMOVG:     "cmovnle",
503
	CMOVE:     "cmovz",
504
	LCALL:     "call far",
505
	LJMP:      "jmp far",
506
	LRET:      "ret far",
507
	ICEBP:     "int1",
508
	MOVSD_XMM: "movsd",
509
	XLATB:     "xlat",
510
}
511

512
var intelReg = [...]string{
513
	F0:  "st0",
514
	F1:  "st1",
515
	F2:  "st2",
516
	F3:  "st3",
517
	F4:  "st4",
518
	F5:  "st5",
519
	F6:  "st6",
520
	F7:  "st7",
521
	M0:  "mmx0",
522
	M1:  "mmx1",
523
	M2:  "mmx2",
524
	M3:  "mmx3",
525
	M4:  "mmx4",
526
	M5:  "mmx5",
527
	M6:  "mmx6",
528
	M7:  "mmx7",
529
	X0:  "xmm0",
530
	X1:  "xmm1",
531
	X2:  "xmm2",
532
	X3:  "xmm3",
533
	X4:  "xmm4",
534
	X5:  "xmm5",
535
	X6:  "xmm6",
536
	X7:  "xmm7",
537
	X8:  "xmm8",
538
	X9:  "xmm9",
539
	X10: "xmm10",
540
	X11: "xmm11",
541
	X12: "xmm12",
542
	X13: "xmm13",
543
	X14: "xmm14",
544
	X15: "xmm15",
545

546
	// TODO: Maybe the constants are named wrong.
547
	SPB: "spl",
548
	BPB: "bpl",
549
	SIB: "sil",
550
	DIB: "dil",
551

552
	R8L:  "r8d",
553
	R9L:  "r9d",
554
	R10L: "r10d",
555
	R11L: "r11d",
556
	R12L: "r12d",
557
	R13L: "r13d",
558
	R14L: "r14d",
559
	R15L: "r15d",
560
}
561