bin/mnemdb.json - development - githubmirror/x64dbg

bin/mnemdb.json
9 518 строк5 MB
Duncan Ogilvie
DBG: sync mnemdb with the latest idaref
12 окт 2019, 17:00
12 окт 2019, 17:0083e1705
{
  "__github_x86-64": "https://github.com/nologic/idaref/blob/master/x86-64.sql", 
  "__license_x86-64": "GPLv2", 
  "_github_x86-64-brief": "https://github.com/radareorg/radare2/blob/c4d416c7b96d2735c24a2f9e2787df3fdb764c71/libr/asm/d/x86.sdb.txt", 
  "_license_x86-64-brief": "GPLv3", 
  "x86-64": [
    {
      "description": "AAA-ASCII Adjust After Addition\r\nOpcode                     Instruction                Op/   64-bit    Compat/ Description\r\n                                                      En    Mode      Leg Mode\r\n37                         AAA                        NP    Invalid   Valid       ASCII adjust AL after addition.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En              Operand 1                 Operand 2                      Operand 3                      Operand 4\r\n     NP                  NA                       NA                             NA                                 NA\r\n\r\nDescription\r\nAdjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied\r\nsource and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD\r\ninstruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The\r\nAAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.\r\nIf the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there\r\nwas no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4\r\nthrough 7 of the AL register are set to 0.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         IF ((AL AND 0FH) > 9) or (AF = 1)\r\n               THEN\r\n                   AX <- AX + 106H;\r\n                   AF <- 1;\r\n                   CF <- 1;\r\n               ELSE\r\n                   AF <- 0;\r\n                   CF <- 0;\r\n         FI;\r\n         AL <- AL AND 0FH;\r\nFI;\r\n\r\nFlags Affected\r\nThe AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF,\r\nSF, ZF, and PF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AAA"
    }, 
    {
      "description": "AAD-ASCII Adjust AX Before Division\r\nOpcode                    Instruction                    Op/   64-bit    Compat/ Description\r\n                                                         En    Mode      Leg Mode\r\nD5 0A                     AAD                            NP    Invalid   Valid      ASCII adjust AX before division.\r\nD5 ib                     AAD imm8                       NP    Invalid   Valid      Adjust AX before division to number base\r\n                                                                                    imm8.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En             Operand 1                      Operand 2                     Operand 3                     Operand 4\r\n    NP                  NA                               NA                         NA                             NA\r\n\r\nDescription\r\nAdjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the\r\nAH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD\r\ninstruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the\r\nAX register by an unpacked BCD value.\r\nThe AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H.\r\nThe value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10)\r\nnumber in registers AH and AL.\r\nThe generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the\r\n\"Operation\" section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH\r\nfor decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust\r\nASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine\r\ncode (D5 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         tempAL <- AL;\r\n         tempAH <- AH;\r\n         AL <- (tempAL + (tempAH * imm8)) AND FFH;\r\n         (* imm8 is set to 0AH for the AAD mnemonic.*)\r\n         AH <- 0;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AAD"
    }, 
    {
      "description": "AAM-ASCII Adjust AX After Multiply\r\nOpcode                   Instruction                 Op/    64-bit     Compat/ Description\r\n                                                     En     Mode       Leg Mode\r\nD4 0A                    AAM                         NP     Invalid    Valid       ASCII adjust AX after multiply.\r\nD4 ib                    AAM imm8                    NP     Invalid    Valid       Adjust AX after multiply to number base\r\n                                                                                   imm8.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n  Op/En             Operand 1                   Operand 2                      Operand 3                     Operand 4\r\n    NP                 NA                           NA                            NA                             NA\r\n\r\nDescription\r\nAdjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD\r\nvalues. The AX register is the implied source and destination operand for this instruction. The AAM instruction is\r\nonly useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and\r\nstores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain\r\nthe correct 2-digit unpacked (base 10) BCD result.\r\nThe generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked\r\ndigits of any number base (see the \"Operation\" section below). Here, the imm8 byte is set to the selected number\r\nbase (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted\r\nby all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the\r\ninstruction must be hand coded in machine code (D4 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         tempAL <- AL;\r\n         AH <- tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)\r\n         AL <- tempAL MOD imm8;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#DE                   If an immediate value of 0 is used.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AAM"
    }, 
    {
      "description": "AAS-ASCII Adjust AL After Subtraction\r\nOpcode                     Instruction                Op/   64-bit    Compat/ Description\r\n                                                      En    Mode      Leg Mode\r\n3F                         AAS                        NP    Invalid   Valid       ASCII adjust AL after subtraction.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En              Operand 1                 Operand 2                     Operand 3                      Operand 4\r\n     NP                   NA                          NA                         NA                              NA\r\n\r\nDescription\r\nAdjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register\r\nis the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows\r\na SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte\r\nresult in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-\r\ndigit unpacked BCD result.\r\nIf the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no\r\ndecimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL\r\nregister is left with its top four bits set to 0.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-bit mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         IF ((AL AND 0FH) > 9) or (AF = 1)\r\n               THEN\r\n                   AX <- AX - 6;\r\n                   AH <- AH - 1;\r\n                   AF <- 1;\r\n                   CF <- 1;\r\n                   AL <- AL AND 0FH;\r\n               ELSE\r\n                   CF <- 0;\r\n                   AF <- 0;\r\n                   AL <- AL AND 0FH;\r\n         FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and\r\nPF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AAS"
    }, 
    {
      "description": "ADC-Add with Carry\r\nOpcode                     Instruction                  Op/    64-bit      Compat/ Description\r\n                                                        En     Mode        Leg Mode\r\n14 ib                      ADC AL, imm8                 I      Valid       Valid       Add with carry imm8 to AL.\r\n15 iw                      ADC AX, imm16                I      Valid       Valid       Add with carry imm16 to AX.\r\n15 id                      ADC EAX, imm32               I      Valid       Valid       Add with carry imm32 to EAX.\r\nREX.W + 15 id              ADC RAX, imm32               I      Valid       N.E.        Add with carry imm32 sign extended to 64-\r\n                                                                                       bits to RAX.\r\n80 /2 ib                   ADC r/m8, imm8               MI     Valid       Valid       Add with carry imm8 to r/m8.\r\n                                      *\r\nREX + 80 /2 ib             ADC r/m8 , imm8              MI     Valid       N.E.        Add with carry imm8 to r/m8.\r\n81 /2 iw                   ADC r/m16, imm16             MI     Valid       Valid       Add with carry imm16 to r/m16.\r\n81 /2 id                   ADC r/m32, imm32             MI     Valid       Valid       Add with CF imm32 to r/m32.\r\nREX.W + 81 /2 id           ADC r/m64, imm32             MI     Valid       N.E.        Add with CF imm32 sign extended to 64-bits\r\n                                                                                       to r/m64.\r\n83 /2 ib                   ADC r/m16, imm8              MI     Valid       Valid       Add with CF sign-extended imm8 to r/m16.\r\n83 /2 ib                   ADC r/m32, imm8              MI     Valid       Valid       Add with CF sign-extended imm8 into r/m32.\r\nREX.W + 83 /2 ib           ADC r/m64, imm8              MI     Valid       N.E.        Add with CF sign-extended imm8 into r/m64.\r\n10 /r                      ADC r/m8, r8                 MR     Valid       Valid       Add with carry byte register to r/m8.\r\nREX + 10 /r                ADC r/m8*, r8*               MR     Valid       N.E.        Add with carry byte register to r/m64.\r\n11 /r                      ADC r/m16, r16               MR     Valid       Valid       Add with carry r16 to r/m16.\r\n11 /r                      ADC r/m32, r32               MR     Valid       Valid       Add with CF r32 to r/m32.\r\nREX.W + 11 /r              ADC r/m64, r64               MR     Valid       N.E.        Add with CF r64 to r/m64.\r\n12 /r                      ADC r8, r/m8                 RM     Valid       Valid       Add with carry r/m8 to byte register.\r\nREX + 12 /r                ADC r8*, r/m8*               RM     Valid       N.E.        Add with carry r/m64 to byte register.\r\n13 /r                      ADC r16, r/m16               RM     Valid       Valid       Add with carry r/m16 to r16.\r\n13 /r                      ADC r32, r/m32               RM     Valid       Valid       Add with CF r/m32 to r32.\r\nREX.W + 13 /r              ADC r64, r/m64               RM     Valid       N.E.        Add with CF r/m64 to r64.\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En              Operand 1                    Operand 2                       Operand 3                      Operand 4\r\n    RM             ModRM:reg (r, w)              ModRM:r/m (r)                        NA                              NA\r\n    MR             ModRM:r/m (r, w)              ModRM:reg (r)                        NA                              NA\r\n    MI             ModRM:r/m (r, w)                  imm8                             NA                              NA\r\n        I          AL/AX/EAX/RAX                     imm8                             NA                              NA\r\n\r\nDescription\r\nAdds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and\r\nstores the result in the destination operand. The destination operand can be a register or a memory location; the\r\nsource operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be\r\nused in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate\r\nvalue is used as an operand, it is sign-extended to the length of the destination operand format.\r\n\r\n\r\n\r\n\r\n\r\nThe ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates\r\nthe result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result,\r\nrespectively. The SF flag indicates the sign of the signed result.\r\nThe ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is\r\nfollowed by an ADC instruction.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST + SRC + CF;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADC:       extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);\r\n\r\nADC:       extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short\r\n*sum_out);\r\n\r\nADC:       extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);\r\n\r\nADC:       extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64\r\n*sum_out);\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If the destination is located in a non-writable segment.\r\n                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                       selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADC"
    }, 
    {
      "description": "ADCX - Unsigned Integer Addition of Two Operands with Carry Flag\r\n Opcode/                                 Op/    64/32bit      CPUID      Description\r\n Instruction                             En     Mode          Feature\r\n                                                Support       Flag\r\n 66 0F 38 F6 /r                          RM     V/V           ADX        Unsigned addition of r32 with CF, r/m32 to r32, writes CF.\r\n ADCX r32, r/m32\r\n 66 REX.w 0F 38 F6 /r                    RM     V/NE          ADX        Unsigned addition of r64 with CF, r/m64 to r64, writes CF.\r\n ADCX r64, r/m64\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n      Op/En                 Operand 1                      Operand 2                    Operand 3                    Operand 4\r\n       RM                ModRM:reg (r, w)                ModRM:r/m (r)                      NA                           NA\r\n\r\nDescription\r\nPerforms an unsigned addition of the destination operand (first operand), the source operand (second operand)\r\nand the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-\r\npurpose register, whereas the source operand can be a general-purpose register or memory location. The state of\r\nCF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the\r\nunsigned addition of the operands.\r\nThe ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with\r\na carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state.\r\nOften, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).\r\nThis instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-\r\nbit mode.\r\nIn 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-\r\ntional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.\r\nADCX executes normally either inside or outside a transaction region.\r\nNote: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 2A.\r\n\r\nOperation\r\nIF OperandSize is 64-bit\r\n    THEN CF:DEST[63:0] <- DEST[63:0] + SRC[63:0] + CF;\r\n    ELSE CF:DEST[31:0] <- DEST[31:0] + SRC[31:0] + CF;\r\nFI;\r\n\r\nFlags Affected\r\nCF is updated based on result. OF, SF, ZF, AF and PF flags are unmodified.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);\r\nunsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n                         If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n\r\n\r\n\r\n#GP(0)              For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n                    selector.\r\n#PF(fault-code)     For a page fault.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)              For an illegal address in the SS segment.\r\n#GP(0)              If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)              For an illegal address in the SS segment.\r\n#GP(0)              If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#PF(fault-code)     For a page fault.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     For a page fault.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADCX"
    }, 
    {
      "description": "ADD-Add\r\nOpcode                    Instruction                   Op/   64-bit       Compat/ Description\r\n                                                        En    Mode         Leg Mode\r\n04 ib                     ADD AL, imm8                  I     Valid        Valid        Add imm8 to AL.\r\n05 iw                     ADD AX, imm16                 I     Valid        Valid        Add imm16 to AX.\r\n05 id                     ADD EAX, imm32                I     Valid        Valid        Add imm32 to EAX.\r\nREX.W + 05 id             ADD RAX, imm32                I     Valid        N.E.         Add imm32 sign-extended to 64-bits to RAX.\r\n80 /0 ib                  ADD r/m8, imm8                MI    Valid        Valid        Add imm8 to r/m8.\r\nREX + 80 /0 ib            ADD r/m8*, imm8               MI    Valid        N.E.         Add sign-extended imm8 to r/m64.\r\n81 /0 iw                  ADD r/m16, imm16              MI    Valid        Valid        Add imm16 to r/m16.\r\n81 /0 id                  ADD r/m32, imm32              MI    Valid        Valid        Add imm32 to r/m32.\r\nREX.W + 81 /0 id          ADD r/m64, imm32              MI    Valid        N.E.         Add imm32 sign-extended to 64-bits to\r\n                                                                                        r/m64.\r\n83 /0 ib                  ADD r/m16, imm8               MI    Valid        Valid        Add sign-extended imm8 to r/m16.\r\n83 /0 ib                  ADD r/m32, imm8               MI    Valid        Valid        Add sign-extended imm8 to r/m32.\r\nREX.W + 83 /0 ib          ADD r/m64, imm8               MI    Valid        N.E.         Add sign-extended imm8 to r/m64.\r\n00 /r                     ADD r/m8, r8                  MR    Valid        Valid        Add r8 to r/m8.\r\n                                     *    *\r\nREX + 00 /r               ADD r/m8 , r8                 MR    Valid        N.E.         Add r8 to r/m8.\r\n01 /r                     ADD r/m16, r16                MR    Valid        Valid        Add r16 to r/m16.\r\n01 /r                     ADD r/m32, r32                MR    Valid        Valid        Add r32 to r/m32.\r\nREX.W + 01 /r             ADD r/m64, r64                MR    Valid        N.E.         Add r64 to r/m64.\r\n02 /r                     ADD r8, r/m8                  RM    Valid        Valid        Add r/m8 to r8.\r\n                                 *        *\r\nREX + 02 /r               ADD r8 , r/m8                 RM    Valid        N.E.         Add r/m8 to r8.\r\n03 /r                     ADD r16, r/m16                RM    Valid        Valid        Add r/m16 to r16.\r\n03 /r                     ADD r32, r/m32                RM    Valid        Valid        Add r/m32 to r32.\r\nREX.W + 03 /r             ADD r64, r/m64                RM    Valid        N.E.         Add r/m64 to r64.\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En             Operand 1                     Operand 2                        Operand 3                     Operand 4\r\n   RM            ModRM:reg (r, w)                ModRM:r/m (r)                        NA                             NA\r\n   MR            ModRM:r/m (r, w)                ModRM:reg (r)                        NA                             NA\r\n   MI            ModRM:r/m (r, w)                    imm8                             NA                             NA\r\n    I            AL/AX/EAX/RAX                       imm8                             NA                             NA\r\n\r\nDescription\r\nAdds the destination operand (first operand) and the source operand (second operand) and then stores the result\r\nin the destination operand. The destination operand can be a register or a memory location; the source operand\r\ncan be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one\r\ninstruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination\r\noperand format.\r\nThe ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer oper-\r\nands and sets the CF and OF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The\r\nSF flag indicates the sign of the signed result.\r\n\r\n\r\n\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST + SRC;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)               If the destination is located in a non-writable segment.\r\n                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                     If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                     selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)               If the memory address is in a non-canonical form.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADD"
    }, 
    {
      "description": "ADDPD-Add Packed Double-Precision Floating-Point Values\r\n Opcode/                               Op /    64/32        CPUID          Description\r\n Instruction                           En      bit Mode     Feature\r\n                                               Support      Flag\r\n 66 0F 58 /r                           RM      V/V          SSE2           Add packed double-precision floating-point values from\r\n ADDPD xmm1, xmm2/m128                                                     xmm2/mem to xmm1 and store result in xmm1.\r\n VEX.NDS.128.66.0F.WIG 58 /r           RVM     V/V          AVX            Add packed double-precision floating-point values from\r\n VADDPD xmm1,xmm2,                                                         xmm3/mem to xmm2 and store result in xmm1.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 58 /r           RVM     V/V          AVX            Add packed double-precision floating-point values from\r\n VADDPD ymm1, ymm2,                                                        ymm3/mem to ymm2 and store result in ymm1.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 58 /r           FV      V/V          AVX512VL       Add packed double-precision floating-point values from\r\n VADDPD xmm1 {k1}{z}, xmm2,                                 AVX512F        xmm3/m128/m64bcst to xmm2 and store result in xmm1\r\n xmm3/m128/m64bcst                                                         with writemask k1.\r\n EVEX.NDS.256.66.0F.W1 58 /r           FV      V/V          AVX512VL       Add packed double-precision floating-point values from\r\n VADDPD ymm1 {k1}{z}, ymm2,                                 AVX512F        ymm3/m256/m64bcst to ymm2 and store result in ymm1\r\n ymm3/m256/m64bcst                                                         with writemask k1.\r\n EVEX.NDS.512.66.0F.W1 58 /r           FV      V/V          AVX512F        Add packed double-precision floating-point values from\r\n VADDPD zmm1 {k1}{z}, zmm2,                                                zmm3/m512/m64bcst to zmm2 and store result in zmm1\r\n zmm3/m512/m64bcst{er}                                                     with writemask k1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n        Op/En                  Operand 1                    Operand 2                     Operand 3                 Operand 4\r\n         RM                 ModRM:reg (r, w)               ModRM:r/m (r)                      NA                        NA\r\n         RVM                 ModRM:reg (w)                   VEX.vvvv                    ModRM:r/m (r)                  NA\r\n       FV-RVM                ModRM:reg (w)                  EVEX.vvvv                    ModRM:r/m (r)                  NA\r\n\r\nDescription\r\nAdd two, four or eight packed double-precision floating-point values from the first source operand to the second\r\nsource operand, and stores the packed double-precision floating-point results in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nVADDPD (EVEX encoded versions) when src2 operand is a vector register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n\r\n\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]\r\n         ELSE\r\n              IF *merging-masking*                ; merging-masking\r\n                   THEN *DEST[i+63:i] remains unchanged*\r\n                   ELSE                           ; zeroing-masking\r\n                        DEST[i+63:i] <- 0\r\n              FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPD (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+63:i] <- SRC1[i+63:i] + SRC2[63:0]\r\n                  ELSE\r\n                       DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                 ; merging-masking\r\n                  THEN *DEST[i+63:i] remains unchanged*\r\n                  ELSE                            ; zeroing-masking\r\n                       DEST[i+63:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] + SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] + SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n.\r\n\r\n\r\n\r\n\r\n\r\nVADDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nADDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] + SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] + SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDPD __m512d _mm512_add_pd (__m512d a, __m512d b);\r\nVADDPD __m512d _mm512_mask_add_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVADDPD __m512d _mm512_maskz_add_pd (__mmask8 k, __m512d a, __m512d b);\r\nVADDPD __m256d _mm256_mask_add_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVADDPD __m256d _mm256_maskz_add_pd (__mmask8 k, __m256d a, __m256d b);\r\nVADDPD __m128d _mm_mask_add_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVADDPD __m128d _mm_maskz_add_pd (__mmask8 k, __m128d a, __m128d b);\r\nVADDPD __m512d _mm512_add_round_pd (__m512d a, __m512d b, int);\r\nVADDPD __m512d _mm512_mask_add_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVADDPD __m512d _mm512_maskz_add_round_pd (__mmask8 k, __m512d a, __m512d b, int);\r\nADDPD __m256d _mm256_add_pd (__m256d a, __m256d b);\r\nADDPD __m128d _mm_add_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDPD"
    }, 
    {
      "description": "ADDPS-Add Packed Single-Precision Floating-Point Values\r\n Opcode/                                Op /   64/32       CPUID      Description\r\n Instruction                            En     bit Mode    Feature\r\n                                               Support     Flag\r\n 0F 58 /r                               RM     V/V         SSE        Add packed single-precision floating-point values from\r\n ADDPS xmm1, xmm2/m128                                                xmm2/m128 to xmm1 and store result in xmm1.\r\n VEX.NDS.128.0F.WIG 58 /r               RVM    V/V         AVX        Add packed single-precision floating-point values from\r\n VADDPS xmm1,xmm2, xmm3/m128                                          xmm3/m128 to xmm2 and store result in xmm1.\r\n VEX.NDS.256.0F.WIG 58 /r               RVM    V/V         AVX        Add packed single-precision floating-point values from\r\n VADDPS ymm1, ymm2, ymm3/m256                                         ymm3/m256 to ymm2 and store result in ymm1.\r\n EVEX.NDS.128.0F.W0 58 /r               FV     V/V         AVX512VL   Add packed single-precision floating-point values from\r\n VADDPS xmm1 {k1}{z}, xmm2,                                AVX512F    xmm3/m128/m32bcst to xmm2 and store result in\r\n xmm3/m128/m32bcst                                                    xmm1 with writemask k1.\r\n EVEX.NDS.256.0F.W0 58 /r               FV     V/V         AVX512VL   Add packed single-precision floating-point values from\r\n VADDPS ymm1 {k1}{z}, ymm2,                                AVX512F    ymm3/m256/m32bcst to ymm2 and store result in\r\n ymm3/m256/m32bcst                                                    ymm1 with writemask k1.\r\n EVEX.NDS.512.0F.W0 58 /r               FV     V/V         AVX512F    Add packed single-precision floating-point values from\r\n VADDPS zmm1 {k1}{z}, zmm2,                                           zmm3/m512/m32bcst to zmm2 and store result in\r\n zmm3/m512/m32bcst {er}                                               zmm1 with writemask k1.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n      Op/En             Operand 1                    Operand 2                Operand 3                     Operand 4\r\n       RM            ModRM:reg (r, w)             ModRM:r/m (r)                  NA                            NA\r\n       RVM            ModRM:reg (w)                  VEX.vvvv              ModRM:r/m (r)                       NA\r\n     FV-RVM           ModRM:reg (w)                  EVEX.vvvv             ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nAdd four, eight or sixteen packed single-precision floating-point values from the first source operand with the\r\nsecond source operand, and stores the packed single-precision floating-point results in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nVADDPS (EVEX encoded versions) when src2 operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\n\r\n\r\n\r\n\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]\r\n         ELSE\r\n              IF *merging-masking*                ; merging-masking\r\n                   THEN *DEST[i+31:i] remains unchanged*\r\n                   ELSE                           ; zeroing-masking\r\n                        DEST[i+31:i] <- 0\r\n              FI\r\n    FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPS (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <-j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <- SRC1[i+31:i] + SRC2[31:0]\r\n                  ELSE\r\n                       DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                 ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                            ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVADDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] + SRC2[159:128]\r\nDEST[191:160]<- SRC1[191:160] + SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] + SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] + SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVADDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nADDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);\r\nVADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);\r\nVADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);\r\nVADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);\r\nVADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);\r\nVADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);\r\nVADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);\r\nADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);\r\nADDPS __m128 _mm_add_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDPS"
    }, 
    {
      "description": "ADDSD-Add Scalar Double-Precision Floating-Point Values\r\n Opcode/                            Op /     64/32        CPUID         Description\r\n Instruction                        En       bit Mode     Feature\r\n                                             Support      Flag\r\n F2 0F 58 /r                        RM       V/V          SSE2          Add the low double-precision floating-point value from\r\n ADDSD xmm1, xmm2/m64                                                   xmm2/mem to xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 58 /r        RVM      V/V          AVX           Add the low double-precision floating-point value from\r\n VADDSD xmm1, xmm2,                                                     xmm3/mem to xmm2 and store the result in xmm1.\r\n xmm3/m64\r\n EVEX.NDS.LIG.F2.0F.W1 58 /r        T1S      V/V          AVX512F       Add the low double-precision floating-point value from\r\n VADDSD xmm1 {k1}{z},                                                   xmm3/m64 to xmm2 and store the result in xmm1 with\r\n xmm2, xmm3/m64{er}                                                     writemask k1.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n        Op/En                    Operand 1                      Operand 2                 Operand 3                   Operand 4\r\n          RM                 ModRM:reg (r, w)               ModRM:r/m (r)                     NA                         NA\r\n         RVM                  ModRM:reg (w)                     VEX.vvvv                ModRM:r/m (r)                    NA\r\n      T1S-RVM                 ModRM:reg (w)                     EVEX.vvvv               ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nAdds the low double-precision floating-point values from the second source operand and the first source operand\r\nand stores the double-precision floating-point result in the destination operand.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nEVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low quadword element of the destination is updated according to the writemask.\r\nSoftware should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVADDSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\n\r\n\r\n\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVADDSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nADDSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] + SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);\r\nVADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);\r\nVADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);\r\nADDSD __m128d _mm_add_sd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDSD"
    }, 
    {
      "description": "ADDSS-Add Scalar Single-Precision Floating-Point Values\r\n Opcode/                             Op /    64/32        CPUID           Description\r\n Instruction                         En      bit Mode     Feature\r\n                                             Support      Flag\r\n F3 0F 58 /r                         RM      V/V          SSE             Add the low single-precision floating-point value from\r\n ADDSS xmm1, xmm2/m32                                                     xmm2/mem to xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 58 /r         RVM     V/V          AVX             Add the low single-precision floating-point value from\r\n VADDSS xmm1,xmm2,                                                        xmm3/mem to xmm2 and store the result in xmm1.\r\n xmm3/m32\r\n EVEX.NDS.LIG.F3.0F.W0 58 /r         T1S     V/V          AVX512F         Add the low single-precision floating-point value from\r\n VADDSS xmm1{k1}{z}, xmm2,                                                xmm3/m32 to xmm2 and store the result in xmm1with\r\n xmm3/m32{er}                                                             writemask k1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n       Op/En                  Operand 1                    Operand 2                      Operand 3                     Operand 4\r\n        RM                ModRM:reg (r, w)                ModRM:r/m (r)                       NA                            NA\r\n        RVM                ModRM:reg (w)                    VEX.vvvv                     ModRM:r/m (r)                      NA\r\n        T1S                ModRM:reg (w)                   EVEX.vvvv                     ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nAdds the low single-precision floating-point values from the second source operand and the first source operand,\r\nand stores the double-precision floating-point result in the destination operand.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:32) of the\r\ncorresponding the destination register remain unchanged.\r\nEVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low doubleword element of the destination is updated according to the writemask.\r\nSoftware should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\nOperation\r\nVADDSS (EVEX encoded versions)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\n\r\n\r\n\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] + SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nADDSS DEST, SRC (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] + SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);\r\nVADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);\r\nVADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);\r\nADDSS __m128 _mm_add_ss (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDSS"
    }, 
    {
      "description": "ADDSUBPD-Packed Double-FP Add/Subtract\r\nOpcode/                                         Op/       64/32-bit CPUID        Description\r\nInstruction                                     En        Mode      Feature\r\n                                                                    Flag\r\n66 0F D0 /r                                     RM        V/V       SSE3         Add/subtract double-precision floating-point\r\nADDSUBPD xmm1, xmm2/m128                                                         values from xmm2/m128 to xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG D0 /r                     RVM V/V             AVX          Add/subtract packed double-precision\r\nVADDSUBPD xmm1, xmm2, xmm3/m128                                                  floating-point values from xmm3/mem to\r\n                                                                                 xmm2 and stores result in xmm1.\r\nVEX.NDS.256.66.0F.WIG D0 /r                     RVM V/V             AVX          Add / subtract packed double-precision\r\nVADDSUBPD ymm1, ymm2, ymm3/m256                                                  floating-point values from ymm3/mem to\r\n                                                                                 ymm2 and stores result in ymm1.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n  Op/En             Operand 1               Operand 2                      Operand 3                      Operand 4\r\n    RM           ModRM:reg (r, w)         ModRM:r/m (r)                        NA                             NA\r\n   RVM            ModRM:reg (w)            VEX.vvvv (r)                   ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nAdds odd-numbered double-precision floating-point values of the first source operand (second operand) with the\r\ncorresponding double-precision floating-point values from the second source operand (third operand); stores the\r\nresult in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered\r\ndouble-precision floating-point values from the second source operand from the corresponding double-precision\r\nfloating values in the first source operand; stores the result into the even-numbered values of the destination\r\noperand.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified. See Figure 3-3.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\n                                             ADDSUBPD xmm1, xmm2/m128\r\n\r\n\r\n                                     [127:64]                           [63:0]              xmm2/m128\r\n\r\n\r\n\r\n\r\n                                                                                            RESULT:\r\n                         xmm1[127:64] + xmm2/m128[127:64]   xmm1[63:0] - xmm2/m128[63:0]\r\n                                                                                            xmm1\r\n\r\n                                     [127:64]                           [63:0]\r\n\r\n\r\n\r\n                              Figure 3-3. ADDSUBPD-Packed Double-FP Add/Subtract\r\n\r\n\r\nOperation\r\nADDSUBPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] - SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] + SRC[127:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVADDSUBPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVADDSUBPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] - SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] + SRC2[255:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADDSUBPD:      __m128d _mm_addsub_pd(__m128d a, __m128d b)\r\n\r\nVADDSUBPD:     __m256d _mm256_addsub_pd (__m256d a, __m256d b)\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection\r\nexception (#GP) will be generated.\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDSUBPD"
    }, 
    {
      "description": "ADDSUBPS-Packed Single-FP Add/Subtract\r\n Opcode/                                        Op/   64/32-bit CPUID        Description\r\n Instruction                                    En    Mode      Feature\r\n                                                                Flag\r\n F2 0F D0 /r                                    RM    V/V       SSE3         Add/subtract single-precision floating-point\r\n ADDSUBPS xmm1, xmm2/m128                                                    values from xmm2/m128 to xmm1.\r\n\r\n VEX.NDS.128.F2.0F.WIG D0 /r                    RVM V/V         AVX          Add/subtract single-precision floating-point\r\n VADDSUBPS xmm1, xmm2, xmm3/m128                                             values from xmm3/mem to xmm2 and stores\r\n                                                                             result in xmm1.\r\n VEX.NDS.256.F2.0F.WIG D0 /r                    RVM V/V         AVX          Add / subtract single-precision floating-point\r\n VADDSUBPS ymm1, ymm2, ymm3/m256                                             values from ymm3/mem to ymm2 and stores\r\n                                                                             result in ymm1.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n  Op/En              Operand 1               Operand 2                  Operand 3                      Operand 4\r\n    RM            ModRM:reg (r, w)         ModRM:r/m (r)                    NA                             NA\r\n   RVM             ModRM:reg (w)            VEX.vvvv (r)               ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nAdds odd-numbered single-precision floating-point values of the first source operand (second operand) with the\r\ncorresponding single-precision floating-point values from the second source operand (third operand); stores the\r\nresult in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered\r\nsingle-precision floating-point values from the second source operand from the corresponding single-precision\r\nfloating values in the first source operand; stores the result into the even-numbered values of the destination\r\noperand.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified. See Figure 3-4.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\n                                           ADDSUBPS xmm1, xmm2/m128\r\n\r\n                                                                                                    xmm2/\r\n                        [127:96]             [95:64]              [63:32]            [31:0]\r\n                                                                                                    m128\r\n\r\n\r\n\r\n\r\n                      xmm1[127:96] +    xmm1[95:64] - xmm2/     xmm1[63:32] +      xmm1[31:0] -     RESULT:\r\n                    xmm2/m128[127:96]      m128[95:64]        xmm2/m128[63:32]   xmm2/m128[31:0]    xmm1\r\n\r\n                        [127:96]             [95:64]              [63:32]            [31:0]\r\n\r\n\r\n                                                                                                        OM15992\r\n\r\n\r\n\r\n                               Figure 3-4. ADDSUBPS-Packed Single-FP Add/Subtract\r\n\r\n\r\nOperation\r\nADDSUBPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- DEST[31:0] - SRC[31:0]\r\nDEST[63:32] <- DEST[63:32] + SRC[63:32]\r\nDEST[95:64] <- DEST[95:64] - SRC[95:64]\r\nDEST[127:96] <- DEST[127:96] + SRC[127:96]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVADDSUBPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVADDSUBPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC2[159:128]\r\nDEST[191:160]<- SRC1[191:160] + SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] - SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] + SRC2[255:224].\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADDSUBPS:      __m128 _mm_addsub_ps(__m128 a, __m128 b)\r\n\r\nVADDSUBPS:     __m256 _mm256_addsub_ps (__m256 a, __m256 b)\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADDSUBPS"
    }, 
    {
      "description": "ADOX - Unsigned Integer Addition of Two Operands with Overflow Flag\r\n Opcode/                           Op/     64/32bit    CPUID       Description\r\n Instruction                       En      Mode        Feature\r\n                                           Support     Flag\r\n F3 0F 38 F6 /r                    RM      V/V         ADX         Unsigned addition of r32 with OF, r/m32 to r32, writes OF.\r\n ADOX r32, r/m32\r\n F3 REX.w 0F 38 F6 /r              RM      V/NE        ADX         Unsigned addition of r64 with OF, r/m64 to r64, writes OF.\r\n ADOX r64, r/m64\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n       Op/En               Operand 1                   Operand 2                     Operand 3                     Operand 4\r\n        RM              ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA\r\n\r\nDescription\r\nPerforms an unsigned addition of the destination operand (first operand), the source operand (second operand)\r\nand the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-\r\npurpose register, whereas the source operand can be a general-purpose register or memory location. The state of\r\nOF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the\r\nunsigned addition of the operands.\r\nThe ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with\r\na carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).\r\nThis instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit\r\nmode.\r\nIn 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-\r\ntional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.\r\nADOX executes normally either inside or outside a transaction region.\r\nNote: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 2A.\r\n\r\nOperation\r\nIF OperandSize is 64-bit\r\n    THEN OF:DEST[63:0] <- DEST[63:0] + SRC[63:0] + OF;\r\n    ELSE OF:DEST[31:0] <- DEST[31:0] + SRC[31:0] + OF;\r\nFI;\r\n\r\nFlags Affected\r\nOF is updated based on result. CF, SF, ZF, AF and PF flags are unmodified.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);\r\nunsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n                         If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#GP(0)                   For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n                         If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n                         selector.\r\n#PF(fault-code)          For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n                         If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#GP(0)                   If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n                         If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#GP(0)                   If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#PF(fault-code)          For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n                         If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                   If the memory address is in a non-canonical form.\r\n#PF(fault-code)          For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ADOX"
    }, 
    {
      "description": "AESDEC-Perform One Round of an AES Decryption Flow\r\nOpcode/                                         Op/      64/32-bit CPUID        Description\r\nInstruction                                     En       Mode      Feature\r\n                                                                   Flag\r\n66 0F 38 DE /r                                  RM       V/V       AES          Perform one round of an AES decryption flow,\r\nAESDEC xmm1, xmm2/m128                                                          using the Equivalent Inverse Cipher, operating\r\n                                                                                on a 128-bit data (state) from xmm1 with a\r\n                                                                                128-bit round key from xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DE /r                   RVM V/V            Both AES     Perform one round of an AES decryption flow,\r\nVAESDEC xmm1, xmm2, xmm3/m128                                      and          using the Equivalent Inverse Cipher, operating\r\n                                                                   AVX flags    on a 128-bit data (state) from xmm2 with a\r\n                                                                                128-bit round key from xmm3/m128; store\r\n                                                                                the result in xmm1.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n  Op/En           Operand 1               Operand2                        Operand3                       Operand4\r\n    RM         ModRM:reg (r, w)          ModRM:r/m (r)                        NA                             NA\r\n   RVM         ModRM:reg (w)             VEX.vvvv (r)                    ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nThis instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the\r\nround key from the second source operand, operating on a 128-bit data (state) from the first source operand, and\r\nstore the result in the destination operand.\r\nUse the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDE-\r\nCLAST instruction.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESDEC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nSTATE <- InvMixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESDEC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nSTATE <- InvMixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESDEC:      __m128i _mm_aesdec (__m128i, __m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESDEC"
    }, 
    {
      "description": "AESDECLAST-Perform Last Round of an AES Decryption Flow\r\nOpcode/                                          Op/     64/32-bit CPUID         Description\r\nInstruction                                      En      Mode      Feature\r\n                                                                   Flag\r\n66 0F 38 DF /r                                   RM      V/V       AES           Perform the last round of an AES decryption\r\nAESDECLAST xmm1, xmm2/m128                                                       flow, using the Equivalent Inverse Cipher,\r\n                                                                                 operating on a 128-bit data (state) from\r\n                                                                                 xmm1 with a 128-bit round key from\r\n                                                                                 xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DF /r                    RVM V/V           Both AES      Perform the last round of an AES decryption\r\nVAESDECLAST xmm1, xmm2, xmm3/m128                                  and           flow, using the Equivalent Inverse Cipher,\r\n                                                                   AVX flags     operating on a 128-bit data (state) from\r\n                                                                                 xmm2 with a 128-bit round key from\r\n                                                                                 xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En             Operand 1                 Operand2                     Operand3                       Operand4\r\n    RM           ModRM:reg (r, w)           ModRM:r/m (r)                      NA                             NA\r\n   RVM           ModRM:reg (w)              VEX.vvvv (r)                 ModRM:r/m (r)                        NA\r\n\r\nDescription\r\nThis instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the\r\nround key from the second source operand, operating on a 128-bit data (state) from the first source operand, and\r\nstore the result in the destination operand.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESDECLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESDECLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESDECLAST:     __m128i _mm_aesdeclast (__m128i, __m128i)\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESDECLAST"
    }, 
    {
      "description": "AESENC-Perform One Round of an AES Encryption Flow\r\nOpcode/                                         Op/    64/32-bit CPUID        Description\r\nInstruction                                     En     Mode      Feature\r\n                                                                 Flag\r\n66 0F 38 DC /r                                  RM     V/V       AES          Perform one round of an AES encryption flow,\r\nAESENC xmm1, xmm2/m128                                                        operating on a 128-bit data (state) from\r\n                                                                              xmm1 with a 128-bit round key from\r\n                                                                              xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DC /r                   RVM V/V          Both AES     Perform one round of an AES encryption flow,\r\nVAESENC xmm1, xmm2, xmm3/m128                                    and          operating on a 128-bit data (state) from\r\n                                                                 AVX flags    xmm2 with a 128-bit round key from the\r\n                                                                              xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n  Op/En           Operand 1                 Operand2                    Operand3                        Operand4\r\n    RM         ModRM:reg (r, w)            ModRM:r/m (r)                     NA                            NA\r\n   RVM          ModRM:reg (w)              VEX.vvvv (r)                ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nThis instruction performs a single round of an AES encryption flow using a round key from the second source\r\noperand, operating on 128-bit data (state) from the first source operand, and store the result in the destination\r\noperand.\r\nUse the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENC-\r\nCLAST instruction.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESENC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nSTATE <- MixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESENC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nSTATE <- MixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESENC:      __m128i _mm_aesenc (__m128i, __m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESENC"
    }, 
    {
      "description": "AESENCLAST-Perform Last Round of an AES Encryption Flow\r\nOpcode/                                           Op/     64/32-bit CPUID        Description\r\nInstruction                                       En      Mode      Feature\r\n                                                                    Flag\r\n66 0F 38 DD /r                                    RM      V/V       AES          Perform the last round of an AES encryption\r\nAESENCLAST xmm1, xmm2/m128                                                       flow, operating on a 128-bit data (state) from\r\n                                                                                 xmm1 with a 128-bit round key from\r\n                                                                                 xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DD /r                     RVM V/V           Both AES     Perform the last round of an AES encryption\r\nVAESENCLAST xmm1, xmm2, xmm3/m128                                   and          flow, operating on a 128-bit data (state) from\r\n                                                                    AVX flags    xmm2 with a 128 bit round key from\r\n                                                                                 xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En             Operand 1                  Operand2                       Operand3                     Operand4\r\n    RM           ModRM:reg (r, w)            ModRM:r/m (r)                      NA                             NA\r\n   RVM           ModRM:reg (w)               VEX.vvvv (r)                 ModRM:r/m (r)                        NA\r\n\r\nDescription\r\nThis instruction performs the last round of an AES encryption flow using a round key from the second source\r\noperand, operating on 128-bit data (state) from the first source operand, and store the result in the destination\r\noperand.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESENCLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESENCLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESENCLAST:     __m128i _mm_aesenclast (__m128i, __m128i)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESENCLAST"
    }, 
    {
      "description": "AESIMC-Perform the AES InvMixColumn Transformation\r\nOpcode/                                            Op/   64/32-bit CPUID        Description\r\nInstruction                                        En    Mode      Feature\r\n                                                                   Flag\r\n66 0F 38 DB /r                                     RM    V/V       AES          Perform the InvMixColumn transformation on\r\nAESIMC xmm1, xmm2/m128                                                          a 128-bit round key from xmm2/m128 and\r\n                                                                                store the result in xmm1.\r\nVEX.128.66.0F38.WIG DB /r                          RM    V/V       Both AES     Perform the InvMixColumn transformation on\r\nVAESIMC xmm1, xmm2/m128                                            and          a 128-bit round key from xmm2/m128 and\r\n                                                                   AVX flags    store the result in xmm1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En             Operand 1                   Operand2                     Operand3                     Operand4\r\n    RM            ModRM:reg (w)               ModRM:r/m (r)                     NA                            NA\r\n\r\nDescription\r\nPerform the InvMixColumns transformation on the source operand and store the result in the destination operand.\r\nThe destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-\r\ntion.\r\nNote: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round\r\nkey) in order to prepare them for decryption using the \"Equivalent Inverse Cipher\" (defined in FIPS 197).\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nAESIMC\r\nDEST[127:0] <- InvMixColumns( SRC );\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESIMC\r\nDEST[127:0] <- InvMixColumns( SRC );\r\nDEST[VLMAX-1:128] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESIMC:     __m128i _mm_aesimc (__m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                   If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESIMC"
    }, 
    {
      "description": "AESKEYGENASSIST-AES Round Key Generation Assist\r\n Opcode/                                               Op/     64/32-bit CPUID        Description\r\n Instruction                                           En      Mode      Feature\r\n                                                                         Flag\r\n 66 0F 3A DF /r ib                                     RMI     V/V       AES          Assist in AES round key generation using an 8\r\n AESKEYGENASSIST xmm1, xmm2/m128, imm8                                                bits Round Constant (RCON) specified in the\r\n                                                                                      immediate byte, operating on 128 bits of data\r\n                                                                                      specified in xmm2/m128 and stores the\r\n                                                                                      result in xmm1.\r\n VEX.128.66.0F3A.WIG DF /r ib                          RMI     V/V       Both AES     Assist in AES round key generation using 8\r\n VAESKEYGENASSIST xmm1, xmm2/m128, imm8                                  and          bits Round Constant (RCON) specified in the\r\n                                                                         AVX flags    immediate byte, operating on 128 bits of data\r\n                                                                                      specified in xmm2/m128 and stores the\r\n                                                                                      result in xmm1.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En            Operand 1                       Operand2                    Operand3                        Operand4\r\n    RMI           ModRM:reg (w)                   ModRM:r/m (r)                      imm8                          NA\r\n\r\nDescription\r\nAssist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using\r\n128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the\r\nresult in the destination operand.\r\nThe destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-\r\ntion.\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nAESKEYGENASSIST\r\nX3[31:0] <- SRC [127: 96];\r\nX2[31:0] <- SRC [95: 64];\r\nX1[31:0] <- SRC [63: 32];\r\nX0[31:0] <- SRC [31: 0];\r\nRCON[31:0] <- ZeroExtend(Imm8[7:0]);\r\nDEST[31:0] <- SubWord(X1);\r\nDEST[63:32 ] <- RotWord( SubWord(X1) ) XOR RCON;\r\nDEST[95:64] <- SubWord(X3);\r\nDEST[127:96] <- RotWord( SubWord(X3) ) XOR RCON;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVAESKEYGENASSIST\r\nX3[31:0] <- SRC [127: 96];\r\nX2[31:0] <- SRC [95: 64];\r\nX1[31:0] <- SRC [63: 32];\r\nX0[31:0] <- SRC [31: 0];\r\nRCON[31:0] <- ZeroExtend(Imm8[7:0]);\r\nDEST[31:0] <- SubWord(X1);\r\nDEST[63:32 ] <- RotWord( SubWord(X1) ) XOR RCON;\r\nDEST[95:64] <- SubWord(X3);\r\nDEST[127:96] <- RotWord( SubWord(X3) ) XOR RCON;\r\nDEST[VLMAX-1:128] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESKEYGENASSIST:    __m128i _mm_aeskeygenassist (__m128i, const int)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                   If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AESKEYGENASSIST"
    }, 
    {
      "description": "AND-Logical AND\r\n Opcode                    Instruction                  Op/    64-bit       Compat/ Description\r\n                                                        En     Mode         Leg Mode\r\n 24 ib                     AND AL, imm8                 I      Valid        Valid        AL AND imm8.\r\n 25 iw                     AND AX, imm16                I      Valid        Valid        AX AND imm16.\r\n 25 id                     AND EAX, imm32               I      Valid        Valid        EAX AND imm32.\r\n REX.W + 25 id             AND RAX, imm32               I      Valid        N.E.         RAX AND imm32 sign-extended to 64-bits.\r\n 80 /4 ib                  AND r/m8, imm8               MI     Valid        Valid        r/m8 AND imm8.\r\n REX + 80 /4 ib            AND r/m8*, imm8              MI     Valid        N.E.         r/m8 AND imm8.\r\n 81 /4 iw                  AND r/m16, imm16             MI     Valid        Valid        r/m16 AND imm16.\r\n 81 /4 id                  AND r/m32, imm32             MI     Valid        Valid        r/m32 AND imm32.\r\n REX.W + 81 /4 id          AND r/m64, imm32             MI     Valid        N.E.         r/m64 AND imm32 sign extended to 64-bits.\r\n 83 /4 ib                  AND r/m16, imm8              MI     Valid        Valid        r/m16 AND imm8 (sign-extended).\r\n 83 /4 ib                  AND r/m32, imm8              MI     Valid        Valid        r/m32 AND imm8 (sign-extended).\r\n REX.W + 83 /4 ib          AND r/m64, imm8              MI     Valid        N.E.         r/m64 AND imm8 (sign-extended).\r\n 20 /r                     AND r/m8, r8                 MR     Valid        Valid        r/m8 AND r8.\r\n REX + 20 /r               AND r/m8*, r8*               MR     Valid        N.E.         r/m64 AND r8 (sign-extended).\r\n 21 /r                     AND r/m16, r16               MR     Valid        Valid        r/m16 AND r16.\r\n 21 /r                     AND r/m32, r32               MR     Valid        Valid        r/m32 AND r32.\r\n REX.W + 21 /r             AND r/m64, r64               MR     Valid        N.E.         r/m64 AND r32.\r\n 22 /r                     AND r8, r/m8                 RM     Valid        Valid        r8 AND r/m8.\r\n REX + 22 /r               AND r8*, r/m8*               RM     Valid        N.E.         r/m64 AND r8 (sign-extended).\r\n 23 /r                     AND r16, r/m16               RM     Valid        Valid        r16 AND r/m16.\r\n 23 /r                     AND r32, r/m32               RM     Valid        Valid        r32 AND r/m32.\r\n REX.W + 23 /r             AND r64, r/m64               RM     Valid        N.E.         r64 AND r/m64.\r\n NOTES:\r\n *In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n  Op/En              Operand 1                     Operand 2                        Operand 3                     Operand 4\r\n    RM            ModRM:reg (r, w)               ModRM:r/m (r)                         NA                             NA\r\n    MR            ModRM:r/m (r, w)               ModRM:reg (r)                         NA                             NA\r\n    MI            ModRM:r/m (r, w)                    imm8                             NA                             NA\r\n     I            AL/AX/EAX/RAX                       imm8                             NA                             NA\r\n\r\nDescription\r\nPerforms a bitwise AND operation on the destination (first) and source (second) operands and stores the result in\r\nthe destination operand location. The source operand can be an immediate, a register, or a memory location; the\r\ndestination operand can be a register or a memory location. (However, two memory operands cannot be used in\r\none instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1;\r\notherwise, it is set to 0.\r\nThis instruction can be used with a LOCK prefix to allow the it to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\n\r\n\r\nOperation\r\nDEST <- DEST AND SRC;\r\n\r\nFlags Affected\r\nThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If the destination operand points to a non-writable segment.\r\n                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "AND"
    }, 
    {
      "description": "ANDN - Logical AND NOT\r\n Opcode/Instruction              Op/     64/32     CPUID        Description\r\n                                 En      -bit      Feature\r\n                                         Mode      Flag\r\n VEX.NDS.LZ.0F38.W0 F2 /r        RVM     V/V       BMI1         Bitwise AND of inverted r32b with r/m32, store result in r32a.\r\n ANDN r32a, r32b, r/m32\r\n VEX.NDS.LZ. 0F38.W1 F2 /r       RVM     V/NE      BMI1         Bitwise AND of inverted r64b with r/m64, store result in r64a.\r\n ANDN r64a, r64b, r/m64\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En             Operand 1                    Operand 2                       Operand 3                      Operand 4\r\n   RVM           ModRM:reg (w)                   VEX.vvvv (r)                  ModRM:r/m (r)                        NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the\r\nsecond source operand). The result is stored in the first operand (destination operand).\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nDEST <- (NOT SRC1) bitwiseAND SRC2;\r\nSF <- DEST[OperandSize -1];\r\nZF <- (DEST = 0);\r\n\r\nFlags Affected\r\nSF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                      If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ANDN"
    }, 
    {
      "description": "ANDNPD-Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values\r\n Opcode/                           Op /    64/32        CPUID           Description\r\n Instruction                       En      bit Mode     Feature\r\n                                           Support      Flag\r\n 66 0F 55 /r                       RM      V/V          SSE2            Return the bitwise logical AND NOT of packed double-\r\n ANDNPD xmm1, xmm2/m128                                                 precision floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 55 /r           RVM     V/V          AVX             Return the bitwise logical AND NOT of packed double-\r\n VANDNPD xmm1, xmm2,                                                    precision floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F 55/r            RVM     V/V          AVX             Return the bitwise logical AND NOT of packed double-\r\n VANDNPD ymm1, ymm2,                                                    precision floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 55 /r       FV      V/V          AVX512VL        Return the bitwise logical AND NOT of packed double-\r\n VANDNPD xmm1 {k1}{z}, xmm2,                            AVX512DQ        precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst                                                      xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 55 /r       FV      V/V          AVX512VL        Return the bitwise logical AND NOT of packed double-\r\n VANDNPD ymm1 {k1}{z}, ymm2,                            AVX512DQ        precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst                                                      ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 55 /r       FV      V/V          AVX512DQ        Return the bitwise logical AND NOT of packed double-\r\n VANDNPD zmm1 {k1}{z}, zmm2,                                            precision floating-point values in zmm2 and\r\n zmm3/m512/m64bcst                                                      zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n        Op/En              Operand 1                     Operand 2                        Operand 3                Operand 4\r\n          RM            ModRM:reg (r, w)               ModRM:r/m (r)                          NA                       NA\r\n         RVM             ModRM:reg (w)                    VEX.vvvv                      ModRM:r/m (r)                  NA\r\n          FV             ModRM:reg (w)                   EVEX.vvvv                      ModRM:r/m (r)                  NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND NOT of the two, four or eight packed double-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDNPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n               IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]\r\n                    ELSE\r\n                         DEST[i+63:i] <- (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] = 0\r\n               FI;\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDNPD (VEX.256 encoded version)\r\nDEST[63:0] <- (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]\r\nDEST[191:128] <- (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]\r\nDEST[255:192] <- (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDNPD (VEX.128 encoded version)\r\nDEST[63:0] <- (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDNPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- (NOT(DEST[63:0])) BITWISE AND SRC[63:0]\r\nDEST[127:64] <- (NOT(DEST[127:64])) BITWISE AND SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);\r\nVANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);\r\nVANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);\r\nVANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);\r\nVANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);\r\nANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ANDNPD"
    }, 
    {
      "description": "ANDNPS-Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values\r\n Opcode/                              Op /    64/32         CPUID          Description\r\n Instruction                          En      bit Mode      Feature\r\n                                              Support       Flag\r\n 0F 55 /r                             RM      V/V           SSE            Return the bitwise logical AND NOT of packed single-precision\r\n ANDNPS xmm1, xmm2/m128                                                    floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 55 /r                 RVM     V/V           AVX            Return the bitwise logical AND NOT of packed single-precision\r\n VANDNPS xmm1, xmm2,                                                       floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F 55 /r                 RVM     V/V           AVX            Return the bitwise logical AND NOT of packed single-precision\r\n VANDNPS ymm1, ymm2,                                                       floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 55 /r             FV      V/V           AVX512VL       Return the bitwise logical AND of packed single-precision\r\n VANDNPS xmm1 {k1}{z},                                      AVX512DQ       floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm2, xmm3/m128/m32bcst                                                   subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 55 /r             FV      V/V           AVX512VL       Return the bitwise logical AND of packed single-precision\r\n VANDNPS ymm1 {k1}{z},                                      AVX512DQ       floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm2, ymm3/m256/m32bcst                                                   subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 55 /r             FV      V/V           AVX512DQ       Return the bitwise logical AND of packed single-precision\r\n VANDNPS zmm1 {k1}{z},                                                     floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm2, zmm3/m512/m32bcst                                                   subject to writemask k1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n          Op/En                   Operand 1                       Operand 2                     Operand 3               Operand 4\r\n            RM                 ModRM:reg (r, w)                 ModRM:r/m (r)                       NA                      NA\r\n           RVM                  ModRM:reg (w)                      VEX.vvvv                   ModRM:r/m (r)                 NA\r\n            FV                  ModRM:reg (w)                     EVEX.vvvv                   ModRM:r/m (r)                 NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND NOT of the four, eight or sixteen packed single-precision floating-point values from\r\nthe first source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDNPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n               IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- (NOT(SRC1[i+31:i])) BITWISE AND SRC2[31:0]\r\n                    ELSE\r\n                         DEST[i+31:i] <- (NOT(SRC1[i+31:i])) BITWISE AND SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] = 0\r\n               FI;\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDNPS (VEX.256 encoded version)\r\nDEST[31:0] <- (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]\r\nDEST[159:128] <- (NOT(SRC1[159:128])) BITWISE AND SRC2[159:128]\r\nDEST[191:160] <- (NOT(SRC1[191:160])) BITWISE AND SRC2[191:160]\r\nDEST[223:192] <- (NOT(SRC1[223:192])) BITWISE AND SRC2[223:192]\r\nDEST[255:224] <- (NOT(SRC1[255:224])) BITWISE AND SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDNPS (VEX.128 encoded version)\r\nDEST[31:0] <- (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDNPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- (NOT(DEST[31:0])) BITWISE AND SRC[31:0]\r\nDEST[63:32] <- (NOT(DEST[63:32])) BITWISE AND SRC[63:32]\r\nDEST[95:64] <- (NOT(DEST[95:64])) BITWISE AND SRC[95:64]\r\nDEST[127:96] <- (NOT(DEST[127:96])) BITWISE AND SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDNPS __m512 _mm512_andnot_ps (__m512 a, __m512 b);\r\nVANDNPS __m512 _mm512_mask_andnot_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVANDNPS __m512 _mm512_maskz_andnot_ps (__mmask16 k, __m512 a, __m512 b);\r\nVANDNPS __m256 _mm256_mask_andnot_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVANDNPS __m256 _mm256_maskz_andnot_ps (__mmask8 k, __m256 a, __m256 b);\r\nVANDNPS __m128 _mm_mask_andnot_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVANDNPS __m128 _mm_maskz_andnot_ps (__mmask8 k, __m128 a, __m128 b);\r\nVANDNPS __m256 _mm256_andnot_ps (__m256 a, __m256 b);\r\nANDNPS __m128 _mm_andnot_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ANDNPS"
    }, 
    {
      "description": "ANDPD-Bitwise Logical AND of Packed Double Precision Floating-Point Values\r\n Opcode/                           Op /    64/32       CPUID          Description\r\n Instruction                       En      bit Mode    Feature\r\n                                           Support     Flag\r\n 66 0F 54 /r                       RM      V/V         SSE2           Return the bitwise logical AND of packed double-\r\n ANDPD xmm1, xmm2/m128                                                precision floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 54 /r           RVM     V/V         AVX            Return the bitwise logical AND of packed double-\r\n VANDPD xmm1, xmm2,                                                   precision floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F 54 /r           RVM     V/V         AVX            Return the bitwise logical AND of packed double-\r\n VANDPD ymm1, ymm2,                                                   precision floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 54 /r       FV      V/V         AVX512VL       Return the bitwise logical AND of packed double-\r\n VANDPD xmm1 {k1}{z}, xmm2,                            AVX512DQ       precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst                                                    xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 54 /r       FV      V/V         AVX512VL       Return the bitwise logical AND of packed double-\r\n VANDPD ymm1 {k1}{z}, ymm2,                            AVX512DQ       precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst                                                    ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 54 /r       FV      V/V         AVX512DQ       Return the bitwise logical AND of packed double-\r\n VANDPD zmm1 {k1}{z}, zmm2,                                           precision floating-point values in zmm2 and\r\n zmm3/m512/m64bcst                                                    zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n         Op/En             Operand 1                   Operand 2                       Operand 3                Operand 4\r\n          RM            ModRM:reg (r, w)              ModRM:r/m (r)                        NA                       NA\r\n         RVM             ModRM:reg (w)                  VEX.vvvv                     ModRM:r/m (r)                  NA\r\n          FV             ModRM:reg (w)                 EVEX.vvvv                     ModRM:r/m (r)                  NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of the two, four or eight packed double-precision floating-point values from the first\r\nsource operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[63:0]\r\n                    ELSE\r\n                         DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[i+63:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                            ; zeroing-masking\r\n                         DEST[i+63:i] = 0\r\n               FI;\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE AND SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] BITWISE AND SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] BITWISE AND SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE AND SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] BITWISE AND SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] BITWISE AND SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);\r\nVANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVANDPD __m512d _mm512_maskz_and_pd (__mmask8 k, __m512d a, __m512d b);\r\nVANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVANDPD __m256d _mm256_maskz_and_pd (__mmask8 k, __m256d a, __m256d b);\r\nVANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);\r\nVANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);\r\nANDPD __m128d _mm_and_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ANDPD"
    }, 
    {
      "description": "ANDPS-Bitwise Logical AND of Packed Single Precision Floating-Point Values\r\n Opcode/                               Op /     64/32         CPUID           Description\r\n Instruction                           En       bit Mode      Feature\r\n                                                Support       Flag\r\n 0F 54 /r                              RM       V/V           SSE             Return the bitwise logical AND of packed single-precision\r\n ANDPS xmm1, xmm2/m128                                                        floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 54 /r                  RVM      V/V           AVX             Return the bitwise logical AND of packed single-precision\r\n VANDPS xmm1,xmm2,                                                            floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F 54 /r                  RVM      V/V           AVX             Return the bitwise logical AND of packed single-precision\r\n VANDPS ymm1, ymm2,                                                           floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 54 /r              FV       V/V           AVX512VL        Return the bitwise logical AND of packed single-precision\r\n VANDPS xmm1 {k1}{z}, xmm2,                                   AVX512DQ        floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst                                                            subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 54 /r              FV       V/V           AVX512VL        Return the bitwise logical AND of packed single-precision\r\n VANDPS ymm1 {k1}{z}, ymm2,                                   AVX512DQ        floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst                                                            subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 54 /r              FV       V/V           AVX512DQ        Return the bitwise logical AND of packed single-precision\r\n VANDPS zmm1 {k1}{z}, zmm2,                                                   floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst                                                            subject to writemask k1.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n       Op/En                  Operand 1                         Operand 2                        Operand 3                Operand 4\r\n         RM               ModRM:reg (r, w)                    ModRM:r/m (r)                          NA                       NA\r\n        RVM                ModRM:reg (w)                         VEX.vvvv                      ModRM:r/m (r)                  NA\r\n         FV                ModRM:reg (w)                        EVEX.vvvv                      ModRM:r/m (r)                  NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of the four, eight or sixteen packed single-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n               IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- SRC1[i+31:i] BITWISE AND SRC2[31:0]\r\n                    ELSE\r\n                         DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                            ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI;\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVANDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE AND SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] BITWISE AND SRC2[159:128]\r\nDEST[191:160] <- SRC1[191:160] BITWISE AND SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] BITWISE AND SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] BITWISE AND SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVANDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE AND SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nANDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- DEST[31:0] BITWISE AND SRC[31:0]\r\nDEST[63:32] <- DEST[63:32] BITWISE AND SRC[63:32]\r\nDEST[95:64] <- DEST[95:64] BITWISE AND SRC[95:64]\r\nDEST[127:96] <- DEST[127:96] BITWISE AND SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);\r\nVANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVANDPS __m512 _mm512_maskz_and_ps (__mmask16 k, __m512 a, __m512 b);\r\nVANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);\r\nVANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVANDPS __m128 _mm_maskz_and_ps (__mmask8 k, __m128 a, __m128 b);\r\nVANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);\r\nANDPS __m128 _mm_and_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ANDPS"
    }, 
    {
      "description": "ARPL-Adjust RPL Field of Segment Selector\r\nOpcode                  Instruction              Op/     64-bit   Compat/ Description\r\n                                                 En      Mode     Leg Mode\r\n63 /r                   ARPL r/m16, r16          NP      N. E.    Valid       Adjust RPL of r/m16 to not less than RPL of\r\n                                                                              r16.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En            Operand 1                 Operand 2                    Operand 3                      Operand 4\r\n    NP           ModRM:r/m (w)             ModRM:reg (r)                     NA                             NA\r\n\r\nDescription\r\nCompares the RPL fields of two segment selectors. The first operand (the destination operand) contains one\r\nsegment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0\r\nand 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand,\r\nthe ZF flag is set and the RPL field of the destination operand is increased to match that of the source operand.\r\nOtherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can\r\nbe a word register or a memory location; the source operand must be a word register.)\r\nThe ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applica-\r\ntions). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system\r\nby an application program to match the privilege level of the application program. Here the segment selector\r\npassed to the operating system is placed in the destination operand and segment selector for the application\r\nprogram's code segment is placed in the source operand. (The RPL field in the source operand represents the priv-\r\nilege level of the application program.) Execution of the ARPL instruction then ensures that the RPL of the segment\r\nselector received by the operating system is no lower (does not have a higher privilege) than the privilege level of\r\nthe application program (the segment selector for the application program's code segment can be read from the\r\nstack following a procedure call).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode.\r\nSee \"Checking Caller Access Privileges\" in Chapter 3, \"Protected-Mode Memory Management,\" of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A, for more information about the use of this instruc-\r\ntion.\r\n\r\nOperation\r\nIF 64-BIT MODE\r\n    THEN\r\n        See MOVSXD;\r\n    ELSE\r\n        IF DEST[RPL] < SRC[RPL]\r\n             THEN\r\n                 ZF <- 1;\r\n                 DEST[RPL] <- SRC[RPL];\r\n             ELSE\r\n                 ZF <- 0;\r\n        FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise,\r\nit is set to 0.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If the destination is located in a non-writable segment.\r\n                         If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                         If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                         selector.\r\n#SS(0)                   If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)          If a page fault occurs.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                      The ARPL instruction is not recognized in real-address mode.\r\n                         If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                      The ARPL instruction is not recognized in virtual-8086 mode.\r\n                         If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nNot applicable.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ARPL"
    }, 
    {
      "description": "BEXTR - Bit Field Extract\r\n Opcode/Instruction                Op/    64/32     CPUID      Description\r\n                                   En     -bit      Feature\r\n                                          Mode      Flag\r\n VEX.NDS.LZ.0F38.W0 F7 /r          RMV    V/V       BMI1       Contiguous bitwise extract from r/m32 using r32b as control; store\r\n BEXTR r32a, r/m32, r32b                                       result in r32a.\r\n VEX.NDS.LZ.0F38.W1 F7 /r          RMV    V/N.E.    BMI1       Contiguous bitwise extract from r/m64 using r64b as control; store\r\n BEXTR r64a, r/m64, r64b                                       result in r64a\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En               Operand 1                     Operand 2                      Operand 3                        Operand 4\r\n   RMV               ModRM:reg (w)                  ModRM:r/m (r)                  VEX.vvvv (r)                          NA\r\n\r\nDescription\r\nExtracts contiguous bits from the first source operand (the second operand) using an index value and length value\r\nspecified in the second source operand (the third operand). Bit 7:0 of the second source operand specifies the\r\nstarting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the\r\nsecond source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH)\r\nbeginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are\r\nextracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher\r\norder bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is\r\ncleared if no bits are extracted.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nSTART <- SRC2[7:0];\r\nLEN <- SRC2[15:8];\r\nTEMP <- ZERO_EXTEND_TO_512 (SRC1 );\r\nDEST <- ZERO_EXTEND(TEMP[START+LEN -1: START]);\r\nZF <- (DEST = 0);\r\n\r\nFlags Affected\r\nZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBEXTR:         unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);\r\n\r\nBEXTR:         unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                      If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BEXTR"
    }, 
    {
      "description": "BLENDPD - Blend Packed Double Precision Floating-Point Values\r\n Opcode/                                            Op/    64/32-bit CPUID       Description\r\n Instruction                                        En     Mode      Feature\r\n                                                                     Flag\r\n 66 0F 3A 0D /r ib                                  RMI    V/V       SSE4_1      Select packed DP-FP values from xmm1 and\r\n BLENDPD xmm1, xmm2/m128, imm8                                                   xmm2/m128 from mask specified in imm8\r\n                                                                                 and store the values into xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 0D /r ib                   RVMI V/V         AVX         Select packed double-precision floating-point\r\n VBLENDPD xmm1, xmm2, xmm3/m128, imm8                                            Values from xmm2 and xmm3/m128 from\r\n                                                                                 mask in imm8 and store the values in xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 0D /r ib                   RVMI V/V         AVX         Select packed double-precision floating-point\r\n VBLENDPD ymm1, ymm2, ymm3/m256, imm8                                            Values from ymm2 and ymm3/m256 from\r\n                                                                                 mask in imm8 and store the values in ymm1.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En               Operand 1              Operand 2                     Operand 3                       Operand 4\r\n   RMI           ModRM:reg (r, w)           ModRM:r/m (r)                     imm8                             NA\r\n   RVMI              ModRM:reg (w)          VEX.vvvv (r)                ModRM:r/m (r)                       imm8[3:0]\r\n\r\nDescription\r\nDouble-precision floating-point values from the second source operand (third operand) are conditionally merged\r\nwith values from the first source operand (second operand) and written to the destination operand (first operand).\r\nThe immediate bits [3:0] determine whether the corresponding double-precision floating-point value in the desti-\r\nnation is copied from the second source or first source. If a bit in the mask, corresponding to a word, is \"1\", then\r\nthe double-precision floating-point value in the second source operand is copied, else the value in the first source\r\noperand is copied.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of\r\nthe corresponding YMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nBLENDPD (128-bit Legacy SSE version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- DEST[63:0]\r\n        ELSE DEST [63:0] <- SRC[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- DEST[127:64]\r\n        ELSE DEST [127:64] <- SRC[127:64] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDPD (VEX.128 encoded version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]\r\n        ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n        ELSE DEST [127:64] <- SRC2[127:64] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVBLENDPD (VEX.256 encoded version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]\r\n        ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n        ELSE DEST [127:64] <- SRC2[127:64] FI\r\nIF (IMM8[2] = 0) THEN DEST[191:128] <- SRC1[191:128]\r\n        ELSE DEST [191:128] <- SRC2[191:128] FI\r\nIF (IMM8[3] = 0) THEN DEST[255:192] <- SRC1[255:192]\r\n        ELSE DEST [255:192] <- SRC2[255:192] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDPD:         __m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);\r\n\r\nVBLENDPD:        __m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLENDPD"
    }, 
    {
      "description": "BLENDPS - Blend Packed Single Precision Floating-Point Values\r\n Opcode/                                                    Op/    64/32-bit CPUID       Description\r\n Instruction                                                En     Mode      Feature\r\n                                                                             Flag\r\n 66 0F 3A 0C /r ib                                          RMI    V/V       SSE4_1      Select packed single precision floating-point\r\n BLENDPS xmm1, xmm2/m128, imm8                                                           values from xmm1 and xmm2/m128 from\r\n                                                                                         mask specified in imm8 and store the values\r\n                                                                                         into xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 0C /r ib                           RVMI V/V         AVX         Select packed single-precision floating-point\r\n VBLENDPS xmm1, xmm2, xmm3/m128, imm8                                                    values from xmm2 and xmm3/m128 from\r\n                                                                                         mask in imm8 and store the values in xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 0C /r ib                           RVMI V/V         AVX         Select packed single-precision floating-point\r\n VBLENDPS ymm1, ymm2, ymm3/m256, imm8                                                    values from ymm2 and ymm3/m256 from\r\n                                                                                         mask in imm8 and store the values in ymm1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n   Op/En               Operand 1                       Operand 2                    Operand 3                      Operand 4\r\n    RMI            ModRM:reg (r, w)                  ModRM:r/m (r)                     imm8                            NA\r\n   RVMI              ModRM:reg (w)                    VEX.vvvv (r)                 ModRM:r/m (r)                     imm8\r\n\r\nDescription\r\nPacked single-precision floating-point values from the second source operand (third operand) are conditionally\r\nmerged with values from the first source operand (second operand) and written to the destination operand (first\r\noperand). The immediate bits [7:0] determine whether the corresponding single precision floating-point value in\r\nthe destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is\r\n\"1\", then the single-precision floating-point value in the second source operand is copied, else the value in the first\r\nsource operand is copied.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: The first source operand an XMM register. The second source operand is an XMM register\r\nor 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the\r\ncorresponding YMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nBLENDPS (128-bit Legacy SSE version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-DEST[31:0]\r\n        ELSE DEST [31:0] <- SRC[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- DEST[63:32]\r\n        ELSE DEST [63:32] <- SRC[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- DEST[95:64]\r\n        ELSE DEST [95:64] <- SRC[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- DEST[127:96]\r\n        ELSE DEST [127:96] <- SRC[127:96] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVBLENDPS (VEX.128 encoded version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]\r\n        ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n        ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n        ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n        ELSE DEST [127:96] <- SRC2[127:96] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDPS (VEX.256 encoded version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]\r\n        ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n        ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n        ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n        ELSE DEST [127:96] <- SRC2[127:96] FI\r\nIF (IMM8[4] = 0) THEN DEST[159:128] <- SRC1[159:128]\r\n        ELSE DEST [159:128] <- SRC2[159:128] FI\r\nIF (IMM8[5] = 0) THEN DEST[191:160] <- SRC1[191:160]\r\n        ELSE DEST [191:160] <- SRC2[191:160] FI\r\nIF (IMM8[6] = 0) THEN DEST[223:192] <- SRC1[223:192]\r\n        ELSE DEST [223:192] <- SRC2[223:192] FI\r\nIF (IMM8[7] = 0) THEN DEST[255:224] <- SRC1[255:224]\r\n        ELSE DEST [255:224] <- SRC2[255:224] FI.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDPS:       __m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);\r\n\r\nVBLENDPS:      __m256 _mm256_blend_ps (__m256 a, __m256 b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLENDPS"
    }, 
    {
      "description": "BLENDVPD - Variable Blend Packed Double Precision Floating-Point Values\r\n Opcode/                                                   Op/       64/32-bit CPUID      Description\r\n Instruction                                               En        Mode      Feature\r\n                                                                               Flag\r\n 66 0F 38 15 /r                                            RM0       V/V       SSE4_1     Select packed DP FP values from xmm1 and\r\n BLENDVPD xmm1, xmm2/m128 , <XMM0>                                                        xmm2 from mask specified in XMM0 and\r\n                                                                                          store the values in xmm1.\r\n VEX.NDS.128.66.0F3A.W0 4B /r /is4                         RVMR V/V            AVX        Conditionally copy double-precision floating-\r\n VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4                                                    point values from xmm2 or xmm3/m128 to\r\n                                                                                          xmm1, based on mask bits in the mask\r\n                                                                                          operand, xmm4.\r\n VEX.NDS.256.66.0F3A.W0 4B /r /is4                         RVMR V/V            AVX        Conditionally copy double-precision floating-\r\n VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4                                                    point values from ymm2 or ymm3/m256 to\r\n                                                                                          ymm1, based on mask bits in the mask\r\n                                                                                          operand, ymm4.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n    Op/En             Operand 1                        Operand 2                     Operand 3                     Operand 4\r\n    RM0            ModRM:reg (r, w)                  ModRM:r/m (r)                implicit XMM0                        NA\r\n    RVMR            ModRM:reg (w)                     VEX.vvvv (r)                ModRM:r/m (r)                    imm8[7:4]\r\n\r\nDescription\r\nConditionally copy each quadword data element of double-precision floating-point value from the second source\r\noperand and the first source operand depending on mask bits defined in the mask register operand. The mask bits\r\nare the most significant bit in each quadword element of the mask register.\r\nEach quadword element of the destination operand is copied from:\r\n.    the corresponding quadword element in the second source operand, if a mask bit is \"1\"; or\r\n.    the corresponding quadword element in the first source operand, if a mask bit is \"0\"\r\nThe register assignment of the implicit mask operand for BLENDVPD is defined to be the architectural register\r\nXMM0.\r\n128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)\r\nof the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined\r\nto be the architectural register XMM0. An attempt to execute BLENDVPD with a VEX prefix will cause #UD.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.\r\nVEX.W must be 0, otherwise, the instruction will #UD.\r\nVEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source\r\noperand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. VEX.W must be 0, otherwise, the instruction will #UD.\r\nVBLENDVPD permits the mask to be any XMM or YMM register. In contrast, BLENDVPD treats XMM0 implicitly as the\r\nmask and do not support non-destructive destination operation.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBLENDVPD (128-bit Legacy SSE version)\r\nMASK <- XMM0\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- DEST[63:0]\r\n        ELSE DEST [63:0] <- SRC[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- DEST[127:64]\r\n        ELSE DEST [127:64] <- SRC[127:64] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDVPD (VEX.128 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]\r\n        ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n        ELSE DEST [127:64] <- SRC2[127:64] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDVPD (VEX.256 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]\r\n        ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n        ELSE DEST [127:64] <- SRC2[127:64] FI\r\nIF (MASK[191] = 0) THEN DEST[191:128] <- SRC1[191:128]\r\n        ELSE DEST [191:128] <- SRC2[191:128] FI\r\nIF (MASK[255] = 0) THEN DEST[255:192] <- SRC1[255:192]\r\n        ELSE DEST [255:192] <- SRC2[255:192] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDVPD:      __m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);\r\n\r\nVBLENDVPD:     __m128 _mm_blendv_pd (__m128d a, __m128d b, __m128d mask);\r\n\r\nVBLENDVPD:     __m256 _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                  If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLENDVPD"
    }, 
    {
      "description": "BLENDVPS - Variable Blend Packed Single Precision Floating-Point Values\r\n Opcode/                                                    Op/      64/32-bit CPUID      Description\r\n Instruction                                                En       Mode      Feature\r\n                                                                               Flag\r\n 66 0F 38 14 /r                                             RM0      V/V       SSE4_1     Select packed single precision floating-point\r\n BLENDVPS xmm1, xmm2/m128, <XMM0>                                                         values from xmm1 and xmm2/m128 from\r\n                                                                                          mask specified in XMM0 and store the values\r\n                                                                                          into xmm1.\r\n VEX.NDS.128.66.0F3A.W0 4A /r /is4                          RVMR V/V           AVX        Conditionally copy single-precision floating-\r\n VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4                                                    point values from xmm2 or xmm3/m128 to\r\n                                                                                          xmm1, based on mask bits in the specified\r\n                                                                                          mask operand, xmm4.\r\n VEX.NDS.256.66.0F3A.W0 4A /r /is4                          RVMR V/V           AVX        Conditionally copy single-precision floating-\r\n VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4                                                    point values from ymm2 or ymm3/m256 to\r\n                                                                                          ymm1, based on mask bits in the specified\r\n                                                                                          mask register, ymm4.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n    Op/En             Operand 1                        Operand 2                     Operand 3                      Operand 4\r\n    RM0            ModRM:reg (r, w)                  ModRM:r/m (r)                implicit XMM0                         NA\r\n    RVMR            ModRM:reg (w)                     VEX.vvvv (r)                ModRM:r/m (r)                     imm8[7:4]\r\n\r\nDescription\r\nConditionally copy each dword data element of single-precision floating-point value from the second source\r\noperand and the first source operand depending on mask bits defined in the mask register operand. The mask bits\r\nare the most significant bit in each dword element of the mask register.\r\nEach quadword element of the destination operand is copied from:\r\n.    the corresponding dword element in the second source operand, if a mask bit is \"1\"; or\r\n.    the corresponding dword element in the first source operand, if a mask bit is \"0\"\r\nThe register assignment of the implicit mask operand for BLENDVPS is defined to be the architectural register\r\nXMM0.\r\n128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)\r\nof the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined\r\nto be the architectural register XMM0. An attempt to execute BLENDVPS with a VEX prefix will cause #UD.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.\r\nVEX.W must be 0, otherwise, the instruction will #UD.\r\nVEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source\r\noperand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. VEX.W must be 0, otherwise, the instruction will #UD.\r\nVBLENDVPS permits the mask to be any XMM or YMM register. In contrast, BLENDVPS treats XMM0 implicitly as the\r\nmask and do not support non-destructive destination operation.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBLENDVPS (128-bit Legacy SSE version)\r\nMASK <- XMM0\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- DEST[31:0]\r\n        ELSE DEST [31:0] <- SRC[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- DEST[63:32]\r\n        ELSE DEST [63:32] <- SRC[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- DEST[95:64]\r\n        ELSE DEST [95:64] <- SRC[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- DEST[127:96]\r\n        ELSE DEST [127:96] <- SRC[127:96] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDVPS (VEX.128 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]\r\n        ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n        ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n        ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n        ELSE DEST [127:96] <- SRC2[127:96] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDVPS (VEX.256 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]\r\n        ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n        ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n        ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n        ELSE DEST [127:96] <- SRC2[127:96] FI\r\nIF (MASK[159] = 0) THEN DEST[159:128] <- SRC1[159:128]\r\n        ELSE DEST [159:128] <- SRC2[159:128] FI\r\nIF (MASK[191] = 0) THEN DEST[191:160] <- SRC1[191:160]\r\n        ELSE DEST [191:160] <- SRC2[191:160] FI\r\nIF (MASK[223] = 0) THEN DEST[223:192] <- SRC1[223:192]\r\n        ELSE DEST [223:192] <- SRC2[223:192] FI\r\nIF (MASK[255] = 0) THEN DEST[255:224] <- SRC1[255:224]\r\n        ELSE DEST [255:224] <- SRC2[255:224] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDVPS:      __m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);\r\n\r\nVBLENDVPS:     __m128 _mm_blendv_ps (__m128 a, __m128 b, __m128 mask);\r\n\r\nVBLENDVPS:     __m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                       If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLENDVPS"
    }, 
    {
      "description": "BLSI - Extract Lowest Set Isolated Bit\r\n Opcode/Instruction                 Op/   64/32     CPUID     Description\r\n                                    En    -bit      Feature\r\n                                          Mode      Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /3           VM    V/V       BMI1      Extract lowest set bit from r/m32 and set that bit in r32.\r\n BLSI r32, r/m32\r\n VEX.NDD.LZ.0F38.W1 F3 /3           VM    V/N.E.    BMI1      Extract lowest set bit from r/m64, and set that bit in r64.\r\n BLSI r64, r/m64\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En               Operand 1                     Operand 2                    Operand 3                       Operand 4\r\n    VM               VEX.vvvv (w)                  ModRM:r/m (r)                      NA                              NA\r\n\r\nDescription\r\nExtracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All\r\nother bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in\r\nthe destination to 0 and sets ZF and CF.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (-SRC) bitwiseAND (SRC);\r\nSF <- temp[OperandSize -1];\r\nZF <- (temp = 0);\r\nIF SRC = 0\r\n    CF <- 0;\r\nELSE\r\n    CF <- 1;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF\r\nflags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSI:          unsigned __int32 _blsi_u32(unsigned __int32 src);\r\n\r\nBLSI:          unsigned __int64 _blsi_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                      If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLSI"
    }, 
    {
      "description": "BLSMSK - Get Mask Up to Lowest Set Bit\r\n Opcode/Instruction                 Op/   64/32     CPUID       Description\r\n                                    En    -bit      Feature\r\n                                          Mode      Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /2           VM    V/V       BMI1        Set all lower bits in r32 to \"1\" starting from bit 0 to lowest set bit in\r\n BLSMSK r32, r/m32                                              r/m32.\r\n VEX.NDD.LZ.0F38.W1 F3 /2           VM    V/N.E.    BMI1        Set all lower bits in r64 to \"1\" starting from bit 0 to lowest set bit in\r\n BLSMSK r64, r/m64                                              r/m64.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En              Operand 1                     Operand 2                        Operand 3                        Operand 4\r\n    VM               VEX.vvvv (w)                  ModRM:r/m (r)                         NA                               NA\r\n\r\nDescription\r\nSets all the lower bits of the destination operand to \"1\" up to and including lowest set bit (=1) in the source\r\noperand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (SRC-1) XOR (SRC) ;\r\nSF <- temp[OperandSize -1];\r\nZF <- 0;\r\nIF SRC = 0\r\n    CF <- 1;\r\nELSE\r\n    CF <- 0;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nSF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are\r\nundefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSMSK:       unsigned __int32 _blsmsk_u32(unsigned __int32 src);\r\n\r\nBLSMSK:       unsigned __int64 _blsmsk_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                     If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLSMSK"
    }, 
    {
      "description": "BLSR - Reset Lowest Set Bit\r\n Opcode/Instruction               Op/   64/32     CPUID        Description\r\n                                  En    -bit      Feature\r\n                                        Mode      Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /1         VM    V/V       BMI1         Reset lowest set bit of r/m32, keep all other bits of r/m32 and write\r\n BLSR r32, r/m32                                               result to r32.\r\n VEX.NDD.LZ.0F38.W1 F3 /1         VM    V/N.E.    BMI1         Reset lowest set bit of r/m64, keep all other bits of r/m64 and write\r\n BLSR r64, r/m64                                               result to r64.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En              Operand 1                    Operand 2                       Operand 3                      Operand 4\r\n    VM              VEX.vvvv (w)                 ModRM:r/m (r)                        NA                              NA\r\n\r\nDescription\r\nCopies all bits from the source operand to the destination operand and resets (=0) the bit position in the destina-\r\ntion operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets\r\nCF.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (SRC-1) bitwiseAND ( SRC );\r\nSF <- temp[OperandSize -1];\r\nZF <- (temp = 0);\r\nIF SRC = 0\r\n    CF <- 1;\r\nELSE\r\n    CF <- 0;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags\r\nare undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSR:          unsigned __int32 _blsr_u32(unsigned __int32 src);\r\n\r\nBLSR:          unsigned __int64 _blsr_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                     If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BLSR"
    }, 
    {
      "description": "BNDCL-Check Lower Bound\r\n Opcode/                       Op/En      64/32       CPUID     Description\r\n Instruction                              bit Mode    Feature\r\n                                          Support     Flag\r\n F3 0F 1A /r                   RM         NE/V        MPX       Generate a #BR if the address in r/m32 is lower than the lower\r\n BNDCL bnd, r/m32                                               bound in bnd.LB.\r\n F3 0F 1A /r                   RM         V/NE        MPX       Generate a #BR if the address in r/m64 is lower than the lower\r\n BNDCL bnd, r/m64                                               bound in bnd.LB.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En                Operand 1                             Operand 2                               Operand 3\r\n       RM                 ModRM:reg (w)                         ModRM:r/m (r)                               NA\r\n\r\nDescription\r\nCompare the address in the second operand with the lower bound in bnd. The second operand can be either a\r\nregister or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H\r\nand signal a #BR exception.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\n\r\nOperation\r\nBNDCL BND, reg\r\nIF reg < BND.LB Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\nBNDCL BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP < BND.LB Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDCL void _bnd_chk_ptr_lbounds(const void *q)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR                   If lower bound check fails.\r\n#UD                   If the LOCK prefix is used.\r\n                      If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                      If 67H prefix is not used and CS.D=0.\r\n                      If 67H prefix is used and CS.D=1.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#BR                 If lower bound check fails.\r\n#UD                 If the LOCK prefix is used.\r\n                    If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                    If 16-bit addressing is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR                 If lower bound check fails.\r\n#UD                 If the LOCK prefix is used.\r\n                    If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                    If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDCL"
    }, 
    {
      "description": "-R:BNDCU", 
      "mnem": "BNDCN"
    }, 
    {
      "description": "BNDCU/BNDCN-Check Upper Bound\r\n Opcode/                        Op/En       64/32       CPUID     Description\r\n Instruction                                bit Mode    Feature\r\n                                            Support     Flag\r\n F2 0F 1A /r                    RM          NE/V        MPX       Generate a #BR if the address in r/m32 is higher than the upper\r\n BNDCU bnd, r/m32                                                 bound in bnd.UB (bnb.UB in 1's complement form).\r\n F2 0F 1A /r                    RM          V/NE        MPX       Generate a #BR if the address in r/m64 is higher than the upper\r\n BNDCU bnd, r/m64                                                 bound in bnd.UB (bnb.UB in 1's complement form).\r\n F2 0F 1B /r                    RM          NE/V        MPX       Generate a #BR if the address in r/m32 is higher than the upper\r\n BNDCN bnd, r/m32                                                 bound in bnd.UB (bnb.UB not in 1's complement form).\r\n F2 0F 1B /r                    RM          V/NE        MPX       Generate a #BR if the address in r/m64 is higher than the upper\r\n BNDCN bnd, r/m64                                                 bound in bnd.UB (bnb.UB not in 1's complement form).\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n    Op/En                    Operand 1                             Operand 2                              Operand 3\r\n      RM                    ModRM:reg (w)                         ModRM:r/m (r)                               NA\r\n\r\nDescription\r\nCompare the address in the second operand with the upper bound in bnd. The second operand can be either a\r\nregister or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to\r\n01H and signal a #BR exception.\r\nBNDCU perform 1's complement operation on the upper bound of bnd first before proceeding with address compar-\r\nison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1's\r\ncomplement form.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\nEffective address computation of m32/64 has identical behavior to LEA\r\n\r\nOperation\r\nBNDCU BND, reg\r\nIF reg > NOT(BND.UB) Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\nBNDCU BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP > NOT(BND.UB) Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\nBNDCN BND, reg\r\nIF reg > BND.UB Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nBNDCN BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP > BND.UB Then\r\n    BNDSTATUS <- 01H;\r\n    #BR;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDCU .void _bnd_chk_ptr_ubounds(const void *q)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR                  If upper bound check fails.\r\n#UD                  If the LOCK prefix is used.\r\n                     If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                     If 67H prefix is not used and CS.D=0.\r\n                     If 67H prefix is used and CS.D=1.\r\n\r\nReal-Address Mode Exceptions\r\n#BR                  If upper bound check fails.\r\n#UD                  If the LOCK prefix is used.\r\n                     If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                     If 16-bit addressing is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR                  If upper bound check fails.\r\n#UD                  If the LOCK prefix is used.\r\n                     If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                     If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                  If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDCU"
    }, 
    {
      "description": "BNDLDX-Load Extended Bounds Using Address Translation\r\n Opcode/                          Op/En     64/32       CPUID     Description\r\n Instruction                                bit Mode    Feature\r\n                                            Support     Flag\r\n 0F 1A /r                         RM        V/V         MPX       Load the bounds stored in a bound table entry (BTE) into bnd with\r\n BNDLDX bnd, mib                                                  address translation using the base of mib and conditional on the\r\n                                                                  index of mib matching the pointer value in the BTE.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n     Op/En                    Operand 1                            Operand 2                               Operand 3\r\n                                                         SIB.base (r): Address of pointer\r\n      RM                    ModRM:reg (w)                                                                     NA\r\n                                                                   SIB.index(r)\r\n\r\nDescription\r\nBNDLDX uses the linear address constructed from the base register and displacement of the SIB-addressing form\r\nof the memory operand (mib) to perform address translation to access a bound table entry and conditionally load\r\nthe bounds in the BTE to the destination. The destination register is updated with the bounds in the BTE, if the\r\ncontent of the index register of mib matches the pointer value stored in the BTE.\r\nIf the pointer value comparison fails, the destination is updated with INIT bounds (lb = 0x0, ub = 0x0) (note: as\r\narticulated earlier, the upper bound is represented using 1's complement, therefore, the 0x0 value of upper bound\r\nallows for access to full memory).\r\nThis instruction does not cause memory access to the linear address of mib nor the effective address referenced by\r\nthe base, and does not read or write any flags.\r\nSegment overrides apply to the linear address computation with the base of mib, and are used during address\r\ntranslation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be\r\nlinear address. There are no segmentation checks performed on the base of mib.\r\nThe base of mib will not be checked for canonical address violation as it does not access memory.\r\nAny encoding of this instruction that does not specify base or index register will treat those registers as zero\r\n(constant). The reg-reg form of this instruction will remain a NOP.\r\nThe scale field of the SIB byte has no effect on these instructions and is ignored.\r\nThe bound register may be partially updated on memory faults. The order in which memory operands are loaded is\r\nimplementation specific.\r\n\r\nOperation\r\nbase <- mib.SIB.base ? mib.SIB.base + Disp: 0;\r\nptr_value <- mib.SIB.index ? mib.SIB.index : 0;\r\n\r\nOutside 64-bit mode\r\nA_BDE[31:0] <- (Zero_extend32(base[31:12] << 2) + (BNDCFG[31:12] <<12 );\r\nA_BT[31:0] <- LoadFrom(A_BDE );\r\nIF A_BT[0] equal 0 Then\r\n    BNDSTATUS <- A_BDE | 02H;\r\n    #BR;\r\nFI;\r\nA_BTE[31:0] <- (Zero_extend32(base[11:2] << 4) + (A_BT[31:2] << 2 );\r\nTemp_lb[31:0] <- LoadFrom(A_BTE);\r\nTemp_ub[31:0] <- LoadFrom(A_BTE + 4);\r\nTemp_ptr[31:0] <- LoadFrom(A_BTE + 8);\r\nIF Temp_ptr equal ptr_value Then\r\n    BND.LB <- Temp_lb;\r\n    BND.UB <- Temp_ub;\r\n\r\n\r\n\r\nELSE\r\n    BND.LB <- 0;\r\n    BND.UB <- 0;\r\nFI;\r\n\r\nIn 64-bit mode\r\nA_BDE[63:0] <- (Zero_extend64(base[47+MAWA:20] << 3) + (BNDCFG[63:20] <<12 );1\r\nA_BT[63:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n    BNDSTATUS <- A_BDE | 02H;\r\n    #BR;\r\nFI;\r\nA_BTE[63:0] <- (Zero_extend64(base[19:3] << 5) + (A_BT[63:3] << 3 );\r\nTemp_lb[63:0] <- LoadFrom(A_BTE);\r\nTemp_ub[63:0] <- LoadFrom(A_BTE + 8);\r\nTemp_ptr[63:0] <- LoadFrom(A_BTE + 16);\r\nIF Temp_ptr equal ptr_value Then\r\n    BND.LB <- Temp_lb;\r\n    BND.UB <- Temp_ub;\r\nELSE\r\n    BND.LB <- 0;\r\n    BND.UB <- 0;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDLDX: Generated by compiler as needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR                    If the bound directory entry is invalid.\r\n#UD                    If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 67H prefix is not used and CS.D=0.\r\n                       If 67H prefix is used and CS.D=1.\r\n#GP(0)                 If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n                       If DS register contains a NULL segment selector.\r\n#PF(fault code)        If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                    If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 16-bit addressing is used.\r\n#GP(0)                 If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n\r\n\r\n\r\n\r\n1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumer-\r\n   ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel 64 and IA-32 Architectures Software Devel-\r\n   oper's Manual, Volume 1.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n                        If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                        If 16-bit addressing is used.\r\n#GP(0)                  If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n#PF(fault code)         If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#BR                     If the bound directory entry is invalid.\r\n#UD                     If ModRM is RIP relative.\r\n                        If the LOCK prefix is used.\r\n                        If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#GP(0)                  If the memory address (A_BDE or A_BTE) is in a non-canonical form.\r\n#PF(fault code)         If a page fault occurs.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDLDX"
    }, 
    {
      "description": "BNDMK-Make Bounds\r\n Opcode/                        Op/En     64/32       CPUID      Description\r\n Instruction                              bit Mode    Feature\r\n                                          Support     Flag\r\n F3 0F 1B /r                    RM        NE/V        MPX        Make lower and upper bounds from m32 and store them in bnd.\r\n BNDMK bnd, m32\r\n F3 0F 1B /r                    RM        V/NE        MPX        Make lower and upper bounds from m64 and store them in bnd.\r\n BNDMK bnd, m64\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n    Op/En                   Operand 1                            Operand 2                             Operand 3\r\n       RM                ModRM:reg (w)                          ModRM:r/m (r)                             NA\r\n\r\nDescription\r\nMakes bounds from the second operand and stores the lower and upper bounds in the bound register bnd. The\r\nsecond operand must be a memory operand. The content of the base register from the memory operand is stored\r\nin the lower bound bnd.LB. The 1's complement of the effective address of m32/m64 is stored in the upper bound\r\nb.UB. Computation of m32/m64 has identical behavior to LEA.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\nIf the instruction did not specify base register, the lower bound will be zero. The reg-reg form of this instruction\r\nretains legacy behavior (NOP).\r\nRIP relative instruction in 64-bit will #UD.\r\n\r\nOperation\r\nBND.LB <- SRCMEM.base;\r\nIF 64-bit mode Then\r\n    BND.UB <- NOT(LEA.64_bits(SRCMEM));\r\nELSE\r\n    BND.UB <- Zero_Extend.64_bits(NOT(LEA.32_bits(SRCMEM)));\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDMKvoid * _bnd_set_ptr_bounds(const void * q, size_t size);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                    If ModRM is RIP relative.\r\n                       If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 67H prefix is not used and CS.D=0.\r\n                       If 67H prefix is used and CS.D=1.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                    If ModRM is RIP relative.\r\n                       If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 16-bit addressing is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 If ModRM is RIP relative.\r\n                    If the LOCK prefix is used.\r\n                    If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                    If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#SS(0)              If the memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDMK"
    }, 
    {
      "description": "BNDMOV-Move Bounds\r\n Opcode/                          Op/En     64/32        CPUID          Description\r\n Instruction                                bit Mode     Feature\r\n                                            Support      Flag\r\n 66 0F 1A /r                      RM        NE/V         MPX            Move lower and upper bound from bnd2/m64 to bound register\r\n BNDMOV bnd1, bnd2/m64                                                  bnd1.\r\n 66 0F 1A /r                      RM        V/NE         MPX            Move lower and upper bound from bnd2/m128 to bound register\r\n BNDMOV bnd1, bnd2/m128                                                 bnd1.\r\n 66 0F 1B /r                      MR        NE/V         MPX            Move lower and upper bound from bnd2 to bnd1/m64.\r\n BNDMOV bnd1/m64, bnd2\r\n 66 0F 1B /r                      MR        V/NE         MPX            Move lower and upper bound from bnd2 to bound register\r\n BNDMOV bnd1/m128, bnd2                                                 bnd1/m128.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n     Op/En                     Operand 1                                  Operand 2                                Operand 3\r\n      RM                    ModRM:reg (w)                            ModRM:r/m (r)                                         NA\r\n      MR                    ModRM:r/m (w)                               ModRM:reg (r)                                      NA\r\n\r\nDescription\r\nBNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the\r\ndestination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction.\r\nThe memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.\r\n\r\n\r\n\r\n\r\n                                                                                                BNDMOV to memory in 64-bit mode\r\n                       Upper Bound (UB)                  Lower Bound (LB)\r\n\r\n\r\n                    16                                                  8                                          0     Byte offset\r\n\r\n\r\n\r\n\r\n                                                                                              BNDMOV to memory in 32-bit mode\r\n                  Upper Bound (UB)                     Lower Bound (LB)\r\n\r\n\r\n                  16                                                8                     4                    0       Byte offset\r\n\r\n\r\n\r\n\r\n                                  Figure 3-5. Memory Layout of BNDMOV to/from Memory\r\n\r\n\r\nThis instruction does not change flags.\r\n\r\nOperation\r\nBNDMOV register to register\r\nDEST.LB <- SRC.LB;\r\nDEST.UB <- SRC.UB;\r\n\r\n\r\n\r\n\r\n\r\nBNDMOV from memory\r\nIF 64-bit mode THEN\r\n         DEST.LB <- LOAD_QWORD(SRC);\r\n         DEST.UB <- LOAD_QWORD(SRC+8);\r\n    ELSE\r\n         DEST.LB <- LOAD_DWORD_ZERO_EXT(SRC);\r\n         DEST.UB <- LOAD_DWORD_ZERO_EXT(SRC+4);\r\nFI;\r\n\r\nBNDMOV to memory\r\nIF 64-bit mode THEN\r\n         DEST[63:0] <- SRC.LB;\r\n         DEST[127:64] <- SRC.UB;\r\n    ELSE\r\n         DEST[31:0] <- SRC.LB;\r\n         DEST[63:32] <- SRC.UB;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDMOV         void * _bnd_copy_ptr_bounds(const void *q, const void *r)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                   If the LOCK prefix is used but the destination is not a memory operand.\r\n                      If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                      If 67H prefix is not used and CS.D=0.\r\n                      If 67H prefix is used and CS.D=1.\r\n#SS(0)                If the memory operand effective address is outside the SS segment limit.\r\n#GP(0)                If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the destination operand points to a non-writable segment\r\n                      If the DS, ES, FS, or GS segment register contains a NULL segment selector.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code)       If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                   If the LOCK prefix is used but the destination is not a memory operand.\r\n                      If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                      If 16-bit addressing is used.\r\n#GP(0)                If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                   If the memory operand effective address is outside the SS segment limit.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n                    If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                    If 16-bit addressing is used.\r\n#GP(0)              If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If the memory operand effective address is outside the SS segment limit.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code)     If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n                    If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#SS(0)              If the memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code)     If a page fault occurs.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDMOV"
    }, 
    {
      "description": "BNDSTX-Store Extended Bounds Using Address Translation\r\n Opcode/                          Op/En     64/32        CPUID     Description\r\n Instruction                                bit Mode     Feature\r\n                                            Support      Flag\r\n 0F 1B /r                         MR        V/V          MPX       Store the bounds in bnd and the pointer value in the index regis-\r\n BNDSTX mib, bnd                                                   ter of mib to a bound table entry (BTE) with address translation\r\n                                                                   using the base of mib.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n     Op/En                     Operand 1                             Operand 2                               Operand 3\r\n                     SIB.base (r): Address of pointer\r\n      MR                                                           ModRM:reg (r)                                 NA\r\n                               SIB.index(r)\r\n\r\nDescription\r\nBNDSTX uses the linear address constructed from the displacement and base register of the SIB-addressing form\r\nof the memory operand (mib) to perform address translation to store to a bound table entry. The bounds in the\r\nsource operand bnd are written to the lower and upper bounds in the BTE. The content of the index register of mib\r\nis written to the pointer value field in the BTE.\r\nThis instruction does not cause memory access to the linear address of mib nor the effective address referenced by\r\nthe base, and does not read or write any flags.\r\nSegment overrides apply to the linear address computation with the base of mib, and are used during address\r\ntranslation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be\r\nlinear address. There are no segmentation checks performed on the base of mib.\r\nThe base of mib will not be checked for canonical address violation as it does not access memory.\r\nAny encoding of this instruction that does not specify base or index register will treat those registers as zero\r\n(constant). The reg-reg form of this instruction will remain a NOP.\r\nThe scale field of the SIB byte has no effect on these instructions and is ignored.\r\nThe bound register may be partially updated on memory faults. The order in which memory operands are loaded is\r\nimplementation specific.\r\n\r\nOperation\r\nbase <- mib.SIB.base ? mib.SIB.base + Disp: 0;\r\nptr_value <- mib.SIB.index ? mib.SIB.index : 0;\r\n\r\nOutside 64-bit mode\r\nA_BDE[31:0] <- (Zero_extend32(base[31:12] << 2) + (BNDCFG[31:12] <<12 );\r\nA_BT[31:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n    BNDSTATUS <- A_BDE | 02H;\r\n    #BR;\r\nFI;\r\nA_DEST[31:0] <- (Zero_extend32(base[11:2] << 4) + (A_BT[31:2] << 2 ); // address of Bound table entry\r\nA_DEST[8][31:0] <- ptr_value;\r\nA_DEST[0][31:0] <- BND.LB;\r\nA_DEST[4][31:0] <- BND.UB;\r\n\r\n\r\n\r\n\r\n\r\nIn 64-bit mode\r\nA_BDE[63:0] <- (Zero_extend64(base[47+MAWA:20] << 3) + (BNDCFG[63:20] <<12 );1\r\nA_BT[63:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n    BNDSTATUS <- A_BDE | 02H;\r\n    #BR;\r\nFI;\r\nA_DEST[63:0] <- (Zero_extend64(base[19:3] << 5) + (A_BT[63:3] << 3 ); // address of Bound table entry\r\nA_DEST[16][63:0] <- ptr_value;\r\nA_DEST[0][63:0] <- BND.LB;\r\nA_DEST[8][63:0] <- BND.UB;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDSTX: _bnd_store_ptr_bounds(const void **ptr_addr, const void *ptr_val);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR                    If the bound directory entry is invalid.\r\n#UD                    If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 67H prefix is not used and CS.D=0.\r\n                       If 67H prefix is used and CS.D=1.\r\n#GP(0)                 If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n                       If DS register contains a NULL segment selector.\r\n                       If the destination operand points to a non-writable segment\r\n#PF(fault code)        If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                    If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 16-bit addressing is used.\r\n#GP(0)                 If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                    If the LOCK prefix is used.\r\n                       If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n                       If 16-bit addressing is used.\r\n#GP(0)                 If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n#PF(fault code)        If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumer-\r\n   ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel 64 and IA-32 Architectures Software Devel-\r\n   oper's Manual, Volume 1.\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#BR                     If the bound directory entry is invalid.\r\n#UD                     If ModRM is RIP relative.\r\n                        If the LOCK prefix is used.\r\n                        If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#GP(0)                  If the memory address (A_BDE or A_BTE) is in a non-canonical form.\r\n                        If the destination operand points to a non-writable segment\r\n#PF(fault code)         If a page fault occurs.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BNDSTX"
    }, 
    {
      "description": "BOUND-Check Array Index Against Bounds\r\nOpcode                  Instruction                  Op/   64-bit    Compat/ Description\r\n                                                     En    Mode      Leg Mode\r\n62 /r                   BOUND r16, m16&16            RM    Invalid   Valid     Check if r16 (array index) is within bounds\r\n                                                                               specified by m16&16.\r\n62 /r                   BOUND r32, m32&32            RM    Invalid   Valid     Check if r32 (array index) is within bounds\r\n                                                                               specified by m32&32.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En             Operand 1                      Operand 2                 Operand 3                    Operand 4\r\n    RM             ModRM:reg (r)                  ModRM:r/m (r)                 NA                            NA\r\n\r\nDescription\r\nBOUND determines if the first operand (array index) is within the bounds of an array specified the second operand\r\n(bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory loca-\r\ntion that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed\r\nword-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the\r\narray and the second doubleword (or word) is the upper bound of the array. The array index must be greater than\r\nor equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index\r\nis not within bounds, a BOUND range exceeded exception (#BR) is signaled. When this exception is generated, the\r\nsaved return instruction pointer points to the BOUND instruction.\r\nThe bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is\r\nusually placed just before the array itself, making the limits addressable via a constant offset from the beginning of\r\nthe array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles\r\nto obtain the effective address of the array bounds.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)\r\n         (* Below lower bound or above upper bound *)\r\n              THEN #BR; FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#BR                   If the bounds test fails.\r\n#UD                   If second operand is not a memory location.\r\n                      If the LOCK prefix is used.\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#BR                    If the bounds test fails.\r\n#UD                    If second operand is not a memory location.\r\n                       If the LOCK prefix is used.\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR                    If the bounds test fails.\r\n#UD                    If second operand is not a memory location.\r\n                       If the LOCK prefix is used.\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                    If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BOUND"
    }, 
    {
      "description": "BSF-Bit Scan Forward\r\n Opcode                   Instruction                 Op/   64-bit   Compat/ Description\r\n                                                      En    Mode     Leg Mode\r\n 0F BC /r                 BSF r16, r/m16              RM    Valid    Valid       Bit scan forward on r/m16.\r\n 0F BC /r                 BSF r32, r/m32              RM    Valid    Valid       Bit scan forward on r/m32.\r\n REX.W + 0F BC /r         BSF r64, r/m64              RM    Valid    N.E.        Bit scan forward on r/m64.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En              Operand 1                     Operand 2                 Operand 3                    Operand 4\r\n    RM              ModRM:reg (w)                 ModRM:r/m (r)                 NA                              NA\r\n\r\nDescription\r\nSearches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is\r\nfound, its bit index is stored in the destination operand (first operand). The source operand can be a register or a\r\nmemory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source\r\noperand. If the content of the source operand is 0, the content of the destination operand is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF SRC = 0\r\n    THEN\r\n        ZF <- 1;\r\n        DEST is undefined;\r\n    ELSE\r\n        ZF <- 0;\r\n        temp <- 0;\r\n        WHILE Bit(SRC, temp) = 0\r\n        DO\r\n            temp <- temp + 1;\r\n        OD;\r\n        DEST <- temp;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BSF"
    }, 
    {
      "description": "BSR-Bit Scan Reverse\r\nOpcode                   Instruction                  Op/     64-bit   Compat/ Description\r\n                                                      En      Mode     Leg Mode\r\n0F BD /r                 BSR r16, r/m16               RM      Valid    Valid      Bit scan reverse on r/m16.\r\n0F BD /r                 BSR r32, r/m32               RM      Valid    Valid      Bit scan reverse on r/m32.\r\nREX.W + 0F BD /r         BSR r64, r/m64               RM      Valid    N.E.       Bit scan reverse on r/m64.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En             Operand 1                     Operand 2                    Operand 3                   Operand 4\r\n   RM              ModRM:reg (w)                 ModRM:r/m (r)                    NA                              NA\r\n\r\nDescription\r\nSearches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is\r\nfound, its bit index is stored in the destination operand (first operand). The source operand can be a register or a\r\nmemory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source\r\noperand. If the content source operand is 0, the content of the destination operand is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF SRC = 0\r\n    THEN\r\n        ZF <- 1;\r\n        DEST is undefined;\r\n    ELSE\r\n        ZF <- 0;\r\n        temp <- OperandSize - 1;\r\n        WHILE Bit(SRC, temp) = 0\r\n        DO\r\n            temp <- temp - 1;\r\n        OD;\r\n        DEST <- temp;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BSR"
    }, 
    {
      "description": "BSWAP-Byte Swap\r\nOpcode                    Instruction                   Op/   64-bit   Compat/ Description\r\n                                                        En    Mode     Leg Mode\r\n0F C8+rd                  BSWAP r32                     O     Valid*   Valid       Reverses the byte order of a 32-bit register.\r\nREX.W + 0F C8+rd          BSWAP r64                     O     Valid    N.E.        Reverses the byte order of a 64-bit register.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En             Operand 1                     Operand 2                    Operand 3                    Operand 4\r\n    O            opcode + rd (r, w)                     NA                        NA                            NA\r\n\r\nDescription\r\nReverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-\r\nendian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG\r\ninstruction. When the BSWAP instruction references a 16-bit register, the result is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nIA-32 Architecture Legacy Compatibility\r\nThe BSWAP instruction is not supported on IA-32 processors earlier than the Intel486 processor family. For\r\ncompatibility with this instruction, software should include functionally equivalent code for execution on Intel\r\nprocessors earlier than the Intel486 processor family.\r\n\r\nOperation\r\nTEMP <- DEST\r\nIF 64-bit mode AND OperandSize = 64\r\n    THEN\r\n         DEST[7:0] <- TEMP[63:56];\r\n         DEST[15:8] <- TEMP[55:48];\r\n         DEST[23:16] <- TEMP[47:40];\r\n         DEST[31:24] <- TEMP[39:32];\r\n         DEST[39:32] <- TEMP[31:24];\r\n         DEST[47:40] <- TEMP[23:16];\r\n         DEST[55:48] <- TEMP[15:8];\r\n         DEST[63:56] <- TEMP[7:0];\r\n    ELSE\r\n         DEST[7:0] <- TEMP[31:24];\r\n         DEST[15:8] <- TEMP[23:16];\r\n         DEST[23:16] <- TEMP[15:8];\r\n         DEST[31:24] <- TEMP[7:0];\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n", 
      "mnem": "BSWAP"
    }, 
    {
      "description": "BT-Bit Test\r\n Opcode                    Instruction                  Op/      64-bit   Compat/ Description\r\n                                                        En       Mode     Leg Mode\r\n 0F A3 /r                  BT r/m16, r16                MR       Valid    Valid       Store selected bit in CF flag.\r\n 0F A3 /r                  BT r/m32, r32                MR       Valid    Valid       Store selected bit in CF flag.\r\n REX.W + 0F A3 /r          BT r/m64, r64                MR       Valid    N.E.        Store selected bit in CF flag.\r\n 0F BA /4 ib               BT r/m16, imm8               MI       Valid    Valid       Store selected bit in CF flag.\r\n 0F BA /4 ib               BT r/m32, imm8               MI       Valid    Valid       Store selected bit in CF flag.\r\n REX.W + 0F BA /4 ib       BT r/m64, imm8               MI       Valid    N.E.        Store selected bit in CF flag.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n    Op/En              Operand 1                     Operand 2                    Operand 3                      Operand 4\r\n     MR             ModRM:r/m (r)                  ModRM:reg (r)                     NA                                NA\r\n     MI             ModRM:r/m (r)                      imm8                          NA                                NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset (specified by the second operand) and stores the value of the bit in the CF flag. The bit base operand\r\ncan be a register or a memory location; the bit offset operand can be a register or an immediate value:\r\n.    If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n     operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n     mode).\r\n.    If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n     that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n     referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit oper-\r\nands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the high-\r\norder bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The\r\nprocessor will ignore the high order bits if they are not zero.\r\nWhen accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit\r\noperand size, using by the following relationship:\r\n\r\n    Effective Address + (4 * (BitOffset DIV 32))\r\nOr, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:\r\n\r\n    Effective Address + (2 * (BitOffset DIV 16))\r\nIt may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit\r\naddressing mechanism, software should avoid referencing areas of memory close to address space holes. In partic-\r\nular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instruc-\r\ntions to load from or store to these addresses, and use the register form of these instructions to manipulate the\r\ndata.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-\r\nands. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit. The ZF flag is unaffected. The OF, SF, AF, and PF flags are\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                     If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)               If the memory address is in a non-canonical form.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BT"
    }, 
    {
      "description": "BTC-Bit Test and Complement\r\n Opcode                    Instruction                    Op/   64-bit   Compat/ Description\r\n                                                          En    Mode     Leg Mode\r\n 0F BB /r                  BTC r/m16, r16                 MR    Valid    Valid        Store selected bit in CF flag and complement.\r\n 0F BB /r                  BTC r/m32, r32                 MR    Valid    Valid        Store selected bit in CF flag and complement.\r\n REX.W + 0F BB /r          BTC r/m64, r64                 MR    Valid    N.E.         Store selected bit in CF flag and complement.\r\n 0F BA /7 ib               BTC r/m16, imm8                MI    Valid    Valid        Store selected bit in CF flag and complement.\r\n 0F BA /7 ib               BTC r/m32, imm8                MI    Valid    Valid        Store selected bit in CF flag and complement.\r\n REX.W + 0F BA /7 ib       BTC r/m64, imm8                MI    Valid    N.E.         Store selected bit in CF flag and complement.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n    Op/En              Operand 1                    Operand 2                    Operand 3                     Operand 4\r\n     MR           ModRM:r/m (r, w)                ModRM:reg (r)                     NA                             NA\r\n     MI           ModRM:r/m (r, w)                       imm8                       NA                             NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected\r\nbit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a\r\nregister or an immediate value:\r\n.    If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n     operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n     mode). This allows any bit position to be selected.\r\n.    If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n     that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n     referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- NOT Bit(BitBase, BitOffset);\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF,\r\nAF, and PF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination operand points to a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BTC"
    }, 
    {
      "description": "BTR-Bit Test and Reset\r\n Opcode                      Instruction            Op/   64-bit     Compat/ Description\r\n                                                    En    Mode       Leg Mode\r\n 0F B3 /r                    BTR r/m16, r16         MR    Valid      Valid      Store selected bit in CF flag and clear.\r\n 0F B3 /r                    BTR r/m32, r32         MR    Valid      Valid      Store selected bit in CF flag and clear.\r\n REX.W + 0F B3 /r            BTR r/m64, r64         MR    Valid      N.E.       Store selected bit in CF flag and clear.\r\n 0F BA /6 ib                 BTR r/m16, imm8        MI    Valid      Valid      Store selected bit in CF flag and clear.\r\n 0F BA /6 ib                 BTR r/m32, imm8        MI    Valid      Valid      Store selected bit in CF flag and clear.\r\n REX.W + 0F BA /6 ib         BTR r/m64, imm8        MI    Valid      N.E.       Store selected bit in CF flag and clear.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n    Op/En                Operand 1               Operand 2                   Operand 3                     Operand 4\r\n     MR             ModRM:r/m (r, w)            ModRM:reg (r)                   NA                             NA\r\n     MI             ModRM:r/m (r, w)               imm8                         NA                             NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the\r\nbit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register\r\nor an immediate value:\r\n.    If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n     operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n     mode). This allows any bit position to be selected.\r\n.    If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n     that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n     referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- 0;\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is cleared. The ZF flag is unaffected. The OF, SF, AF, and\r\nPF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination operand points to a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BTR"
    }, 
    {
      "description": "BTS-Bit Test and Set\r\n Opcode                    Instruction             Op/     64-bit    Compat/ Description\r\n                                                   En      Mode      Leg Mode\r\n 0F AB /r                  BTS r/m16, r16          MR      Valid     Valid       Store selected bit in CF flag and set.\r\n 0F AB /r                  BTS r/m32, r32          MR      Valid     Valid       Store selected bit in CF flag and set.\r\n REX.W + 0F AB /r          BTS r/m64, r64          MR      Valid     N.E.        Store selected bit in CF flag and set.\r\n 0F BA /5 ib               BTS r/m16, imm8         MI      Valid     Valid       Store selected bit in CF flag and set.\r\n 0F BA /5 ib               BTS r/m32, imm8         MI      Valid     Valid       Store selected bit in CF flag and set.\r\n REX.W + 0F BA /5 ib       BTS r/m64, imm8         MI      Valid     N.E.        Store selected bit in CF flag and set.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n    Op/En              Operand 1               Operand 2                     Operand 3                      Operand 4\r\n     MR           ModRM:r/m (r, w)            ModRM:reg (r)                     NA                              NA\r\n     MI           ModRM:r/m (r, w)               imm8                           NA                              NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and sets the selected bit in the\r\nbit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register\r\nor an immediate value:\r\n.    If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n     operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n     mode). This allows any bit position to be selected.\r\n.    If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n     that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n     referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- 1;\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is set. The ZF flag is unaffected. The OF, SF, AF, and PF\r\nflags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination operand points to a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BTS"
    }, 
    {
      "description": "BZHI - Zero High Bits Starting with Specified Bit Position\r\n  Opcode/Instruction                  Op/      64/32         CPUID       Description\r\n                                      En       -bit          Feature\r\n                                               Mode          Flag\r\n  VEX.NDS.LZ.0F38.W0 F5 /r            RMV      V/V           BMI2        Zero bits in r/m32 starting with the position in r32b, write result to\r\n  BZHI r32a, r/m32, r32b                                                 r32a.\r\n  VEX.NDS.LZ.0F38.W1 F5 /r            RMV      V/N.E.        BMI2        Zero bits in r/m64 starting with the position in r64b, write result to\r\n  BZHI r64a, r/m64, r64b                                                 r64a.\r\n\r\n\r\n\r\n                                                        Instruction Operand Encoding\r\n   Op/En                Operand 1                            Operand 2                      Operand 3                       Operand 4\r\n    RMV              ModRM:reg (w)                      ModRM:r/m (r)                      VEX.vvvv (r)                         NA\r\n\r\nDescription\r\nBZHI copies the bits of the first source operand (the second operand) into the destination operand (the first\r\noperand) and clears the higher bits in the destination according to the INDEX value specified by the second source\r\noperand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is\r\nsaturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand\r\nis greater than OperandSize -1.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nN <- SRC2[7:0]\r\nDEST <- SRC1\r\nIF (N < OperandSize)\r\n    DEST[OperandSize-1:N] <- 0\r\nFI\r\nIF (N > OperandSize - 1)\r\n    CF <- 1\r\nELSE\r\n    CF <- 0\r\nFI\r\n\r\nFlags Affected\r\nZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBZHI:           unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);\r\n\r\nBZHI:           unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                        If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "BZHI"
    }, 
    {
      "description": "CALL-Call Procedure\r\n    Opcode             Instruction          Op/    64-bit    Compat/ Description\r\n                                            En     Mode      Leg Mode\r … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CALL"
    }, 
    {
      "description": "CBW/CWDE/CDQE-Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword\r\nOpcode                    Instruction                 Op/     64-bit     Compat/ Description\r\n                                                      En      Mode       Leg Mode\r\n98                        CBW                         NP      Valid      Valid       AX <- sign-extend of AL.\r\n98                        CWDE                        NP      Valid      Valid       EAX <- sign-extend of AX.\r\nREX.W + 98                CDQE                        NP      Valid      N.E.        RAX <- sign-extend of EAX.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En             Operand 1                     Operand 2                      Operand 3                     Operand 4\r\n     NP                 NA                           NA                             NA                            NA\r\n\r\nDescription\r\nDouble the size of the source operand by means of sign extension. The CBW (convert byte to word) instruction\r\ncopies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to double-\r\nword) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register.\r\nCBW and CWDE reference the same opcode. The CBW instruction is intended for use when the operand-size attri-\r\nbute is 16; CWDE is intended for use when the operand-size attribute is 32. Some assemblers may force the\r\noperand size. Others may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of the\r\noperand-size attribute to determine the size of values to be converted.\r\nIn 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes\r\nthis instruction (CDQE when promoted) to operate on 64-bit operands. In which case, CDQE copies the sign (bit\r\n31) of the doubleword in the EAX register into the high 32 bits of RAX.\r\n\r\nOperation\r\nIF OperandSize = 16 (* Instruction = CBW *)\r\n    THEN\r\n        AX <- SignExtend(AL);\r\n    ELSE IF (OperandSize = 32, Instruction = CWDE)\r\n        EAX <- SignExtend(AX); FI;\r\n    ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)\r\n        RAX <- SignExtend(EAX);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CBW"
    }, 
    {
      "description": "-R:CWD", 
      "mnem": "CDQ"
    }, 
    {
      "description": "-R:CBW", 
      "mnem": "CDQE"
    }, 
    {
      "description": "CLAC-Clear AC Flag in EFLAGS Register\r\nOpcode/                                   Op /    64/32 bit   CPUID     Description\r\nInstruction                               En      Mode        Feature\r\n                                                  Support     Flag\r\n0F 01 CA                                  NP      V/V         SMAP      Clear the AC flag in the EFLAGS register.\r\nCLAC\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n  Op/En           Operand 1                Operand 2                    Operand 3                      Operand 4\r\n    NP               NA                          NA                        NA                              NA\r\n\r\nDescription\r\nClears the AC flag bit in EFLAGS register. This disables any alignment checking of user-mode data accesses. If the\r\nSMAP bit is set in the CR4 register, this disallows explicit supervisor-mode data accesses to user-mode pages.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when\r\nCPL > 0 cause #UD.\r\n\r\nOperation\r\nEFLAGS.AC <- 0;\r\n\r\nFlags Affected\r\nAC cleared. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If the CPL > 0.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 The CLAC instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If the CPL > 0.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n                    If the CPL > 0.\r\n                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLAC"
    }, 
    {
      "description": "CLC-Clear Carry Flag\r\n Opcode                    Instruction                 Op/   64-bit   Compat/ Description\r\n                                                       En    Mode     Leg Mode\r\n F8                        CLC                         NP    Valid    Valid      Clear CF flag.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n   Op/En               Operand 1                 Operand 2                    Operand 3                   Operand 4\r\n      NP                  NA                           NA                        NA                          NA\r\n\r\nDescription\r\nClears the CF flag in the EFLAGS register. Operation is the same in all modes.\r\n\r\nOperation\r\nCF <- 0;\r\n\r\nFlags Affected\r\nThe CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                      If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLC"
    }, 
    {
      "description": "CLD-Clear Direction Flag\r\nOpcode                 Instruction                 Op/   64-bit   Compat/ Description\r\n                                                   En    Mode     Leg Mode\r\nFC                     CLD                         NP    Valid    Valid         Clear DF flag.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En            Operand 1                 Operand 2                    Operand 3               Operand 4\r\n     NP               NA                           NA                        NA                       NA\r\n\r\nDescription\r\nClears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index regis-\r\nters (ESI and/or EDI). Operation is the same in all modes.\r\n\r\nOperation\r\nDF <- 0;\r\n\r\nFlags Affected\r\nThe DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                  If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLD"
    }, 
    {
      "description": "CLFLUSH-Flush Cache Line\r\n Opcode                    Instruction                 Op/    64-bit      Compat/ Description\r\n                                                       En     Mode        Leg Mode\r\n 0F AE /7                  CLFLUSH m8                  M      Valid       Valid       Flushes cache line containing m8.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En             Operand 1                     Operand 2                       Operand 3                    Operand 4\r\n    M             ModRM:r/m (w)                       NA                             NA                            NA\r\n\r\nDescription\r\nInvalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the\r\nlinear address specified with the memory operand. If that cache line contains modified data at any level of the\r\ncache hierarchy, that data is written back to memory. The source operand is a byte memory location.\r\nThe availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH\r\n(CPUID.01H:EDX[bit 19]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8\r\nthrough 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions\r\nassigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh\r\ninstructions can be used to provide the processor with hints for this speculative behavior. Because this speculative\r\nfetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with\r\nrespect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be specula-\r\ntively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references\r\nthe cache line).\r\nExecutions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked\r\nread-modify-write instructions, fence instructions, and executions of CLFLUSHOPT to the same cache line.1 They\r\nare not ordered with respect to executions of CLFLUSHOPT to different cache lines.\r\nThe CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults asso-\r\nciated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an execute-\r\nonly segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.\r\nIn some implementations, the CLFLUSH instruction may always cause transactional abort with Transactional\r\nSynchronization Extensions (TSX). The CLFLUSH instruction is not expected to be commonly used inside typical\r\ntransactional regions. However, programmers must not rely on CLFLUSH instruction to force a transactional abort,\r\nsince whether they cause transactional abort is implementation dependent.\r\nThe CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature\r\nflag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the pres-\r\nence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is imple-\r\nmented in the processor.\r\nCLFLUSH operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFlush_Cache_Line(SRC);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nCLFLUSH:    void _mm_clflush(void const *p)\r\n\r\n\r\n\r\n\r\n1. Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction.\r\n   All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0)              For an illegal address in the SS segment.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD                 If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code)     For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLFLUSH"
    }, 
    {
      "description": "CLFLUSHOPT-Flush Cache Line Optimized\r\n Opcode                   Instruction                Op/     64-bit   Compat/ Description\r\n                                                     En      Mode     Leg Mode\r\n 66 0F AE /7              CLFLUSHOPT m8              M       Valid    Valid       Flushes cache line containing m8.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En             Operand 1                    Operand 2                    Operand 3                    Operand 4\r\n    M             ModRM:r/m (w)                     NA                           NA                           NA\r\n\r\nDescription\r\nInvalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the\r\nlinear address specified with the memory operand. If that cache line contains modified data at any level of the\r\ncache hierarchy, that data is written back to memory. The source operand is a byte memory location.\r\nThe availability of CLFLUSHOPT is indicated by the presence of the CPUID feature flag CLFLUSHOPT\r\n(CPUID.(EAX=7,ECX=0):EBX[bit 23]). The aligned cache line size affected is also indicated with the CPUID instruc-\r\ntion (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions\r\nassigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh\r\ninstructions can be used to provide the processor with hints for this speculative behavior. Because this speculative\r\nfetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with\r\nrespect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be specula-\r\ntively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references\r\nthe cache line).\r\nExecutions of the CLFLUSHOPT instruction are ordered with respect to fence instructions and to locked read-\r\nmodify-write instructions; they are also ordered with respect to the following accesses to the cache line being\r\ninvalidated: writes, executions of CLFLUSH, and executions of CLFLUSHOPT. They are not ordered with respect to\r\nwrites, executions of CLFLUSH, or executions of CLFLUSHOPT that access other cache lines; to enforce ordering\r\nwith such an operation, software can insert an SFENCE instruction between CFLUSHOPT and that operation.\r\nThe CLFLUSHOPT instruction can be used at all privilege levels and is subject to all permission checking and faults\r\nassociated with a byte load (and in addition, a CLFLUSHOPT instruction is allowed to flush a linear address in an\r\nexecute-only segment). Like a load, the CLFLUSHOPT instruction sets the A bit but not the D bit in the page tables.\r\nIn some implementations, the CLFLUSHOPT instruction may always cause transactional abort with Transactional\r\nSynchronization Extensions (TSX). The CLFLUSHOPT instruction is not expected to be commonly used inside\r\ntypical transactional regions. However, programmers must not rely on CLFLUSHOPT instruction to force a transac-\r\ntional abort, since whether they cause transactional abort is implementation dependent.\r\nCLFLUSHOPT operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFlush_Cache_Line_Optimized(SRC);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nCLFLUSHOPT:void _mm_clflushopt(void const *p)\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0)              For an illegal address in the SS segment.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD                 If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code)     For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If an instruction prefix F2H or F3H is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLFLUSHOPT"
    }, 
    {
      "description": "CLI - Clear Interrupt Flag\r\n Opcode                       Instruction                  Op/    64-bit        Compat/ Description\r\n                                                           En     Mode          Leg Mode\r\n FA                           CLI                          NP     Valid         Valid         Clear interrupt flag; interrupts disabled when\r\n                                                                                              interrupt flag cleared.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n  Op/En                 Operand 1                     Operand 2                          Operand 3                        Operand 4\r\n      NP                     NA                            NA                                 NA                              NA\r\n\r\nDescription\r\nIf protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags\r\nare affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the\r\nCLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.\r\nWhen protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the\r\nEFLAGS register, leaving IF unaffected. Table 3-7 indicates the action of the CLI instruction depending on the\r\nprocessor operating mode and the CPL/IOPL of the running program or procedure.\r\nOperation is the same in all modes.\r\n\r\n\r\n                                             Table 3-7. Decision Table for CLI Results\r\n       PE               VM           IOPL            CPL            PVI                 VIP          VME                   CLI Result\r\n           0             X             X              X              X                  X             X         IF = 0\r\n           1             0           >= CPL            X              X                  X             X         IF = 0\r\n           1             0           < CPL            3              1                  X             X         VIF = 0\r\n           1             0           < CPL           <3              X                  X             X         GP Fault\r\n           1             0           < CPL            X              0                  X             X         GP Fault\r\n           1             1             3              X              X                  X             X         IF = 0\r\n           1             1            <3              X              X                  X             1         VIF = 0\r\n           1             1            <3              X              X                  X             0         GP Fault\r\n NOTES:\r\n * X = This setting has no impact.\r\n\r\nOperation\r\nIF PE = 0\r\n    THEN\r\n         IF <- 0; (* Reset Interrupt Flag *)\r\n    ELSE\r\n         IF VM = 0;\r\n             THEN\r\n                   IF IOPL >= CPL\r\n                        THEN\r\n                              IF <- 0; (* Reset Interrupt Flag *)\r\n                   ELSE\r\n                        IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))\r\n                              THEN\r\n                                  VIF <- 0; (* Reset Virtual Interrupt Flag *)\r\n                              ELSE\r\n                                  #GP(0);\r\n\r\n\r\n                       FI;\r\n                  FI;\r\n              ELSE (* VM = 1 *)\r\n                  IF IOPL = 3\r\n                       THEN\r\n                            IF <- 0; (* Reset Interrupt Flag *)\r\n                       ELSE\r\n                            IF (IOPL < 3) AND (VME = 1)\r\n                                  THEN\r\n                                      VIF <- 0; (* Reset Virtual Interrupt Flag *)\r\n                                  ELSE\r\n                                      #GP(0);\r\n                            FI;\r\n                  FI;\r\n        FI;\r\nFI;\r\n\r\nFlags Affected\r\nIf protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the IOPL; other-\r\nwise, it is not affected. Other flags are unaffected.\r\nWhen protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the\r\nEFLAGS register, leaving IF unaffected. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                   If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                   If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD                      If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLI"
    }, 
    {
      "description": "CLTS-Clear Task-Switched Flag in CR0\r\n Opcode                     Instruction                Op/    64-bit   Compat/ Description\r\n                                                       En     Mode     Leg Mode\r\n 0F 06                      CLTS                       NP     Valid    Valid       Clears TS flag in CR0.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n   Op/En              Operand 1                   Operand 2                    Operand 3                    Operand 4\r\n    NP                    NA                           NA                         NA                           NA\r\n\r\nDescription\r\nClears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system\r\nprocedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-\r\naddress mode to allow initialization for protected mode.\r\nThe processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU\r\ncontext in multitasking applications. See the description of the TS flag in the section titled \"Control Registers\" in\r\nChapter 2 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information\r\nabout this flag.\r\nCLTS operation is the same in non-64-bit modes and 64-bit mode.\r\nSee Chapter 25, \"VMX Non-Root Operation,\" of the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.\r\n\r\nOperation\r\nCR0.TS[bit 3] <- 0;\r\n\r\nFlags Affected\r\nThe TS flag in CR0 register is cleared.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If the current privilege level is not 0.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                   CLTS is not recognized in virtual-8086 mode.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                   If the CPL is greater than 0.\r\n#UD                      If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLTS"
    }, 
    {
      "description": "CLWB-Cache Line Write Back\r\n Opcode/                     Op/      64/32 bit   CPUID          Description\r\n Instruction                 En       Mode        Feature Flag\r\n                                      Support\r\n 66 0F AE /6                 M        V/V         CLWB           Writes back modified cache line containing m8, and may\r\n CLWB m8                                                         retain the line in cache hierarchy in non-modified state.\r\n\r\n\r\n                                             Instruction Operand Encoding1\r\n     Op/En              Operand 1                  Operand 2                   Operand 3                     Operand 4\r\n        M             ModRM:r/m (w)                   NA                          NA                            NA\r\n\r\nDescription\r\nWrites back to memory the cache line (if modified) that contains the linear address specified with the memory\r\noperand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the\r\ncache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization\r\n(treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may\r\nchoose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from\r\nthe cache hierarchy. The source operand is a byte memory location.\r\nThe availability of CLWB instruction is indicated by the presence of the CPUID feature flag CLWB (bit 24 of the EBX\r\nregister, see \"CPUID - CPU Identification\" in this chapter). The aligned cache line size affected is also indicated\r\nwith the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions that\r\nare assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types).\r\nPREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this\r\nspeculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not\r\nordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can\r\nbe speculatively loaded into a cache line just before, during, or after the execution of a CLWB instruction that refer-\r\nences the cache line).\r\nCLWB instruction is ordered only by store-fencing operations. For example, software can use an SFENCE, MFENCE,\r\nXCHG, or LOCK-prefixed instructions to ensure that previous stores are included in the write-back. CLWB instruc-\r\ntion need not be ordered by another CLWB or CLFLUSHOPT instruction. CLWB is implicitly ordered with older stores\r\nexecuted by the logical processor to the same address.\r\nFor usages that require only writing back modified data from cache lines to memory (do not require the line to be\r\ninvalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate\r\nfencing) instead of CLFLUSH or CLFLUSHOPT for improved performance.\r\nThe CLWB instruction can be used at all privilege levels and is subject to all permission checking and faults associ-\r\nated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page\r\ntables.\r\nIn some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchro-\r\nnization Extensions (TSX). CLWB instruction is not expected to be commonly used inside typical transactional\r\nregions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether\r\nthey cause transactional abort is implementation dependent.\r\n\r\nOperation\r\nCache_Line_Write_Back(m8);\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n1. ModRM.MOD != 011B\r\n\r\n\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nCLWB void _mm_clwb(void const *p);\r\n\r\nProtected Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n                        If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#GP(0)                  For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0)                  For an illegal address in the SS segment.\r\n#PF(fault-code)         For a page fault.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n                        If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#GP                     If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code)         For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                     If the LOCK prefix is used.\r\n                        If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#SS(0)                  If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                  If the memory address is in a non-canonical form.\r\n#PF(fault-code)         For a page fault.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CLWB"
    }, 
    {
      "description": "CMC-Complement Carry Flag\r\nOpcode                  Instruction                 Op/   64-bit   Compat/ Description\r\n                                                    En    Mode     Leg Mode\r\nF5                      CMC                         NP    Valid    Valid        Complement CF flag.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En            Operand 1                 Operand 2                     Operand 3                     Operand 4\r\n     NP               NA                        NA                            NA                             NA\r\n\r\nDescription\r\nComplements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nEFLAGS.CF[bit 0]<- NOT EFLAGS.CF[bit 0];\r\n\r\nFlags Affected\r\nThe CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CMC"
    }, 
    {
      "description": "CMOVcc-Conditional Move\r\n Opcode                   Instruction          Op/   64-Bit   Compat/ Description\r\n                                               En    Mode     Leg  … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMOVcc"
    }, 
    {
      "description": "CMP-Compare Two Operands\r\nOpcode                     Instruction                 Op/     64-Bit      Compat/ Description\r\n                                                       En      Mode        Leg Mode\r\n3C ib                      CMP AL, imm8                I       Valid       Valid       Compare imm8 with AL.\r\n3D iw                      CMP AX, imm16               I       Valid       Valid       Compare imm16 with AX.\r\n3D id                      CMP EAX, imm32              I       Valid       Valid       Compare imm32 with EAX.\r\nREX.W + 3D id              CMP RAX, imm32              I       Valid       N.E.        Compare imm32 sign-extended to 64-bits\r\n                                                                                       with RAX.\r\n80 /7 ib                   CMP r/m8, imm8              MI      Valid       Valid       Compare imm8 with r/m8.\r\nREX + 80 /7 ib             CMP r/m8*, imm8             MI      Valid       N.E.        Compare imm8 with r/m8.\r\n81 /7 iw                   CMP r/m16, imm16            MI      Valid       Valid       Compare imm16 with r/m16.\r\n81 /7 id                   CMP r/m32, imm32            MI      Valid       Valid       Compare imm32 with r/m32.\r\nREX.W + 81 /7 id           CMP r/m64, imm32            MI      Valid       N.E.        Compare imm32 sign-extended to 64-bits\r\n                                                                                       with r/m64.\r\n83 /7 ib                   CMP r/m16, imm8             MI      Valid       Valid       Compare imm8 with r/m16.\r\n83 /7 ib                   CMP r/m32, imm8             MI      Valid       Valid       Compare imm8 with r/m32.\r\nREX.W + 83 /7 ib           CMP r/m64, imm8             MI      Valid       N.E.        Compare imm8 with r/m64.\r\n38 /r                      CMP r/m8, r8                MR      Valid       Valid       Compare r8 with r/m8.\r\n                                       *   *\r\nREX + 38 /r                CMP r/m8 , r8               MR      Valid       N.E.        Compare r8 with r/m8.\r\n39 /r                      CMP r/m16, r16              MR      Valid       Valid       Compare r16 with r/m16.\r\n39 /r                      CMP r/m32, r32              MR      Valid       Valid       Compare r32 with r/m32.\r\nREX.W + 39 /r              CMP r/m64,r64               MR      Valid       N.E.        Compare r64 with r/m64.\r\n3A /r                      CMP r8, r/m8                RM      Valid       Valid       Compare r/m8 with r8.\r\n                                   *       *\r\nREX + 3A /r                CMP r8 , r/m8               RM      Valid       N.E.        Compare r/m8 with r8.\r\n3B /r                      CMP r16, r/m16              RM      Valid       Valid       Compare r/m16 with r16.\r\n3B /r                      CMP r32, r/m32              RM      Valid       Valid       Compare r/m32 with r32.\r\nREX.W + 3B /r              CMP r64, r/m64              RM      Valid       N.E.        Compare r/m64 with r64.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En             Operand 1                      Operand 2                       Operand 3                     Operand 4\r\n    RM             ModRM:reg (r)                 ModRM:r/m (r)                        NA                             NA\r\n    MR             ModRM:r/m (r)                 ModRM:reg (r)                        NA                             NA\r\n    MI             ModRM:r/m (r)                     imm8                             NA                             NA\r\n     I           AL/AX/EAX/RAX (r)                   imm8                             NA                             NA\r\n\r\nDescription\r\nCompares the first source operand with the second source operand and sets the status flags in the EFLAGS register\r\naccording to the results. The comparison is performed by subtracting the second operand from the first operand\r\nand then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as\r\nan operand, it is sign-extended to the length of the first operand.\r\nThe condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction.\r\nAppendix B, \"EFLAGS Condition Codes,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1, shows the relationship of the status flags and the condition codes.\r\n\r\n\r\n\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\ntemp <- SRC1 - SignExtend(SRC2);\r\nModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CMP"
    }, 
    {
      "description": "CMPPD-Compare Packed Double-Precision Floating-Point Values\r\n Opcode/                                    Op /     64/32        CPUID      Description\r\n Instruction            … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMPPD"
    }, 
    {
      "description": "CMPPS-Compare Packed Single-Precision Floating-Point Values\r\n Opcode/                             Op /   64/32      CPUID      Description\r\n Instruction                       … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMPPS"
    }, 
    {
      "description": "CMPS/CMPSB/CMPSW/CMPSD/CMPSQ-Compare String Operands\r\n Opcode             Instruction           Op/    64-Bit      Compat/ Description\r\n                                       … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMPS"
    }, 
    {
      "description": "-R:CMPS", 
      "mnem": "CMPSB"
    }, 
    {
      "description": "-R:CMPS", 
      "mnem": "CMPSD"
    }, 
    {
      "description": "CMPSD-Compare Scalar Double-Precision Floating-Point Value\r\n    Opcode/                             Op /     64/32       CPUID     Description\r\n    Instruction                … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMPSD"
    }, 
    {
      "description": "-R:CMPS", 
      "mnem": "CMPSQ"
    }, 
    {
      "description": "CMPSS-Compare Scalar Single-Precision Floating-Point Value\r\n    Opcode/                                  Op /      64/32         CPUID     Description\r\n    Instruction        … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CMPSS"
    }, 
    {
      "description": "-R:CMPS", 
      "mnem": "CMPSW"
    }, 
    {
      "description": "CMPXCHG-Compare and Exchange\r\nOpcode/                                Op/    64-Bit       Compat/ Description\r\nInstruction                            En     Mode         Leg Mode\r\n0F B0/r                                MR     Valid        Valid*      Compare AL with r/m8. If equal, ZF is set and r8 is loaded into\r\nCMPXCHG r/m8, r8                                                       r/m8. Else, clear ZF and load r/m8 into AL.\r\n\r\nREX + 0F B0/r                          MR     Valid        N.E.        Compare AL with r/m8. If equal, ZF is set and r8 is loaded into\r\nCMPXCHG r/m8**,r8                                                      r/m8. Else, clear ZF and load r/m8 into AL.\r\n\r\n0F B1/r                                MR     Valid        Valid*      Compare AX with r/m16. If equal, ZF is set and r16 is loaded\r\nCMPXCHG r/m16, r16                                                     into r/m16. Else, clear ZF and load r/m16 into AX.\r\n0F B1/r                                MR     Valid        Valid*      Compare EAX with r/m32. If equal, ZF is set and r32 is loaded\r\nCMPXCHG r/m32, r32                                                     into r/m32. Else, clear ZF and load r/m32 into EAX.\r\n\r\nREX.W + 0F B1/r                        MR     Valid        N.E.        Compare RAX with r/m64. If equal, ZF is set and r64 is loaded\r\nCMPXCHG r/m64, r64                                                     into r/m64. Else, clear ZF and load r/m64 into RAX.\r\n\r\nNOTES:\r\n* See the IA-32 Architecture Compatibility section below.\r\n** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En               Operand 1                         Operand 2                     Operand 3                    Operand 4\r\n    MR             ModRM:r/m (r, w)                    ModRM:reg (r)                     NA                            NA\r\n\r\nDescription\r\nCompares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two\r\nvalues are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the\r\ndestination operand is loaded into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the\r\ninterface to the processor's bus, the destination operand receives a write cycle without regard to the result of the\r\ncomparison. The destination operand is written back if the comparison fails; otherwise, the source operand is\r\nwritten into the destination. (The processor never produces a locked read without also producing a locked write.)\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nIA-32 Architecture Compatibility\r\nThis instruction is not supported on Intel processors earlier than the Intel486 processors.\r\n\r\nOperation\r\n(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)\r\nTEMP <- DEST\r\nIF accumulator = TEMP\r\n    THEN\r\n        ZF <- 1;\r\n        DEST <- SRC;\r\n    ELSE\r\n        ZF <- 0;\r\n        accumulator <- TEMP;\r\n        DEST <- TEMP;\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nThe ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is\r\ncleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)               If the destination is located in a non-writable segment.\r\n                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                     If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)               If the memory address is in a non-canonical form.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CMPXCHG"
    }, 
    {
      "description": "-R:CMPXCHG8B", 
      "mnem": "CMPXCHG16B"
    }, 
    {
      "description": "CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes\r\nOpcode/                                Op/    64-Bit          Compat/ Description\r\nInstruction                            En     Mode            Leg Mode\r\n0F C7 /1 m64                           M      Valid           Valid*   Compare EDX:EAX with m64. If equal, set ZF and load\r\nCMPXCHG8B m64                                                          ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.\r\n\r\nREX.W + 0F C7 /1 m128                  M      Valid           N.E.     Compare RDX:RAX with m128. If equal, set ZF and load\r\nCMPXCHG16B m128                                                        RCX:RBX into m128. Else, clear ZF and load m128 into\r\n                                                                       RDX:RAX.\r\nNOTES:\r\n*See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En              Operand 1                        Operand 2                  Operand 3                    Operand 4\r\n    M            ModRM:r/m (r, w)                        NA                         NA                            NA\r\n\r\nDescription\r\nCompares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand\r\n(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored\r\nin the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX).\r\nThe destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For\r\nthe EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the\r\nlow-order 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-\r\norder 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the\r\ninterface to the processor's bus, the destination operand receives a write cycle without regard to the result of the\r\ncomparison. The destination operand is written back if the comparison fails; otherwise, the source operand is\r\nwritten into the destination. (The processor never produces a locked read without also producing a locked write.)\r\nIn 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that\r\nCMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the\r\nbeginning of this section for encoding data and limits. For information on the CPUID flag that indicates\r\nCMPXCHG16B, see page 3-206.\r\n\r\nIA-32 Architecture Compatibility\r\nThis instruction encoding is not supported on Intel processors earlier than the Pentium processors.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF (64-Bit Mode and OperandSize = 64)\r\n    THEN\r\n         TEMP128 <- DEST\r\n         IF (RDX:RAX = TEMP128)\r\n              THEN\r\n                  ZF <- 1;\r\n                  DEST <- RCX:RBX;\r\n              ELSE\r\n                  ZF <- 0;\r\n                  RDX:RAX <- TEMP128;\r\n                  DEST <- TEMP128;\r\n                  FI;\r\n         FI\r\n    ELSE\r\n         TEMP64 <- DEST;\r\n         IF (EDX:EAX = TEMP64)\r\n              THEN\r\n                  ZF <- 1;\r\n                  DEST <- ECX:EBX;\r\n              ELSE\r\n                  ZF <- 0;\r\n                  EDX:EAX <- TEMP64;\r\n                  DEST <- TEMP64;\r\n                  FI;\r\n         FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and\r\nOF flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#UD                  If the destination is not a memory operand.\r\n#GP(0)               If the destination is located in a non-writable segment.\r\n                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                     If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                  If the destination operand is not a memory location.\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                  If the destination operand is not a memory location.\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)               If the memory address is in a non-canonical form.\r\n                     If memory operand for CMPXCHG16B is not aligned on a 16-byte boundary.\r\n                     If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.\r\n#UD                  If the destination operand is not a memory location.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CMPXCHG8B"
    }, 
    {
      "description": "COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/                              Op /    64/32        CPUID         Description\r\n Instruction                          En      bit Mode     Feature\r\n                                              Support      Flag\r\n 66 0F 2F /r                          RM      V/V          SSE2          Compare low double-precision floating-point values in\r\n COMISD xmm1, xmm2/m64                                                   xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n                                                                         accordingly.\r\n VEX.128.66.0F.WIG 2F /r              RM      V/V          AVX           Compare low double-precision floating-point values in\r\n VCOMISD xmm1, xmm2/m64                                                  xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n                                                                         accordingly.\r\n EVEX.LIG.66.0F.W1 2F /r              T1S     V/V          AVX512F       Compare low double-precision floating-point values in\r\n VCOMISD xmm1, xmm2/m64{sae}                                             xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n                                                                         accordingly.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n      Op/En            Operand 1                    Operand 2                   Operand 3                      Operand 4\r\n       RM            ModRM:reg (w)              ModRM:r/m (r)                       NA                            NA\r\n       T1S           ModRM:reg (w)              ModRM:r/m (r)                       NA                            NA\r\n\r\nDescription\r\nCompares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and\r\noperand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-\r\ndered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-\r\ndered result is returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory\r\nlocation. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point\r\ninvalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals\r\nan invalid numeric exception only if a source operand is an SNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nCOMISD (all versions)\r\nRESULT <- OrderedCompare(DEST[63:0] <> SRC[63:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n    UNORDERED: ZF,PF,CF <- 111;\r\n    GREATER_THAN: ZF,PF,CF <- 000;\r\n    LESS_THAN: ZF,PF,CF <- 001;\r\n    EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <-0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);\r\nVCOMISD int _mm_comieq_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comilt_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comile_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comigt_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comige_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comineq_sd (__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN or QNaN operands), Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "COMISD"
    }, 
    {
      "description": "COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/                              Op /    64/32         CPUID          Description\r\n Instruction                          En      bit Mode      Feature\r\n                                              Support       Flag\r\n 0F 2F /r                             RM      V/V           SSE            Compare low single-precision floating-point values in\r\n COMISS xmm1, xmm2/m32                                                     xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n                                                                           accordingly.\r\n VEX.128.0F.WIG 2F /r                 RM      V/V           AVX            Compare low single-precision floating-point values in\r\n VCOMISS xmm1, xmm2/m32                                                    xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n                                                                           accordingly.\r\n EVEX.LIG.0F.W0 2F /r                 T1S     V/V           AVX512F        Compare low single-precision floating-point values in\r\n VCOMISS xmm1, xmm2/m32{sae}                                               xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n                                                                           accordingly.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n     Op/En             Operand 1                    Operand 2                      Operand 3                     Operand 4\r\n       RM            ModRM:reg (w)              ModRM:r/m (r)                          NA                            NA\r\n      T1S            ModRM:reg (w)              ModRM:r/m (r)                          NA                            NA\r\n\r\nDescription\r\nCompares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand\r\n2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered,\r\ngreater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result\r\nis returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.\r\nThe COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-\r\ntion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid\r\nnumeric exception only if a source operand is an SNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nCOMISS (all versions)\r\nRESULT <- OrderedCompare(DEST[31:0] <> SRC[31:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n    UNORDERED: ZF,PF,CF <- 111;\r\n    GREATER_THAN: ZF,PF,CF <- 000;\r\n    LESS_THAN: ZF,PF,CF <- 001;\r\n    EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <- 0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);\r\nVCOMISS int _mm_comieq_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comilt_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comile_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comigt_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comige_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comineq_ss (__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN or QNaN operands), Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "COMISS"
    }, 
    {
      "description": "CPUID-CPU Identification\r\nOpcode                    Instruction                  Op/   64-Bit      Compat/ Description\r\n                                                       … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "CPUID"
    }, 
    {
      "description": "-R:CWD", 
      "mnem": "CQO"
    }, 
    {
      "description": "CRC32 - Accumulate CRC32 Value\r\nOpcode/                                                 Op/     64-Bit     Compat/ Description\r\nInstruction                                             En      Mode       Leg Mode\r\nF2 0F 38 F0 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m8.\r\nCRC32 r32, r/m8\r\nF2 REX 0F 38 F0 /r                                      RM      Valid      N.E.         Accumulate CRC32 on r/m8.\r\nCRC32 r32, r/m8*\r\nF2 0F 38 F1 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m16.\r\nCRC32 r32, r/m16\r\nF2 0F 38 F1 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m32.\r\nCRC32 r32, r/m32\r\nF2 REX.W 0F 38 F0 /r                                    RM      Valid      N.E.         Accumulate CRC32 on r/m8.\r\nCRC32 r64, r/m8\r\nF2 REX.W 0F 38 F1 /r                                    RM      Valid      N.E.         Accumulate CRC32 on r/m64.\r\nCRC32 r64, r/m64\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En              Operand 1                      Operand 2                      Operand 3                      Operand 4\r\n    RM            ModRM:reg (r, w)                ModRM:r/m (r)                       NA                             NA\r\n\r\nDescription\r\nStarting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial\r\n11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The\r\nsource operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If\r\nthe destination is an r64 register, then the 32-bit result is stored in the least significant double word and\r\n00000000H is stored in the most significant double word of the r64 register.\r\nThe initial value supplied in the destination operand is a double word integer stored in the r32 register or the least\r\nsignificant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result\r\nof the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new\r\ninput data in the source operand. Data contained in the source operand is processed in reflected bit order. This\r\nmeans that the most significant bit of the source operand is treated as the least significant bit of the quotient, and\r\nso on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination\r\noperand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the\r\nleast significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.\r\n\r\nOperation\r\n\r\nNotes:\r\n   BIT_REFLECT64: DST[63-0] = SRC[0-63]\r\n   BIT_REFLECT32: DST[31-0] = SRC[0-31]\r\n   BIT_REFLECT16: DST[15-0] = SRC[0-15]\r\n   BIT_REFLECT8: DST[7-0] = SRC[0-7]\r\n   MOD2: Remainder from Polynomial division modulus 2\r\n\r\n\r\n\r\n\r\n\r\nCRC32 instruction for 64-bit source operand and 64-bit destination operand:\r\n\r\n   TEMP1[63-0] <- BIT_REFLECT64 (SRC[63-0])\r\n   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n   TEMP3[95-0] <- TEMP1[63-0] << 32\r\n   TEMP4[95-0] <- TEMP2[31-0] << 64\r\n   TEMP5[95-0] <- TEMP3[95-0] XOR TEMP4[95-0]\r\n   TEMP6[31-0] <- TEMP5[95-0] MOD2 11EDC6F41H\r\n   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n   DEST[63-32] <- 00000000H\r\nCRC32 instruction for 32-bit source operand and 32-bit destination operand:\r\n\r\n   TEMP1[31-0] <- BIT_REFLECT32 (SRC[31-0])\r\n   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n   TEMP3[63-0] <- TEMP1[31-0] << 32\r\n   TEMP4[63-0] <- TEMP2[31-0] << 32\r\n   TEMP5[63-0] <- TEMP3[63-0] XOR TEMP4[63-0]\r\n   TEMP6[31-0] <- TEMP5[63-0] MOD2 11EDC6F41H\r\n   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\nCRC32 instruction for 16-bit source operand and 32-bit destination operand:\r\n\r\n   TEMP1[15-0] <- BIT_REFLECT16 (SRC[15-0])\r\n   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n   TEMP3[47-0] <- TEMP1[15-0] << 32\r\n   TEMP4[47-0] <- TEMP2[31-0] << 16\r\n   TEMP5[47-0] <- TEMP3[47-0] XOR TEMP4[47-0]\r\n   TEMP6[31-0] <- TEMP5[47-0] MOD2 11EDC6F41H\r\n   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\nCRC32 instruction for 8-bit source operand and 64-bit destination operand:\r\n\r\n   TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])\r\n   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n   TEMP3[39-0] <- TEMP1[7-0] << 32\r\n   TEMP4[39-0] <- TEMP2[31-0] << 8\r\n   TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]\r\n   TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H\r\n   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n   DEST[63-32] <- 00000000H\r\nCRC32 instruction for 8-bit source operand and 32-bit destination operand:\r\n\r\n   TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])\r\n   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n   TEMP3[39-0] <- TEMP1[7-0] << 32\r\n   TEMP4[39-0] <- TEMP2[31-0] << 8\r\n   TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]\r\n   TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H\r\n   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )\r\nunsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )\r\nunsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )\r\nunsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )\r\n\r\nSIMD Floating Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code)       For a page fault.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n                       If LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0)                 If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n                       If LOCK prefix is used.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0)                 If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code)       For a page fault.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n                       If LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code)       For a page fault.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n                       If LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CRC32"
    }, 
    {
      "description": "CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point\r\nValues\r\n Opcode/                            Op /    64/32         CPUID          Description\r\n Instruction                        En      bit Mode      Feature\r\n                                            Support       Flag\r\n F3 0F E6 /r                        RM      V/V           SSE2           Convert two packed signed doubleword integers from\r\n CVTDQ2PD xmm1, xmm2/m64                                                 xmm2/mem to two packed double-precision floating-\r\n                                                                         point values in xmm1.\r\n VEX.128.F3.0F.WIG E6 /r            RM      V/V           AVX            Convert two packed signed doubleword integers from\r\n VCVTDQ2PD xmm1, xmm2/m64                                                xmm2/mem to two packed double-precision floating-\r\n                                                                         point values in xmm1.\r\n VEX.256.F3.0F.WIG E6 /r            RM      V/V           AVX            Convert four packed signed doubleword integers from\r\n VCVTDQ2PD ymm1, xmm2/m128                                               xmm2/mem to four packed double-precision floating-\r\n                                                                         point values in ymm1.\r\n EVEX.128.F3.0F.W0 E6 /r            HV      V/V           AVX512VL       Convert 2 packed signed doubleword integers from\r\n VCVTDQ2PD xmm1 {k1}{z},                                  AVX512F        xmm2/m128/m32bcst to eight packed double-precision\r\n xmm2/m128/m32bcst                                                       floating-point values in xmm1 with writemask k1.\r\n EVEX.256.F3.0F.W0 E6 /r            HV      V/V           AVX512VL       Convert 4 packed signed doubleword integers from\r\n VCVTDQ2PD ymm1 {k1}{z},                                  AVX512F        xmm2/m128/m32bcst to 4 packed double-precision\r\n xmm2/m128/m32bcst                                                       floating-point values in ymm1 with writemask k1.\r\n EVEX.512.F3.0F.W0 E6 /r            HV      V/V           AVX512F        Convert eight packed signed doubleword integers from\r\n VCVTDQ2PD zmm1 {k1}{z},                                                 ymm2/m256/m32bcst to eight packed double-precision\r\n ymm2/m256/m32bcst                                                       floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n     Op/En            Operand 1                   Operand 2                     Operand 3                      Operand 4\r\n       RM           ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA\r\n       HV           ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA\r\n\r\nDescription\r\nConverts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,\r\nfour or eight packed double-precision floating-point values in the destination operand (the first operand).\r\nEVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit\r\nmemory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand\r\nis a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX\r\nembedded rounding is ignored.\r\nVEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a YMM register.\r\nVEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n                            SRC                                              X3         X2     X1        X0\r\n\r\n\r\n\r\n\r\n                            DEST        X3                     X2                  X1               X0\r\n\r\n\r\n\r\n                                      Figure 3-11. CVTDQ2PD (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTDQ2PD (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    k <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <-\r\n               Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTDQ2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 64\r\n   k <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+63:i] <-\r\n             Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\n                  ELSE\r\n                       DEST[i+63:i] <-\r\n             Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+63:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+63:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTDQ2PD (VEX.256 encoded version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[191:128] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])\r\nDEST[255:192] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTDQ2PD (VEX.128 encoded version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTDQ2PD (128-bit Legacy SSE version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);\r\nVCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);\r\nVCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);\r\nCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)\r\nCVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 5;\r\nEVEX-encoded instructions, see Exceptions Type E5.\r\n#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTDQ2PD"
    }, 
    {
      "description": "CVTDQ2PS-Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point\r\nValues\r\n Opcode                               Op /    64/32         CPUID          Description\r\n Instruction                          En      bit Mode      Feature\r\n                                              Support       Flag\r\n 0F 5B /r                             RM      V/V           SSE2           Convert four packed signed doubleword integers from\r\n CVTDQ2PS xmm1, xmm2/m128                                                  xmm2/mem to four packed single-precision floating-\r\n                                                                           point values in xmm1.\r\n VEX.128.0F.WIG 5B /r                 RM       V/V          AVX            Convert four packed signed doubleword integers from\r\n VCVTDQ2PS xmm1, xmm2/m128                                                 xmm2/mem to four packed single-precision floating-\r\n                                                                           point values in xmm1.\r\n VEX.256.0F.WIG 5B /r                 RM       V/V          AVX            Convert eight packed signed doubleword integers from\r\n VCVTDQ2PS ymm1, ymm2/m256                                                 ymm2/mem to eight packed single-precision floating-\r\n                                                                           point values in ymm1.\r\n EVEX.128.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert four packed signed doubleword integers from\r\n VCVTDQ2PS xmm1 {k1}{z},                                    AVX512F        xmm2/m128/m32bcst to four packed single-precision\r\n xmm2/m128/m32bcst                                                         floating-point values in xmm1with writemask k1.\r\n EVEX.256.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert eight packed signed doubleword integers from\r\n VCVTDQ2PS ymm1 {k1}{z},                                    AVX512F        ymm2/m256/m32bcst to eight packed single-precision\r\n ymm2/m256/m32bcst                                                         floating-point values in ymm1with writemask k1.\r\n EVEX.512.0F.W0 5B /r                 FV      V/V           AVX512F        Convert sixteen packed signed doubleword integers\r\n VCVTDQ2PS zmm1 {k1}{z},                                                   from zmm2/m512/m32bcst to sixteen packed single-\r\n zmm2/m512/m32bcst{er}                                                     precision floating-point values in zmm1with writemask\r\n                                                                           k1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n       Op/En            Operand 1                    Operand 2                    Operand 3                      Operand 4\r\n        RM            ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA\r\n        FV            ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen\r\npacked single-precision floating-point values in the destination operand.\r\nEVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmod-\r\nified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTDQ2PS (EVEX encoded versions) when SRC operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);              ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\n    ELSE\r\n         SET_RM(MXCSR.RM);             ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN DEST[i+31:i] <-\r\n             Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <-j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <-\r\n             Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\n                  ELSE\r\n                       DEST[i+31:i] <-\r\n             Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTDQ2PS (VEX.256 encoded version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)\r\nDEST[159:128] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])\r\nDEST[191:160] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])\r\nDEST[223:192] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])\r\nDEST[255:224] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTDQ2PS (VEX.128 encoded version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTDQ2PS (128-bit Legacy SSE version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);\r\nVCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);\r\nVCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);\r\nVCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);\r\nVCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);\r\nVCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);\r\nVCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);\r\nVCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);\r\nVCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);\r\nVCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);\r\nCVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)\r\nCVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTDQ2PS"
    }, 
    {
      "description": "CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values to Packed Doubleword\r\nIntegers\r\n Opcode                                      Op /    64/32         CPUID         Description\r\n Instruction                                 En      bit Mode      Feature\r\n                                                     Support       Flag\r\n F2 0F E6 /r                                 RM      V/V           SSE2          Convert two packed double-precision floating-point\r\n CVTPD2DQ xmm1, xmm2/m128                                                        values in xmm2/mem to two signed doubleword\r\n                                                                                 integers in xmm1.\r\n VEX.128.F2.0F.WIG E6 /r                     RM      V/V           AVX           Convert two packed double-precision floating-point\r\n VCVTPD2DQ xmm1, xmm2/m128                                                       values in xmm2/mem to two signed doubleword\r\n                                                                                 integers in xmm1.\r\n VEX.256.F2.0F.WIG E6 /r                     RM      V/V           AVX           Convert four packed double-precision floating-point\r\n VCVTPD2DQ xmm1, ymm2/m256                                                       values in ymm2/mem to four signed doubleword\r\n                                                                                 integers in xmm1.\r\n EVEX.128.F2.0F.W1 E6 /r                     FV      V/V           AVX512VL      Convert two packed double-precision floating-point\r\n VCVTPD2DQ xmm1 {k1}{z},                                           AVX512F       values in xmm2/m128/m64bcst to two signed\r\n xmm2/m128/m64bcst                                                               doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.256.F2.0F.W1 E6 /r                     FV      V/V           AVX512VL      Convert four packed double-precision floating-point\r\n VCVTPD2DQ xmm1 {k1}{z},                                           AVX512F       values in ymm2/m256/m64bcst to four signed\r\n ymm2/m256/m64bcst                                                               doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.512.F2.0F.W1 E6 /r                     FV      V/V           AVX512F       Convert eight packed double-precision floating-point\r\n VCVTPD2DQ ymm1 {k1}{z},                                                         values in zmm2/m512/m64bcst to eight signed\r\n zmm2/m512/m64bcst{er}                                                           doubleword integers in ymm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n      Op/En                Operand 1                    Operand 2                      Operand 3                  Operand 4\r\n       RM                ModRM:reg (w)                ModRM:r/m (r)                        NA                        NA\r\n        FV               ModRM:reg (w)                ModRM:r/m (r)                        NA                        NA\r\n\r\nDescription\r\nConverts packed double-precision floating-point values in the source operand (second operand) to packed signed\r\ndoubleword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit\r\nvector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-\r\ntionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are\r\nzeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits\r\n(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n                SRC        X3                   X2                   X1                  X0\r\n\r\n\r\n\r\n\r\n                DEST                   0                      X3          X2       X1         X0\r\n\r\n\r\n\r\n                                 Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPD2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   k <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN DEST[i+31:i] <-\r\n             Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPD2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    k <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1)\r\n                    THEN\r\n                         DEST[i+31:i] <-\r\n               Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\n                    ELSE\r\n                         DEST[i+31:i] <-\r\n               Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTPD2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])\r\nDEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVCVTPD2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[MAX_VL-1:64]<-0\r\n\r\nCVTPD2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);\r\nVCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);\r\nVCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);\r\nVCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);\r\nVCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);\r\nVCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);\r\nVCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)\r\nCVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                  If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPD2DQ"
    }, 
    {
      "description": "CVTPD2PI-Convert Packed Double-Precision FP Values to Packed Dword Integers\r\nOpcode/                                                  Op/    64-Bit        Compat/ Description\r\nInstruction                                              En     Mode          Leg Mode\r\n66 0F 2D /r                                              RM     Valid         Valid     Convert two packed double-precision floating-\r\nCVTPD2PI mm, xmm/m128                                                                   point values from xmm/m128 to two packed\r\n                                                                                        signed doubleword integers in mm.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En               Operand 1                        Operand 2                     Operand 3                   Operand 4\r\n    RM               ModRM:reg (w)                    ModRM:r/m (r)                      NA                          NA\r\n\r\nDescription\r\nConverts two packed double-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand).\r\nThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-\r\nnology register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid\r\nexception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);\r\nDEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPD1PI:      __m64 _mm_cvtpd_pi32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision.\r\n\r\nOther Exceptions\r\nSee Table 22-4, \"Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-\r\nment,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPD2PI"
    }, 
    {
      "description": "CVTPD2PS-Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision\r\nFloating-Point Values\r\n Opcode/                                  Op /     64/32        CPUID          Description\r\n Instruction                              En       bit Mode     Feature\r\n                                                   Support      Flag\r\n 66 0F 5A /r                              RM       V/V          SSE2           Convert two packed double-precision floating-point\r\n CVTPD2PS xmm1, xmm2/m128                                                      values in xmm2/mem to two single-precision\r\n                                                                               floating-point values in xmm1.\r\n VEX.128.66.0F.WIG 5A /r                  RM       V/V          AVX            Convert two packed double-precision floating-point\r\n VCVTPD2PS xmm1, xmm2/m128                                                     values in xmm2/mem to two single-precision\r\n                                                                               floating-point values in xmm1.\r\n VEX.256.66.0F.WIG 5A /r                  RM       V/V          AVX            Convert four packed double-precision floating-point\r\n VCVTPD2PS xmm1, ymm2/m256                                                     values in ymm2/mem to four single-precision\r\n                                                                               floating-point values in xmm1.\r\n EVEX.128.66.0F.W1 5A /r                  FV       V/V          AVX512VL       Convert two packed double-precision floating-point\r\n VCVTPD2PS xmm1 {k1}{z},                                        AVX512F        values in xmm2/m128/m64bcst to two single-\r\n xmm2/m128/m64bcst                                                             precision floating-point values in xmm1with\r\n                                                                               writemask k1.\r\n EVEX.256.66.0F.W1 5A /r                  FV       V/V          AVX512VL       Convert four packed double-precision floating-point\r\n VCVTPD2PS xmm1 {k1}{z},                                        AVX512F        values in ymm2/m256/m64bcst to four single-\r\n ymm2/m256/m64bcst                                                             precision floating-point values in xmm1with\r\n                                                                               writemask k1.\r\n EVEX.512.66.0F.W1 5A /r                  FV       V/V          AVX512F        Convert eight packed double-precision floating-point\r\n VCVTPD2PS ymm1 {k1}{z},                                                       values in zmm2/m512/m64bcst to eight single-\r\n zmm2/m512/m64bcst{er}                                                         precision floating-point values in ymm1with\r\n                                                                               writemask k1.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En             Operand 1                        Operand 2                    Operand 3                      Operand 4\r\n       RM             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA\r\n       FV             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA\r\n\r\nDescription\r\nConverts two, four or eight packed double-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed single-precision floating-point values in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or\r\na 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a\r\nYMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-\r\n1:256/128/64) of the corresponding destination are zeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits\r\n(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n                   SRC         X3                      X2                   X1                   X0\r\n\r\n\r\n\r\n\r\n                   DEST                      0                        X3         X2       X1          X0\r\n\r\n\r\n\r\n                                      Figure 3-13. VCVTPD2PS (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPD2PS (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   k <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPD2PS (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   k <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <-Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])\r\n                  ELSE\r\n                       DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTPD2PS (VEX.256 encoded version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[95:64] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])\r\nDEST[127:96] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTPD2PS (VEX.128 encoded version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nCVTPD2PS (128-bit Legacy SSE version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[127:64] <- 0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);\r\nVCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);\r\nVCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);\r\nVCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);\r\nVCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);\r\nVCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);\r\nVCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);\r\nVCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);\r\nVCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);\r\nVCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)\r\nCVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Underflow, Overflow, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                       If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPD2PS"
    }, 
    {
      "description": "CVTPI2PD-Convert Packed Dword Integers to Packed Double-Precision FP Values\r\nOpcode/                                                 Op/    64-Bit       Compat/ Description\r\nInstruction                                             En     Mode         Leg Mode\r\n66 0F 2A /r                                             RM     Valid        Valid       Convert two packed signed doubleword\r\nCVTPI2PD xmm, mm/m64*                                                                   integers from mm/mem64 to two packed\r\n                                                                                        double-precision floating-point values in xmm.\r\nNOTES:\r\n*Operation is different for different operand sets; see the Description section.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n    Op/En             Operand 1                      Operand 2                      Operand 3                      Operand 4\r\n     RM             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA\r\n\r\nDescription\r\nConverts two packed signed doubleword integers in the source operand (second operand) to two packed double-\r\nprecision floating-point values in the destination operand (first operand).\r\nThe source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an\r\nXMM register. In addition, depending on the operand configuration:\r\n.    For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that\r\n     is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this\r\n     instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before\r\n     the CVTPI2PD instruction is executed.\r\n.    For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take\r\n     x87 FPU exceptions.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPI2PD:       __m128d _mm_cvtpi32_pd(__m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Table 22-6, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception,\" in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPI2PD"
    }, 
    {
      "description": "CVTPI2PS-Convert Packed Dword Integers to Packed Single-Precision FP Values\r\nOpcode/                                                    Op/    64-Bit      Compat/ Description\r\nInstruction                                                En     Mode        Leg Mode\r\n0F 2A /r                                                   RM     Valid       Valid       Convert two signed doubleword integers\r\nCVTPI2PS xmm, mm/m64                                                                      from mm/m64 to two single-precision\r\n                                                                                          floating-point values in xmm.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n   Op/En              Operand 1                       Operand 2                       Operand 3                  Operand 4\r\n    RM              ModRM:reg (w)                   ModRM:r/m (r)                        NA                          NA\r\n\r\nDescription\r\nConverts two packed signed doubleword integers in the source operand (second operand) to two packed single-\r\nprecision floating-point values in the destination operand (first operand).\r\nThe source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an\r\nXMM register. The results are stored in the low quadword of the destination operand, and the high quadword\r\nremains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control\r\nbits in the MXCSR register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);\r\n(* High quadword of destination unchanged *)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPI2PS:      __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPI2PS"
    }, 
    {
      "description": "CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values to Packed Signed\r\nDoubleword Integer Values\r\n Opcode/                              Op /   64/32       CPUID          Description\r\n Instruction                          En     bit Mode    Feature\r\n                                             Support     Flag\r\n 66 0F 5B /r                          RM     V/V         SSE2           Convert four packed single-precision floating-point values\r\n CVTPS2DQ xmm1, xmm2/m128                                               from xmm2/mem to four packed signed doubleword\r\n                                                                        values in xmm1.\r\n VEX.128.66.0F.WIG 5B /r              RM     V/V         AVX            Convert four packed single-precision floating-point values\r\n VCVTPS2DQ xmm1, xmm2/m128                                              from xmm2/mem to four packed signed doubleword\r\n                                                                        values in xmm1.\r\n VEX.256.66.0F.WIG 5B /r              RM     V/V         AVX            Convert eight packed single-precision floating-point values\r\n VCVTPS2DQ ymm1, ymm2/m256                                              from ymm2/mem to eight packed signed doubleword\r\n                                                                        values in ymm1.\r\n EVEX.128.66.0F.W0 5B /r              FV     V/V         AVX512VL       Convert four packed single precision floating-point values\r\n VCVTPS2DQ xmm1 {k1}{z},                                 AVX512F        from xmm2/m128/m32bcst to four packed signed\r\n xmm2/m128/m32bcst                                                      doubleword values in xmm1 subject to writemask k1.\r\n EVEX.256.66.0F.W0 5B /r              FV     V/V         AVX512VL       Convert eight packed single precision floating-point values\r\n VCVTPS2DQ ymm1 {k1}{z},                                 AVX512F        from ymm2/m256/m32bcst to eight packed signed\r\n ymm2/m256/m32bcst                                                      doubleword values in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F.W0 5B /r              FV     V/V         AVX512F        Convert sixteen packed single-precision floating-point\r\n VCVTPS2DQ zmm1 {k1}{z},                                                values from zmm2/m512/m32bcst to sixteen packed\r\n zmm2/m512/m32bcst{er}                                                  signed doubleword values in zmm1 subject to writemask\r\n                                                                        k1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n     Op/En              Operand 1                   Operand 2                      Operand 3                     Operand 4\r\n       RM             ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA\r\n       FV             ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or\r\nsixteen signed doubleword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nEVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPS2DQ (encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO 15\r\n   i <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\n                  ELSE\r\n                       DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPS2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)\r\nDEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])\r\nDEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])\r\nDEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])\r\nDEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])\r\n\r\nVCVTPS2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTPS2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);\r\nVCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);\r\nVCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);\r\nVCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);\r\nVCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);\r\nVCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);\r\nVCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);\r\nVCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)\r\nCVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPS2DQ"
    }, 
    {
      "description": "CVTPS2PD-Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision\r\nFloating-Point Values\r\n Opcode/                                  Op /    64/32         CPUID           Description\r\n Instruction                              En      bit Mode      Feature\r\n                                                  Support       Flag\r\n 0F 5A /r                                 RM      V/V           SSE2            Convert two packed single-precision floating-point values in\r\n CVTPS2PD xmm1, xmm2/m64                                                        xmm2/m64 to two packed double-precision floating-point\r\n                                                                                values in xmm1.\r\n VEX.128.0F.WIG 5A /r                     RM      V/V           AVX             Convert two packed single-precision floating-point values in\r\n VCVTPS2PD xmm1, xmm2/m64                                                       xmm2/m64 to two packed double-precision floating-point\r\n                                                                                values in xmm1.\r\n VEX.256.0F.WIG 5A /r                     RM      V/V           AVX             Convert four packed single-precision floating-point values\r\n VCVTPS2PD ymm1, xmm2/m128                                                      in xmm2/m128 to four packed double-precision floating-\r\n                                                                                point values in ymm1.\r\n EVEX.128.0F.W0 5A /r                     HV      V/V           AVX512VL        Convert two packed single-precision floating-point values in\r\n VCVTPS2PD xmm1 {k1}{z},                                        AVX512F         xmm2/m64/m32bcst to packed double-precision floating-\r\n xmm2/m64/m32bcst                                                               point values in xmm1 with writemask k1.\r\n EVEX.256.0F.W0 5A /r                     HV      V/V           AVX512VL        Convert four packed single-precision floating-point values\r\n VCVTPS2PD ymm1 {k1}{z},                                                        in xmm2/m128/m32bcst to packed double-precision\r\n xmm2/m128/m32bcst                                                              floating-point values in ymm1 with writemask k1.\r\n EVEX.512.0F.W0 5A /r                     HV      V/V           AVX512F         Convert eight packed single-precision floating-point values\r\n VCVTPS2PD zmm1 {k1}{z},                                                        in ymm2/m256/b32bcst to eight packed double-precision\r\n ymm2/m256/m32bcst{sae}                                                         floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n      Op/En                 Operand 1                      Operand 2                      Operand 3                      Operand 4\r\n       RM                ModRM:reg (w)                   ModRM:r/m (r)                        NA                            NA\r\n       HV                ModRM:reg (w)                   ModRM:r/m (r)                        NA                            NA\r\n\r\nDescription\r\nConverts two, four or eight packed single-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed double-precision floating-point values in the destination operand (first operand).\r\nEVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory\r\nlocation or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a YMM register. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n                 SRC                                              X3         X2        X1         X0\r\n\r\n\r\n\r\n\r\n                 DEST       X3                     X2                   X1                   X0\r\n\r\n\r\n\r\n\r\n                                   Figure 3-14. CVTPS2PD (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPS2PD (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    k <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <-\r\n               Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 64\r\n   k <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+63:i] <-\r\n             Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\n                  ELSE\r\n                       DEST[i+63:i] <-\r\n             Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n             FI;\r\n        ELSE\r\n\r\n\r\n\r\n              IF *merging-masking*                ; merging-masking\r\n                   THEN *DEST[i+63:i] remains unchanged*\r\n                   ELSE                           ; zeroing-masking\r\n                       DEST[i+63:i] <- 0\r\n              FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2PD (VEX.256 encoded version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[191:128] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])\r\nDEST[255:192] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTPS2PD (VEX.128 encoded version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTPS2PD (128-bit Legacy SSE version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);\r\nVCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);\r\nVCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);\r\nVCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);\r\nVCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);\r\nVCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);\r\nVCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);\r\nVCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);\r\nVCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);\r\nVCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);\r\nVCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)\r\nCVTPS2PD __m128d _mm_cvtps_pd (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n#UD                       If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPS2PD"
    }, 
    {
      "description": "CVTPS2PI-Convert Packed Single-Precision FP Values to Packed Dword Integers\r\n Opcode/                                             Op/   64-Bit      Compat/ Description\r\n Instruction                                         En    Mode        Leg Mode\r\n 0F 2D /r                                            RM    Valid       Valid        Convert two packed single-precision floating-\r\n CVTPS2PI mm, xmm/m64                                                               point values from xmm/m64 to two packed\r\n                                                                                    signed doubleword integers in mm.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n  Op/En              Operand 1                    Operand 2                      Operand 3                      Operand 4\r\n    RM             ModRM:reg (w)                 ModRM:r/m (r)                       NA                             NA\r\n\r\nDescription\r\nConverts two packed single-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand).\r\nThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-\r\nnology register. When the source operand is an XMM register, the two single-precision floating-point values are\r\ncontained in the low quadword of the register. When a conversion is inexact, the value returned is rounded\r\naccording to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum\r\nsigned doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-\r\ninite integer value (80000000H) is returned.\r\nCVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer\r\nis set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-\r\npoint exception is pending, the exception is handled before the CVTPS2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nDEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPS2PI:       __m64 _mm_cvtps_pi32(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTPS2PI"
    }, 
    {
      "description": "CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer\r\n Opcode/                                     Op /    64/32         CPUID          Description\r\n Instruction                                 En      bit Mode      Feature\r\n                                                     Support       Flag\r\n F2 0F 2D /r                                 RM      V/V           SSE2           Convert one double-precision floating-point value from\r\n CVTSD2SI r32, xmm1/m64                                                           xmm1/m64 to one signed doubleword integer r32.\r\n F2 REX.W 0F 2D /r                           RM      V/N.E.        SSE2           Convert one double-precision floating-point value from\r\n CVTSD2SI r64, xmm1/m64                                                           xmm1/m64 to one signed quadword integer sign-\r\n                                                                                  extended into r64.\r\n VEX.128.F2.0F.W0 2D /r                      RM      V/V           AVX            Convert one double-precision floating-point value from\r\n VCVTSD2SI r32, xmm1/m64                                                          xmm1/m64 to one signed doubleword integer r32.\r\n VEX.128.F2.0F.W1 2D /r                      RM      V/N.E.1       AVX            Convert one double-precision floating-point value from\r\n VCVTSD2SI r64, xmm1/m64                                                          xmm1/m64 to one signed quadword integer sign-\r\n                                                                                  extended into r64.\r\n EVEX.LIG.F2.0F.W0 2D /r                     T1F     V/V           AVX512F        Convert one double-precision floating-point value from\r\n VCVTSD2SI r32, xmm1/m64{er}                                                      xmm1/m64 to one signed doubleword integer r32.\r\n EVEX.LIG.F2.0F.W1 2D /r                     T1F     V/N.E.1       AVX512F        Convert one double-precision floating-point value from\r\n VCVTSD2SI r64, xmm1/m64{er}                                                      xmm1/m64 to one signed quadword integer sign-\r\n                                                                                  extended into r64.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n       Op/En                  Operand 1                       Operand 2                   Operand 3                    Operand 4\r\n         RM                ModRM:reg (w)                   ModRM:r/m (r)                        NA                        NA\r\n        T1F                ModRM:reg (w)                   ModRM:r/m (r)                        NA                        NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit\r\nmemory location. The destination operand is a general-purpose register. When the source operand is an XMM\r\nregister, the double-precision floating-point value is contained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister.\r\nIf a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode\r\nwith REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000H) is returned.\r\nIf a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and\r\nREX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000_00000000H) is returned.\r\nLegacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSD2SI (EVEX encoded version)\r\nIF SRC *is register* AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode and OperandSize = 64\r\n    THEN      DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\n    ELSE      DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nFI\r\n\r\n(V)CVTSD2SI\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nELSE\r\n    DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSD2SI int _mm_cvtsd_i32(__m128d);\r\nVCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);\r\nVCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);\r\nVCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);\r\nCVTSD2SI __int64 _mm_cvtsd_si64(__m128d);\r\nCVTSD2SI int _mm_cvtsd_si32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSD2SI"
    }, 
    {
      "description": "CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision\r\nFloating-Point Value\r\n Opcode/                                      Op /     64/32         CPUID           Description\r\n Instruction                                  En       bit Mode      Feature\r\n                                                       Support       Flag\r\n F2 0F 5A /r                                  RM       V/V           SSE2            Convert one double-precision floating-point value in\r\n CVTSD2SS xmm1, xmm2/m64                                                             xmm2/m64 to one single-precision floating-point value\r\n                                                                                     in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5A /r                  RVM      V/V           AVX             Convert one double-precision floating-point value in\r\n VCVTSD2SS xmm1,xmm2,                                                                xmm3/m64 to one single-precision floating-point value\r\n xmm3/m64                                                                            and merge with high bits in xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 5A /r                  T1S      V/V           AVX512F         Convert one double-precision floating-point value in\r\n VCVTSD2SS xmm1 {k1}{z}, xmm2,                                                       xmm3/m64 to one single-precision floating-point value\r\n xmm3/m64{er}                                                                        and merge with high bits in xmm2 under writemask k1.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n      Op/En                  Operand 1                        Operand 2                       Operand 3                      Operand 4\r\n        RM                 ModRM:reg (w)                     ModRM:r/m (r)                         NA                           NA\r\n       RVM                 ModRM:reg (w)                       VEX.vvvv                     ModRM:r/m (r)                       NA\r\n       T1S                 ModRM:reg (w)                      EVEX.vvvv                     ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the \"convert-from\" source operand (the second operand in\r\nSSE2 version, otherwise the third operand) to a single-precision floating-point value in the destination operand.\r\nWhen the \"convert-from\" operand is an XMM register, the double-precision floating-point value is contained in the\r\nlow quadword of the register. The result is stored in the low doubleword of the destination operand. When the\r\nconversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.\r\n128-bit Legacy SSE version: The \"convert-from\" source operand (the second operand) is an XMM register or\r\nmemory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged. The destina-\r\ntion operand is an XMM register.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be an XMM\r\nregister or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of\r\nthe XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX encoded version: the converted result in written to the low doubleword element of the destination under the\r\nwritemask.\r\nSoftware should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSD2SS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                   THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSD2SS (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSD2SS (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);\r\n(* DEST[MAX_VL-1:32] Unmodified *)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);\r\nVCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);\r\nVCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);\r\nVCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);\r\nVCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);\r\nCVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSD2SS"
    }, 
    {
      "description": "CVTSI2SD-Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value\r\n Opcode/                                           Op /      64/32        CPUID        Description\r\n Instruction                                       En        bit Mode     Feature\r\n                                                             Support      Flag\r\n F2 0F 2A /r                                       RM        V/V          SSE2         Convert one signed doubleword integer from\r\n CVTSI2SD xmm1, r32/m32                                                                r32/m32 to one double-precision floating-point\r\n                                                                                       value in xmm1.\r\n F2 REX.W 0F 2A /r                                 RM        V/N.E.       SSE2         Convert one signed quadword integer from r/m64\r\n CVTSI2SD xmm1, r/m64                                                                  to one double-precision floating-point value in\r\n                                                                                       xmm1.\r\n VEX.NDS.128.F2.0F.W0 2A /r                        RVM       V/V          AVX          Convert one signed doubleword integer from\r\n VCVTSI2SD xmm1, xmm2, r/m32                                                           r/m32 to one double-precision floating-point\r\n                                                                                       value in xmm1.\r\n VEX.NDS.128.F2.0F.W1 2A /r                        RVM       V/N.E.1      AVX          Convert one signed quadword integer from r/m64\r\n VCVTSI2SD xmm1, xmm2, r/m64                                                           to one double-precision floating-point value in\r\n                                                                                       xmm1.\r\n EVEX.NDS.LIG.F2.0F.W0 2A /r                       T1S       V/V          AVX512F      Convert one signed doubleword integer from\r\n VCVTSI2SD xmm1, xmm2, r/m32                                                           r/m32 to one double-precision floating-point\r\n                                                                                       value in xmm1.\r\n EVEX.NDS.LIG.F2.0F.W1 2A /r                       T1S       V/N.E.1      AVX512F      Convert one signed quadword integer from r/m64\r\n VCVTSI2SD xmm1, xmm2, r/m64{er}                                                       to one double-precision floating-point value in\r\n                                                                                       xmm1.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n      Op/En                 Operand 1                      Operand 2                   Operand 3                    Operand 4\r\n        RM                ModRM:reg (w)                   ModRM:r/m (r)                    NA                          NA\r\n       RVM                ModRM:reg (w)                     VEX.vvvv                  ModRM:r/m (r)                    NA\r\n       T1S                ModRM:reg (w)                    EVEX.vvvv                  ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nConverts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the \"convert-from\"\r\nsource operand to a double-precision floating-point value in the destination operand. The result is stored in the low\r\nquadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the\r\nvalue returned is rounded according to the rounding control bits in the MXCSR register.\r\nThe second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and\r\ndestination operands are XMM registers.\r\n128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The \"convert-\r\nfrom\" source operand (the second operand) is a general-purpose register or memory location. The destination is\r\nan XMM register Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be a general-\r\npurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)\r\nof the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.\r\nSoftware should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSI2SD (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);\r\nELSE\r\n    DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSI2SD (VEX.128 encoded version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);\r\nELSE\r\n    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\nFI;\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSI2SD\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);\r\nVCVTSI2SD __m128d _mm_cvt_roundi32_sd(__m128d s, int a, int r);\r\nVCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);\r\nVCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);\r\nCVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);\r\nCVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3 if W1, else Type 5.\r\nEVEX-encoded instructions, see Exceptions Type E3NF if W1, else Type E10NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSI2SD"
    }, 
    {
      "description": "CVTSI2SS-Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value\r\n Opcode/                                         Op /     64/32         CPUID         Description\r\n Instruction                                     En       bit Mode      Feature\r\n                                                          Support       Flag\r\n F3 0F 2A /r                                     RM       V/V           SSE           Convert one signed doubleword integer from r/m32\r\n CVTSI2SS xmm1, r/m32                                                                 to one single-precision floating-point value in xmm1.\r\n F3 REX.W 0F 2A /r                               RM       V/N.E.        SSE           Convert one signed quadword integer from r/m64\r\n CVTSI2SS xmm1, r/m64                                                                 to one single-precision floating-point value in xmm1.\r\n VEX.NDS.128.F3.0F.W0 2A /r                      RVM      V/V           AVX           Convert one signed doubleword integer from r/m32\r\n VCVTSI2SS xmm1, xmm2, r/m32                                                          to one single-precision floating-point value in xmm1.\r\n VEX.NDS.128.F3.0F.W1 2A /r                      RVM      V/N.E.1       AVX           Convert one signed quadword integer from r/m64\r\n VCVTSI2SS xmm1, xmm2, r/m64                                                          to one single-precision floating-point value in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W0 2A /r                     T1S      V/V           AVX512F       Convert one signed doubleword integer from r/m32\r\n VCVTSI2SS xmm1, xmm2, r/m32{er}                                                      to one single-precision floating-point value in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W1 2A /r                     T1S      V/N.E.1       AVX512F       Convert one signed quadword integer from r/m64\r\n VCVTSI2SS xmm1, xmm2, r/m64{er}                                                      to one single-precision floating-point value in xmm1.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n       Op/En                 Operand 1                      Operand 2                    Operand 3                     Operand 4\r\n        RM                 ModRM:reg (w)                  ModRM:r/m (r)                      NA                            NA\r\n       RVM                 ModRM:reg (w)                     VEX.vvvv                  ModRM:r/m (r)                       NA\r\n        T1S                ModRM:reg (w)                    EVEX.vvvv                  ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nConverts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the \"convert-from\"\r\nsource operand to a single-precision floating-point value in the destination operand (first operand). The \"convert-\r\nfrom\" source operand can be a general-purpose register or a memory location. The destination operand is an XMM\r\nregister. The result is stored in the low doubleword of the destination operand, and the upper three doublewords\r\nare left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control\r\nbits in the MXCSR register or the embedded rounding control bits.\r\n128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input\r\nvalue. The \"convert-from\" source operand (the second operand) is a general-purpose register or memory location.\r\nBits (MAX_VL-1:32) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be a general-\r\npurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)\r\nof the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX encoded version: the converted result in written to the low doubleword element of the destination under the\r\nwritemask.\r\nSoftware should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSI2SS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n    DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSI2SS (VEX.128 encoded version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSI2SS (128-bit Legacy SSE version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);\r\nVCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);\r\nVCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);\r\nVCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);\r\nCVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);\r\nCVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSI2SS"
    }, 
    {
      "description": "CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision\r\nFloating-Point Value\r\n Opcode/                                      Op /    64/32          CPUID          Description\r\n Instruction                                  En      bit Mode       Feature\r\n                                                      Support        Flag\r\n F3 0F 5A /r                                  RM      V/V            SSE2           Convert one single-precision floating-point value in\r\n CVTSS2SD xmm1, xmm2/m32                                                            xmm2/m32 to one double-precision floating-point value\r\n                                                                                    in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5A /r                  RVM      V/V           AVX            Convert one single-precision floating-point value in\r\n VCVTSS2SD xmm1, xmm2,                                                              xmm3/m32 to one double-precision floating-point value\r\n xmm3/m32                                                                           and merge with high bits of xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 5A /r                  T1S     V/V            AVX512F        Convert one single-precision floating-point value in\r\n VCVTSS2SD xmm1 {k1}{z}, xmm2,                                                      xmm3/m32 to one double-precision floating-point value\r\n xmm3/m32{sae}                                                                      and merge with high bits of xmm2 under writemask k1.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n       Op/En                  Operand 1                       Operand 2                      Operand 3                      Operand 4\r\n        RM                  ModRM:reg (w)                    ModRM:r/m (r)                        NA                           NA\r\n        RVM                 ModRM:reg (w)                      VEX.vvvv                    ModRM:r/m (r)                       NA\r\n        T1S                 ModRM:reg (w)                     EVEX.vvvv                    ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the \"convert-from\" source operand to a double-precision\r\nfloating-point value in the destination operand. When the \"convert-from\" source operand is an XMM register, the\r\nsingle-precision floating-point value is contained in the low doubleword of the register. The result is stored in the\r\nlow quadword of the destination operand.\r\n128-bit Legacy SSE version: The \"convert-from\" source operand (the second operand) is an XMM register or\r\nmemory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destina-\r\ntion operand is an XMM register.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be an XMM\r\nregister or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of\r\nthe XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nSoftware should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVCVTSS2SD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[63:0] = 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTSS2SD (VEX.128 encoded version)\r\nDEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSS2SD (128-bit Legacy SSE version)\r\nDEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);\r\nVCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);\r\nVCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);\r\nVCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);\r\nVCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);\r\nCVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSS2SD"
    }, 
    {
      "description": "CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer\r\n Opcode/                                    Op /     64/32          CPUID         Description\r\n Instruction                                En       bit Mode       Feature\r\n                                                     Support        Flag\r\n F3 0F 2D /r                                RM       V/V            SSE           Convert one single-precision floating-point value from\r\n CVTSS2SI r32, xmm1/m32                                                           xmm1/m32 to one signed doubleword integer in r32.\r\n F3 REX.W 0F 2D /r                          RM       V/N.E.         SSE           Convert one single-precision floating-point value from\r\n CVTSS2SI r64, xmm1/m32                                                           xmm1/m32 to one signed quadword integer in r64.\r\n VEX.128.F3.0F.W0 2D /r                     RM       V/V            AVX           Convert one single-precision floating-point value from\r\n VCVTSS2SI r32, xmm1/m32                                                          xmm1/m32 to one signed doubleword integer in r32.\r\n VEX.128.F3.0F.W1 2D /r                     RM       V/N.E.1        AVX           Convert one single-precision floating-point value from\r\n VCVTSS2SI r64, xmm1/m32                                                          xmm1/m32 to one signed quadword integer in r64.\r\n EVEX.LIG.F3.0F.W0 2D /r                    T1F      V/V            AVX512F       Convert one single-precision floating-point value from\r\n VCVTSS2SI r32, xmm1/m32{er}                                                      xmm1/m32 to one signed doubleword integer in r32.\r\n EVEX.LIG.F3.0F.W1 2D /r                    T1F      V/N.E.1        AVX512F       Convert one single-precision floating-point value from\r\n VCVTSS2SI r64, xmm1/m32{er}                                                      xmm1/m32 to one signed quadword integer in r64.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n       Op/En                  Operand 1                        Operand 2                   Operand 3                    Operand 4\r\n        RM                  ModRM:reg (w)                     ModRM:r/m (r)                     NA                          NA\r\n        T1F                 ModRM:reg (w)                     ModRM:r/m (r)                     NA                          NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).\r\nThe source operand can be an XMM register or a memory location. The destination operand is a general-purpose\r\nregister. When the source operand is an XMM register, the single-precision floating-point value is contained in the\r\nlow doubleword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSS2SI (EVEX encoded version)\r\nIF (SRC *is register*) AND (EVEX.b = 1)\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nELSE\r\n    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nFI;\r\n\r\n(V)CVTSS2SI (Legacy and VEX.128 encoded version)\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nELSE\r\n    DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSS2SI int _mm_cvtss_i32( __m128 a);\r\nVCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);\r\nVCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);\r\nVCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD                   If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTSS2SI"
    }, 
    {
      "description": "CVTTPD2DQ-Convert with Truncation Packed Double-Precision Floating-Point Values to\r\nPacked Doubleword Integers\r\n Opcode/                                    Op /    64/32         CPUID          Description\r\n Instruction                                En      bit Mode      Feature\r\n                                                    Support       Flag\r\n 66 0F E6 /r                                RM      V/V           SSE2           Convert two packed double-precision floating-point\r\n CVTTPD2DQ xmm1, xmm2/m128                                                       values in xmm2/mem to two signed doubleword\r\n                                                                                 integers in xmm1 using truncation.\r\n VEX.128.66.0F.WIG E6 /r                    RM      V/V           AVX            Convert two packed double-precision floating-point\r\n VCVTTPD2DQ xmm1, xmm2/m128                                                      values in xmm2/mem to two signed doubleword\r\n                                                                                 integers in xmm1 using truncation.\r\n VEX.256.66.0F.WIG E6 /r                    RM      V/V           AVX            Convert four packed double-precision floating-point\r\n VCVTTPD2DQ xmm1, ymm2/m256                                                      values in ymm2/mem to four signed doubleword\r\n                                                                                 integers in xmm1 using truncation.\r\n EVEX.128.66.0F.W1 E6 /r                    FV      V/V           AVX512VL       Convert two packed double-precision floating-point\r\n VCVTTPD2DQ xmm1 {k1}{z},                                         AVX512F        values in xmm2/m128/m64bcst to two signed\r\n xmm2/m128/m64bcst                                                               doubleword integers in xmm1 using truncation subject\r\n                                                                                 to writemask k1.\r\n EVEX.256.66.0F.W1 E6 /r                    FV      V/V           AVX512VL       Convert four packed double-precision floating-point\r\n VCVTTPD2DQ xmm1 {k1}{z},                                         AVX512F        values in ymm2/m256/m64bcst to four signed\r\n ymm2/m256/m64bcst                                                               doubleword integers in xmm1 using truncation subject\r\n                                                                                 to writemask k1.\r\n EVEX.512.66.0F.W1 E6 /r                    FV      V/V           AVX512F        Convert eight packed double-precision floating-point\r\n VCVTTPD2DQ ymm1 {k1}{z},                                                        values in zmm2/m512/m64bcst to eight signed\r\n zmm2/m512/m64bcst{sae}                                                          doubleword integers in ymm1 using truncation subject\r\n                                                                                 to writemask k1.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n      Op/En                Operand 1                      Operand 2                    Operand 3                   Operand 4\r\n        RM               ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA\r\n        FV               ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA\r\n\r\nDescription\r\nConverts two, four or eight packed double-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed signed doubleword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or\r\na 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a\r\nYMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of\r\nthe corresponding destination are zeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n                SRC        X3                     X2                  X1                  X0\r\n\r\n\r\n\r\n\r\n                DEST                    0                       X3         X2       X1         X0\r\n\r\n\r\n\r\n\r\n                                 Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTTPD2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   k <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN DEST[i+31:i] <-\r\n             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPD2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   k <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <-\r\n             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\n                  ELSE\r\n                       DEST[i+31:i] <-\r\n             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTTPD2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])\r\nDEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVCVTTPD2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[MAX_VL-1:64]<-0\r\n\r\nCVTTPD2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);\r\nVCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);\r\nVCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);\r\nVCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);\r\nCVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                  If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTPD2DQ"
    }, 
    {
      "description": "CVTTPD2PI-Convert with Truncation Packed Double-Precision FP Values to Packed Dword\r\nIntegers\r\n Opcode/                                                  Op/   64-Bit       Compat/ Description\r\n Instruction                                              En    Mode         Leg Mode\r\n 66 0F 2C /r                                              RM    Valid        Valid        Convert two packer double-precision floating-\r\n CVTTPD2PI mm, xmm/m128                                                                   point values from xmm/m128 to two packed\r\n                                                                                          signed doubleword integers in mm using\r\n                                                                                          truncation.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En              Operand 1                        Operand 2                      Operand 3                     Operand 4\r\n    RM              ModRM:reg (w)                    ModRM:r/m (r)                        NA                           NA\r\n\r\nDescription\r\nConverts two packed double-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand). The source operand can be an XMM register\r\nor a 128-bit memory location. The destination operand is an MMX technology register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger\r\nthan the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);\r\nDEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32_\r\n               Truncate(SRC[127:64]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTTPD1PI:       __m64 _mm_cvttpd_pi32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Mode Exceptions\r\nSee Table 22-4, \"Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-\r\nment,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTPD2PI"
    }, 
    {
      "description": "CVTTPS2DQ-Convert with Truncation Packed Single-Precision Floating-Point Values to Packed\r\nSigned Doubleword Integer Values\r\n Opcode/                                 Op /    64/32         CPUID          Description\r\n Instruction                             En      bit Mode      Feature\r\n                                                 Support       Flag\r\n F3 0F 5B /r                             RM      V/V           SSE2           Convert four packed single-precision floating-point\r\n CVTTPS2DQ xmm1, xmm2/m128                                                    values from xmm2/mem to four packed signed\r\n                                                                              doubleword values in xmm1 using truncation.\r\n VEX.128.F3.0F.WIG 5B /r                 RM      V/V           AVX            Convert four packed single-precision floating-point\r\n VCVTTPS2DQ xmm1, xmm2/m128                                                   values from xmm2/mem to four packed signed\r\n                                                                              doubleword values in xmm1 using truncation.\r\n VEX.256.F3.0F.WIG 5B /r                 RM      V/V           AVX            Convert eight packed single-precision floating-point\r\n VCVTTPS2DQ ymm1, ymm2/m256                                                   values from ymm2/mem to eight packed signed\r\n                                                                              doubleword values in ymm1 using truncation.\r\n EVEX.128.F3.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert four packed single precision floating-point\r\n VCVTTPS2DQ xmm1 {k1}{z},                                      AVX512F        values from xmm2/m128/m32bcst to four packed\r\n xmm2/m128/m32bcst                                                            signed doubleword values in xmm1 using truncation\r\n                                                                              subject to writemask k1.\r\n EVEX.256.F3.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert eight packed single precision floating-point\r\n VCVTTPS2DQ ymm1 {k1}{z},                                      AVX512F        values from ymm2/m256/m32bcst to eight packed\r\n ymm2/m256/m32bcst                                                            signed doubleword values in ymm1 using truncation\r\n                                                                              subject to writemask k1.\r\n EVEX.512.F3.0F.W0 5B /r                 FV      V/V           AVX512F        Convert sixteen packed single-precision floating-point\r\n VCVTTPS2DQ zmm1 {k1}{z},                                                     values from zmm2/m512/m32bcst to sixteen packed\r\n zmm2/m512/m32bcst {sae}                                                      signed doubleword values in zmm1 using truncation\r\n                                                                              subject to writemask k1.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n     Op/En            Operand 1                     Operand 2                       Operand 3                       Operand 4\r\n      RM            ModRM:reg (w)                  ModRM:r/m (r)                        NA                              NA\r\n      FV            ModRM:reg (w)                  ModRM:r/m (r)                        NA                              NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or\r\nsixteen signed doubleword integers in the destination operand.\r\nWhen a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or\r\na 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTTPS2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTTPS2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO 15\r\n   i <- j * 32\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b = 1)\r\n                  THEN\r\n                       DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\n                  ELSE\r\n                       DEST[i+31:i] <-\r\n             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                ; merging-masking\r\n                  THEN *DEST[i+31:i] remains unchanged*\r\n                  ELSE                           ; zeroing-masking\r\n                       DEST[i+31:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTTPS2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)\r\nDEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])\r\nDEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])\r\nDEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])\r\nDEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])\r\n\r\n\r\n\r\nVCVTTPS2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTTPS2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);\r\nVCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);\r\nVCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);\r\nVCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)\r\nCVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2; additionally\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTPS2DQ"
    }, 
    {
      "description": "CVTTPS2PI-Convert with Truncation Packed Single-Precision FP Values to Packed Dword\r\nIntegers\r\n Opcode/                                                   Op/    64-Bit       Compat/ Description\r\n Instruction                                               En     Mode         Leg Mode\r\n 0F 2C /r                                                  RM     Valid        Valid       Convert two single-precision floating-point\r\n CVTTPS2PI mm, xmm/m64                                                                     values from xmm/m64 to two signed\r\n                                                                                           doubleword signed integers in mm using\r\n                                                                                           truncation.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n   Op/En              Operand 1                       Operand 2                        Operand 3                     Operand 4\r\n    RM              ModRM:reg (w)                   ModRM:r/m (r)                          NA                            NA\r\n\r\nDescription\r\nConverts two packed single-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand). The source operand can be an XMM register\r\nor a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is\r\nan XMM register, the two single-precision floating-point values are contained in the low quadword of the register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger\r\nthan the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nDEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTTPS2PI:        __m64 _mm_cvttps_pi32(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTPS2PI"
    }, 
    {
      "description": "CVTTSD2SI-Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed\r\nInteger\r\n Opcode/                              Op /    64/32         CPUID         Description\r\n Instruction                          En      bit Mode      Feature\r\n                                              Support       Flag\r\n F2 0F 2C /r                          RM      V/V           SSE2          Convert one double-precision floating-point value from\r\n CVTTSD2SI r32, xmm1/m64                                                  xmm1/m64 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n F2 REX.W 0F 2C /r                    RM      V/N.E.        SSE2          Convert one double-precision floating-point value from\r\n CVTTSD2SI r64, xmm1/m64                                                  xmm1/m64 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\n VEX.128.F2.0F.W0 2C /r               RM      V/V           AVX           Convert one double-precision floating-point value from\r\n VCVTTSD2SI r32, xmm1/m64                                                 xmm1/m64 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n VEX.128.F2.0F.W1 2C /r               T1F     V/N.E.1       AVX           Convert one double-precision floating-point value from\r\n VCVTTSD2SI r64, xmm1/m64                                                 xmm1/m64 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\n EVEX.LIG.F2.0F.W0 2C /r              T1F     V/V           AVX512F       Convert one double-precision floating-point value from\r\n VCVTTSD2SI r32, xmm1/m64{sae}                                            xmm1/m64 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n EVEX.LIG.F2.0F.W1 2C /r              T1F     V/N.E.1       AVX512F       Convert one double-precision floating-point value from\r\n VCVTTSD2SI r64, xmm1/m64{sae}                                            xmm1/m64 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n  sion is used.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n     Op/En            Operand 1                 Operand 2                       Operand 3                       Operand 4\r\n      RM            ModRM:reg (w)              ModRM:r/m (r)                        NA                              NA\r\n      T1F           ModRM:reg (w)              ModRM:r/m (r)                        NA                              NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).\r\nThe source operand can be an XMM register or a 64-bit memory location. The destination operand is a general\r\npurpose register. When the source operand is an XMM register, the double-precision floating-point value is\r\ncontained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister.\r\nIf a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode\r\nwith REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000H) is returned.\r\nIf a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and\r\nREX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000_00000000H) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nSoftware should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may\r\nencounter unpredictable behavior across different processor generations.\r\n\r\nOperation\r\n(V)CVTTSD2SI (All versions)\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);\r\nELSE\r\n    DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSD2SI int _mm_cvttsd_i32( __m128d a);\r\nVCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);\r\nVCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);\r\nVCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);\r\nCVTTSD2SI int _mm_cvttsd_si32( __m128d a);\r\nCVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD                       If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTSD2SI"
    }, 
    {
      "description": "CVTTSS2SI-Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer\r\n Opcode/                              Op /    64/32        CPUID          Description\r\n Instruction                          En      bit Mode     Feature\r\n                                              Support      Flag\r\n F3 0F 2C /r                          RM      V/V          SSE            Convert one single-precision floating-point value from\r\n CVTTSS2SI r32, xmm1/m32                                                  xmm1/m32 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n F3 REX.W 0F 2C /r                    RM      V/N.E.       SSE            Convert one single-precision floating-point value from\r\n CVTTSS2SI r64, xmm1/m32                                                  xmm1/m32 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\n VEX.128.F3.0F.W0 2C /r               RM      V/V          AVX            Convert one single-precision floating-point value from\r\n VCVTTSS2SI r32, xmm1/m32                                                 xmm1/m32 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n VEX.128.F3.0F.W1 2C /r               RM      V/N.E.1      AVX            Convert one single-precision floating-point value from\r\n VCVTTSS2SI r64, xmm1/m32                                                 xmm1/m32 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\n EVEX.LIG.F3.0F.W0 2C /r              T1F     V/V          AVX512F        Convert one single-precision floating-point value from\r\n VCVTTSS2SI r32, xmm1/m32{sae}                                            xmm1/m32 to one signed doubleword integer in r32\r\n                                                                          using truncation.\r\n EVEX.LIG.F3.0F.W1 2C /r              T1F     V/N.E.1      AVX512F        Convert one single-precision floating-point value from\r\n VCVTTSS2SI r64, xmm1/m32{sae}                                            xmm1/m32 to one signed quadword integer in r64\r\n                                                                          using truncation.\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n  sion is used.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n      Op/En             Operand 1                   Operand 2                     Operand 3                      Operand 4\r\n       RM             ModRM:reg (w)             ModRM:r/m (r)                         NA                             NA\r\n       T1F            ModRM:reg (w)             ModRM:r/m (r)                         NA                             NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword\r\ninteger (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The\r\nsource operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose\r\nregister. When the source operand is an XMM register, the single-precision floating-point value is contained in the\r\nlow doubleword of the register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,\r\nthe indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may\r\nencounter unpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n(V)CVTTSS2SI (All versions)\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nELSE\r\n    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSS2SI int _mm_cvttss_i32( __m128 a);\r\nVCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);\r\nVCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);\r\nVCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);\r\nCVTTSS2SI int _mm_cvttss_si32( __m128 a);\r\nCVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Exceptions Type 3; additionally\r\n#UD                       If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CVTTSS2SI"
    }, 
    {
      "description": "CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword\r\nOpcode                    Instruction                 Op/    64-Bit     Compat/ Description\r\n                                                      En     Mode       Leg Mode\r\n99                        CWD                         NP     Valid      Valid       DX:AX <- sign-extend of AX.\r\n99                        CDQ                         NP     Valid      Valid       EDX:EAX <- sign-extend of EAX.\r\nREX.W + 99                CQO                         NP     Valid      N.E.        RDX:RAX<- sign-extend of RAX.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n     Op/En             Operand 1                     Operand 2                   Operand 3                    Operand 4\r\n      NP                  NA                            NA                           NA                          NA\r\n\r\nDescription\r\nDoubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign\r\nextension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction\r\ncopies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction\r\ncopies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-\r\ntion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position\r\nin the RDX register.\r\nThe CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ\r\ninstruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO\r\ninstruction can be used to produce a double quadword dividend from a quadword before a quadword division.\r\nThe CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the\r\noperand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers\r\nmay force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these\r\nmnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the\r\nsize of values to be converted, regardless of the mnemonic used.\r\nIn 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same\r\nopcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\n\r\nIF OperandSize = 16 (* CWD instruction *)\r\n    THEN\r\n        DX <- SignExtend(AX);\r\n    ELSE IF OperandSize = 32 (* CDQ instruction *)\r\n        EDX <- SignExtend(EAX); FI;\r\n    ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)\r\n        RDX <- SignExtend(RAX); FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nExceptions (All Operating Modes)\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "CWD"
    }, 
    {
      "description": "-R:CBW", 
      "mnem": "CWDE"
    }, 
    {
      "description": "DAA-Decimal Adjust AL after Addition\r\n Opcode                     Instruction                Op/     64-Bit    Compat/ Description\r\n                                                       En      Mode      Leg Mode\r\n 27                         DAA                        NP      Invalid   Valid     Decimal adjust AL after addition.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En              Operand 1                    Operand 2                  Operand 3                    Operand 4\r\n       NP                    NA                           NA                        NA                            NA\r\n\r\nDescription\r\nAdjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and\r\ndestination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-\r\ntion) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts\r\nthe contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the\r\nCF and AF flags are set accordingly.\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         old_AL <- AL;\r\n         old_CF <- CF;\r\n         CF <- 0;\r\n         IF (((AL AND 0FH) > 9) or AF = 1)\r\n                THEN\r\n                    AL <- AL + 6;\r\n                    CF <- old_CF or (Carry from AL <- AL + 6);\r\n                    AF <- 1;\r\n                ELSE\r\n                    AF <- 0;\r\n         FI;\r\n         IF ((old_AL > 99H) or (old_CF = 1))\r\n               THEN\r\n                    AL <- AL + 60H;\r\n                    CF <- 1;\r\n               ELSE\r\n                    CF <- 0;\r\n         FI;\r\nFI;\r\n\r\nExample\r\nADD      AL, BL   Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX\r\n                  After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000\r\nDAA               Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000\r\n                  After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111\r\nDAA               Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000\r\n                  After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101\r\n\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see\r\nthe \"Operation\" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                  If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                  If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD                  If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                  If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DAA"
    }, 
    {
      "description": "DAS-Decimal Adjust AL after Subtraction\r\n Opcode                     Instruction               Op/      64-Bit    Compat/ Description\r\n                                                      En       Mode      Leg Mode\r\n 2F                         DAS                       NP       Invalid   Valid      Decimal adjust AL after subtraction.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n      Op/En             Operand 1                  Operand 2                     Operand 3                    Operand 4\r\n       NP                   NA                         NA                           NA                            NA\r\n\r\nDescription\r\nAdjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the\r\nimplied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that\r\nsubtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL\r\nregister. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD\r\nresult. If a decimal borrow is detected, the CF and AF flags are set accordingly.\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         #UD;\r\n    ELSE\r\n         old_AL <- AL;\r\n         old_CF <- CF;\r\n         CF <- 0;\r\n         IF (((AL AND 0FH) > 9) or AF = 1)\r\n               THEN\r\n                   AL <- AL - 6;\r\n                   CF <- old_CF or (Borrow from AL <- AL - 6);\r\n                   AF <- 1;\r\n               ELSE\r\n                   AF <- 0;\r\n         FI;\r\n         IF ((old_AL > 99H) or (old_CF = 1))\r\n                THEN\r\n                   AL <- AL - 60H;\r\n                   CF <- 1;\r\n         FI;\r\nFI;\r\n\r\nExample\r\nSUB      AL, BL   Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX\r\n                  After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111\r\nDAA               Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111\r\n                  After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111\r\n\r\nFlags Affected\r\nThe CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result\r\n(see the \"Operation\" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is unde-\r\nfined.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                 If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DAS"
    }, 
    {
      "description": "DEC-Decrement by 1\r\n Opcode                    Instruction                  Op/      64-Bit    Compat/ Description\r\n                                                        En       Mode      Leg Mode\r\n FE /1                     DEC r/m8                     M        Valid     Valid        Decrement r/m8 by 1.\r\n                                      *\r\n REX + FE /1               DEC r/m8                     M        Valid     N.E.         Decrement r/m8 by 1.\r\n FF /1                     DEC r/m16                    M        Valid     Valid        Decrement r/m16 by 1.\r\n FF /1                     DEC r/m32                    M        Valid     Valid        Decrement r/m32 by 1.\r\n REX.W + FF /1             DEC r/m64                    M        Valid     N.E.         Decrement r/m64 by 1.\r\n 48+rw                     DEC r16                      O        N.E.      Valid        Decrement r16 by 1.\r\n 48+rd                     DEC r32                      O        N.E.      Valid        Decrement r32 by 1.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n    Op/En               Operand 1                       Operand 2                     Operand 3                    Operand 4\r\n         M           ModRM:r/m (r, w)                       NA                            NA                           NA\r\n         O           opcode + rd (r, w)                     NA                            NA                           NA\r\n\r\nDescription\r\nSubtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be\r\na register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.\r\n(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of\r\n1.)\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).\r\nOtherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to\r\nadditional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST - 1;\r\n\r\nFlags Affected\r\nThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the destination operand is located in a non-writable segment.\r\n                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DEC"
    }, 
    {
      "description": "DIV-Unsigned Divide\r\nOpcode                     Instruction                  Op/    64-Bit      Compat/ Description\r\n                                                        En     Mode        Leg Mode\r\nF6 /6                      DIV r/m8                     M      Valid       Valid       Unsigned divide AX by r/m8, with result\r\n                                                                                       stored in AL <- Quotient, AH <- Remainder.\r\nREX + F6 /6                DIV r/m8*                    M      Valid       N.E.        Unsigned divide AX by r/m8, with result\r\n                                                                                       stored in AL <- Quotient, AH <- Remainder.\r\nF7 /6                      DIV r/m16                    M      Valid       Valid       Unsigned divide DX:AX by r/m16, with result\r\n                                                                                       stored in AX <- Quotient, DX <- Remainder.\r\nF7 /6                      DIV r/m32                    M      Valid       Valid       Unsigned divide EDX:EAX by r/m32, with\r\n                                                                                       result stored in EAX <- Quotient, EDX <-\r\n                                                                                       Remainder.\r\nREX.W + F7 /6              DIV r/m64                    M      Valid       N.E.        Unsigned divide RDX:RAX by r/m64, with\r\n                                                                                       result stored in RAX <- Quotient, RDX <-\r\n                                                                                       Remainder.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En                Operand 1                   Operand 2                      Operand 3                      Operand 4\r\n     M                ModRM:r/m (w)                     NA                             NA                             NA\r\n\r\nDescription\r\nDivides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand\r\n(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can\r\nbe a general-purpose register or a memory location. The action of this instruction depends on the operand size\r\n(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.\r\nNon-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-\r\ntude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is\r\napplied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in\r\nRAX, the remainder in RDX.\r\nSee the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.\r\n                                                    Table 3-15. DIV Action\r\n                                                                                                                  Maximum\r\n Operand Size                          Dividend         Divisor         Quotient            Remainder             Quotient\r\n Word/byte                             AX               r/m8            AL                  AH                    255\r\n Doubleword/word                       DX:AX            r/m16           AX                  DX                    65,535\r\n Quadword/doubleword                   EDX:EAX          r/m32           EAX                 EDX                   232 - 1\r\n Doublequadword/                       RDX:RAX          r/m64           RAX                 RDX                   264 - 1\r\n quadword\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF SRC = 0\r\n    THEN #DE; FI; (* Divide Error *)\r\nIF OperandSize = 8 (* Word/Byte Operation *)\r\n    THEN\r\n        temp <- AX / SRC;\r\n        IF temp > FFH\r\n             THEN #DE; (* Divide error *)\r\n             ELSE\r\n                  AL <- temp;\r\n                  AH <- AX MOD SRC;\r\n        FI;\r\n    ELSE IF OperandSize = 16 (* Doubleword/word operation *)\r\n        THEN\r\n             temp <- DX:AX / SRC;\r\n             IF temp > FFFFH\r\n                  THEN #DE; (* Divide error *)\r\n             ELSE\r\n                  AX <- temp;\r\n                  DX <- DX:AX MOD SRC;\r\n             FI;\r\n        FI;\r\n    ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)\r\n        THEN\r\n             temp <- EDX:EAX / SRC;\r\n             IF temp > FFFFFFFFH\r\n                  THEN #DE; (* Divide error *)\r\n             ELSE\r\n                  EAX <- temp;\r\n                  EDX <- EDX:EAX MOD SRC;\r\n             FI;\r\n        FI;\r\n    ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)\r\n        THEN\r\n             temp <- RDX:RAX / SRC;\r\n             IF temp > FFFFFFFFFFFFFFFFH\r\n                  THEN #DE; (* Divide error *)\r\n             ELSE\r\n                  RAX <- temp;\r\n                  RDX <- RDX:RAX MOD SRC;\r\n             FI;\r\n        FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#DE                   If the source operand (divisor) is 0\r\n                      If the quotient is too large for the designated register.\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#DE                   If the source operand (divisor) is 0.\r\n                      If the quotient is too large for the designated register.\r\n#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#DE                   If the source operand (divisor) is 0.\r\n                      If the quotient is too large for the designated register.\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                   If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#DE                   If the source operand (divisor) is 0\r\n                      If the quotient is too large for the designated register.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DIV"
    }, 
    {
      "description": "DIVPD-Divide Packed Double-Precision Floating-Point Values\r\n Opcode/                              Op /   64/32        CPUID      Description\r\n Instruction                          En     bit Mode     Feature\r\n                                             Support      Flag\r\n 66 0F 5E /r                          RM     V/V          SSE2       Divide packed double-precision floating-point values\r\n DIVPD xmm1, xmm2/m128                                               in xmm1 by packed double-precision floating-point\r\n                                                                     values in xmm2/mem.\r\n VEX.NDS.128.66.0F.WIG 5E /r          RVM    V/V          AVX        Divide packed double-precision floating-point values\r\n VDIVPD xmm1, xmm2, xmm3/m128                                        in xmm2 by packed double-precision floating-point\r\n                                                                     values in xmm3/mem.\r\n VEX.NDS.256.66.0F.WIG 5E /r          RVM    V/V          AVX        Divide packed double-precision floating-point values\r\n VDIVPD ymm1, ymm2, ymm3/m256                                        in ymm2 by packed double-precision floating-point\r\n                                                                     values in ymm3/mem.\r\n EVEX.NDS.128.66.0F.W1 5E /r          FV     V/V          AVX512VL   Divide packed double-precision floating-point values\r\n VDIVPD xmm1 {k1}{z}, xmm2,                               AVX512F    in xmm2 by packed double-precision floating-point\r\n xmm3/m128/m64bcst                                                   values in xmm3/m128/m64bcst and write results to\r\n                                                                     xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5E /r          FV     V/V          AVX512VL   Divide packed double-precision floating-point values\r\n VDIVPD ymm1 {k1}{z}, ymm2,                               AVX512F    in ymm2 by packed double-precision floating-point\r\n ymm3/m256/m64bcst                                                   values in ymm3/m256/m64bcst and write results to\r\n                                                                     ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5E /r          FV     V/V          AVX512F    Divide packed double-precision floating-point values\r\n VDIVPD zmm1 {k1}{z}, zmm2,                                          in zmm2 by packed double-precision FP values in\r\n zmm3/m512/m64bcst{er}                                               zmm3/m512/m64bcst and write results to zmm1\r\n                                                                     subject to writemask k1.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n     Op/En            Operand 1               Operand 2                  Operand 3                       Operand 4\r\n      RM           ModRM:reg (r, w)          ModRM:r/m (r)                   NA                              NA\r\n     RVM            ModRM:reg (w)              VEX.vvvv                ModRM:r/m (r)                         NA\r\n      FV            ModRM:reg (w)             EVEX.vvvv                ModRM:r/m (r)                         NA\r\n\r\nDescription\r\nPerforms a SIMD divide of the double-precision floating-point values in the first source operand by the floating-\r\npoint values in the second source operand (the third operand). Results are written to the destination operand (the\r\nfirst operand).\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source\r\noperand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper\r\nbits (MAX_VL-1:256) of the corresponding destination are zeroed.\r\nVEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source\r\noperand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper\r\nbits (MAX_VL-1:128) of the corresponding destination are zeroed.\r\n128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-\r\nbit memory location. The destination is the same as the first source operand. The upper bits (MAX_VL-1:128) of the\r\ncorresponding destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);          ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- SRC1[i+63:i] / SRC2[63:0]\r\n                    ELSE\r\n                         DEST[i+63:i] <- SRC1[i+63:i] / SRC2[i+63:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                    ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                               ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVDIVPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[191:128] <-SRC1[191:128] / SRC2[191:128]\r\nDEST[255:192] <-SRC1[255:192] / SRC2[255:192]\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVDIVPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nDIVPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);\r\nVDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);\r\nVDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);\r\nVDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);\r\nDIVPD __m128d _mm_div_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DIVPD"
    }, 
    {
      "description": "DIVPS-Divide Packed Single-Precision Floating-Point Values\r\n Opcode/                                          Op /       64/32        CPUID      Description\r\n Instruction                                      En         bit Mode     Feature\r\n                                                             Support      Flag\r\n 0F 5E /r                                         RM         V/V          SSE        Divide packed single-precision floating-point values\r\n DIVPS xmm1, xmm2/m128                                                               in xmm1 by packed single-precision floating-point\r\n                                                                                     values in xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5E /r                         RVM        V/V          AVX        Divide packed single-precision floating-point values\r\n VDIVPS xmm1, xmm2, xmm3/m128                                                        in xmm2 by packed single-precision floating-point\r\n                                                                                     values in xmm3/mem.\r\n VEX.NDS.256.0F.WIG 5E /r                         RVM        V/V          AVX        Divide packed single-precision floating-point values\r\n VDIVPS ymm1, ymm2, ymm3/m256                                                        in ymm2 by packed single-precision floating-point\r\n                                                                                     values in ymm3/mem.\r\n EVEX.NDS.128.0F.W0 5E /r                         FV         V/V          AVX512VL   Divide packed single-precision floating-point values\r\n VDIVPS xmm1 {k1}{z}, xmm2,                                               AVX512F    in xmm2 by packed single-precision floating-point\r\n xmm3/m128/m32bcst                                                                   values in xmm3/m128/m32bcst and write results to\r\n                                                                                     xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5E /r                         FV         V/V          AVX512VL   Divide packed single-precision floating-point values\r\n VDIVPS ymm1 {k1}{z}, ymm2,                                               AVX512F    in ymm2 by packed single-precision floating-point\r\n ymm3/m256/m32bcst                                                                   values in ymm3/m256/m32bcst and write results to\r\n                                                                                     ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5E /r                         FV         V/V          AVX512F    Divide packed single-precision floating-point values\r\n VDIVPS zmm1 {k1}{z}, zmm2,                                                          in zmm2 by packed single-precision floating-point\r\n zmm3/m512/m32bcst{er}                                                               values in zmm3/m512/m32bcst and write results to\r\n                                                                                     zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                                       Instruction Operand Encoding\r\n      Op/En                 Operand 1                         Operand 2                  Operand 3                    Operand 4\r\n       RM               ModRM:reg (r, w)                     ModRM:r/m (r)                  NA                            NA\r\n      RVM                ModRM:reg (w)                         VEX.vvvv                ModRM:r/m (r)                      NA\r\n       FV                ModRM:reg (w)                        EVEX.vvvv                ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nPerforms a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the\r\nsecond source operand (the third operand). Results are written to the destination operand (the first operand).\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- SRC1[i+31:i] / SRC2[31:0]\r\n                    ELSE\r\n                         DEST[i+31:i] <- SRC1[i+31:i] / SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                            ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVDIVPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[159:128] <-SRC1[159:128] / SRC2[159:128]\r\nDEST[191:160]<-SRC1[191:160] / SRC2[191:160]\r\nDEST[223:192] <-SRC1[223:192] / SRC2[223:192]\r\nDEST[255:224] <-SRC1[255:224] / SRC2[255:224].\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVDIVPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nDIVPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);\r\nVDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);\r\nVDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);\r\nVDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);\r\nVDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);\r\nDIVPS __m128 _mm_div_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DIVPS"
    }, 
    {
      "description": "DIVSD-Divide Scalar Double-Precision Floating-Point Value\r\n Opcode/                                Op /     64/32        CPUID     Description\r\n Instruction                            En       bit Mode     Feature\r\n                                                 Support      Flag\r\n F2 0F 5E /r                            RM       V/V          SSE2      Divide low double-precision floating-point value in\r\n DIVSD xmm1, xmm2/m64                                                   xmm1 by low double-precision floating-point value\r\n                                                                        in xmm2/m64.\r\n VEX.NDS.128.F2.0F.WIG 5E /r            RVM      V/V          AVX       Divide low double-precision floating-point value in\r\n VDIVSD xmm1, xmm2, xmm3/m64                                            xmm2 by low double-precision floating-point value\r\n                                                                        in xmm3/m64.\r\n EVEX.NDS.LIG.F2.0F.W1 5E /r            T1S      V/V          AVX512F   Divide low double-precision floating-point value in\r\n VDIVSD xmm1 {k1}{z}, xmm2,                                             xmm2 by low double-precision floating-point value\r\n xmm3/m64{er}                                                           in xmm3/m64.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n     Op/En             Operand 1                  Operand 2                Operand 3                       Operand 4\r\n       RM           ModRM:reg (r, w)            ModRM:r/m (r)                  NA                              NA\r\n      RVM            ModRM:reg (w)                VEX.vvvv               ModRM:r/m (r)                         NA\r\n      T1S            ModRM:reg (w)               EVEX.vvvv               ModRM:r/m (r)                         NA\r\n\r\nDescription\r\nDivides the low double-precision floating-point value in the first source operand by the low double-precision\r\nfloating-point value in the second source operand, and stores the double-precision floating-point result in the desti-\r\nnation operand. The second source operand can be an XMM register or a 64-bit memory location. The first source\r\nand destination are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:64) of the corresponding ZMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits\r\n127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword\r\nelement of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low quadword element of the destination is updated according to the writemask.\r\nSoftware should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC1[63:0] / SRC2[63:0]\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVDIVSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nDIVSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] / SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);\r\nVDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nDIVSD __m128d _mm_div_sd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DIVSD"
    }, 
    {
      "description": "DIVSS-Divide Scalar Single-Precision Floating-Point Values\r\n Opcode/                                Op /     64/32         CPUID     Description\r\n Instruction                            En       bit Mode      Feature\r\n                                                 Support       Flag\r\n F3 0F 5E /r                            RM       V/V           SSE       Divide low single-precision floating-point value in\r\n DIVSS xmm1, xmm2/m32                                                    xmm1 by low single-precision floating-point value in\r\n                                                                         xmm2/m32.\r\n VEX.NDS.128.F3.0F.WIG 5E /r            RVM      V/V           AVX       Divide low single-precision floating-point value in\r\n VDIVSS xmm1, xmm2, xmm3/m32                                             xmm2 by low single-precision floating-point value in\r\n                                                                         xmm3/m32.\r\n EVEX.NDS.LIG.F3.0F.W0 5E /r            T1S      V/V           AVX512F   Divide low single-precision floating-point value in\r\n VDIVSS xmm1 {k1}{z}, xmm2,                                              xmm2 by low single-precision floating-point value in\r\n xmm3/m32{er}                                                            xmm3/m32.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n     Op/En             Operand 1                   Operand 2                Operand 3                        Operand 4\r\n      RM            ModRM:reg (r, w)             ModRM:r/m (r)                   NA                              NA\r\n      RVM            ModRM:reg (w)                 VEX.vvvv                ModRM:r/m (r)                         NA\r\n      T1S            ModRM:reg (w)                 EVEX.vvvv               ModRM:r/m (r)                         NA\r\n\r\nDescription\r\nDivides the low single-precision floating-point value in the first source operand by the low single-precision floating-\r\npoint value in the second source operand, and stores the single-precision floating-point result in the destination\r\noperand. The second source operand can be an XMM register or a 32-bit memory location.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order\r\ndoublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the\r\ndestination register are zeroed.\r\nEVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword\r\nelements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low doubleword element of the destination is updated according to the writemask.\r\nSoftware should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVSS (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC1[31:0] / SRC2[31:0]\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVDIVSS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nDIVSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] / SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);\r\nVDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);\r\nVDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nDIVSS __m128 _mm_div_ss(__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DIVSS"
    }, 
    {
      "description": "DPPD - Dot Product of Packed Double Precision Floating-Point Values\r\n Opcode/                                         Op/      64/32-bit CPUID        Description\r\n Instruction                                     En       Mode      Feature\r\n                                                                    Flag\r\n 66 0F 3A 41 /r ib                               RMI      V/V       SSE4_1       Selectively multiply packed DP floating-point\r\n DPPD xmm1, xmm2/m128, imm8                                                      values from xmm1 with packed DP floating-\r\n                                                                                 point values from xmm2, add and selectively\r\n                                                                                 store the packed DP floating-point values to\r\n                                                                                 xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 41 /r ib                RVMI V/V           AVX          Selectively multiply packed DP floating-point\r\n VDPPD xmm1,xmm2, xmm3/m128, imm8                                                values from xmm2 with packed DP floating-\r\n                                                                                 point values from xmm3, add and selectively\r\n                                                                                 store the packed DP floating-point values to\r\n                                                                                 xmm1.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n  Op/En               Operand 1            Operand 2                      Operand 3                         Operand 4\r\n   RMI           ModRM:reg (r, w)         ModRM:r/m (r)                     imm8                                NA\r\n   RVMI              ModRM:reg (w)         VEX.vvvv (r)                 ModRM:r/m (r)                          imm8\r\n\r\nDescription\r\nConditionally multiplies the packed double-precision floating-point values in the destination operand (first operand)\r\nwith the packed double-precision floating-point values in the source (second operand) depending on a mask\r\nextracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corre-\r\nsponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1.\r\nThe two resulting double-precision values are summed into an intermediate result. The intermediate result is\r\nconditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.\r\nIf a broadcast mask bit is \"1\", the intermediate result is copied to the corresponding qword element in the destina-\r\ntion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.\r\nDPPD follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do\r\nnot cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of\r\nthose NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-\r\nated NaNs will have at least one NaN propagated to the destination.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nIf VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDP_primitive (SRC1, SRC2)\r\nIF (imm8[4] = 1)\r\n     THEN Temp1[63:0] <- DEST[63:0] * SRC[63:0]; // update SIMD exception flags\r\n     ELSE Temp1[63:0] <- +0.0; FI;\r\nIF (imm8[5] = 1)\r\n     THEN Temp1[127:64] <- DEST[127:64] * SRC[127:64]; // update SIMD exception flags\r\n     ELSE Temp1[127:64] <- +0.0; FI;\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nTemp2[63:0] <- Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nIF (imm8[0] = 1)\r\n     THEN DEST[63:0] <- Temp2[63:0];\r\n     ELSE DEST[63:0] <- +0.0; FI;\r\nIF (imm8[1] = 1)\r\n     THEN DEST[127:64] <- Temp2[63:0];\r\n     ELSE DEST[127:64] <- +0.0; FI;\r\n\r\nDPPD (128-bit Legacy SSE version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVDPPD (VEX.128 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nDPPD:     __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\nExceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the\r\ndestination untouched.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\n#UD                       If VEX.L= 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DPPD"
    }, 
    {
      "description": "DPPS - Dot Product of Packed Single Precision Floating-Point Values\r\n Opcode/                                        Op/    64/32-bit CPUID         Description\r\n Instruction                                    En     Mode      Feature\r\n                                                                 Flag\r\n 66 0F 3A 40 /r ib                              RMI    V/V       SSE4_1        Selectively multiply packed SP floating-point\r\n DPPS xmm1, xmm2/m128, imm8                                                    values from xmm1 with packed SP floating-\r\n                                                                               point values from xmm2, add and selectively\r\n                                                                               store the packed SP floating-point values or\r\n                                                                               zero values to xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 40 /r ib               RVMI V/V         AVX           Multiply packed SP floating point values from\r\n VDPPS xmm1,xmm2, xmm3/m128, imm8                                              xmm1 with packed SP floating point values\r\n                                                                               from xmm2/mem selectively add and store to\r\n                                                                               xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 40 /r ib               RVMI V/V         AVX           Multiply packed single-precision floating-point\r\n VDPPS ymm1, ymm2, ymm3/m256, imm8                                             values from ymm2 with packed SP floating\r\n                                                                               point values from ymm3/mem, selectively add\r\n                                                                               pairs of elements and store to ymm1.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n   Op/En                Operand 1            Operand 2                   Operand 3                         Operand 4\r\n    RMI              ModRM:reg (r, w)       ModRM:r/m (r)                   imm8                               NA\r\n   RVMI              ModRM:reg (w)           VEX.vvvv (r)              ModRM:r/m (r)                          imm8\r\n\r\nDescription\r\nConditionally multiplies the packed single precision floating-point values in the destination operand (first operand)\r\nwith the packed single-precision floats in the source (second operand) depending on a mask extracted from the\r\nhigh 4 bits of the immediate byte (third operand). If a condition mask bit in Imm8[7:4] is zero, the corresponding\r\nmultiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 1.\r\nThe four resulting single-precision values are summed into an intermediate result. The intermediate result is condi-\r\ntionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.\r\nIf a broadcast mask bit is \"1\", the intermediate result is copied to the corresponding dword element in the destina-\r\ntion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.\r\nDPPS follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do\r\nnot cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of\r\nthose NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-\r\nated NaNs will have at least one NaN propagated to the destination.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDP_primitive (SRC1, SRC2)\r\nIF (imm8[4] = 1)\r\n     THEN Temp1[31:0] <- DEST[31:0] * SRC[31:0]; // update SIMD exception flags\r\n     ELSE Temp1[31:0] <- +0.0; FI;\r\nIF (imm8[5] = 1)\r\n     THEN Temp1[63:32] <- DEST[63:32] * SRC[63:32]; // update SIMD exception flags\r\n     ELSE Temp1[63:32] <- +0.0; FI;\r\nIF (imm8[6] = 1)\r\n     THEN Temp1[95:64] <- DEST[95:64] * SRC[95:64]; // update SIMD exception flags\r\n     ELSE Temp1[95:64] <- +0.0; FI;\r\nIF (imm8[7] = 1)\r\n     THEN Temp1[127:96] <- DEST[127:96] * SRC[127:96]; // update SIMD exception flags\r\n     ELSE Temp1[127:96] <- +0.0; FI;\r\n\r\nTemp2[31:0] <- Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\nTemp3[31:0] <- Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\nTemp4[31:0] <- Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nIF (imm8[0] = 1)\r\n     THEN DEST[31:0] <- Temp4[31:0];\r\n     ELSE DEST[31:0] <- +0.0; FI;\r\nIF (imm8[1] = 1)\r\n     THEN DEST[63:32] <- Temp4[31:0];\r\n     ELSE DEST[63:32] <- +0.0; FI;\r\nIF (imm8[2] = 1)\r\n     THEN DEST[95:64] <- Temp4[31:0];\r\n     ELSE DEST[95:64] <- +0.0; FI;\r\nIF (imm8[3] = 1)\r\n     THEN DEST[127:96] <- Temp4[31:0];\r\n     ELSE DEST[127:96] <- +0.0; FI;\r\n\r\nDPPS (128-bit Legacy SSE version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVDPPS (VEX.128 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVDPPS (VEX.256 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[255:128]<-DP_Primitive(SRC1[255:128], SRC2[255:128]);\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)DPPS:    __m128 _mm_dp_ps ( __m128 a, __m128 b, const int mask);\r\n\r\nVDPPS:      __m256 _mm256_dp_ps ( __m256 a, __m256 b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\nExceptions are determined separately for each add and multiply operation, in the order of their execution.\r\nUnmasked exceptions will leave the destination operands unchanged.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "DPPS"
    }, 
    {
      "description": "EMMS-Empty MMX Technology State\r\nOpcode                  Instruction                 Op/   64-Bit   Compat/ Description\r\n                                                    En    Mode     Leg Mode\r\n0F 77                   EMMS                        NP    Valid    Valid      Set the x87 FPU tag word to empty.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n    Op/En             Operand 1                  Operand 2                 Operand 3                  Operand 4\r\n      NP                 NA                          NA                       NA                         NA\r\n\r\nDescription\r\nSets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data\r\nregisters (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-\r\ntions. (See Figure 8-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the\r\nformat of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in\r\nx87 FPU tag word to valid (all 0s).\r\nThe EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures\r\nor subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.\r\nIf a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag\r\nword has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will\r\nresult in an x87 floating-point exception or incorrect result.\r\nEMMS operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nx87FPUTagWord <- FFFFH;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_empty()\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                   If CR0.EM[bit 2] = 1.\r\n#NM                   If CR0.TS[bit 3] = 1.\r\n#MF                   If there is a pending FPU exception.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n", 
      "mnem": "EMMS"
    }, 
    {
      "description": "ENTER-Make Stack Frame for Procedure Parameters\r\nOpcode                 Instruction              Op/      64-Bit   Compat/ Description\r\n                                                En       Mode     Leg Mode\r\nC8 iw 00               ENTER imm16, 0           II       Valid    Valid       Create a stack frame for a procedure.\r\nC8 iw 01               ENTER imm16,1            II       Valid    Valid       Create a stack frame with a nested pointer for\r\n                                                                              a procedure.\r\nC8 iw ib               ENTER imm16, imm8        II       Valid    Valid       Create a stack frame with nested pointers for\r\n                                                                              a procedure.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n    Op/En          Operand 1                 Operand 2                    Operand 3                     Operand 4\r\n      II              iw                       imm8                          NA                            NA\r\n\r\nDescription\r\nCreates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure.\r\nThe first operand (imm16) specifies the size of the dynamic storage in the stack frame (that is, the number of bytes\r\nof dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level\r\n(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in\r\nbytes of the storage space for frame pointers.\r\nThe nesting level determines the number of frame pointers that are copied into the \"display area\" of the new stack\r\nframe from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be\r\noverridden using the 66H prefix. Thus, the OperandSize attribute determines the size of each frame pointer that\r\nwill be copied into the stack frame and the data being transferred from SP/ESP/RSP register into the BP/EBP/RBP\r\nregister.\r\nThe ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER\r\ninstruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for\r\na procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to\r\nrelease the stack frame.\r\nIf the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP register onto the stack,\r\ncopies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the\r\nSP/ESP/RSP register with the current stack-pointer value minus the value in the size operand. For nesting levels of\r\n1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These\r\nadditional frame pointers provide the called procedure with access points to other nested frames on the stack. See\r\n\"Procedure Calls for Block-Structured Languages\" in Chapter 6 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1, for more information about the actions of the ENTER instruction.\r\nThe ENTER instruction causes a page fault whenever a write using the final value of the stack pointer (within the\r\ncurrent stack segment) would do so.\r\nIn 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot be encoded. Use of 66H prefix\r\nchanges frame pointer operand size to 16 bits.\r\nWhen the 66H prefix is used and causing the OperandSize attribute to be less than the StackAddrSize, software is\r\nresponsible for the following:\r\n.   The companion LEAVE instruction must also use the 66H prefix,\r\n.   The value in the RBP/EBP register prior to executing \"66H ENTER\" must be within the same 16KByte region of\r\n    the current stack pointer (RSP/ESP), such that the value of RBP/EBP after \"66H ENTER\" remains a valid address\r\n    in the stack. This ensures \"66H LEAVE\" can restore 16-bits of data from the stack.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nAllocSize <- imm16;\r\nNestingLevel <- imm8 MOD 32;\r\nIF (OperandSize = 64)\r\n    THEN\r\n         Push(RBP); (* RSP decrements by 8 *)\r\n         FrameTemp <- RSP;\r\n    ELSE IF OperandSize = 32\r\n         THEN\r\n             Push(EBP); (* (E)SP decrements by 4 *)\r\n             FrameTemp <- ESP; FI;\r\n    ELSE (* OperandSize = 16 *)\r\n             Push(BP); (* RSP or (E)SP decrements by 2 *)\r\n             FrameTemp <- SP;\r\nFI;\r\n\r\nIF NestingLevel = 0\r\n    THEN GOTO CONTINUE;\r\nFI;\r\n\r\nIF (NestingLevel > 1)\r\n    THEN FOR i <- 1 to (NestingLevel - 1)\r\n         DO\r\n             IF (OperandSize = 64)\r\n                  THEN\r\n                      RBP <- RBP - 8;\r\n                      Push([RBP]); (* Quadword push *)\r\n                  ELSE IF OperandSize = 32\r\n                      THEN\r\n                           IF StackSize = 32\r\n                                EBP <- EBP - 4;\r\n                                Push([EBP]); (* Doubleword push *)\r\n                           ELSE (* StackSize = 16 *)\r\n                                BP <- BP - 4;\r\n                                Push([BP]); (* Doubleword push *)\r\n                           FI;\r\n                      FI;\r\n                  ELSE (* OperandSize = 16 *)\r\n                      IF StackSize = 32\r\n                           THEN\r\n                                EBP <- EBP - 2;\r\n                                Push([EBP]); (* Word push *)\r\n                           ELSE (* StackSize = 16 *)\r\n                                BP <- BP - 2;\r\n                                Push([BP]); (* Word push *)\r\n                      FI;\r\n                  FI;\r\n    OD;\r\nFI;\r\n\r\nIF (OperandSize = 64) (* nestinglevel 1 *)\r\n    THEN\r\n        Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)\r\n    ELSE IF OperandSize = 32\r\n\r\n\r\n\r\n\r\n          THEN\r\n               Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)\r\n      ELSE (* OperandSize = 16 *)\r\n               Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)\r\nFI;\r\n\r\nCONTINUE:\r\nIF 64-Bit Mode (StackSize = 64)\r\n    THEN\r\n             RBP <- FrameTemp;\r\n             RSP <- RSP - AllocSize;\r\n    ELSE IF OperandSize = 32\r\n         THEN\r\n             EBP <- FrameTemp;\r\n             ESP <- ESP - AllocSize; FI;\r\n    ELSE (* OperandSize = 16 *)\r\n             BP <- FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)\r\n             SP <- SP - AllocSize;\r\nFI;\r\n\r\nEND;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#SS(0)                   If the new value of the SP or ESP register is outside the stack segment limit.\r\n#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n                         stack segment) would cause a page fault.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#SS                      If the new value of the SP or ESP register is outside the stack segment limit.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#SS(0)                   If the new value of the SP or ESP register is outside the stack segment limit.\r\n#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n                         stack segment) would cause a page fault.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                   If the stack address is in a non-canonical form.\r\n#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n                         stack segment) would cause a page fault.\r\n#UD                      If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ENTER"
    }, 
    {
      "description": "EXTRACTPS-Extract Packed Floating-Point Values\r\n Opcode/                                         Op /    64/32         CPUID     Description\r\n Instruction                                     En      bit Mode      Feature\r\n                                                         Support       Flag\r\n 66 0F 3A 17 /r ib                               RMI     VV            SSE4_1    Extract one single-precision floating-point value\r\n EXTRACTPS reg/m32, xmm1, imm8                                                   from xmm1 at the offset specified by imm8 and\r\n                                                                                 store the result in reg or m32. Zero extend the\r\n                                                                                 results in 64-bit register if applicable.\r\n VEX.128.66.0F3A.WIG 17 /r ib                    RMI     V/V           AVX       Extract one single-precision floating-point value\r\n VEXTRACTPS reg/m32, xmm1, imm8                                                  from xmm1 at the offset specified by imm8 and\r\n                                                                                 store the result in reg or m32. Zero extend the\r\n                                                                                 results in 64-bit register if applicable.\r\n EVEX.128.66.0F3A.WIG 17 /r ib                   T1S     V/V           AVX512F   Extract one single-precision floating-point value\r\n VEXTRACTPS reg/m32, xmm1, imm8                                                  from xmm1 at the offset specified by imm8 and\r\n                                                                                 store the result in reg or m32. Zero extend the\r\n                                                                                 results in 64-bit register if applicable.\r\n\r\n\r\n\r\n                                                       Instruction Operand Encoding\r\n        Op/En                  Operand 1                        Operand 2               Operand 3                   Operand 4\r\n         RMI                ModRM:r/m (w)                      ModRM:reg (r)              Imm8                          NA\r\n         T1S                ModRM:r/m (w)                      ModRM:reg (r)              Imm8                          NA\r\n\r\nDescription\r\nExtracts a single-precision floating-point value from the source operand (second operand) at the 32-bit offset spec-\r\nified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.\r\nThe extracted single-precision floating-point value is stored in the low 32-bits of the destination operand\r\nIn 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register\r\nare filled with zero. REX.W is ignored.\r\nVEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general\r\npurpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.\r\nVEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as\r\na destination operand, the packed single quantity is zero extended to 64 bits.\r\nThe source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the\r\n32-bit floating-point value.\r\nIf VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause\r\nan #UD exception.\r\n\r\nOperation\r\nVEXTRACTPS (EVEX and VEX.128 encoded version)\r\nSRC_OFFSET <- IMM8[1:0]\r\nIF (64-Bit Mode and DEST is register)\r\n    DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\n    DEST[63:32] <- 0\r\nELSE\r\n    DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nEXTRACTPS (128-bit Legacy SSE version)\r\nSRC_OFFSET <-IMM8[1:0]\r\nIF (64-Bit Mode and DEST is register)\r\n    DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\n    DEST[63:32] <-0\r\nELSE\r\n    DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nEXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 5; Additionally\r\nEVEX-encoded instructions, see Exceptions Type E9NF.\r\n#UD                   IF VEX.L = 0.\r\n#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "EXTRACTPS"
    }, 
    {
      "description": "F2XM1-Compute 2x-1\r\nOpcode                   Instruction              64-Bit      Compat/       Description\r\n                                                  Mode        Leg Mode\r\nD9 F0                    F2XM1                    Valid       Valid         Replace ST(0) with (2ST(0) - 1).\r\n\r\n\r\n\r\nDescription\r\nComputes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in\r\nregister ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range -1.0 to\r\n+1.0. If the source value is outside this range, the result is undefined.\r\nThe following table shows the results obtained when computing the exponential value of various classes of\r\nnumbers, assuming that neither overflow nor underflow occurs.\r\n                                         Table 3-16. Results Obtained from F2XM1\r\n                           ST(0) SRC                                                   ST(0) DEST\r\n                           - 1.0 to -0                                                 - 0.5 to - 0\r\n                               -0                                                           -0\r\n                               +0                                                           +0\r\n                           + 0 to +1.0                                                  + 0 to 1.0\r\n\r\nValues other than 2 can be exponentiated using the following formula:\r\n\r\n     xy <- 2(y * log2x)\r\n\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- (2ST(0) - 1);\r\n\r\nFPU Flags Affected\r\nC1                       Set to 0 if stack underflow occurred.\r\n                         Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3               Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                      Stack underflow occurred.\r\n#IA                      Source operand is an SNaN value or unsupported format.\r\n#D                       Source is a denormal value.\r\n#U                       Result is too small for destination format.\r\n#P                       Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                      CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "F2XM1"
    }, 
    {
      "description": "FABS-Absolute Value\r\n Opcode                 Instruction               64-Bit   Compat/    Description\r\n                                                  Mode     Leg Mode\r\n D9 E1                  FABS                      Valid    Valid      Replace ST with its absolute value.\r\n\r\n\r\n\r\nDescription\r\nClears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results\r\nobtained when creating the absolute value of various classes of numbers.\r\n\r\n                                        Table 3-17. Results Obtained from FABS\r\n                            ST(0) SRC                                                ST(0) DEST\r\n                               -inf                                                       +inf\r\n                               -F                                                         +F\r\n                               -0                                                         +0\r\n                               +0                                                         +0\r\n                               +F                                                         +F\r\n                               +inf                                                       +inf\r\n                               NaN                                                       NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- |ST(0)|;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n", 
      "mnem": "FABS"
    }, 
    {
      "description": "FADD/FADDP/FIADD-Add\r\nOpcode              Instruction               64-Bit     Compat/     Description\r\n                                              Mode       Leg Mode\r\nD8 /0               FADD m32fp                Valid      Valid       Add m32fp to ST(0) and store result in ST(0).\r\nDC /0               FADD m64fp                Valid      Valid       Add m64fp to ST(0) and store result in ST(0).\r\nD8 C0+i             FADD ST(0), ST(i)         Valid      Valid       Add ST(0) to ST(i) and store result in ST(0).\r\nDC C0+i             FADD ST(i), ST(0)         Valid      Valid       Add ST(i) to ST(0) and store result in ST(i).\r\nDE C0+i             FADDP ST(i), ST(0)        Valid      Valid       Add ST(0) to ST(i), store result in ST(i), and pop the\r\n                                                                     register stack.\r\nDE C1               FADDP                     Valid      Valid       Add ST(0) to ST(1), store result in ST(1), and pop the\r\n                                                                     register stack.\r\nDA /0               FIADD m32int              Valid      Valid       Add m32int to ST(0) and store result in ST(0).\r\nDE /0               FIADD m16int              Valid      Valid       Add m16int to ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nAdds the destination and source operands and stores the sum in the destination location. The destination operand\r\nis always an FPU register; the source operand can be a register or a memory location. Source operands in memory\r\ncan be in single-precision or double-precision floating-point format or in word or doubleword integer format.\r\nThe no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-\r\noperand version adds the contents of a memory location (either a floating-point or an integer value) to the contents\r\nof the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice\r\nversa. The value in ST(0) can be doubled by coding:\r\n\r\n   FADD ST(0), ST(0);\r\nThe FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. (The no-operand version of the floating-point add instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)\r\nThe FIADD instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the addition.\r\nThe table on the following page shows the results obtained when adding various classes of numbers, assuming that\r\nneither overflow nor underflow occurs.\r\nWhen the sum of two operands with opposite signs is 0, the result is +0, except for the round toward -inf mode, in\r\nwhich case the result is -0. When the source operand is an integer 0, it is treated as a +0.\r\nWhen both operand are infinities of the same sign, the result is inf of the expected sign. If both operands are infini-\r\nties of opposite signs, an invalid-operation exception is generated. See Table 3-18.\r\n\r\n\r\n\r\n\r\n\r\n                                            Table 3-18. FADD/FADDP/FIADD Results\r\n                                                                          DEST\r\n                               -inf           -F               -0             +0    +F               +inf           NaN\r\n              -inf               -inf           -inf               -inf             -inf    -inf               *            NaN\r\n              - F or - I       -inf           -F               SRC            SRC   +- F or +- 0       +inf           NaN\r\n SRC          -0               -inf           DEST             -0             +-0    DEST             +inf           NaN\r\n              +0               -inf           DEST             +-0             +0    DEST             +inf           NaN\r\n              + F or + I       -inf           +- F or +- 0       SRC            SRC   +F               +inf           NaN\r\n              +inf               *            +inf               +inf             +inf    +inf               +inf           NaN\r\n              NaN              NaN          NaN              NaN            NaN   NaN              NaN          NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FIADD\r\n     THEN\r\n         DEST <- DEST + ConvertToDoubleExtendedPrecisionFP(SRC);\r\n     ELSE (* Source operand is floating-point value *)\r\n         DEST <- DEST + SRC;\r\nFI;\r\n\r\nIF Instruction = FADDP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                         Set to 0 if stack underflow occurred.\r\n                           Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3                 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                        Stack underflow occurred.\r\n#IA                        Operand is an SNaN value or unsupported format.\r\n                           Operands are infinities of unlike sign.\r\n#D                         Source operand is a denormal value.\r\n#U                         Result is too small for destination format.\r\n#O                         Result is too large for destination format.\r\n#P                         Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FADD"
    }, 
    {
      "description": "-R:FADD", 
      "mnem": "FADDP"
    }, 
    {
      "description": "FBLD-Load Binary Coded Decimal\r\n Opcode                Instruction                64-Bit   Compat/    Description\r\n                                                  Mode     Leg Mode\r\n DF /4                 FBLD m80dec                Valid    Valid      Convert BCD value to floating-point and push onto the\r\n                                                                      FPU stack.\r\n\r\n\r\n\r\nDescription\r\nConverts the BCD source operand into double extended-precision floating-point format and pushes the value onto\r\nthe FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved,\r\nincluding that of -0.\r\nThe packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits\r\n(AH through FH). Attempting to load an invalid encoding produces an undefined result.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n\r\nFPU Flags Affected\r\nC1                      Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                     If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FBLD"
    }, 
    {
      "description": "FBSTP-Store BCD Integer and Pop\r\nOpcode              Instruction                   64-Bit     Compat/    Description\r\n                                                  Mode       Leg Mode\r\nDF /6               FBSTP m80bcd                  Valid      Valid      Store ST(0) in m80bcd and pop ST(0).\r\n\r\n\r\n\r\nDescription\r\nConverts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination\r\noperand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value,\r\naccording to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the\r\nprocessor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe destination operand specifies the address where the first byte destination value is to be stored. The BCD value\r\n(including its sign bit) requires 10 bytes of space in memory.\r\nThe following table shows the results obtained when storing various classes of numbers in packed BCD format.\r\n                                                     Table 3-19. FBSTP Results\r\n                              ST(0)                                                           DEST\r\n            - inf or Value Too Large for DEST Format                                              *\r\n                              F<=-1                                                             -D\r\n                            -1 < F < -0                                                         **\r\n                                  -0                                                           -0\r\n                                  +0                                                           +0\r\n                           + 0 < F < +1                                                         **\r\n                              F >= +1                                                           +D\r\n            + inf or Value Too Large for DEST Format                                              *\r\n                               NaN                                                              *\r\n NOTES:\r\n F Means finite floating-point value.\r\n D Means packed-BCD number.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n ** +-0 or +-1, depending on the rounding mode.\r\n\r\nIf the converted value is too large for the destination format, or if the source operand is an inf, SNaN, QNAN, or is in\r\nan unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is\r\nnot masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination\r\noperand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- BCD(ST(0));\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 Converted value that exceeds 18 BCD digits in length.\r\n                    Source operand is an SNaN, QNaN, +-inf, or in an unsupported format.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a segment register is being loaded with a segment selector that points to a non-writable\r\n                    segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FBSTP"
    }, 
    {
      "description": "FCHS-Change Sign\r\nOpcode                 Instruction             64-Bit   Compat/    Description\r\n                                               Mode     Leg Mode\r\nD9 E0                  FCHS                    Valid    Valid      Complements sign of ST(0).\r\n\r\n\r\n\r\nDescription\r\nComplements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-\r\ntude or vice versa. The following table shows the results obtained when changing the sign of various classes of\r\nnumbers.\r\n                                                Table 3-20. FCHS Results\r\n                            ST(0) SRC                                              ST(0) DEST\r\n -inf                                                        +inf\r\n -F                                                        +F\r\n -0                                                        +0\r\n +0                                                        -0\r\n +F                                                        -F\r\n +inf                                                        -inf\r\n NaN                                                       NaN\r\n NOTES:\r\n * F means finite floating-point value.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nSignBit(ST(0)) <- NOT (SignBit(ST(0)));\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCHS"
    }, 
    {
      "description": "FCLEX/FNCLEX - Clear Exceptions\r\n Opcode*                Instruction             64-Bit   Compat/    Description\r\n                                                Mode     Leg Mode\r\n 9B DB E2               FCLEX                   Valid    Valid      Clear floating-point exception flags after checking for\r\n                                                                    pending unmasked floating-point exceptions.\r\n DB E2                  FNCLEX*                 Valid    Valid      Clear floating-point exception flags without checking for\r\n                                                                    pending unmasked floating-point exceptions.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nClears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the\r\nstack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles\r\nany pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does\r\nnot.\r\nThe assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\nThis instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point\r\nexception flags in the MXCRS register.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUStatusWord[0:7] <- 0;\r\nFPUStatusWord[15] <- 0;\r\n\r\nFPU Flags Affected\r\nThe PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are\r\nundefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCLEX"
    }, 
    {
      "description": "FCMOVcc-Floating-Point Conditional Move\r\nOpcode*            Instruction                          64-Bit    Compat/   Description\r\n                                                        Mode      Leg Mode*\r\nDA C0+i            FCMOVB ST(0), ST(i)                  Valid     Valid     Move if below (CF=1).\r\nDA C8+i            FCMOVE ST(0), ST(i)                  Valid     Valid     Move if equal (ZF=1).\r\nDA D0+i            FCMOVBE ST(0), ST(i)                 Valid     Valid     Move if below or equal (CF=1 or ZF=1).\r\nDA D8+i            FCMOVU ST(0), ST(i)                  Valid     Valid     Move if unordered (PF=1).\r\nDB C0+i            FCMOVNB ST(0), ST(i)                 Valid     Valid     Move if not below (CF=0).\r\nDB C8+i            FCMOVNE ST(0), ST(i)                 Valid     Valid     Move if not equal (ZF=0).\r\nDB D0+i            FCMOVNBE ST(0), ST(i)                Valid     Valid     Move if not below or equal (CF=0 and ZF=0).\r\nDB D8+i            FCMOVNU ST(0), ST(i)                 Valid     Valid     Move if not unordered (PF=0).\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nTests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination\r\noperand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Descrip-\r\ntion column above and in Chapter 8 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n1. The source operand is always in the ST(i) register and the destination operand is always ST(0).\r\nThe FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching\r\noverhead for IF operations and the possibility of branch mispredictions by the processor.\r\nA processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are\r\nsupported by checking the processor's feature information with the CPUID instruction (see \"COMISS-Compare\r\nScalar Ordered Single-Precision Floating-Point Values and Set EFLAGS\" in this chapter). If both the CMOV and FPU\r\nfeature bits are set, the FCMOVcc instructions are supported.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not avail-\r\nable in earlier IA-32 processors.\r\n\r\nOperation\r\nIF condition TRUE\r\n    THEN ST(0) <- ST(i);\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                        Set to 0 if stack underflow occurred.\r\nC0, C2, C3                Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                       Stack underflow occurred.\r\n\r\nInteger Flags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCMOVcc"
    }, 
    {
      "description": "FCOM/FCOMP/FCOMPP-Compare Floating Point Values\r\n Opcode               Instruction                     64-Bit       Compat/       Description\r\n                                                      Mode         Leg Mode\r\n D8 /2                FCOM m32fp                      Valid        Valid         Compare ST(0) with m32fp.\r\n DC /2                FCOM m64fp                      Valid        Valid         Compare ST(0) with m64fp.\r\n D8 D0+i              FCOM ST(i)                      Valid        Valid         Compare ST(0) with ST(i).\r\n D8 D1                FCOM                            Valid        Valid         Compare ST(0) with ST(1).\r\n D8 /3                FCOMP m32fp                     Valid        Valid         Compare ST(0) with m32fp and pop register stack.\r\n DC /3                FCOMP m64fp                     Valid        Valid         Compare ST(0) with m64fp and pop register stack.\r\n D8 D8+i              FCOMP ST(i)                     Valid        Valid         Compare ST(0) with ST(i) and pop register stack.\r\n D8 D9                FCOMP                           Valid        Valid         Compare ST(0) with ST(1) and pop register stack.\r\n DE D9                FCOMPP                          Valid        Valid         Compare ST(0) with ST(1) and pop register stack\r\n                                                                                 twice.\r\n\r\n\r\n\r\nDescription\r\nCompares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU\r\nstatus word according to the results (see the table below). The source operand can be a data register or a memory\r\nlocation. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is\r\nignored, so that -0.0 is equal to +0.0.\r\n                                          Table 3-21. FCOM/FCOMP/FCOMPP Results\r\n                  Condition                               C3                            C2                          C0\r\n                 ST(0) > SRC                               0                            0                            0\r\n                 ST(0) < SRC                               0                            0                            1\r\n                 ST(0) = SRC                               1                            0                            0\r\n                 Unordered*                                1                            1                            1\r\n NOTES:\r\n * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nThis instruction checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\" in this\r\nchapter). If either operand is a NaN or is in an unsupported format, an invalid-arithmetic-operand exception (#IA)\r\nis raised and, if the exception is masked, the condition flags are set to \"unordered.\" If the invalid-arithmetic-\r\noperand exception is unmasked, the condition code flags are not set.\r\nThe FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction\r\npops the register stack twice following the comparison operation. To pop the register stack, the processor marks\r\nthe ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they\r\nhandle QNaN operands. The FCOM instructions raise an invalid-arithmetic-operand exception (#IA) when either or\r\nboth of the operands is a NaN value or is in an unsupported format. The FUCOM instructions perform the same\r\noperation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for\r\nQNaNs.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n   ST > SRC:          C3, C2, C0 <- 000;\r\n   ST < SRC:          C3, C2, C0 <- 001;\r\n   ST = SRC:          C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nIF ST(0) or SRC = NaN or unsupported format\r\n    THEN\r\n         #IA\r\n         IF FPUControlWord.IM = 1\r\n              THEN\r\n                  C3, C2, C0 <- 111;\r\n         FI;\r\nFI;\r\n\r\nIF Instruction = FCOMP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nIF Instruction = FCOMPP\r\n     THEN\r\n         PopRegisterStack;\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0.\r\nC0, C2, C3             See table on previous page.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n#IA                    One or both operands are NaN values or have unsupported formats.\r\n                       Register is marked empty.\r\n#D                     One or both operands are denormal values.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCOM"
    }, 
    {
      "description": "FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values and Set EFLAGS\r\n Opcode              Instruction                  64-Bit     Compat/       Description\r\n                                                  Mode       Leg Mode\r\n DB F0+i             FCOMI ST, ST(i)              Valid      Valid         Compare ST(0) with ST(i) and set status flags accordingly.\r\n DF F0+i             FCOMIP ST, ST(i)             Valid      Valid         Compare ST(0) with ST(i), set status flags accordingly, and\r\n                                                                           pop register stack.\r\n DB E8+i             FUCOMI ST, ST(i)             Valid      Valid        Compare ST(0) with ST(i), check for ordered values, and set\r\n                                                                          status flags accordingly.\r\n DF E8+i             FUCOMIP ST, ST(i)            Valid      Valid         Compare ST(0) with ST(i), check for ordered values, set\r\n                                                                           status flags accordingly, and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nPerforms an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and\r\nCF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for compari-\r\nsons, so that -0.0 is equal to +0.0.\r\n                                   Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results\r\n                     Comparison Results*                                    ZF                      PF                     CF\r\n                           ST0 > ST(i)                                       0                       0                      0\r\n                           ST0 < ST(i)                                       0                       0                      1\r\n                           ST0 = ST(i)                                       1                       0                      0\r\n                          Unordered**                                        1                       1                      1\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n ** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nAn unordered comparison checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\"\r\nin this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instruc-\r\ntions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception\r\n(#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition\r\ncode flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions\r\nraise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an\r\nunsupported format.\r\nIf the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS\r\nregister are set only if the exception is masked.\r\nThe FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags to zero in the EFLAGS register\r\n(regardless of whether an invalid-operation exception is detected).\r\nThe FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the\r\nregister stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture in the P6 family\r\nprocessors and are not available in earlier IA-32 processors.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n   ST(0) > ST(i):     ZF, PF, CF <- 000;\r\n   ST(0) < ST(i):     ZF, PF, CF <- 001;\r\n   ST(0) = ST(i):     ZF, PF, CF <- 100;\r\nESAC;\r\n\r\nIF Instruction is FCOMI or FCOMIP\r\n     THEN\r\n         IF ST(0) or ST(i) = NaN or unsupported format\r\n              THEN\r\n                   #IA\r\n                   IF FPUControlWord.IM = 1\r\n                        THEN\r\n                             ZF, PF, CF <- 111;\r\n                   FI;\r\n         FI;\r\nFI;\r\n\r\nIF Instruction is FUCOMI or FUCOMIP\r\n    THEN\r\n         IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format\r\n              THEN\r\n                   ZF, PF, CF <- 111;\r\n              ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)\r\n                    #IA;\r\n                   IF FPUControlWord.IM = 1\r\n                         THEN\r\n                             ZF, PF, CF <- 111;\r\n                   FI;\r\n         FI;\r\nFI;\r\n\r\nIF Instruction is FCOMIP or FUCOMIP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0.\r\nC0, C2, C3              Not affected.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported\r\n                        formats.\r\n                        (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or\r\n                        have undefined formats. Detection of a QNaN value does not raise an invalid-operand excep-\r\n                        tion.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCOMI"
    }, 
    {
      "description": "-R:FCOMI", 
      "mnem": "FCOMIP"
    }, 
    {
      "description": "-R:FCOM", 
      "mnem": "FCOMP"
    }, 
    {
      "description": "-R:FCOM", 
      "mnem": "FCOMPP"
    }, 
    {
      "description": "FCOS- Cosine\r\nOpcode                 Instruction                 64-Bit     Compat/     Description\r\n                                                   Mode       Leg Mode\r\nD9 FF                  FCOS                        Valid      Valid       Replace ST(0) with its approximate cosine.\r\n\r\n\r\n\r\nDescription\r\nComputes the approximate cosine of the source operand in register ST(0) and stores the result in ST(0). The\r\nsource operand must be given in radians and must be within the range -263 to +263. The following table shows the\r\nresults obtained when taking the cosine of various classes of numbers.\r\n                                                       Table 3-23. FCOS Results\r\n                            ST(0) SRC                                                     ST(0) DEST\r\n                               -inf                                                              *\r\n                               -F                                                          -1 to +1\r\n                               -0                                                             +1\r\n                               +0                                                             +1\r\n                               +F                                                          - 1 to + 1\r\n                               +inf                                                              *\r\n                               NaN                                                            NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF |ST(0)| < 263\r\nTHEN\r\n     C2 <- 0;\r\n     ST(0) <- FCOS(ST(0)); // approximation of cosine\r\nELSE (* Source operand is out-of-range *)\r\n     C2 <- 1;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nFPU Flags Affected\r\nC1                   Set to 0 if stack underflow occurred.\r\n                     Set if result was rounded up; cleared otherwise.\r\n                     Undefined if C2 is 1.\r\nC2                   Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3               Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                  Stack underflow occurred.\r\n#IA                  Source operand is an SNaN value, inf, or unsupported format.\r\n#D                   Source is a denormal value.\r\n#P                   Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                  If there is a pending x87 FPU exception.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FCOS"
    }, 
    {
      "description": "FDECSTP-Decrement Stack-Top Pointer\r\n Opcode                Instruction            64-Bit      Compat/       Description\r\n                                              Mode        Leg Mode\r\n D9 F6                 FDECSTP                Valid       Valid         Decrement TOP field in FPU status word.\r\n\r\n\r\n\r\nDescription\r\nSubtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field\r\ncontains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the\r\nFPU data registers and tag register are not affected.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF TOP = 0\r\n    THEN TOP <- 7;\r\n    ELSE TOP <- TOP - 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FDECSTP"
    }, 
    {
      "description": "FDIV/FDIVP/FIDIV-Divide\r\nOpcode              Instruction                64-Bit   Compat/      Description\r\n                                               Mode     Leg Mode\r\nD8 /6               FDIV m32fp                 Valid    Valid        Divide ST(0) by m32fp and store result in ST(0).\r\nDC /6               FDIV m64fp                 Valid    Valid        Divide ST(0) by m64fp and store result in ST(0).\r\nD8 F0+i             FDIV ST(0), ST(i)          Valid    Valid        Divide ST(0) by ST(i) and store result in ST(0).\r\nDC F8+i             FDIV ST(i), ST(0)          Valid    Valid        Divide ST(i) by ST(0) and store result in ST(i).\r\nDE F8+i             FDIVP ST(i), ST(0)         Valid    Valid        Divide ST(i) by ST(0), store result in ST(i), and pop the\r\n                                                                     register stack.\r\nDE F9               FDIVP                      Valid    Valid        Divide ST(1) by ST(0), store result in ST(1), and pop\r\n                                                                     the register stack.\r\nDA /6               FIDIV m32int               Valid    Valid        Divide ST(0) by m32int and store result in ST(0).\r\nDE /6               FIDIV m16int               Valid    Valid        Divide ST(0) by m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nDivides the destination operand by the source operand and stores the result in the destination location. The desti-\r\nnation operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory\r\nlocation. Source operands in memory can be in single-precision or double-precision floating-point format, word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0)\r\nregister. The one-operand version divides the contents of the ST(0) register by the contents of a memory location\r\n(either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by\r\nthe contents of the ST(i) register or vice versa.\r\nThe FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. The no-operand version of the floating-point divide instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.\r\nThe FIDIV instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the division. When the source operand is an integer 0, it is treated as a +0.\r\nIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of\r\nthe appropriate sign is stored in the destination operand.\r\nThe following table shows the results obtained when dividing various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n                                             Table 3-24. FDIV/FDIVP/FIDIV Results\r\n                                                                           DEST\r\n                              -inf             -F              -0              +0    +F        +inf           NaN\r\n               -inf             *              +0              +0              -0    -0        *            NaN\r\n               -F             +inf             +F              +0              -0    -F        -inf           NaN\r\n               -I             +inf             +F              +0              -0    -F        -inf           NaN\r\n     SRC       -0             +inf             **              *               *     **        -inf           NaN\r\n               +0             -inf             **              *               *     **        +inf           NaN\r\n               +I             -inf             -F              -0              +0    +F        +inf           NaN\r\n               +F             -inf             -F              -0              +0    +F        +inf           NaN\r\n               +inf             *              -0              -0              +0    +0        *            NaN\r\n               NaN            NaN            NaN             NaN             NaN   NaN       NaN          NaN\r\n  NOTES:\r\n  F Means finite floating-point value.\r\n  I Means integer.\r\n  * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n  ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF SRC = 0\r\n    THEN\r\n        #Z;\r\n    ELSE\r\n        IF Instruction is FIDIV\r\n              THEN\r\n                  DEST <- DEST / ConvertToDoubleExtendedPrecisionFP(SRC);\r\n              ELSE (* Source operand is floating-point value *)\r\n                  DEST <- DEST / SRC;\r\n        FI;\r\nFI;\r\n\r\nIF Instruction = FDIVP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                        Set to 0 if stack underflow occurred.\r\n                          Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3                Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 Operand is an SNaN value or unsupported format.\r\n                    +-inf / +-inf; +-0 / +-0\r\n#D                  Source is a denormal value.\r\n#Z                  DEST / +-0, where DEST is not equal to +-0.\r\n#U                  Result is too small for destination format.\r\n#O                  Result is too large for destination format.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FDIV"
    }, 
    {
      "description": "-R:FDIV", 
      "mnem": "FDIVP"
    }, 
    {
      "description": "FDIVR/FDIVRP/FIDIVR-Reverse Divide\r\nOpcode               Instruction             64-Bit   Compat/     Description\r\n                                             Mode     Leg Mode\r\nD8 /7                FDIVR m32fp             Valid    Valid       Divide m32fp by ST(0) and store result in ST(0).\r\nDC /7                FDIVR m64fp             Valid    Valid       Divide m64fp by ST(0) and store result in ST(0).\r\nD8 F8+i              FDIVR ST(0), ST(i)      Valid    Valid       Divide ST(i) by ST(0) and store result in ST(0).\r\nDC F0+i              FDIVR ST(i), ST(0)      Valid    Valid       Divide ST(0) by ST(i) and store result in ST(i).\r\nDE F0+i              FDIVRP ST(i), ST(0)     Valid    Valid       Divide ST(0) by ST(i), store result in ST(i), and pop the\r\n                                                                  register stack.\r\nDE F1                FDIVRP                  Valid    Valid       Divide ST(0) by ST(1), store result in ST(1), and pop the\r\n                                                                  register stack.\r\nDA /7                FIDIVR m32int           Valid    Valid       Divide m32int by ST(0) and store result in ST(0).\r\nDE /7                FIDIVR m16int           Valid    Valid       Divide m16int by ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nDivides the source operand by the destination operand and stores the result in the destination location. The desti-\r\nnation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory\r\nlocation. Source operands in memory can be in single-precision or double-precision floating-point format, word or\r\ndoubleword integer format.\r\nThese instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to\r\nsupport more efficient coding.\r\nThe no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1)\r\nregister. The one-operand version divides the contents of a memory location (either a floating-point or an integer\r\nvalue) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by\r\nthe contents of the ST(0) register or vice versa.\r\nThe FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. The no-operand version of the floating-point divide instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.\r\nThe FIDIVR instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the division.\r\nIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of\r\nthe appropriate sign is stored in the destination operand.\r\nThe following table shows the results obtained when dividing various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n                                          Table 3-25. FDIVR/FDIVRP/FIDIVR Results\r\n                                                                          DEST\r\n                                  -inf              -F              -0             +0    +F             +inf            NaN\r\n                   -inf              *             +inf              +inf              -inf    -inf               *           NaN\r\n     SRC           -F             +0              +F              **             **    -F              -0           NaN\r\n                   -I             +0              +F              **             **    -F              -0           NaN\r\n                   -0             +0              +0               *              *    -0              -0           NaN\r\n                   +0             -0              -0               *              *    +0              +0           NaN\r\n                   +I             -0              -F              **             **    +F              +0           NaN\r\n                   +F             -0              -F              **             **    +F              +0           NaN\r\n                   +inf              *              -inf             -inf              +inf    +inf               *           NaN\r\n                  NaN            NaN             NaN             NaN             NaN   NaN            NaN           NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the source operand is an integer 0, it is treated as a +0. This instruction's operation is the same in non-64-bit\r\nmodes and 64-bit mode.\r\n\r\nOperation\r\nIF DEST = 0\r\n    THEN\r\n        #Z;\r\n    ELSE\r\n        IF Instruction = FIDIVR\r\n              THEN\r\n                  DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;\r\n              ELSE (* Source operand is floating-point value *)\r\n                  DEST <- SRC / DEST;\r\n        FI;\r\nFI;\r\n\r\nIF Instruction = FDIVRP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Operand is an SNaN value or unsupported format.\r\n                       +-inf / +-inf; +-0 / +-0\r\n#D                      Source is a denormal value.\r\n#Z                     SRC / +-0, where SRC is not equal to +-0.\r\n#U                      Result is too small for destination format.\r\n#O                      Result is too large for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                     If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FDIVR"
    }, 
    {
      "description": "-R:FDIVR", 
      "mnem": "FDIVRP"
    }, 
    {
      "description": "FFREE-Free Floating-Point Register\r\nOpcode             Instruction              64-Bit    Compat/       Description\r\n                                            Mode      Leg Mode\r\nDD C0+i            FFREE ST(i)              Valid     Valid         Sets tag for ST(i) to empty.\r\n\r\n\r\n\r\nDescription\r\nSets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU\r\nstack-top pointer (TOP) are not affected.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTAG(i) <- 11B;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                  If there is a pending x87 FPU exception.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FFREE"
    }, 
    {
      "description": "-R:FADD", 
      "mnem": "FIADD"
    }, 
    {
      "description": "FICOM/FICOMP-Compare Integer\r\n Opcode                Instruction              64-Bit   Compat/    Description\r\n                                                Mode     Leg Mode\r\n DE /2                 FICOM m16int             Valid    Valid      Compare ST(0) with m16int.\r\n DA /2                 FICOM m32int             Valid    Valid      Compare ST(0) with m32int.\r\n DE /3                 FICOMP m16int            Valid    Valid      Compare ST(0) with m16int and pop stack register.\r\n DA /3                 FICOMP m32int            Valid    Valid      Compare ST(0) with m32int and pop stack register.\r\n\r\n\r\n\r\nDescription\r\nCompares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in\r\nthe FPU status word according to the results (see table below). The integer value is converted to double extended-\r\nprecision floating-point format before the comparison is made.\r\n                                          Table 3-26. FICOM/FICOMP Results\r\n                      Condition                          C3                       C2                      C0\r\n                      ST(0) > SRC                         0                       0                        0\r\n                     ST(0) < SRC                          0                       0                        1\r\n                     ST(0) = SRC                          1                       0                        0\r\n                      Unordered                           1                       1                        1\r\n\r\nThese instructions perform an \"unordered comparison.\" An unordered comparison also checks the class of the\r\nnumbers being compared (see \"FXAM-Examine Floating-Point\" in this chapter). If either operand is a NaN or is in\r\nan undefined format, the condition flags are set to \"unordered.\"\r\nThe sign of zero is ignored, so that -0.0 <- +0.0.\r\nThe FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor\r\nmarks the ST(0) register empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n   ST(0) > SRC:       C3, C2, C0 <- 000;\r\n   ST(0) < SRC:       C3, C2, C0 <- 001;\r\n   ST(0) = SRC:       C3, C2, C0 <- 100;\r\n   Unordered:         C3, C2, C0 <- 111;\r\nESAC;\r\n\r\nIF Instruction = FICOMP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0.\r\nC0, C2, C3             See table on previous page.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n#IA                    One or both operands are NaN values or have unsupported formats.\r\n#D                     One or both operands are denormal values.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FICOM"
    }, 
    {
      "description": "-R:FICOM", 
      "mnem": "FICOMP"
    }, 
    {
      "description": "-R:FDIV", 
      "mnem": "FIDIV"
    }, 
    {
      "description": "-R:FDIVR", 
      "mnem": "FIDIVR"
    }, 
    {
      "description": "FILD-Load Integer\r\n Opcode               Instruction          64-Bit    Compat/      Description\r\n                                           Mode      Leg Mode\r\n DF /0                FILD m16int          Valid     Valid        Push m16int onto the FPU register stack.\r\n DB /0                FILD m32int          Valid     Valid        Push m32int onto the FPU register stack.\r\n DF /5                FILD m64int          Valid     Valid        Push m64int onto the FPU register stack.\r\n\r\n\r\n\r\nDescription\r\nConverts the signed-integer source operand into double extended-precision floating-point format and pushes the\r\nvalue onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded\r\nwithout rounding errors. The sign of the source operand is preserved.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n\r\nFPU Flags Affected\r\nC1                   Set to 1 if stack overflow occurred; set to 0 otherwise.\r\nC0, C2, C3           Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                  Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                     If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the\r\n                     current privilege level is 3.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)      If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                  If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FILD"
    }, 
    {
      "description": "-R:FMUL", 
      "mnem": "FIMUL"
    }, 
    {
      "description": "FINCSTP-Increment Stack-Top Pointer\r\n Opcode                 Instruction        64-Bit     Compat/      Description\r\n                                           Mode       Leg Mode\r\n D9 F7                  FINCSTP            Valid      Valid        Increment the TOP field in the FPU status register.\r\n\r\n\r\n\r\nDescription\r\nAdds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a\r\n7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data\r\nregisters and tag register are not affected. This operation is not equivalent to popping the stack, because the tag\r\nfor the previous top-of-stack register is not marked empty.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF TOP = 7\r\n    THEN TOP <- 0;\r\n    ELSE TOP <- TOP + 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FINCSTP"
    }, 
    {
      "description": "FINIT/FNINIT-Initialize Floating-Point Unit\r\nOpcode               Instruction              64-Bit    Compat/    Description\r\n                                              Mode      Leg Mode\r\n9B DB E3             FINIT                    Valid     Valid      Initialize FPU after checking for pending unmasked\r\n                                                                   floating-point exceptions.\r\nDB E3                FNINIT*                  Valid     Valid      Initialize FPU without checking for pending unmasked\r\n                                                                   floating-point exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nSets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU\r\ncontrol word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared\r\n(no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all\r\ntagged as empty (11B). Both the instruction and data pointers are cleared.\r\nThe FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing\r\nthe initialization; the FNINIT instruction does not.\r\nThe assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT\r\ninstruction), and the processor executes each of these instructions in separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNINIT instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNINIT instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\nIn the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear the instruction and data pointers.\r\nThis instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers.\r\n\r\nOperation\r\nFPUControlWord <- 037FH;\r\nFPUStatusWord <- 0;\r\nFPUTagWord <- FFFFH;\r\nFPUDataPointer <- 0;\r\nFPUInstructionPointer <- 0;\r\nFPULastInstructionOpcode <- 0;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 set to 0.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM                        CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                        If there is a pending x87 FPU exception.\r\n#UD                        If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FINIT"
    }, 
    {
      "description": "FIST/FISTP-Store Integer\r\nOpcode                     Instruction                64-Bit    Compat/       Description\r\n                                                      Mode      Leg Mode\r\nDF /2                      FIST m16int                Valid     Valid         Store ST(0) in m16int.\r\nDB /2                      FIST m32int                Valid     Valid         Store ST(0) in m32int.\r\nDF /3                      FISTP m16int               Valid     Valid         Store ST(0) in m16int and pop register stack.\r\nDB /3                      FISTP m32int               Valid     Valid         Store ST(0) in m32int and pop register stack.\r\nDF /7                      FISTP m64int               Valid     Valid         Store ST(0) in m64int and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nThe FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the desti-\r\nnation operand. Values can be stored in word or doubleword integer format. The destination operand specifies the\r\naddress where the first byte of the destination value is to be stored.\r\nThe FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop\r\nthe register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FISTP instruction also stores values in quadword integer format.\r\nThe following table shows the results obtained when storing various classes of numbers in integer format.\r\n                                                 Table 3-27. FIST/FISTP Results\r\n                             ST(0)                                                          DEST\r\n           - inf or Value Too Large for DEST Format                                            *\r\n                             F <= -1                                                          -I\r\n                          -1 < F < -0                                                        **\r\n                              -0                                                             0\r\n                              +0                                                             0\r\n                         +0<F<+1                                                             **\r\n                            F>=+1                                                             +I\r\n           + inf or Value Too Large for DEST Format                                            *\r\n                              NaN                                                            *\r\nNOTES:\r\nF Means finite floating-point value.\r\nI Means integer.\r\n* Indicates floating-point invalid-operation (#IA) exception.\r\n** 0 or +-1, depending on the rounding mode.\r\n\r\n\r\nIf the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode spec-\r\nified by the RC field of the FPU control word.\r\nIf the converted value is too large for the destination format, or if the source operand is an inf, SNaN, QNAN, or is in\r\nan unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is\r\nnot masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination\r\noperand. If the invalid-operation exception is masked, the integer indefinite value is stored in memory.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDEST <- Integer(ST(0));\r\n\r\nIF Instruction = FISTP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                         Set to 0 if stack underflow occurred.\r\n                           Indicates rounding direction of if the inexact exception (#P) is generated: 0 <- not roundup; 1\r\n                           <- roundup.\r\n                           Set to 0 otherwise.\r\nC0, C2, C3                 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                        Stack underflow occurred.\r\n#IA                        Converted value is too large for the destination format.\r\n                           Source operand is an SNaN, QNaN, +-inf, or unsupported format.\r\n#P                         Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                     If the destination is located in a non-writable segment.\r\n                           If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                           If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                           selector.\r\n#SS(0)                     If a memory operand effective address is outside the SS segment limit.\r\n#NM                        CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)            If a page fault occurs.\r\n#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made while the\r\n                           current privilege level is 3.\r\n#UD                        If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                        If a memory operand effective address is outside the SS segment limit.\r\n#NM                        CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                        If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                     If a memory operand effective address is outside the SS segment limit.\r\n#NM                        CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)            If a page fault occurs.\r\n#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                        If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FIST"
    }, 
    {
      "description": "-R:FIST", 
      "mnem": "FISTP"
    }, 
    {
      "description": "FISTTP-Store Integer with Truncation\r\n Opcode                 Instruction                  64-Bit Mode Compat/         Description\r\n                                                                 Leg Mode\r\n DF /1                  FISTTP m16int                Valid      Valid            Store ST(0) in m16int with truncation.\r\n DB /1                  FISTTP m32int                Valid      Valid            Store ST(0) in m32int with truncation.\r\n DD /1                  FISTTP m64int                Valid      Valid            Store ST(0) in m64int with truncation.\r\n\r\n\r\n\r\nDescription\r\nFISTTP converts the value in ST into a signed integer using truncation (chop) as rounding mode, transfers the\r\nresult to the destination, and pop ST. FISTTP accepts word, short integer, and long integer destinations.\r\nThe following table shows the results obtained when storing various classes of numbers in integer format.\r\n                                                    Table 3-28. FISTTP Results\r\n                               ST(0)                                                           DEST\r\n- inf or Value Too Large for DEST Format                                                          *\r\nF<= -1                                                                                           -I\r\n-1<F<+1                                                                                         0\r\nFS+1                                                                                            +I\r\n+ inf or Value Too Large for DEST Format                                                          *\r\nNaN                                                                                             *\r\nNOTES:\r\nF Means finite floating-point value.\r\nI Means integer.\r\n* Indicates floating-point invalid-operation (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- ST;\r\npop ST;\r\n\r\nFlags Affected\r\nC1 is cleared; C0, C2, C3 undefined.\r\n\r\nNumeric Exceptions\r\nInvalid, Stack Invalid (stack underflow), Precision.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If the destination is in a nonwritable segment.\r\n                         For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#PF(fault-code)          For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n#NM                      If CR0.EM[bit 2] = 1.\r\n                         If CR0.TS[bit 3] = 1.\r\n#UD                      If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n                         If the LOCK prefix is used.\r\n\r\n\r\n\r\nReal Address Mode Exceptions\r\nGP(0)               If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.\r\n#NM                 If CR0.EM[bit 2] = 1.\r\n                    If CR0.TS[bit 3] = 1.\r\n#UD                 If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n                    If the LOCK prefix is used.\r\n\r\nVirtual 8086 Mode Exceptions\r\nGP(0)               If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.\r\n#NM                 If CR0.EM[bit 2] = 1.\r\n                    If CR0.TS[bit 3] = 1.\r\n#UD                 If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n                    If the LOCK prefix is used.\r\n#PF(fault-code)     For a page fault.\r\n#AC(0)              For unaligned memory reference if the current privilege is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FISTTP"
    }, 
    {
      "description": "-R:FSUB", 
      "mnem": "FISUB"
    }, 
    {
      "description": "-R:FSUBR", 
      "mnem": "FISUBR"
    }, 
    {
      "description": "FLD-Load Floating Point Value\r\n Opcode                   Instruction        64-Bit   Compat/     Description\r\n                                             Mode     Leg Mode\r\n D9 /0                    FLD m32fp          Valid    Valid       Push m32fp onto the FPU register stack.\r\n DD /0                    FLD m64fp          Valid    Valid       Push m64fp onto the FPU register stack.\r\n DB /5                    FLD m80fp          Valid    Valid       Push m80fp onto the FPU register stack.\r\n D9 C0+i                  FLD ST(i)          Valid    Valid       Push ST(i) onto the FPU register stack.\r\n\r\n\r\n\r\nDescription\r\nPushes the source operand onto the FPU register stack. The source operand can be in single-precision, double-\r\nprecision, or double extended-precision floating-point format. If the source operand is in single-precision or\r\ndouble-precision floating-point format, it is automatically converted to the double extended-precision floating-\r\npoint format before being pushed on the stack.\r\nThe FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack. Here, pushing register\r\nST(0) duplicates the stack top.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF SRC is ST(i)\r\n    THEN\r\n         temp <- ST(i);\r\nFI;\r\n\r\nTOP <- TOP    - 1;\r\nIF SRC is memory-operand\r\n    THEN\r\n         ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n    ELSE (* SRC is ST(i) *)\r\n         ST(0) <- temp;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                       Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3               Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                      Stack underflow or overflow occurred.\r\n#IA                      Source operand is an SNaN. Does not occur if the source operand is in double extended-preci-\r\n                         sion floating-point format (FLD m80fp or FLD ST(i)).\r\n#D                       Source operand is a denormal value. Does not occur if the source operand is in double\r\n                         extended-precision floating-point format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If destination is located in a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FLD"
    }, 
    {
      "description": "FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ-Load Constant\r\nOpcode*               Instruction             64-Bit    Compat/    Description\r\n                                              Mode      Leg Mode\r\nD9 E8                 FLD1                    Valid     Valid      Push +1.0 onto the FPU register stack.\r\nD9 E9                 FLDL2T                  Valid     Valid      Push log210 onto the FPU register stack.\r\nD9 EA                 FLDL2E                  Valid     Valid      Push log2e onto the FPU register stack.\r\nD9 EB                 FLDPI                   Valid     Valid      Push pi onto the FPU register stack.\r\nD9 EC                 FLDLG2                  Valid     Valid      Push log102 onto the FPU register stack.\r\nD9 ED                 FLDLN2                  Valid     Valid      Push loge2 onto the FPU register stack.\r\nD9 EE                 FLDZ                    Valid     Valid      Push +0.0 onto the FPU register stack.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nPush one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU\r\nregister stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, pi, log102,\r\nand loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control\r\nword) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a\r\nresult of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up.\r\nSee the section titled \"Approximation of Pi\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1, for a description of the pi constant.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel\r\n8087 and Intel 287 math coprocessors.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- CONSTANT;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3             Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FLD1"
    }, 
    {
      "description": "FLDCW-Load x87 FPU Control Word\r\n Opcode                  Instruction                 64-Bit   Compat/    Description\r\n                                                     Mode     Leg Mode\r\n D9 /5                   FLDCW m2byte                Valid    Valid      Load FPU control word from m2byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruc-\r\ntion is typically used to establish or change the FPU's mode of operation.\r\nIf one or more exception flags are set in the FPU status word prior to loading a new FPU control word and the new\r\ncontrol word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution\r\nof the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled \"Soft-\r\nware Exception Handling\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1). To avoid raising exceptions when changing FPU operating modes, clear any pending exceptions (using\r\nthe FCLEX or FNCLEX instruction) before loading the new control word.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone; however, this operation might unmask a pending exception in the FPU status word. That exception is then\r\ngenerated upon execution of the next \"waiting\" floating-point instruction.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                       selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FLDCW"
    }, 
    {
      "description": "FLDENV-Load x87 FPU Environment\r\nOpcode            Instruction                      64-Bit   Compat/     Description\r\n                                                   Mode     Leg Mode\r\nD9 /4             FLDENV m14/28byte                Valid    Valid       Load FPU environment from m14byte or m28byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the complete x87 FPU operating environment from memory into the FPU registers. The source operand spec-\r\nifies the first byte of the operating-environment data in memory. This data is typically written to the specified\r\nmemory location by a FSTENV or FNSTENV instruction.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the loaded environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used.\r\nThe FLDENV instruction should be executed in the same operating mode as the corresponding FSTENV/FNSTENV\r\ninstruction.\r\nIf one or more unmasked exception flags are set in the new FPU status word, a floating-point exception will be\r\ngenerated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions,\r\nsee the section titled \"Software Exception Handling\" in Chapter 8 of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1). To avoid generating exceptions when loading a new environment, clear all\r\nthe exception flags in the FPU status word that is being loaded.\r\nIf a page or limit fault occurs during the execution of this instruction, the state of the x87 FPU registers as seen by\r\nthe fault handler may be different than the state being loaded from memory. In such situations, the fault handler\r\nshould ignore the status of the x87 FPU registers, handle the fault, and return. The FLDENV instruction will then\r\ncomplete the loading of the x87 FPU registers with no resulting context inconsistency.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC[FPUControlWord];\r\nFPUStatusWord <- SRC[FPUStatusWord];\r\nFPUTagWord <- SRC[FPUTagWord];\r\nFPUDataPointer <- SRC[FPUDataPointer];\r\nFPUInstructionPointer <- SRC[FPUInstructionPointer];\r\nFPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, C3 flags are loaded.\r\n\r\nFloating-Point Exceptions\r\nNone; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next\r\n\"waiting\" floating-point instruction.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FLDENV"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDL2E"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDL2T"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDLG2"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDLN2"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDPI"
    }, 
    {
      "description": "-R:FLD1", 
      "mnem": "FLDZ"
    }, 
    {
      "description": "FMUL/FMULP/FIMUL-Multiply\r\n Opcode            Instruction                  64-Bit   Compat/     Description\r\n                                                Mode     Leg Mode\r\n D8 /1             FMUL m32fp                   Valid    Valid       Multiply ST(0) by m32fp and store result in ST(0).\r\n DC /1             FMUL m64fp                   Valid    Valid       Multiply ST(0) by m64fp and store result in ST(0).\r\n D8 C8+i           FMUL ST(0), ST(i)            Valid    Valid       Multiply ST(0) by ST(i) and store result in ST(0).\r\n DC C8+i           FMUL ST(i), ST(0)            Valid    Valid       Multiply ST(i) by ST(0) and store result in ST(i).\r\n DE C8+i           FMULP ST(i), ST(0)           Valid    Valid       Multiply ST(i) by ST(0), store result in ST(i), and pop the\r\n                                                                     register stack.\r\n DE C9             FMULP                        Valid    Valid       Multiply ST(1) by ST(0), store result in ST(1), and pop\r\n                                                                     the register stack.\r\n DA /1             FIMUL m32int                 Valid    Valid       Multiply ST(0) by m32int and store result in ST(0).\r\n DE /1             FIMUL m16int                 Valid    Valid       Multiply ST(0) by m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nMultiplies the destination and source operands and stores the product in the destination location. The destination\r\noperand is always an FPU data register; the source operand can be an FPU data register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0)\r\nregister and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0)\r\nregister by the contents of a memory location (either a floating point or an integer value) and stores the product in\r\nthe ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the\r\nST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the desti-\r\nnation operand).\r\nThe FMULP instructions perform the additional operation of popping the FPU register stack after storing the\r\nproduct. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack\r\npointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register\r\nstack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.\r\nThe FIMUL instructions convert an integer source operand to double extended-\r\nprecision floating-point format before performing the multiplication.\r\nThe sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multi-\r\nplied is 0 or inf. When the source operand is an integer 0, it is treated as a +0.\r\nThe following table shows the results obtained when multiplying various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n                                           Table 3-29. FMUL/FMULP/FIMUL Results\r\n                                                                  DEST\r\n                                 -inf              -F         -0           +0          +F      +inf           NaN\r\n                  -inf             +inf              +inf          *             *         -inf      -inf           NaN\r\n                   -F            +inf              +F         +0           -0          -F      -inf           NaN\r\n                   -I            +inf              +F         +0           -0          -F      -inf           NaN\r\n      SRC          -0              *             +0         +0           -0          -0       *           NaN\r\n                   +0              *             -0         -0           +0          +0       *           NaN\r\n                   +I            -inf              -F         -0           +0          +F      +inf           NaN\r\n                   +F            -inf              -F         -0           +0          +F      +inf           NaN\r\n                  +inf             -inf              -inf          *             *         +inf      +inf           NaN\r\n                  NaN            NaN             NaN       NaN           NaN         NaN    NaN           NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means Integer.\r\n * Indicates invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FIMUL\r\n     THEN\r\n         DEST <- DEST * ConvertToDoubleExtendedPrecisionFP(SRC);\r\n     ELSE (* Source operand is floating-point value *)\r\n         DEST <- DEST * SRC;\r\nFI;\r\n\r\nIF Instruction = FMULP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Operand is an SNaN value or unsupported format.\r\n                        One operand is +-0 and the other is +-inf.\r\n#D                      Source operand is a denormal value.\r\n#U                      Result is too small for destination format.\r\n#O                      Result is too large for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                      selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                   If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                   If there is a pending x87 FPU exception.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FMUL"
    }, 
    {
      "description": "-R:FMUL", 
      "mnem": "FMULP"
    }, 
    {
      "description": "-R:FCLEX", 
      "mnem": "FNCLEX"
    }, 
    {
      "description": "-R:FINIT", 
      "mnem": "FNINIT"
    }, 
    {
      "description": "FNOP-No Operation\r\n Opcode                  Instruction        64-Bit   Compat/     Description\r\n                                            Mode     Leg Mode\r\n D9 D0                   FNOP               Valid    Valid       No operation is performed.\r\n\r\n\r\n\r\nDescription\r\nPerforms no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or\r\nmachine context, except the EIP register and the FPU Instruction Pointer.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                  If there is a pending x87 FPU exception.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FNOP"
    }, 
    {
      "description": "-R:FSAVE", 
      "mnem": "FNSAVE"
    }, 
    {
      "description": "-R:FSTCW", 
      "mnem": "FNSTCW"
    }, 
    {
      "description": "-R:FSTENV", 
      "mnem": "FNSTENV"
    }, 
    {
      "description": "-R:FSTSW", 
      "mnem": "FNSTSW"
    }, 
    {
      "description": "FPATAN-Partial Arctangent\r\nOpcode*              Instruction            64-Bit        Compat/         Description\r\n                                            Mode          Leg Mode\r\nD9 F3                FPATAN                 Valid         Valid           Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nComputes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0),\r\nstores the result in ST(1), and pops the FPU register stack. The result in register ST(0) has the same sign as the\r\nsource operand ST(1) and a magnitude less than +pi.\r\nThe FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where\r\nY (the ordinate) is ST(1) and X (the abscissa) is ST(0). The angle depends on the sign of X and Y independently,\r\nnot just on the sign of the ratio Y/X. This is because a point (-X,Y) is in the second quadrant, resulting in an angle\r\nbetween pi/2 and pi, while a point (X,-Y) is in the fourth quadrant, resulting in an angle between 0 and -pi/2. A point\r\n(-X,-Y) is in the third quadrant, giving an angle between -pi/2 and -pi.\r\nThe following table shows the results obtained when computing the arctangent of various classes of numbers,\r\nassuming that underflow does not occur.\r\n                                                    Table 3-30. FPATAN Results\r\n                                                                              ST(0)\r\n                             -inf            -F                     -0              +0            +F              +inf                 NaN\r\n              -inf             - 3pi/4*       - pi/2                  - pi/2           - pi/2         - pi/2           - pi/4*             NaN\r\n   ST(1)      -F             -p            -pi to -pi/2             -pi/2            -pi/2          -pi/2 to -0      -0                 NaN\r\n              -0             -p            -p                     -p*             - 0*          -0              -0                 NaN\r\n              +0             +p            +p                     + pi*            + 0*          +0              +0                 NaN\r\n              +F             +p            +pi to +pi/2             + pi/2           +pi/2          +pi/2 to +0      +0                 NaN\r\n              +inf             +3pi/4*        +pi/2                   +pi/2            +pi/2          + pi/2           + pi/4*             NaN\r\n                   NaN             NaN              NaN                 NaN            NaN           NaN             NaN           NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Table 8-10 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, specifies that the ratios 0/0 and inf/inf\r\n   generate the floating-point invalid arithmetic-operation exception and, if this exception is masked, the floating-point QNaN indefi-\r\n   nite value is returned. With the FPATAN instruction, the 0/0 or inf/inf value is actually not calculated using division. Instead, the arc-\r\n   tangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers as\r\n   arguments. In this complex variable formulation, arctangent(0,0) etc. has well defined values. These values are needed to develop\r\n   a library to compute transcendental functions with complex arguments, based on the FPU functions that only allow floating-point\r\n   values as arguments.\r\n\r\nThere is no restriction on the range of source operands that FPATAN can accept.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe source operands for this instruction are restricted for the 80287 math coprocessor to the following range:\r\n\r\n0 <= |ST(1)| < |ST(0)| < +inf\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nST(1) <- arctan(ST(1) / ST(0));\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Source operand is an SNaN value or unsupported format.\r\n#D                      Source operand is a denormal value.\r\n#U                      Result is too small for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FPATAN"
    }, 
    {
      "description": "FPREM-Partial Remainder\r\nOpcode                   Instruction          64-Bit       Compat/         Description\r\n                                              Mode         Leg Mode\r\nD9 F8                    FPREM                Valid        Valid           Replace ST(0) with the remainder obtained from dividing\r\n                                                                           ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nComputes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the\r\nST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following\r\nvalue:\r\nRemainder <- ST(0) - (Q * ST(1))\r\nHere, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)]\r\ntoward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is\r\nless than that of the modulus, unless a partial remainder was computed (as described below).\r\nThis instruction produces an exact result; the inexact-result exception does not occur and the rounding control has\r\nno effect. The following table shows the results obtained when computing the remainder of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n                                                      Table 3-31. FPREM Results\r\n                                                                          ST(1)\r\n                                       -inf          -F              -0             +0            +F             +inf            NaN\r\n                   -inf                   *             *             *              *             *              *            NaN\r\n ST(0)              -F             ST(0)        -F or -0           **             **          -F or -0       ST(0)           NaN\r\n                    -0                 -0          -0               *              *            -0             -0            NaN\r\n                   +0                  +0         +0                *              *            +0             +0            NaN\r\n                   +F              ST(0)       +F or +0            **             **         +F or +0        ST(0)           NaN\r\n                   +inf                   *             *             *              *             *              *            NaN\r\n                  NaN                  NaN        NaN              NaN            NaN          NaN            NaN            NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the result is 0, its sign is the same as that of the dividend. When the modulus is inf, the result is equal to the\r\nvalue in ST(0).\r\nThe FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder\r\ncan be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel\r\n8087 and Intel287 math coprocessors.\r\nThe FPREM instruction gets its name \"partial remainder\" because of the way it computes the remainder. This\r\ninstruction arrives at a remainder through iterative subtraction. It can, however, reduce the exponent of ST(0) by\r\nno more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that is\r\nless than the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2\r\nis set, and the result in ST(0) is called the partial remainder. The exponent of the partial remainder will be less\r\nthan the exponent of the original dividend by at least 32. Software can re-execute the instruction (using the partial\r\nremainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing such a remainder-computation\r\nloop, a higher-priority interrupting routine that needs the FPU can force a context switch in-between the instruc-\r\ntions in the loop.)\r\nAn important use of the FPREM instruction is to reduce the arguments of periodic functions. When reduction is\r\ncomplete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU\r\n\r\n\r\n\r\nstatus word. This information is important in argument reduction for the tangent function (using a modulus of pi/4),\r\nbecause it locates the original angle in the correct one of eight sectors of the unit circle.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nD <- exponent(ST(0)) - exponent(ST(1));\r\n\r\nIF D < 64\r\n    THEN\r\n        Q <- Integer(TruncateTowardZero(ST(0) / ST(1)));\r\n        ST(0) <- ST(0) - (ST(1) * Q);\r\n        C2 <- 0;\r\n        C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)\r\n    ELSE\r\n        C2 <- 1;\r\n        N <- An implementation-dependent number between 32 and 63;\r\n        QQ <- Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D - N)));\r\n        ST(0) <- ST(0) - (ST(1) * QQ * 2(D - N));\r\nFI;\r\n\r\nFPU Flags Affected\r\nC0                    Set to bit 2 (Q2) of the quotient.\r\nC1                    Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0).\r\nC2                    Set to 0 if reduction complete; set to 1 if incomplete.\r\nC3                    Set to bit 1 (Q1) of the quotient.\r\n\r\nFloating-Point Exceptions\r\n#IS                   Stack underflow occurred.\r\n#IA                   Source operand is an SNaN value, modulus is 0, dividend is inf, or unsupported format.\r\n#D                    Source operand is a denormal value.\r\n#U                    Result is too small for destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                   If there is a pending x87 FPU exception.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FPREM"
    }, 
    {
      "description": "FPREM1-Partial Remainder\r\n Opcode              Instruction               64-Bit       Compat/       Description\r\n                                               Mode         Leg Mode\r\n D9 F5               FPREM1                    Valid        Valid         Replace ST(0) with the IEEE remainder obtained from dividing\r\n                                                                          ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nComputes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in\r\nthe ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following\r\nvalue:\r\nRemainder <- ST(0) - (Q * ST(1))\r\nHere, Q is an integer value that is obtained by rounding the floating-point number quotient of [ST(0) / ST(1)]\r\ntoward the nearest integer value. The magnitude of the remainder is less than or equal to half the magnitude of the\r\nmodulus, unless a partial remainder was computed (as described below).\r\nThis instruction produces an exact result; the precision (inexact) exception does not occur and the rounding control\r\nhas no effect. The following table shows the results obtained when computing the remainder of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n                                                   Table 3-32. FPREM1 Results\r\n                                                                          ST(1)\r\n                                   -inf             -F                -0            +0             +F            +inf            NaN\r\n                   -inf               *              *                 *             *              *              *           NaN\r\n ST(0)             -F            ST(0)         +-F or -0             **            **         +- F or - 0       ST(0)          NaN\r\n                   -0              -0             -0                 *             *             -0             -0           NaN\r\n                   +0              +0             +0                 *             *             +0             +0           NaN\r\n                   +F            ST(0)         +- F or + 0           **            **         +- F or + 0       ST(0)          NaN\r\n                   +inf               *              *                 *             *              *              *           NaN\r\n                  NaN              NaN           NaN                NaN           NaN           NaN            NaN           NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the result is 0, its sign is the same as that of the dividend. When the modulus is inf, the result is equal to the\r\nvalue in ST(0).\r\nThe FPREM1 instruction computes the remainder specified in IEEE Standard 754. This instruction operates differ-\r\nently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see\r\nthe \"Operation\" section below).\r\nLike the FPREM instruction, FPREM1 computes the remainder through iterative subtraction, but can reduce the\r\nexponent of ST(0) by no more than 63 in one execution of the instruction. If the instruction succeeds in producing\r\na remainder that is less than one half the modulus, the operation is complete and the C2 flag in the FPU status word\r\nis cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder. The exponent of the partial\r\nremainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the\r\ninstruction (using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing\r\nsuch a remainder-computation loop, a higher-priority interrupting routine that needs the FPU can force a context\r\nswitch in-between the instructions in the loop.)\r\nAn important use of the FPREM1 instruction is to reduce the arguments of periodic functions. When reduction is\r\ncomplete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU\r\n\r\n\r\n\r\n\r\nstatus word. This information is important in argument reduction for the tangent function (using a modulus of pi/4),\r\nbecause it locates the original angle in the correct one of eight sectors of the unit circle.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nD <- exponent(ST(0)) - exponent(ST(1));\r\n\r\nIF D < 64\r\n    THEN\r\n        Q <- Integer(RoundTowardNearestInteger(ST(0) / ST(1)));\r\n        ST(0) <- ST(0) - (ST(1) * Q);\r\n        C2 <- 0;\r\n        C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)\r\n    ELSE\r\n        C2 <- 1;\r\n        N <- An implementation-dependent number between 32 and 63;\r\n        QQ <- Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D - N)));\r\n        ST(0) <- ST(0) - (ST(1) * QQ * 2(D - N));\r\nFI;\r\n\r\nFPU Flags Affected\r\nC0                    Set to bit 2 (Q2) of the quotient.\r\nC1                    Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0).\r\nC2                    Set to 0 if reduction complete; set to 1 if incomplete.\r\nC3                    Set to bit 1 (Q1) of the quotient.\r\n\r\nFloating-Point Exceptions\r\n#IS                   Stack underflow occurred.\r\n#IA                   Source operand is an SNaN value, modulus (divisor) is 0, dividend is inf, or unsupported\r\n                      format.\r\n#D                    Source operand is a denormal value.\r\n#U                    Result is too small for destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                   If there is a pending x87 FPU exception.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FPREM1"
    }, 
    {
      "description": "FPTAN-Partial Tangent\r\nOpcode                  Instruction              64-Bit        Compat/    Description\r\n                                                 Mode          Leg Mode\r\nD9 F2                   FPTAN                    Valid         Valid      Replace ST(0) with its approximate tangent and push 1\r\n                                                                          onto the FPU stack.\r\n\r\n\r\n\r\nDescription\r\nComputes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes\r\na 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than +-263. The\r\nfollowing table shows the unmasked results obtained when computing the partial tangent of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n                                                   Table 3-33. FPTAN Results\r\n                           ST(0) SRC                                                      ST(0) DEST\r\n                              -inf                                                               *\r\n                              -F                                                           - F to + F\r\n                              -0                                                              -0\r\n                              +0                                                              +0\r\n                              +F                                                           - F to + F\r\n                              +inf                                                               *\r\n                              NaN                                                            NaN\r\nNOTES:\r\nF Means finite floating-point value.\r\n* Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFPTAN only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThe value 1.0 is pushed onto the register stack after the tangent has been computed to maintain compatibility with\r\nthe Intel 8087 and Intel287 math coprocessors. This operation also simplifies the calculation of other trigonometric\r\nfunctions. For instance, the cotangent (which is the reciprocal of the tangent) can be computed by executing a\r\nFDIVR instruction after the FPTAN instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ST(0) < 263\r\n    THEN\r\n         C2 <- 0;\r\n         ST(0) <- fptan(ST(0)); // approximation of tan\r\n         TOP <- TOP - 1;\r\n         ST(0) <- 1.0;\r\n    ELSE (* Source operand is out-of-range *)\r\n         C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC2                      Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3                  Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow or overflow occurred.\r\n#IA                     Source operand is an SNaN value, inf, or unsupported format.\r\n#D                      Source operand is a denormal value.\r\n#U                      Result is too small for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FPTAN"
    }, 
    {
      "description": "FRNDINT-Round to Integer\r\nOpcode                     Instruction      64-Bit     Compat/      Description\r\n                                            Mode       Leg Mode\r\nD9 FC                      FRNDINT          Valid      Valid        Round ST(0) to an integer.\r\n\r\n\r\n\r\nDescription\r\nRounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding\r\nmode (setting of the RC field of the FPU control word), and stores the result in ST(0).\r\nIf the source value is inf, the value is not changed. If the source value is not an integral value, the floating-point\r\ninexact-result exception (#P) is generated.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- RoundToIntegralValue(ST(0));\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0 if stack underflow occurred.\r\n                       Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3             Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n#IA                    Source operand is an SNaN value or unsupported format.\r\n#D                     Source operand is a denormal value.\r\n#P                     Source operand is not an integral value.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FRNDINT"
    }, 
    {
      "description": "FRSTOR-Restore x87 FPU State\r\nOpcode                Instruction                    64-Bit   Compat/      Description\r\n                                                     Mode     Leg Mode\r\nDD /4                 FRSTOR m94/108byte             Valid    Valid        Load FPU state from m94byte or m108byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the FPU state (operating environment and register stack) from the memory area specified with the source\r\noperand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc-\r\ntion.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following\r\nthe operating environment image.\r\nThe FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE\r\ninstruction.\r\nIf one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be\r\ngenerated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in\r\nthe FPU status word that is being loaded.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC[FPUControlWord];\r\nFPUStatusWord <- SRC[FPUStatusWord];\r\nFPUTagWord <- SRC[FPUTagWord];\r\nFPUDataPointer <- SRC[FPUDataPointer];\r\nFPUInstructionPointer <- SRC[FPUInstructionPointer];\r\nFPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];\r\n\r\nST(0) <- SRC[ST(0)];\r\nST(1) <- SRC[ST(1)];\r\nST(2) <- SRC[ST(2)];\r\nST(3) <- SRC[ST(3)];\r\nST(4) <- SRC[ST(4)];\r\nST(5) <- SRC[ST(5)];\r\nST(6) <- SRC[ST(6)];\r\nST(7) <- SRC[ST(7)];\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, C3 flags are loaded.\r\n\r\nFloating-Point Exceptions\r\nNone; however, this operation might unmask an existing exception that has been detected but not generated,\r\nbecause it was masked. Here, the exception is generated at the completion of the instruction.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                      selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FRSTOR"
    }, 
    {
      "description": "FSAVE/FNSAVE-Store x87 FPU State\r\n Opcode           Instruction                            64-Bit   Compat/    Description\r\n                                                         Mode     Leg Mode\r\n 9B DD /6         FSAVE m94/108byte                      Valid    Valid      Store FPU state to m94byte or m108byte after\r\n                                                                             checking for pending unmasked floating-point\r\n                                                                             exceptions. Then re-initialize the FPU.\r\n DD /6            FNSAVE* m94/108byte                    Valid    Valid      Store FPU environment to m94byte or m108byte\r\n                                                                             without checking for pending unmasked floating-\r\n                                                                             point exceptions. Then re-initialize the FPU.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current FPU state (operating environment and register stack) at the specified destination in memory,\r\nand then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmasked floating-point\r\nexceptions before storing the FPU state; the FNSAVE instruction does not.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately follow\r\nthe operating environment image.\r\nThe saved image reflects the state of the FPU after all floating-point instructions preceding the FSAVE/FNSAVE\r\ninstruction in the instruction stream have been executed.\r\nAfter the FPU state has been saved, the FPU is reset to the same default values it is set to with the FINIT/FNINIT\r\ninstructions (see \"FINIT/FNINIT-Initialize Floating-Point Unit\" in this chapter).\r\nThe FSAVE/FNSAVE instructions are typically used when the operating system needs to perform a context switch,\r\nan exception handler needs to use the FPU, or an application program needs to pass a \"clean\" FPU to a procedure.\r\nThe assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nFor Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be\r\nexecuted before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction. This\r\nFWAIT instruction helps ensure that the storage operation has been completed.\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSAVE instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNSAVE instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n(* Save FPU State and Registers *)\r\n\r\nDEST[FPUControlWord] <- FPUControlWord;\r\nDEST[FPUStatusWord] <- FPUStatusWord;\r\nDEST[FPUTagWord] <- FPUTagWord;\r\nDEST[FPUDataPointer] <- FPUDataPointer;\r\nDEST[FPUInstructionPointer] <- FPUInstructionPointer;\r\nDEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;\r\n\r\nDEST[ST(0)] <- ST(0);\r\nDEST[ST(1)] <- ST(1);\r\nDEST[ST(2)] <- ST(2);\r\nDEST[ST(3)] <- ST(3);\r\nDEST[ST(4)]<- ST(4);\r\nDEST[ST(5)] <- ST(5);\r\nDEST[ST(6)] <- ST(6);\r\nDEST[ST(7)] <- ST(7);\r\n\r\n(* Initialize FPU *)\r\n\r\nFPUControlWord <- 037FH;\r\nFPUStatusWord <- 0;\r\nFPUTagWord <- FFFFH;\r\nFPUDataPointer <- 0;\r\nFPUInstructionPointer <- 0;\r\nFPULastInstructionOpcode <- 0;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 flags are saved and then cleared.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If destination is located in a non-writable segment.\r\n                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                       selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSAVE"
    }, 
    {
      "description": "FSCALE-Scale\r\nOpcode                     Instruction           64-Bit      Compat/       Description\r\n                                                 Mode        Leg Mode\r\nD9 FD                      FSCALE                Valid       Valid         Scale ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nTruncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of\r\nthe destination operand. The destination and source operands are floating-point values located in registers ST(0)\r\nand ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2. The\r\nfollowing table shows the results obtained when scaling various classes of numbers, assuming that neither over-\r\nflow nor underflow occurs.\r\n\r\n\r\n                                                   Table 3-34. FSCALE Results\r\n                   ST(1)\r\n                                         -inf       -F           -0          +0             +F           +inf           NaN\r\n                       -inf            NaN          -inf           -inf          -inf            -inf            -inf           NaN\r\n ST(0)                 -F                -0       -F           -F          -F             -F           -inf           NaN\r\n                       -0                -0       -0           -0          -0             -0           NaN          NaN\r\n                       +0                +0       +0           +0          +0             +0           NaN          NaN\r\n                       +F                +0       +F           +F          +F             +F           +inf           NaN\r\n                       +inf            NaN          +inf           +inf          +inf            +inf            +inf           NaN\r\n                      NaN            NaN          NaN         NaN         NaN            NaN           NaN          NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n\r\nIn most cases, only the exponent is changed and the mantissa (significand) remains unchanged. However, when\r\nthe value being scaled in ST(0) is a denormal value, the mantissa is also changed and the result may turn out to be\r\na normalized number. Similarly, if overflow or underflow results from a scale operation, the resulting mantissa will\r\ndiffer from the source's mantissa.\r\nThe FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following\r\nexample:\r\n     FXTRACT;\r\n     FSCALE;\r\n     FSTP ST(1);\r\nIn this example, the FXTRACT instruction extracts the significand and exponent from the value in ST(0) and stores\r\nthem in ST(0) and ST(1) respectively. The FSCALE then scales the significand in ST(0) by the exponent in ST(1),\r\nrecreating the original value before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites\r\nthe exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its orig-\r\ninal state with only one register [ST(0)] occupied.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- ST(0) * 2RoundTowardZero(ST(1));\r\n\r\nFPU Flags Affected\r\nC1                          Set to 0 if stack underflow occurred.\r\n                            Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3                  Undefined.\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 Source operand is an SNaN value or unsupported format.\r\n#D                  Source operand is a denormal value.\r\n#U                  Result is too small for destination format.\r\n#O                  Result is too large for destination format.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSCALE"
    }, 
    {
      "description": "FSIN-Sine\r\nOpcode                   Instruction             64-Bit        Compat/            Description\r\n                                                 Mode          Leg Mode\r\nD9 FE                    FSIN                    Valid         Valid          Replace ST(0) with the approximate of its sine.\r\n\r\n\r\n\r\nDescription\r\nComputes an approximation of the sine of the source operand in register ST(0) and stores the result in ST(0). The\r\nsource operand must be given in radians and must be within the range -263 to +263. The following table shows the\r\nresults obtained when taking the sine of various classes of numbers, assuming that underflow does not occur.\r\n                                                     Table 3-35. FSIN Results\r\n                           SRC (ST(0))                                                          DEST (ST(0))\r\n                                -inf                                                                    *\r\n                                -F                                                               - 1 to + 1\r\n                                -0                                                                   -0\r\n                                +0                                                                  +0\r\n                                +F                                                                - 1 to +1\r\n                                +inf                                                                    *\r\n                                NaN                                                                 NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFSIN only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/4. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF -263 < ST(0) < 263\r\n    THEN\r\n         C2 <- 0;\r\n         ST(0) <- fsin(ST(0)); // approximation of the mathematical sin function\r\n    ELSE (* Source operand out of range *)\r\n         C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC2                      Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3                  Undefined.\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 Source operand is an SNaN value, inf, or unsupported format.\r\n#D                  Source operand is a denormal value.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSIN"
    }, 
    {
      "description": "FSINCOS-Sine and Cosine\r\n Opcode                   Instruction            64-Bit    Compat/         Description\r\n                                                 Mode      Leg Mode\r\n D9 FB                    FSINCOS                Valid     Valid           Compute the sine and cosine of ST(0); replace ST(0) with the\r\n                                                                           approximate sine, and push the approximate cosine onto the\r\n                                                                           register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes both the approximate sine and the cosine of the source operand in register ST(0), stores the sine in\r\nST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the\r\nFSIN and FCOS instructions in succession.)\r\nThe source operand must be given in radians and must be within the range -263 to +263. The following table shows\r\nthe results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does\r\nnot occur.\r\n                                                   Table 3-36. FSINCOS Results\r\n                    SRC                                                                  DEST\r\n                   ST(0)                                    ST(1) Cosine                                    ST(0) Sine\r\n                    -inf                                              *                                            *\r\n                    -F                                        - 1 to + 1                                     - 1 to + 1\r\n                    -0                                             +1                                           -0\r\n                    +0                                             +1                                           +0\r\n                    +F                                        - 1 to + 1                                     - 1 to + 1\r\n                    +inf                                              *                                            *\r\n                   NaN                                             NaN                                         NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFSINCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ST(0) < 263\r\n    THEN\r\n         C2 <- 0;\r\n         TEMP <- fcos(ST(0)); // approximation of cosine\r\n         ST(0) <- fsin(ST(0)); // approximation of sine\r\n         TOP <- TOP - 1;\r\n         ST(0) <- TEMP;\r\n    ELSE (* Source operand out of range *)\r\n         C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs.\r\n                       Set if result was rounded up; cleared otherwise.\r\nC2                     Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3                 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow or overflow occurred.\r\n#IA                    Source operand is an SNaN value, inf, or unsupported format.\r\n#D                     Source operand is a denormal value.\r\n#U                     Result is too small for destination format.\r\n#P                     Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSINCOS"
    }, 
    {
      "description": "FSQRT-Square Root\r\nOpcode                  Instruction            64-Bit     Compat/         Description\r\n                                               Mode       Leg Mode\r\nD9 FA                   FSQRT                  Valid      Valid           Computes square root of ST(0) and stores the result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nComputes the square root of the source value in the ST(0) register and stores the result in ST(0).\r\nThe following table shows the results obtained when taking the square root of various classes of numbers,\r\nassuming that neither overflow nor underflow occurs.\r\n                                                    Table 3-37. FSQRT Results\r\n                           SRC (ST(0))                                                         DEST (ST(0))\r\n                                -inf                                                                   *\r\n                                -F                                                                   *\r\n                                -0                                                                  -0\r\n                                +0                                                                  +0\r\n                                +F                                                                  +F\r\n                                +inf                                                                  +inf\r\n                              NaN                                                                   NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- SquareRoot(ST(0));\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Source operand is an SNaN value or unsupported format.\r\n                        Source operand is a negative value (except for -0).\r\n#D                      Source operand is a denormal value.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSQRT"
    }, 
    {
      "description": "FST/FSTP-Store Floating Point Value\r\n Opcode                   Instruction         64-Bit   Compat/       Description\r\n                                              Mode     Leg Mode\r\n D9 /2                    FST m32fp           Valid    Valid         Copy ST(0) to m32fp.\r\n DD /2                    FST m64fp           Valid    Valid         Copy ST(0) to m64fp.\r\n DD D0+i                  FST ST(i)           Valid    Valid         Copy ST(0) to ST(i).\r\n D9 /3                    FSTP m32fp          Valid    Valid         Copy ST(0) to m32fp and pop register stack.\r\n DD /3                    FSTP m64fp          Valid    Valid         Copy ST(0) to m64fp and pop register stack.\r\n DB /7                    FSTP m80fp          Valid    Valid         Copy ST(0) to m80fp and pop register stack.\r\n DD D8+i                  FSTP ST(i)          Valid    Valid         Copy ST(0) to ST(i) and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nThe FST instruction copies the value in the ST(0) register to the destination operand, which can be a memory loca-\r\ntion or another register in the FPU register stack. When storing the value in memory, the value is converted to\r\nsingle-precision or double-precision floating-point format.\r\nThe FSTP instruction performs the same operation as the FST instruction and then pops the register stack. To pop\r\nthe register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FSTP instruction can also store values in memory in double extended-precision floating-point format.\r\nIf the destination operand is a memory location, the operand specifies the address where the first byte of the desti-\r\nnation value is to be stored. If the destination operand is a register, the operand specifies a register in the register\r\nstack relative to the top of the stack.\r\nIf the destination size is single-precision or double-precision, the significand of the value being stored is rounded\r\nto the width of the destination (according to the rounding mode specified by the RC field of the FPU control word),\r\nand the exponent is converted to the width and bias of the destination format. If the value being stored is too large\r\nfor the destination format, a numeric overflow exception (#O) is generated and, if the exception is unmasked, no\r\nvalue is stored in the destination operand. If the value being stored is a denormal value, the denormal exception\r\n(#D) is not generated. This condition is simply signaled as a numeric underflow exception (#U) condition.\r\nIf the value being stored is +-0, +-inf, or a NaN, the least-significant bits of the significand and the exponent are trun-\r\ncated to fit the destination format. This operation preserves the value's identity as a 0, inf, or NaN.\r\nIf the destination operand is a non-empty register, the invalid-operation exception is not generated.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- ST(0);\r\n\r\nIF Instruction = FSTP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                       Set to 0 if stack underflow occurred.\r\n                         Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0 <-\r\n                         not roundup; 1 <- roundup.\r\nC0, C2, C3               Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 If destination result is an SNaN value or unsupported format, except when the destination\r\n                    format is in double extended-precision floating-point format.\r\n#U                  Result is too small for the destination format.\r\n#O                  Result is too large for the destination format.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination is located in a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FST"
    }, 
    {
      "description": "FSTCW/FNSTCW-Store x87 FPU Control Word\r\nOpcode               Instruction                    64-Bit   Compat/    Description\r\n                                                    Mode     Leg Mode\r\n9B D9 /7             FSTCW m2byte                   Valid    Valid      Store FPU control word to m2byte after checking for\r\n                                                                        pending unmasked floating-point exceptions.\r\nD9 /7                FNSTCW* m2byte                 Valid    Valid      Store FPU control word to m2byte without checking for\r\n                                                                        pending unmasked floating-point exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current value of the FPU control word at the specified destination in memory. The FSTCW instruction\r\nchecks for and handles pending unmasked floating-point exceptions before storing the control word; the FNSTCW\r\ninstruction does not.\r\nThe assembler issues two instructions for the FSTCW instruction (an FWAIT instruction followed by an FNSTCW\r\ninstruction), and the processor executes each of these instructions in separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTCW instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTCW instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST <- FPUControlWord;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If the destination is located in a non-writable segment.\r\n                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                       selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSTCW"
    }, 
    {
      "description": "FSTENV/FNSTENV-Store x87 FPU Environment\r\n Opcode               Instruction                        64-Bit   Compat/    Description\r\n                                                         Mode     Leg Mode\r\n 9B D9 /6             FSTENV m14/28byte                  Valid    Valid      Store FPU environment to m14byte or m28byte\r\n                                                                             after checking for pending unmasked floating-point\r\n                                                                             exceptions. Then mask all floating-point exceptions.\r\n D9 /6                FNSTENV* m14/28byte                Valid    Valid      Store FPU environment to m14byte or m28byte\r\n                                                                             without checking for pending unmasked floating-\r\n                                                                             point exceptions. Then mask all floating-\r\n                                                                             point exceptions.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nSaves the current FPU operating environment at the memory location specified with the destination operand, and\r\nthen masks all floating-point exceptions. The FPU operating environment consists of the FPU control word, status\r\nword, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, show the layout in memory of the stored environ-\r\nment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute\r\n(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.\r\nThe FSTENV instruction checks for and handles any pending unmasked floating-point exceptions before storing\r\nthe FPU environment; the FNSTENV instruction does not. The saved image reflects the state of the FPU after all\r\nfloating-point instructions preceding the FSTENV/FNSTENV instruction in the instruction stream have been\r\nexecuted.\r\nThese instructions are often used by exception handlers because they provide access to the FPU instruction and\r\ndata pointers. The environment is typically saved in the stack. Masking all exceptions after saving the environment\r\nprevents floating-point exceptions from interrupting the exception handler.\r\nThe assembler issues two instructions for the FSTENV instruction (an FWAIT instruction followed by an FNSTENV\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTENV instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST[FPUControlWord] <- FPUControlWord;\r\nDEST[FPUStatusWord] <- FPUStatusWord;\r\nDEST[FPUTagWord] <- FPUTagWord;\r\nDEST[FPUDataPointer] <- FPUDataPointer;\r\nDEST[FPUInstructionPointer] <- FPUInstructionPointer;\r\nDEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 are undefined.\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination is located in a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSTENV"
    }, 
    {
      "description": "-R:FST", 
      "mnem": "FSTP"
    }, 
    {
      "description": "FSTSW/FNSTSW-Store x87 FPU Status Word\r\nOpcode               Instruction                    64-Bit      Compat/    Description\r\n                                                    Mode        Leg Mode\r\n9B DD /7             FSTSW m2byte                       Valid   Valid      Store FPU status word at m2byte after checking\r\n                                                                           for pending unmasked floating-point exceptions.\r\n9B DF E0             FSTSW AX                           Valid   Valid      Store FPU status word in AX register after\r\n                                                                           checking for pending unmasked floating-point\r\n                                                                           exceptions.\r\nDD /7                FNSTSW* m2byte                     Valid   Valid      Store FPU status word at m2byte without\r\n                                                                           checking for pending unmasked floating-point\r\n                                                                           exceptions.\r\nDF E0                FNSTSW* AX                         Valid   Valid      Store FPU status word in AX register without\r\n                                                                           checking for pending unmasked floating-point\r\n                                                                           exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current value of the x87 FPU status word in the destination location. The destination operand can be\r\neither a two-byte memory location or the AX register. The FSTSW instruction checks for and handles pending\r\nunmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.\r\nThe FNSTSW AX form of the instruction is used primarily in conditional branching (for instance, after an FPU\r\ncomparison instruction or an FPREM, FPREM1, or FXAM instruction), where the direction of the branch depends on\r\nthe state of the FPU condition code flags. (See the section titled \"Branching and Conditional Moves on FPU Condi-\r\ntion Codes\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1.) This\r\ninstruction can also be used to invoke exception handlers (by examining the exception flags) in environments that\r\ndo not use interrupts. When the FNSTSW AX instruction is executed, the AX register is updated before the\r\nprocessor executes any further instructions. The status stored in the AX register is thus guaranteed to be from the\r\ncompletion of the prior FPU instruction.\r\nThe assembler issues two instructions for the FSTSW instruction (an FWAIT instruction followed by an FNSTSW\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTSW instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST <- FPUStatusWord;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination is located in a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSTSW"
    }, 
    {
      "description": "FSUB/FSUBP/FISUB-Subtract\r\nOpcode             Instruction               64-Bit      Compat/       Description\r\n                                             Mode        Leg Mode\r\nD8 /4              FSUB m32fp                Valid       Valid         Subtract m32fp from ST(0) and store result in ST(0).\r\nDC /4              FSUB m64fp                Valid       Valid         Subtract m64fp from ST(0) and store result in ST(0).\r\nD8 E0+i            FSUB ST(0), ST(i)         Valid       Valid         Subtract ST(i) from ST(0) and store result in ST(0).\r\nDC E8+i            FSUB ST(i), ST(0)         Valid       Valid         Subtract ST(0) from ST(i) and store result in ST(i).\r\nDE E8+i            FSUBP ST(i), ST(0)        Valid       Valid         Subtract ST(0) from ST(i), store result in ST(i), and\r\n                                                                       pop register stack.\r\nDE E9              FSUBP                     Valid       Valid         Subtract ST(0) from ST(1), store result in ST(1), and\r\n                                                                       pop register stack.\r\nDA /4              FISUB m32int              Valid       Valid         Subtract m32int from ST(0) and store result in ST(0).\r\nDE /4              FISUB m16int              Valid       Valid         Subtract m16int from ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nSubtracts the source operand from the destination operand and stores the difference in the destination location.\r\nThe destination operand is always an FPU data register; the source operand can be a register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction subtracts the contents of the ST(0) register from the ST(1) register and\r\nstores the result in ST(1). The one-operand version subtracts the contents of a memory location (either a floating-\r\npoint or an integer value) from the contents of the ST(0) register and stores the result in ST(0). The two-operand\r\nversion, subtracts the contents of the ST(0) register from the ST(i) register or vice versa.\r\nThe FSUBP instructions perform the additional operation of popping the FPU register stack following the subtrac-\r\ntion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer\r\n(TOP) by 1. The no-operand version of the floating-point subtract instructions always results in the register stack\r\nbeing popped. In some assemblers, the mnemonic for this instruction is FSUB rather than FSUBP.\r\nThe FISUB instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the subtraction.\r\nTable 3-38 shows the results obtained when subtracting various classes of numbers from one another, assuming\r\nthat neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST - SRC =\r\nresult).\r\nWhen the difference between two operands of like sign is 0, the result is +0, except for the round toward -inf mode,\r\nin which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the\r\nsource operand is an integer 0, it is treated as a +0.\r\nWhen one operand is inf, the result is inf of the expected sign. If both operands are inf of the same sign, an invalid-\r\noperation exception is generated.\r\n\r\n\r\n\r\n\r\n\r\n                                            Table 3-38. FSUB/FSUBP/FISUB Results\r\n                                                                          SRC\r\n                                  -inf           - F or - I        -0             +0     + F or + I    +inf            NaN\r\n                   -inf              *             -inf              -inf             -inf       -inf          -inf            NaN\r\n                   -F             +inf           +-F or +-0         DEST            DEST      -F         -inf            NaN\r\n DEST              -0             +inf            -SRC              +-0            -0      - SRC        -inf            NaN\r\n                   +0             +inf            -SRC             +0              +-0     - SRC        -inf            NaN\r\n                   +F             +inf              +F            DEST            DEST   +-F or +-0      -inf            NaN\r\n                   +inf             +inf             +inf              +inf             +inf       +inf            *           NaN\r\n                  NaN            NaN             NaN             NaN            NaN      NaN         NaN           NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FISUB\r\n     THEN\r\n         DEST <- DEST - ConvertToDoubleExtendedPrecisionFP(SRC);\r\n     ELSE (* Source operand is floating-point value *)\r\n         DEST <- DEST - SRC;\r\nFI;\r\n\r\nIF Instruction = FSUBP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Operand is an SNaN value or unsupported format.\r\n                        Operands are infinities of like sign.\r\n#D                      Source operand is a denormal value.\r\n#U                      Result is too small for destination format.\r\n#O                      Result is too large for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                      selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                   If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#NM                   CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                   If there is a pending x87 FPU exception.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSUB"
    }, 
    {
      "description": "-R:FSUB", 
      "mnem": "FSUBP"
    }, 
    {
      "description": "FSUBR/FSUBRP/FISUBR-Reverse Subtract\r\n Opcode           Instruction                   64-Bit    Compat/      Description\r\n                                                Mode      Leg Mode\r\n D8 /5            FSUBR m32fp                   Valid     Valid        Subtract ST(0) from m32fp and store result in ST(0).\r\n DC /5            FSUBR m64fp                   Valid     Valid        Subtract ST(0) from m64fp and store result in ST(0).\r\n D8 E8+i          FSUBR ST(0), ST(i)            Valid     Valid        Subtract ST(0) from ST(i) and store result in ST(0).\r\n DC E0+i          FSUBR ST(i), ST(0)            Valid     Valid        Subtract ST(i) from ST(0) and store result in ST(i).\r\n DE E0+i          FSUBRP ST(i), ST(0)           Valid     Valid        Subtract ST(i) from ST(0), store result in ST(i), and\r\n                                                                       pop register stack.\r\n DE E1            FSUBRP                        Valid     Valid        Subtract ST(1) from ST(0), store result in ST(1), and\r\n                                                                       pop register stack.\r\n DA /5            FISUBR m32int                 Valid     Valid        Subtract ST(0) from m32int and store result in ST(0).\r\n DE /5            FISUBR m16int                 Valid     Valid        Subtract ST(0) from m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nSubtracts the destination operand from the source operand and stores the difference in the destination location.\r\nThe destination operand is always an FPU register; the source operand can be a register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThese instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions. They are provided\r\nto support more efficient coding.\r\nThe no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and\r\nstores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents\r\nof a memory location (either a floating-point or an integer value) and stores the result in ST(0). The two-operand\r\nversion, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.\r\nThe FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtrac-\r\ntion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer\r\n(TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register\r\nstack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.\r\nThe FISUBR instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the subtraction.\r\nThe following table shows the results obtained when subtracting various classes of numbers from one another,\r\nassuming that neither overflow nor underflow occurs. Here, the DEST value is subtracted from the SRC value (SRC\r\n- DEST = result).\r\nWhen the difference between two operands of like sign is 0, the result is +0, except for the round toward -inf mode,\r\nin which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the\r\nsource operand is an integer 0, it is treated as a +0.\r\nWhen one operand is inf, the result is inf of the expected sign. If both operands are inf of the same sign, an invalid-\r\noperation exception is generated.\r\n\r\n\r\n\r\n\r\n\r\n                                         Table 3-39. FSUBR/FSUBRP/FISUBR Results\r\n                                                                          SRC\r\n                                  -inf           -F or -I           -0             +0     +F or +I       +inf           NaN\r\n                   -inf              *              +inf             +inf              +inf       +inf           +inf           NaN\r\n                   -F             -inf           +-F or +-0        -DEST            -DEST     +F           +inf           NaN\r\n DEST              -0             -inf             SRC              +-0             +0      SRC           +inf           NaN\r\n                   +0             -inf             SRC              -0             +-0      SRC           +inf           NaN\r\n                   +F             -inf              -F           -DEST            -DEST   +-F or +-0       +inf           NaN\r\n                   +inf             -inf              -inf             -inf              -inf       -inf             *          NaN\r\n                  NaN            NaN             NaN             NaN            NaN      NaN           NaN          NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FISUBR\r\n     THEN\r\n         DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) - DEST;\r\n     ELSE (* Source operand is floating-point value *)\r\n         DEST <- SRC - DEST; FI;\r\nIF Instruction = FSUBRP\r\n     THEN\r\n         PopRegisterStack; FI;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred.\r\n                        Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow occurred.\r\n#IA                     Operand is an SNaN value or unsupported format.\r\n                        Operands are infinities of like sign.\r\n#D                      Source operand is a denormal value.\r\n#U                      Result is too small for destination format.\r\n#O                      Result is too large for destination format.\r\n#P                      Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FSUBR"
    }, 
    {
      "description": "-R:FSUBR", 
      "mnem": "FSUBRP"
    }, 
    {
      "description": "FTST-TEST\r\nOpcode                    Instruction           64-Bit    Compat/         Description\r\n                                                Mode      Leg Mode\r\nD9 E4                     FTST                  Valid     Valid           Compare ST(0) with 0.0.\r\n\r\n\r\n\r\nDescription\r\nCompares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU\r\nstatus word according to the results (see table below).\r\n                                               Table 3-40. FTST Results\r\n                      Condition                              C3                    C2                      C0\r\n                     ST(0) > 0.0                             0                     0                       0\r\n                     ST(0) < 0.0                             0                     0                       1\r\n                     ST(0) = 0.0                             1                     0                       0\r\n                     Unordered                               1                     1                       1\r\n\r\nThis instruction performs an \"unordered comparison.\" An unordered comparison also checks the class of the\r\nnumbers being compared (see \"FXAM-Examine Floating-Point\" in this chapter). If the value in register ST(0) is a\r\nNaN or is in an undefined format, the condition flags are set to \"unordered\" and the invalid operation exception is\r\ngenerated.\r\nThe sign of zero is ignored, so that (- 0.0 <- +0.0).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n   Not comparable: C3, C2, C0 <- 111;\r\n   ST(0) > 0.0:       C3, C2, C0 <- 000;\r\n   ST(0) < 0.0:       C3, C2, C0 <- 001;\r\n   ST(0) = 0.0:       C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0.\r\nC0, C2, C3             See Table 3-40.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n#IA                    The source operand is a NaN value or is in an unsupported format.\r\n#D                     The source operand is a denormal value.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FTST"
    }, 
    {
      "description": "FUCOM/FUCOMP/FUCOMPP-Unordered Compare Floating Point Values\r\nOpcode                Instruction               64-Bit       Compat/      Description\r\n                                                Mode         Leg Mode\r\nDD E0+i               FUCOM ST(i)               Valid        Valid        Compare ST(0) with ST(i).\r\nDD E1                 FUCOM                     Valid        Valid        Compare ST(0) with ST(1).\r\nDD E8+i               FUCOMP ST(i)              Valid        Valid        Compare ST(0) with ST(i) and pop register stack.\r\nDD E9                 FUCOMP                    Valid        Valid        Compare ST(0) with ST(1) and pop register stack.\r\nDA E9                 FUCOMPP                   Valid        Valid        Compare ST(0) with ST(1) and pop register stack twice.\r\n\r\n\r\n\r\nDescription\r\nPerforms an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2,\r\nand C3 in the FPU status word according to the results (see the table below). If no operand is specified, the\r\ncontents of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that -0.0 is equal to +0.0.\r\n                                        Table 3-41. FUCOM/FUCOMP/FUCOMPP Results\r\n                     Comparison Results*                                   C3                     C2                    C0\r\n                          ST0 > ST(i)                                       0                      0                     0\r\n                          ST0 < ST(i)                                       0                      0                     1\r\n                          ST0 = ST(i)                                       1                      0                     0\r\n                           Unordered                                        1                      1                     1\r\n NOTES:\r\n * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nAn unordered comparison checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\"\r\nin this chapter). The FUCOM/FUCOMP/FUCOMPP instructions perform the same operations as the\r\nFCOM/FCOMP/FCOMPP instructions. The only difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise\r\nthe invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsup-\r\nported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be\r\ngenerated. The FCOM/FCOMP/FCOMPP instructions raise an invalid-operation exception when either or both of the\r\noperands are a NaN value of any kind or are in an unsupported format.\r\nAs with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalid-arithmetic-operand exception\r\nbeing raised, the condition code flags are set only if the exception is masked.\r\nThe FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction\r\npops the register stack twice following the comparison operation. To pop the register stack, the processor marks\r\nthe ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n   ST > SRC:          C3, C2, C0 <- 000;\r\n   ST < SRC:          C3, C2, C0 <- 001;\r\n   ST = SRC:          C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nIF ST(0) or SRC = QNaN, but not SNaN or unsupported format\r\n    THEN\r\n         C3, C2, C0 <- 111;\r\n    ELSE (* ST(0) or SRC is SNaN or unsupported format *)\r\n          #IA;\r\n         IF FPUControlWord.IM = 1\r\n               THEN\r\n                   C3, C2, C0 <- 111;\r\n         FI;\r\nFI;\r\n\r\nIF Instruction = FUCOMP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nIF Instruction = FUCOMPP\r\n     THEN\r\n         PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0 if stack underflow occurred.\r\nC0, C2, C3             See Table 3-41.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n#IA                    One or both operands are SNaN values or have unsupported formats. Detection of a QNaN\r\n                       value in and of itself does not raise an invalid-operand exception.\r\n#D                     One or both operands are denormal values.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FUCOM"
    }, 
    {
      "description": "-R:FCOMI", 
      "mnem": "FUCOMI"
    }, 
    {
      "description": "-R:FCOMI", 
      "mnem": "FUCOMIP"
    }, 
    {
      "description": "-R:FUCOM", 
      "mnem": "FUCOMP"
    }, 
    {
      "description": "-R:FUCOM", 
      "mnem": "FUCOMPP"
    }, 
    {
      "description": "-R:WAIT", 
      "mnem": "FWAIT"
    }, 
    {
      "description": "FXAM-Examine Floating-Point\r\n    Opcode                 Instruction              64-Bit     Compat/       Description\r\n                                                    Mode       Leg Mode\r\n    D9 E5                  FXAM                     Valid       Valid        Classify value or number in ST(0).\r\n\r\n\r\n\r\nDescription\r\nExamines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word\r\nto indicate the class of value or number in the register (see the table below).\r\n                                                       Table 3-42. FXAM Results\r\n.\r\n\r\n\r\n\r\n\r\n                             Class                                      C3                   C2                      C0\r\n    Unsupported                                                         0                     0                      0\r\n    NaN                                                                 0                     0                      1\r\n    Normal finite number                                                0                     1                      0\r\n    Infinity                                                            0                     1                      1\r\n    Zero                                                                1                     0                      0\r\n    Empty                                                               1                     0                      1\r\n    Denormal number                                                     1                     1                      0\r\n\r\nThe C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nC1 <- sign bit of ST; (* 0 for positive, 1 for negative *)\r\n\r\nCASE (class of value or number in ST(0)) OF\r\n   Unsupported:C3, C2, C0 <- 000;\r\n   NaN:           C3, C2, C0 <- 001;\r\n   Normal:        C3, C2, C0 <- 010;\r\n   Infinity:      C3, C2, C0 <- 011;\r\n   Zero:          C3, C2, C0 <- 100;\r\n   Empty:         C3, C2, C0 <- 101;\r\n   Denormal:      C3, C2, C0 <- 110;\r\nESAC;\r\n\r\nFPU Flags Affected\r\nC1                         Sign of value in ST(0).\r\nC0, C2, C3                 See Table 3-42.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM                        CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                        If there is a pending x87 FPU exception.\r\n#UD                        If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FXAM"
    }, 
    {
      "description": "FXCH-Exchange Register Contents\r\nOpcode                  Instruction         64-Bit    Compat/       Description\r\n                                            Mode      Leg Mode\r\nD9 C8+i                 FXCH ST(i)          Valid     Valid         Exchange the contents of ST(0) and ST(i).\r\nD9 C9                   FXCH                Valid     Valid         Exchange the contents of ST(0) and ST(1).\r\n\r\n\r\n\r\nDescription\r\nExchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and\r\nST(1) are exchanged.\r\nThis instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)],\r\nso that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For\r\nexample, the following instruction sequence takes the square root of the third register from the top of the register\r\nstack:\r\n     FXCH ST(3);\r\n     FSQRT;\r\n     FXCH ST(3);\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF (Number-of-operands) is 1\r\n    THEN\r\n        temp <- ST(0);\r\n        ST(0) <- SRC;\r\n        SRC <- temp;\r\n    ELSE\r\n        temp <- ST(0);\r\n        ST(0) <- ST(1);\r\n        ST(1) <- temp;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1                     Set to 0.\r\nC0, C2, C3             Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                    Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                    If there is a pending x87 FPU exception.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FXCH"
    }, 
    {
      "description": "FXRSTOR-Restore x87 FPU, MMX, XMM, and MXCSR State\r\n Opcode/                                         Op/     64-Bit   Compat/ Description\r\n Instruction                                     En      Mode     Leg Mode\r\n 0F AE /1                                        M       Valid    Valid        Restore the x87 FPU, MMX, XMM, and MXCSR\r\n FXRSTOR m512byte                                                              register state from m512byte.\r\n\r\n REX.W+ 0F AE /1                                 M       Valid    N.E.         Restore the x87 FPU, MMX, XMM, and MXCSR\r\n FXRSTOR64 m512byte                                                            register state from m512byte.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n   Op/En            Operand 1                Operand 2                    Operand 3                     Operand 4\r\n     M             ModRM:r/m (r)                 NA                           NA                           NA\r\n\r\nDescription\r\nReloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in\r\nthe source operand. This data should have been written to memory previously using the FXSAVE instruction, and\r\nin the same format as required by the operating modes. The first byte of the data should be located on a 16-byte\r\nboundary. There are three distinct layouts of the FXSAVE state map: one for legacy and compatibility mode, a\r\nsecond format for 64-bit mode FXSAVE/FXRSTOR with REX.W=0, and the third format is for 64-bit mode with\r\nFXSAVE64/FXRSTOR64. Table 3-43 shows the layout of the legacy/compatibility mode state information in memory\r\nand describes the fields in the memory image for the FXRSTOR and FXSAVE instructions. Table 3-46 shows the\r\nlayout of the 64-bit mode state information when REX.W is set (FXSAVE64/FXRSTOR64). Table 3-47 shows the\r\nlayout of the 64-bit mode state information when REX.W is clear (FXSAVE/FXRSTOR).\r\nThe state image referenced with an FXRSTOR instruction must have been saved using an FXSAVE instruction or be\r\nin the same format as required by Table 3-43, Table 3-46, or Table 3-47. Referencing a state image saved with an\r\nFSAVE, FNSAVE instruction or incompatible field layout will result in an incorrect state restoration.\r\nThe FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and raise exceptions when loading\r\nx87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.\r\nIf the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not restore the states of the XMM\r\nand MXCSR registers. This behavior is implementation dependent.\r\nIf the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register\r\nwith the FXRSTOR instruction will not result in a SIMD floating-point error condition being generated. Only the next\r\noccurrence of this unmasked exception will result in the exception being generated.\r\nBits 16 through 32 of the MXCSR register are defined as reserved and should be set to 0. Attempting to write a 1 in\r\nany of these bits from the saved state image will result in a general protection exception (#GP) being generated.\r\nBytes 464:511 of an FXSAVE image are available for software use. FXRSTOR ignores the content of bytes 464:511\r\nin an FXSAVE state image.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n        (x87 FPU, MMX, XMM15-XMM0, MXCSR) Load(SRC);\r\n    ELSE\r\n         (x87 FPU, MMX, XMM7-XMM0, MXCSR) <- Load(SRC);\r\nFI;\r\n\r\nx87 FPU and SIMD Floating-Point Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n                       If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See align-\r\n                       ment check exception [#AC] below.)\r\n                       For an attempt to set reserved bits in MXCSR.\r\n#SS(0)                 For an illegal address in the SS segment.\r\n#PF(fault-code)        For a page fault.\r\n#NM                    If CR0.TS[bit 3] = 1.\r\n                       If CR0.EM[bit 2] = 1.\r\n#UD                    If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n                       If instruction is preceded by a LOCK prefix.\r\n#AC                    If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n                       operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n                       exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n                       vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n                       general protection exception is signaled in its place. In addition, the width of the alignment\r\n                       check may also vary with implementation. For instance, for a given implementation, an align-\r\n                       ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n                       tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n                       misalignments).\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n                       If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n                       For an attempt to set reserved bits in MXCSR.\r\n#NM                    If CR0.TS[bit 3] = 1.\r\n                       If CR0.EM[bit 2] = 1.\r\n#UD                    If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n                       If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code)        For a page fault.\r\n#AC                    For unaligned memory reference.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n                    If memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n                    For an attempt to set reserved bits in MXCSR.\r\n#PF(fault-code)     For a page fault.\r\n#NM                 If CR0.TS[bit 3] = 1.\r\n                    If CR0.EM[bit 2] = 1.\r\n#UD                 If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n                    If instruction is preceded by a LOCK prefix.\r\n#AC                 If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n                    operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n                    exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n                    vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n                    general protection exception is signaled in its place. In addition, the width of the alignment\r\n                    check may also vary with implementation. For instance, for a given implementation, an align-\r\n                    ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n                    tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n                    misalignments).\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FXRSTOR"
    }, 
    {
      "description": "FXSAVE-Save x87 FPU, MMX Technology, and SSE State\r\n Opcode/                                                Op/      64-Bit       Compat/ Description\r\n Instruction            … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "FXSAVE"
    }, 
    {
      "description": "FXTRACT-Extract Exponent and Significand\r\n Opcode/                                       64-Bit   Compat/    Description\r\n Instruction                                   Mode     Leg Mode\r\n D9 F4                                         Valid    Valid      Separate value in ST(0) into exponent and significand, store\r\n FXTRACT                                                           exponent in ST(0), and push the significand onto the register\r\n                                                                   stack.\r\n\r\n\r\n\r\nDescription\r\nSeparates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0),\r\nand pushes the significand onto the register stack. Following this operation, the new top-of-stack register ST(0)\r\ncontains the value of the original significand expressed as a floating-point value. The sign and significand of this\r\nvalue are the same as those found in the source operand, and the exponent is 3FFFH (biased value for a true expo-\r\nnent of zero). The ST(1) register contains the value of the original operand's true (unbiased) exponent expressed\r\nas a floating-point value. (The operation performed by this instruction is a superset of the IEEE-recommended\r\nlogb(x) function.)\r\nThis instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The\r\nFXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to\r\ndecimal representations (e.g., for printing or displaying).\r\nIf the floating-point zero-divide exception (#Z) is masked and the source operand is zero, an exponent value of -\r\ninf is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTEMP <- Significand(ST(0));\r\nST(0) <- Exponent(ST(0));\r\nTOP<- TOP - 1;\r\nST(0) <- TEMP;\r\n\r\nFPU Flags Affected\r\nC1                      Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.\r\nC0, C2, C3              Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                     Stack underflow or overflow occurred.\r\n#IA                     Source operand is an SNaN value or unsupported format.\r\n#Z                      ST(0) operand is +-0.\r\n#D                      Source operand is a denormal value.\r\n\r\nProtected Mode Exceptions\r\n#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                     If there is a pending x87 FPU exception.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FXTRACT"
    }, 
    {
      "description": "FYL2X-Compute y * log2x\r\nOpcode                   Instruction             64-Bit           Compat/           Description\r\n                                                 Mode             Leg Mode\r\nD9 F1                    FYL2X                   Valid            Valid             Replace ST(1) with (ST(1) * log2ST(0)) and pop the\r\n                                                                                    register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes (ST(1) * log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source\r\noperand in ST(0) must be a non-zero positive number.\r\nThe following table shows the results obtained when taking the log of various classes of numbers, assuming that\r\nneither overflow nor underflow occurs.\r\n                                                    Table 3-48. FYL2X Results\r\n                                                                            ST(0)\r\n                                 -inf         -F            +-0              +0<+F<+1            +1        +F>+1           +inf           NaN\r\n\r\n                   -inf             *          *            +inf                 +inf                   *        -inf           -inf           NaN\r\n\r\n     ST(1)         -F             *          *            **                 +F               -0           -F           -inf           NaN\r\n\r\n                   -0             *          *                *              +0               -0           -0             *          NaN\r\n\r\n                   +0             *          *                *              -0               +0           +0             *          NaN\r\n\r\n                   +F             *          *            **                 -F               +0           +F           +inf           NaN\r\n\r\n                   +inf             *          *            -   inf              -inf                   *        +inf           +inf           NaN\r\n\r\n                   NaN           NaN       NaN            NaN                NaN              NaN          NaN          NaN          NaN\r\n\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\n\r\nIf the divide-by-zero exception is masked and register ST(0) contains +-0, the instruction returns inf with a sign that\r\nis the opposite of the sign of the source operand in register ST(1).\r\nThe FYL2X instruction is designed with a built-in multiplication to optimize the calculation of logarithms with an\r\narbitrary positive base (b):\r\n\r\n     logbx <- (log2b)-1 * log2x\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(1) <- ST(1) * log2ST(0);\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1                        Set to 0 if stack underflow occurred.\r\n                          Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3                Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS                 Stack underflow occurred.\r\n#IA                 Either operand is an SNaN or unsupported format.\r\n                    Source operand in register ST(0) is a negative finite value\r\n                    (not -0).\r\n#Z                  Source operand in register ST(0) is +-0.\r\n#D                  Source operand is a denormal value.\r\n#U                  Result is too small for destination format.\r\n#O                  Result is too large for destination format.\r\n#P                  Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                 If there is a pending x87 FPU exception.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FYL2X"
    }, 
    {
      "description": "FYL2XP1-Compute y * log2(x +1)\r\n Opcode                   Instruction              64-Bit        Compat/             Description\r\n                                                   Mode          Leg Mode\r\n D9 F9                    FYL2XP1                  Valid         Valid               Replace ST(1) with ST(1) * log2(ST(0) + 1.0) and pop the\r\n                                                                                     register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes (ST(1) * log2(ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The\r\nsource operand in ST(0) must be in the range:\r\n     - ( 1 - 2 / 2 ) )to ( 1 - 2 / 2 )\r\nThe source operand in ST(1) can range from -inf to +inf. If the ST(0) operand is outside of its acceptable range, the\r\nresult is undefined and software should not rely on an exception being generated. Under some circumstances\r\nexceptions may be generated when ST(0) is out of range, but this behavior is implementation specific and not\r\nguaranteed.\r\nThe following table shows the results obtained when taking the log epsilon of various classes of numbers, assuming\r\nthat underflow does not occur.\r\n                                                     Table 3-49. FYL2XP1 Results\r\n                                                                             ST(0)\r\n                                     -(1 - ( 2 / 2 )) to -0          -0              +0             +0 to +(1 - ( 2 / 2 ))          NaN\r\n                     -inf                       +inf                         *            *                     -inf                      NaN\r\n     ST(1)           -F                       +F                     +0               -0                     -F                     NaN\r\n                     -0                       +0                     +0               -0                     -0                     NaN\r\n                     +0                       -0                    -0               +0                      +0                     NaN\r\n                     +F                       -F                    -0               +0                      +F                     NaN\r\n                     +inf                       -inf                         *            *                     +inf                      NaN\r\n                    NaN                      NaN                    NaN              NaN                    NaN                     NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n\r\nThis instruction provides optimal accuracy for values of epsilon [the value in register ST(0)] that are close to 0. For\r\nsmall epsilon (e) values, more significant digits can be retained by using the FYL2XP1 instruction than by using\r\n(e+1) as an argument to the FYL2X instruction. The (e+1) expression is commonly found in compound interest and\r\nannuity calculations. The result can be simply converted into a value in another logarithm base by including a scale\r\nfactor in the ST(1) source operand. The following equation is used to calculate the scale factor for a particular loga-\r\nrithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction:\r\n\r\n   scale factor <- logn 2\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(1) <- ST(1) * log2(ST(0) + 1.0);\r\nPopRegisterStack;\r\n\r\n\r\n\r\n\r\n\r\nFPU Flags Affected\r\nC1                   Set to 0 if stack underflow occurred.\r\n                     Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3           Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS                  Stack underflow occurred.\r\n#IA                  Either operand is an SNaN value or unsupported format.\r\n#D                   Source operand is a denormal value.\r\n#U                   Result is too small for destination format.\r\n#O                   Result is too large for destination format.\r\n#P                   Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF                  If there is a pending x87 FPU exception.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "FYL2XP1"
    }, 
    {
      "description": "HADDPD-Packed Double-FP Horizontal Add\r\n Opcode/                                              Op/      64/32-bit CPUID            Description\r\n Instruction                                          En       Mode      Feature\r\n                                                                         Flag\r\n 66 0F 7C /r                                          RM       V/V        SSE3            Horizontal add packed double-precision\r\n HADDPD xmm1, xmm2/m128                                                                   floating-point values from xmm2/m128 to\r\n                                                                                          xmm1.\r\n VEX.NDS.128.66.0F.WIG 7C /r                          RVM V/V             AVX             Horizontal add packed double-precision\r\n VHADDPD xmm1,xmm2, xmm3/m128                                                             floating-point values from xmm2 and\r\n                                                                                          xmm3/mem.\r\n VEX.NDS.256.66.0F.WIG 7C /r                          RVM V/V             AVX             Horizontal add packed double-precision\r\n VHADDPD ymm1, ymm2, ymm3/m256                                                            floating-point values from ymm2 and\r\n                                                                                          ymm3/mem.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En             Operand 1                    Operand 2                       Operand 3                           Operand 4\r\n    RM           ModRM:reg (r, w)              ModRM:r/m (r)                             NA                             NA\r\n   RVM            ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                             NA\r\n\r\nDescription\r\nAdds the double-precision floating-point values in the high and low quadwords of the destination operand and\r\nstores the result in the low quadword of the destination operand.\r\nAdds the double-precision floating-point values in the high and low quadwords of the source operand and stores the\r\nresult in the high quadword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nSee Figure 3-16 for HADDPD; see Figure 3-17 for VHADDPD.\r\n\r\n\r\n\r\n\r\n                                                 HADDPD xmm1, xmm2/m128\r\n\r\n                                                                                                         xmm2\r\n                                          [127:64]                              [63:0]\r\n                                                                                                         /m128\r\n\r\n\r\n\r\n\r\n                                          [127:64]                              [63:0]                   xmm1\r\n\r\n\r\n\r\n\r\n                                     xmm2/m128[63:0] +                                                   Result:\r\n                                                                     xmm1[63:0] + xmm1[127:64]\r\n                                     xmm2/m128[127:64]                                                   xmm1\r\n\r\n                                          [127:64]                               [63:0]\r\n\r\n\r\n                                                                                                           OM15993\r\n\r\n\r\n\r\n                                  Figure 3-16. HADDPD-Packed Double-FP Horizontal Add\r\n\r\n\r\n\r\n\r\n\r\n                       SRC1         X3               X2             X1            X0\r\n\r\n\r\n\r\n                       SRC2         Y3               Y2             Y1            Y0\r\n\r\n\r\n\r\n                       DEST      Y2 + Y3          X2 + X3        Y0 + Y1       X0 + X1\r\n\r\n\r\n\r\n\r\n                                            Figure 3-17. VHADDPD operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nHADDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHADDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHADDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[191:128] <- SRC1[255:192] + SRC1[191:128]\r\nDEST[255:192] <- SRC2[255:192] + SRC2[191:128]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVHADDPD: __m256d _mm256_hadd_pd (__m256d a, __m256d b);\r\n\r\nHADDPD:      __m128d _mm_hadd_pd (__m128d a, __m128d b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\n\r\n\r\n\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "HADDPD"
    }, 
    {
      "description": "HADDPS-Packed Single-FP Horizontal Add\r\nOpcode/                                         Op/    64/32-bit CPUID       Description\r\nInstruction                                     En     Mode      Feature\r\n                                                                 Flag\r\nF2 0F 7C /r                                     RM     V/V       SSE3        Horizontal add packed single-precision\r\nHADDPS xmm1, xmm2/m128                                                       floating-point values from xmm2/m128 to\r\n                                                                             xmm1.\r\nVEX.NDS.128.F2.0F.WIG 7C /r                     RVM V/V          AVX         Horizontal add packed single-precision\r\nVHADDPS xmm1, xmm2, xmm3/m128                                                floating-point values from xmm2 and\r\n                                                                             xmm3/mem.\r\nVEX.NDS.256.F2.0F.WIG 7C /r                     RVM V/V          AVX         Horizontal add packed single-precision\r\nVHADDPS ymm1, ymm2, ymm3/m256                                                floating-point values from ymm2 and\r\n                                                                             ymm3/mem.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n   Op/En            Operand 1                  Operand 2                   Operand 3                     Operand 4\r\n     RM          ModRM:reg (r, w)            ModRM:r/m (r)                    NA                            NA\r\n    RVM           ModRM:reg (w)               VEX.vvvv (r)              ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nAdds the single-precision floating-point values in the first and second dwords of the destination operand and stores\r\nthe result in the first dword of the destination operand.\r\nAdds single-precision floating-point values in the third and fourth dword of the destination operand and stores the\r\nresult in the second dword of the destination operand.\r\nAdds single-precision floating-point values in the first and second dword of the source operand and stores the\r\nresult in the third dword of the destination operand.\r\nAdds single-precision floating-point values in the third and fourth dword of the source operand and stores the result\r\nin the fourth dword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nSee Figure 3-18 for HADDPS; see Figure 3-19 for VHADDPS.\r\n\r\n\r\n\r\n                                                      HADDPS xmm1, xmm2/m128\r\n\r\n                                                                                                               xmm2/\r\n                                  [127:96]               [95:64]               [63:32]          [31:0]\r\n                                                                                                               m128\r\n\r\n\r\n\r\n\r\n                                  [127:96]               [95:64]               [63:32]          [31:0]         xmm1\r\n\r\n\r\n\r\n\r\n                                 xmm2/m128             xmm2/m128\r\n                                                                         xmm1[95:64] +      xmm1[31:0] +       RESULT:\r\n                               [95:64] + xmm2/        [31:0] + xmm2/\r\n                                                                         xmm1[127:96]       xmm1[63:32]        xmm1\r\n                                m128[127:96]           m128[63:32]\r\n\r\n\r\n                                  [127:96]               [95:64]            [63:32]               [31:0]\r\n\r\n\r\n                                                                                                                      OM15994\r\n\r\n\r\n                                  Figure 3-18. HADDPS-Packed Single-FP Horizontal Add\r\n\r\n\r\n\r\n\r\n                           SRC1     X7           X6         X5         X4           X3     X2            X1      X0\r\n\r\n\r\n\r\n                           SRC2     Y7           Y6         Y5         Y4           Y3     Y2            Y1      Y0\r\n\r\n\r\n\r\n                           DEST Y6+Y7        Y4+Y5         X6+X7       X4+X5      Y2+Y3   Y0+Y1      X2+X3      X0+X1\r\n\r\n\r\n\r\n\r\n                                                  Figure 3-19. VHADDPS operation\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nHADDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHADDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHADDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[159:128] <- SRC1[191:160] + SRC1[159:128]\r\nDEST[191:160] <- SRC1[255:224] + SRC1[223:192]\r\nDEST[223:192] <- SRC2[191:160] + SRC2[159:128]\r\nDEST[255:224] <- SRC2[255:224] + SRC2[223:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHADDPS:      __m128 _mm_hadd_ps (__m128 a, __m128 b);\r\n\r\nVHADDPS:     __m256 _mm256_hadd_ps (__m256 a, __m256 b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "HADDPS"
    }, 
    {
      "description": "HLT-Halt\r\nOpcode                  Instruction                 Op/    64-Bit   Compat/ Description\r\n                                                    En     Mode     Leg Mode\r\nF4                      HLT                         NP     Valid    Valid       Halt\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n   Op/En            Operand 1                  Operand 2                    Operand 3              Operand 4\r\n     NP                NA                         NA                           NA                      NA\r\n\r\nDescription\r\nStops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and\r\nSMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an\r\ninterrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer\r\n(CS:EIP) points to the instruction following the HLT instruction.\r\nWhen a HLT instruction is executed on an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology,\r\nonly the logical processor that executes the instruction is halted. The other logical processors in the physical\r\nprocessor remain active, unless they are each individually halted by executing a HLT instruction.\r\nThe HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode,\r\nthe privilege level of a program or procedure must be 0 to execute the HLT instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nEnter Halt state;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                If the current privilege level is not 0.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nNone.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "HLT"
    }, 
    {
      "description": "HSUBPD-Packed Double-FP Horizontal Subtract\r\nOpcode/                                               Op/    64/32-bit CPUID            Description\r\nInstruction                                           En     Mode      Feature\r\n                                                                       Flag\r\n66 0F 7D /r                                           RM     V/V        SSE3            Horizontal subtract packed double-precision\r\nHSUBPD xmm1, xmm2/m128                                                                  floating-point values from xmm2/m128 to\r\n                                                                                        xmm1.\r\nVEX.NDS.128.66.0F.WIG 7D /r                           RVM V/V           AVX             Horizontal subtract packed double-precision\r\nVHSUBPD xmm1,xmm2, xmm3/m128                                                            floating-point values from xmm2 and\r\n                                                                                        xmm3/mem.\r\nVEX.NDS.256.66.0F.WIG 7D /r                           RVM V/V           AVX             Horizontal subtract packed double-precision\r\nVHSUBPD ymm1, ymm2, ymm3/m256                                                           floating-point values from ymm2 and\r\n                                                                                        ymm3/mem.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En           Operand 1                        Operand 2                     Operand 3                        Operand 4\r\n    RM          ModRM:reg (r, w)               ModRM:r/m (r)                            NA                             NA\r\n    RVM          ModRM:reg (w)                     VEX.vvvv (r)                 ModRM:r/m (r)                          NA\r\n\r\nDescription\r\nThe HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.\r\nSubtracts the double-precision floating-point value in the high quadword of the destination operand from the low\r\nquadword of the destination operand and stores the result in the low quadword of the destination operand.\r\nSubtracts the double-precision floating-point value in the high quadword of the source operand from the low quad-\r\nword of the source operand and stores the result in the high quadword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\n\r\nSee Figure 3-20 for HSUBPD; see Figure 3-21 for VHSUBPD.\r\n\r\n\r\n                                                   HSUBPD xmm1, xmm2/m128\r\n\r\n                                                                                                      xmm2\r\n                                        [127:64]                              [63:0]\r\n                                                                                                      /m128\r\n\r\n\r\n\r\n\r\n                                        [127:64]                              [63:0]                  xmm1\r\n\r\n\r\n\r\n\r\n                                    xmm2/m128[63:0] -                                                 Result:\r\n                                                                   xmm1[63:0] - xmm1[127:64]\r\n                                   xmm2/m128[127:64]                                                  xmm1\r\n\r\n                                        [127:64]                               [63:0]\r\n\r\n\r\n                                                                                                        OM15995\r\n\r\n\r\n\r\n                           Figure 3-20. HSUBPD-Packed Double-FP Horizontal Subtract\r\n\r\n\r\n\r\n\r\n\r\n                         SRC1           X3              X2             X1          X0\r\n\r\n\r\n\r\n                         SRC2           Y3              Y2             Y1          Y0\r\n\r\n\r\n\r\n                         DEST        Y2 - Y3         X2 - X3        Y0 - Y1     X0 - X1\r\n\r\n\r\n\r\n\r\n                                               Figure 3-21. VHSUBPD operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nHSUBPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHSUBPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHSUBPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] - SRC1[255:192]\r\nDEST[255:192] <- SRC2[191:128] - SRC2[255:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHSUBPD:       __m128d _mm_hsub_pd(__m128d a, __m128d b)\r\n\r\nVHSUBPD:      __m256d _mm256_hsub_pd (__m256d a, __m256d b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "HSUBPD"
    }, 
    {
      "description": "HSUBPS-Packed Single-FP Horizontal Subtract\r\n Opcode/                                           Op/   64/32-bit CPUID       Description\r\n Instruction                                       En    Mode      Feature\r\n                                                                   Flag\r\n F2 0F 7D /r                                       RM    V/V       SSE3        Horizontal subtract packed single-precision\r\n HSUBPS xmm1, xmm2/m128                                                        floating-point values from xmm2/m128 to\r\n                                                                               xmm1.\r\n VEX.NDS.128.F2.0F.WIG 7D /r                       RVM V/V         AVX         Horizontal subtract packed single-precision\r\n VHSUBPS xmm1, xmm2, xmm3/m128                                                 floating-point values from xmm2 and\r\n                                                                               xmm3/mem.\r\n VEX.NDS.256.F2.0F.WIG 7D /r                       RVM V/V         AVX         Horizontal subtract packed single-precision\r\n VHSUBPS ymm1, ymm2, ymm3/m256                                                 floating-point values from ymm2 and\r\n                                                                               ymm3/mem.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En              Operand 1                 Operand 2                    Operand 3                    Operand 4\r\n     RM            ModRM:reg (r, w)           ModRM:r/m (r)                     NA                           NA\r\n    RVM             ModRM:reg (w)              VEX.vvvv (r)               ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nSubtracts the single-precision floating-point value in the second dword of the destination operand from the first\r\ndword of the destination operand and stores the result in the first dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the fourth dword of the destination operand from the third\r\ndword of the destination operand and stores the result in the second dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the second dword of the source operand from the first dword\r\nof the source operand and stores the result in the third dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword\r\nof the source operand and stores the result in the fourth dword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nSee Figure 3-22 for HSUBPS; see Figure 3-23 for VHSUBPS.\r\n\r\n\r\n\r\n\r\n\r\n                                                HSUBPS xmm1, xmm2/m128\r\n\r\n                                                                                                              xmm2/\r\n                             [127:96]                 [95:64]              [63:32]             [31:0]\r\n                                                                                                              m128\r\n\r\n\r\n\r\n\r\n                             [127:96]                 [95:64]              [63:32]             [31:0]         xmm1\r\n\r\n\r\n\r\n\r\n                             xmm2/m128              xmm2/m128\r\n                                                                      xmm1[95:64] -       xmm1[31:0] -        RESULT:\r\n                           [95:64] - xmm2/         [31:0] - xmm2/\r\n                                                                      xmm1[127:96]        xmm1[63:32]         xmm1\r\n                            m128[127:96]            m128[63:32]\r\n\r\n\r\n                              [127:96]                [95:64]             [63:32]               [31:0]\r\n\r\n\r\n                                                                                                                     OM15996\r\n\r\n\r\n\r\n                           Figure 3-22. HSUBPS-Packed Single-FP Horizontal Subtract\r\n\r\n\r\n\r\n\r\n                         SRC1    X7           X6          X5         X4             X3    X2             X1      X0\r\n\r\n\r\n\r\n                         SRC2    Y7           Y6          Y5         Y4             Y3    Y2             Y1      Y0\r\n\r\n\r\n\r\n                         DEST Y6-Y7          Y4-Y5       X6-X7      X4-X5      Y2-Y3     Y0-Y1      X2-X3      X0-X1\r\n\r\n\r\n\r\n\r\n                                               Figure 3-23. VHSUBPS operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nHSUBPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHSUBPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHSUBPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC1[191:160]\r\nDEST[191:160] <- SRC1[223:192] - SRC1[255:224]\r\nDEST[223:192] <- SRC2[159:128] - SRC2[191:160]\r\nDEST[255:224] <- SRC2[223:192] - SRC2[255:224]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHSUBPS:     __m128 _mm_hsub_ps(__m128 a, __m128 b);\r\n\r\nVHSUBPS: __m256 _mm256_hsub_ps (__m256 a, __m256 b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "HSUBPS"
    }, 
    {
      "description": "IDIV-Signed Divide\r\n Opcode                   Instruction                  Op/    64-Bit          Compat/ Description\r\n                                                       En     Mode            Leg Mode\r\n F6 /7                    IDIV r/m8                    M      Valid           Valid       Signed divide AX by r/m8, with result stored in:\r\n                                                                                          AL <- Quotient, AH <- Remainder.\r\n REX + F6 /7              IDIV r/m8*                   M      Valid           N.E.        Signed divide AX by r/m8, with result stored in\r\n                                                                                          AL <- Quotient, AH <- Remainder.\r\n F7 /7                    IDIV r/m16                   M      Valid           Valid       Signed divide DX:AX by r/m16, with result\r\n                                                                                          stored in AX <- Quotient, DX <- Remainder.\r\n F7 /7                    IDIV r/m32                   M      Valid           Valid       Signed divide EDX:EAX by r/m32, with result\r\n                                                                                          stored in EAX <- Quotient, EDX <- Remainder.\r\n REX.W + F7 /7            IDIV r/m64                   M      Valid           N.E.        Signed divide RDX:RAX by r/m64, with result\r\n                                                                                          stored in RAX <- Quotient, RDX <- Remainder.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n   Op/En              Operand 1                     Operand 2                          Operand 3                      Operand 4\r\n     M              ModRM:r/m (r)                       NA                                NA                             NA\r\n\r\nDescription\r\nDivides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source operand (divisor) and stores the\r\nresult in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a\r\nmemory location. The action of this instruction depends on the operand size (dividend/divisor).\r\nNon-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-\r\ntude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is\r\napplied, the instruction divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit\r\nquotient; RDX contains a 64-bit remainder.\r\nSee the summary chart at the beginning of this section for encoding data and limits. See Table 3-50.\r\n                                                     Table 3-50. IDIV Results\r\n           Operand Size                 Dividend        Divisor             Quotient        Remainder              Quotient Range\r\n Word/byte                          AX               r/m8              AL                 AH                 -128 to +127\r\n Doubleword/word                    DX:AX            r/m16             AX                 DX                 -32,768 to +32,767\r\n Quadword/doubleword                EDX:EAX          r/m32             EAX                EDX                -231 to 231 - 1\r\n Doublequadword/ quadword           RDX:RAX          r/m64             RAX                RDX                -263 to 263 - 1\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF SRC = 0\r\n    THEN #DE; (* Divide error *)\r\nFI;\r\n\r\nIF OperandSize = 8 (* Word/byte operation *)\r\n    THEN\r\n        temp <- AX / SRC; (* Signed division *)\r\n        IF (temp > 7FH) or (temp < 80H)\r\n        (* If a positive result is greater than 7FH or a negative result is less than 80H *)\r\n              THEN #DE; (* Divide error *)\r\n              ELSE\r\n                    AL <- temp;\r\n                    AH <- AX SignedModulus SRC;\r\n        FI;\r\n    ELSE IF OperandSize = 16 (* Doubleword/word operation *)\r\n        THEN\r\n              temp <- DX:AX / SRC; (* Signed division *)\r\n              IF (temp > 7FFFH) or (temp < 8000H)\r\n              (* If a positive result is greater than 7FFFH\r\n              or a negative result is less than 8000H *)\r\n                    THEN\r\n                         #DE; (* Divide error *)\r\n                    ELSE\r\n                         AX <- temp;\r\n                         DX <- DX:AX SignedModulus SRC;\r\n              FI;\r\n        FI;\r\n    ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)\r\n              temp <- EDX:EAX / SRC; (* Signed division *)\r\n              IF (temp > 7FFFFFFFH) or (temp < 80000000H)\r\n              (* If a positive result is greater than 7FFFFFFFH\r\n              or a negative result is less than 80000000H *)\r\n                    THEN\r\n                         #DE; (* Divide error *)\r\n                    ELSE\r\n                         EAX <- temp;\r\n                         EDX <- EDXE:AX SignedModulus SRC;\r\n              FI;\r\n        FI;\r\n    ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)\r\n              temp <- RDX:RAX / SRC; (* Signed division *)\r\n              IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)\r\n              (* If a positive result is greater than 7FFFFFFFFFFFFFFFH\r\n              or a negative result is less than 8000000000000000H *)\r\n                    THEN\r\n                         #DE; (* Divide error *)\r\n                    ELSE\r\n                         RAX <- temp;\r\n                         RDX <- RDE:RAX SignedModulus SRC;\r\n              FI;\r\n        FI;\r\nFI;\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#DE                  If the source operand (divisor) is 0.\r\n                     The signed result (quotient) is too large for the destination.\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#DE                  If the source operand (divisor) is 0.\r\n\r\n                    The signed result (quotient) is too large for the destination.\r\n#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                  If a memory operand effective address is outside the SS segment limit.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#DE                  If the source operand (divisor) is 0.\r\n\r\n                    The signed result (quotient) is too large for the destination.\r\n#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)               If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                  If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#DE                  If the source operand (divisor) is 0\r\n                     If the quotient is too large for the designated register.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                  If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "IDIV"
    }, 
    {
      "description": "IMUL-Signed Multiply\r\n Opcode                    Instruction                  Op/      64-Bit     Compat/ Description\r\n                                                        … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "IMUL"
    }, 
    {
      "description": "IN-Input from Port\r\n Opcode                   Instruction                  Op/   64-Bit    Compat/ Description\r\n                                                       En    Mode      Leg Mode\r\n E4 ib                    IN AL, imm8                  I     Valid     Valid      Input byte from imm8 I/O port address into\r\n                                                                                  AL.\r\n E5 ib                    IN AX, imm8                  I     Valid     Valid      Input word from imm8 I/O port address into\r\n                                                                                  AX.\r\n E5 ib                    IN EAX, imm8                 I     Valid     Valid      Input dword from imm8 I/O port address into\r\n                                                                                  EAX.\r\n EC                       IN AL,DX                     NP    Valid     Valid      Input byte from I/O port in DX into AL.\r\n ED                       IN AX,DX                     NP    Valid     Valid      Input word from I/O port in DX into AX.\r\n ED                       IN EAX,DX                    NP    Valid     Valid      Input doubleword from I/O port in DX into\r\n                                                                                  EAX.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En           Operand 1                    Operand 2                   Operand 3                     Operand 4\r\n         I              imm8                           NA                         NA                            NA\r\n       NP                 NA                           NA                         NA                            NA\r\n\r\nDescription\r\nCopies the value from the I/O port specified with the second operand (source operand) to the destination operand\r\n(first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be\r\nregister AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the\r\nDX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte imme-\r\ndiate allows I/O port addresses 0 to 255 to be accessed.\r\nWhen accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port,\r\nthe operand-size attribute determines the port size. At the machine code level, I/O instructions are shorter when\r\naccessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.\r\nThis instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 18,\r\n\"Input/Output,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more infor-\r\nmation on accessing I/O ports in the I/O address space.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n     THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n         IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n              THEN (* I/O operation is not allowed *)\r\n                   #GP(0);\r\n              ELSE ( * I/O operation is allowed *)\r\n                   DEST <- SRC; (* Read from selected I/O port *)\r\n         FI;\r\n     ELSE (Real Mode or Protected Mode with CPL <= IOPL *)\r\n         DEST <- SRC; (* Read from selected I/O port *)\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n                    corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n                    corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "IN"
    }, 
    {
      "description": "INC-Increment by 1\r\n Opcode                      Instruction               Op/    64-Bit      Compat/ Description\r\n                                                       En     Mode        Leg Mode\r\n FE /0                       INC r/m8                  M      Valid       Valid        Increment r/m byte by 1.\r\n REX + FE /0                 INC r/m8*                 M      Valid       N.E.         Increment r/m byte by 1.\r\n FF /0                       INC r/m16                 M      Valid       Valid        Increment r/m word by 1.\r\n FF /0                       INC r/m32                 M      Valid       Valid        Increment r/m doubleword by 1.\r\n REX.W + FF /0               INC r/m64                 M      Valid       N.E.         Increment r/m quadword by 1.\r\n          **\r\n 40+ rw                      INC r16                   O      N.E.        Valid        Increment word register by 1.\r\n 40+ rd                      INC r32                   O      N.E.        Valid        Increment doubleword register by 1.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n ** 40H through 47H are REX prefixes in 64-bit mode.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En                Operand 1                    Operand 2                      Operand 3                      Operand 4\r\n     M               ModRM:r/m (r, w)                   NA                             NA                              NA\r\n     O               opcode + rd (r, w)                 NA                             NA                              NA\r\n\r\nDescription\r\nAdds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a\r\nregister or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.\r\n(Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the\r\nCF flag.)\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes).\r\nOtherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to\r\nadditional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\n\r\nOperation\r\nDEST <- DEST + 1;\r\n\r\nAFlags Affected\r\nThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                     If the destination operand is located in a non-writable segment.\r\n                           If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                           If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment\r\n                           selector.\r\n#SS(0)                     If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)            If a page fault occurs.\r\n#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made while the\r\n                           current privilege level is 3.\r\n#UD                        If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "INC"
    }, 
    {
      "description": "INS/INSB/INSW/INSD-Input from Port to String\r\n Opcode                     Instruction                  Op/   64-Bit       Compat/ Description\r\n                                … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "INS"
    }, 
    {
      "description": "-R:INS", 
      "mnem": "INSB"
    }, 
    {
      "description": "-R:INS", 
      "mnem": "INSD"
    }, 
    {
      "description": "INSERTPS-Insert Scalar Single-Precision Floating-Point Value\r\n Opcode/                                 Op /    64/32       CPUID     Description\r\n Instruction                             En      bit Mode    Feature\r\n                                                 Support     Flag\r\n 66 0F 3A 21 /r ib                       RMI     V/V         SSE4_1    Insert a single-precision floating-point value selected\r\n INSERTPS xmm1, xmm2/m32, imm8                                         by imm8 from xmm2/m32 into xmm1 at the specified\r\n                                                                       destination element specified by imm8 and zero out\r\n                                                                       destination elements in xmm1 as indicated in imm8.\r\n VEX.NDS.128.66.0F3A.WIG 21 /r ib        RVMI    V/V         AVX       Insert a single-precision floating-point value selected\r\n VINSERTPS xmm1, xmm2,                                                 by imm8 from xmm3/m32 and merge with values in\r\n xmm3/m32, imm8                                                        xmm2 at the specified destination element specified\r\n                                                                       by imm8 and write out the result and zero out\r\n                                                                       destination elements in xmm1 as indicated in imm8.\r\n EVEX.NDS.128.66.0F3A.W0 21 /r ib        T1S     V/V         AVX512F   Insert a single-precision floating-point value selected\r\n VINSERTPS xmm1, xmm2,                                                 by imm8 from xmm3/m32 and merge with values in\r\n xmm3/m32, imm8                                                        xmm2 at the specified destination element specified\r\n                                                                       by imm8 and write out the result and zero out\r\n                                                                       destination elements in xmm1 as indicated in imm8.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n       Op/En                Operand 1                  Operand 2               Operand 3                      Operand 4\r\n        RMI              ModRM:reg (r, w)           ModRM:r/m (r)                Imm8                             NA\r\n       RVMI              ModRM:reg (w)                 VEX.vvvv              ModRM:r/m (r)                       Imm8\r\n        T1S              ModRM:reg (w)                 EVEX.vvvv             ModRM:r/m (r)                       Imm8\r\n\r\nDescription\r\n(register source form)\r\nSelect a single-precision floating-point element from second source as indicated by Count_S bits of the immediate\r\noperand and destination operand it into the first source at the location indicated by the Count_D bits of the imme-\r\ndiate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate\r\noperand.\r\n(memory source form)\r\nLoad a floating-point element from a 32-bit memory location and destination operand it into the first source at the\r\nlocation indicated by the Count_D bits of the immediate operand. Store in the destination and zero out destination\r\nelements based on the ZMask bits of the immediate operand.\r\n128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an\r\nXMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\nVEX.128 and EVEX encoded version: The destination and first source register is an XMM register. The second\r\nsource operand is either an XMM register or a 32-bit memory location. The upper bits (MAX_VL-1:128) of the corre-\r\nsponding register destination are zeroed.\r\nIf VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause\r\nan #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVINSERTPS (VEX.128 and EVEX encoded version)\r\nIF (SRC = REG) THEN COUNT_S <- imm8[7:6]\r\n    ELSE COUNT_S <- 0\r\nCOUNT_D <- imm8[5:4]\r\nZMASK <- imm8[3:0]\r\nCASE (COUNT_S) OF\r\n    0: TMP <- SRC2[31:0]\r\n    1: TMP <- SRC2[63:32]\r\n    2: TMP <- SRC2[95:64]\r\n    3: TMP <- SRC2[127:96]\r\nESAC;\r\nCASE (COUNT_D) OF\r\n    0: TMP2[31:0] <- TMP\r\n         TMP2[127:32] <- SRC1[127:32]\r\n    1: TMP2[63:32] <- TMP\r\n         TMP2[31:0] <- SRC1[31:0]\r\n         TMP2[127:64] <- SRC1[127:64]\r\n    2: TMP2[95:64] <- TMP\r\n         TMP2[63:0] <- SRC1[63:0]\r\n         TMP2[127:96] <- SRC1[127:96]\r\n    3: TMP2[127:96] <- TMP\r\n         TMP2[95:0] <- SRC1[95:0]\r\nESAC;\r\n\r\nIF (ZMASK[0] = 1) THEN DEST[31:0] <- 00000000H\r\n    ELSE DEST[31:0] <- TMP2[31:0]\r\nIF (ZMASK[1] = 1) THEN DEST[63:32] <- 00000000H\r\n    ELSE DEST[63:32] <- TMP2[63:32]\r\nIF (ZMASK[2] = 1) THEN DEST[95:64] <- 00000000H\r\n    ELSE DEST[95:64] <- TMP2[95:64]\r\nIF (ZMASK[3] = 1) THEN DEST[127:96] <- 00000000H\r\n    ELSE DEST[127:96] <- TMP2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nINSERTPS (128-bit Legacy SSE version)\r\nIF (SRC = REG) THEN COUNT_S <-imm8[7:6]\r\n    ELSE COUNT_S <-0\r\nCOUNT_D <-imm8[5:4]\r\nZMASK <-imm8[3:0]\r\nCASE (COUNT_S) OF\r\n    0: TMP <-SRC[31:0]\r\n    1: TMP <-SRC[63:32]\r\n    2: TMP <-SRC[95:64]\r\n    3: TMP <-SRC[127:96]\r\nESAC;\r\n\r\nCASE (COUNT_D) OF\r\n   0: TMP2[31:0] <-TMP\r\n        TMP2[127:32] <-DEST[127:32]\r\n   1: TMP2[63:32] <-TMP\r\n        TMP2[31:0] <-DEST[31:0]\r\n        TMP2[127:64] <-DEST[127:64]\r\n   2: TMP2[95:64] <-TMP\r\n\r\n\r\n\r\n        TMP2[63:0] <-DEST[63:0]\r\n        TMP2[127:96] <-DEST[127:96]\r\n   3: TMP2[127:96] <-TMP\r\n        TMP2[95:0] <-DEST[95:0]\r\nESAC;\r\n\r\nIF (ZMASK[0] = 1) THEN DEST[31:0] <-00000000H\r\n    ELSE DEST[31:0] <-TMP2[31:0]\r\nIF (ZMASK[1] = 1) THEN DEST[63:32] <-00000000H\r\n    ELSE DEST[63:32] <-TMP2[63:32]\r\nIF (ZMASK[2] = 1) THEN DEST[95:64] <-00000000H\r\n    ELSE DEST[95:64] <-TMP2[95:64]\r\nIF (ZMASK[3] = 1) THEN DEST[127:96] <-00000000H\r\n    ELSE DEST[127:96] <-TMP2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);\r\nINSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                   If VEX.L = 0.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "INSERTPS"
    }, 
    {
      "description": "-R:INS", 
      "mnem": "INSW"
    }, 
    {
      "description": "-R:INT n", 
      "mnem": "INT 3"
    }, 
    {
      "description": "INT n/INTO/INT 3-Call to Interrupt Procedure\r\n Opcode                      Instruction            Op/     64-Bit    Compat/ Description\r\n                                      … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "INT n"
    }, 
    {
      "description": "-R:INT n", 
      "mnem": "INTO"
    }, 
    {
      "description": "INVD-Invalidate Internal Caches\r\n Opcode                      Instruction                Op/   64-Bit   Compat/ Description\r\n                                                        En    Mode     Leg Mode\r\n 0F 08                       INVD                       NP    Valid    Valid      Flush internal caches; initiate flushing of\r\n                                                                                  external caches.\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n    Op/En               Operand 1                   Operand 2                  Operand 3                     Operand 4\r\n     NP                     NA                          NA                        NA                             NA\r\n\r\nDescription\r\nInvalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external\r\ncaches to also flush themselves. Data held in internal caches is not written back to main memory.\r\nAfter executing this instruction, the processor does not wait for the external caches to complete their flushing oper-\r\nation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush\r\nsignal.\r\nThe INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a\r\nprogram or procedure must be 0 to execute this instruction.\r\nThe INVD instruction may be used when the cache is used as temporary memory and the cache contents need to\r\nbe invalidated rather than written back to memory. When the cache is used as temporary memory, no external\r\ndevice should be actively writing data to main memory.\r\nUse this instruction with care. Data cached internally and not written back to main memory will be lost. Note that\r\nany data from an external device to main memory (for example, via a PCIWrite) can be temporarily stored in the\r\ncaches; these data can be lost when an INVD instruction is executed. Unless there is a specific requirement or\r\nbenefit to flushing caches without writing back modified cache lines (for example, temporary memory, testing, or\r\nfault recovery where cache coherency with main memory is not a concern), software should instead use the\r\nWBINVD instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe INVD instruction is implementation dependent; it may be implemented differently on different families of Intel\r\n64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.\r\n\r\nOperation\r\nFlush(InternalCaches);\r\nSignalFlush(ExternalCaches);\r\nContinue (* Continue execution *)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                    If the current privilege level is not 0.\r\n#UD                       If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                       If the LOCK prefix is used.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              The INVD instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "INVD"
    }, 
    {
      "description": "INVLPG-Invalidate TLB Entries\r\n Opcode                     Instruction                 Op/    64-Bit      Compat/ Description\r\n                                                        En     Mode        Leg Mode\r\n 0F 01/7                    INVLPG m                    M      Valid       Valid       Invalidate TLB entries for page containing m.\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n  Op/En              Operand 1                     Operand 2                       Operand 3                    Operand 4\r\n    M              ModRM:r/m (r)                      NA                              NA                            NA\r\n\r\nDescription\r\nInvalidates any translation lookaside buffer (TLB) entries specified with the source operand. The source operand is\r\na memory address. The processor determines the page that contains that address and flushes all TLB entries for\r\nthat page.1\r\nThe INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL must\r\nbe 0 to execute this instruction.\r\nThe INVLPG instruction normally flushes TLB entries only for the specified page; however, in some cases, it may\r\nflush more entries, even the entire TLB. The instruction is guaranteed to invalidates only TLB entries associated\r\nwith the current PCID. (If PCIDs are disabled - CR4.PCIDE = 0 - the current PCID is 000H.) The instruction also\r\ninvalidates any global TLB entries for the specified page, regardless of PCID.\r\nFor more details on operations that flush the TLB, see \"MOV-Move to/from Control Registers\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 2B and Section 4.10.4.1, \"Operations that Invalidate\r\nTLBs and Paging-Structure Caches,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 3A.\r\nThis instruction's operation is the same in all non-64-bit modes. It also operates the same in 64-bit mode, except\r\nif the memory address is in non-canonical form. In this case, INVLPG is the same as a NOP.\r\n\r\nIA-32 Architecture Compatibility\r\nThe INVLPG instruction is implementation dependent, and its function may be implemented differently on different\r\nfamilies of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the\r\nIntel486 processor.\r\n\r\nOperation\r\nInvalidate(RelevantTLBEntries);\r\nContinue; (* Continue execution *)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If the current privilege level is not 0.\r\n#UD                      Operand is a register.\r\n                         If the LOCK prefix is used.\r\n\r\n\r\n\r\n1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page\r\n   (see Section 4.10.2.3, \"Details of TLB Use,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A), the\r\n   instruction invalidates all of them.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 Operand is a register.\r\n                    If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              The INVLPG instruction cannot be executed at the virtual-8086 mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n#UD                 Operand is a register.\r\n                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "INVLPG"
    }, 
    {
      "description": "INVPCID-Invalidate Process-Context Identifier\r\n Opcode/Instruction                                  Op/     64/32-   CPUID        Description\r\n                                                     En      bit      Feature\r\n                                                             Mode     Flag\r\n 66 0F 38 82 /r                                      RM      NE/V     INVPCID      Invalidates entries in the TLBs and paging-structure\r\n INVPCID r32, m128                                                                 caches based on invalidation type in r32 and descrip-\r\n                                                                                   tor in m128.\r\n\r\n 66 0F 38 82 /r                                      RM      V/NE     INVPCID      Invalidates entries in the TLBs and paging-structure\r\n INVPCID r64, m128                                                                 caches based on invalidation type in r64 and descrip-\r\n                                                                                   tor in m128.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n    Op/En               Operand 1                     Operand 2                       Operand 3                     Operand 4\r\n     RM               ModRM:reg (R)                 ModRM:r/m (R)                        NA                             NA\r\n\r\nDescription\r\nInvalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on process-\r\ncontext identifier (PCID). (See Section 4.10, \"Caching Translation Information,\" in Intel 64 and IA-32 Architecture\r\nSoftware Developer's Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register\r\noperand and the INVPCID descriptor specified in the memory operand.\r\nOutside 64-bit mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode the\r\nregister operand has 64 bits.\r\nThere are four INVPCID types currently defined:\r\n.    Individual-address invalidation: If the INVPCID type is 0, the logical processor invalidates mappings-except\r\n     global translations-for the linear address and PCID specified in the INVPCID descriptor.1 In some cases, the\r\n     instruction may invalidate global translations or mappings for other linear addresses (or other PCIDs) as well.\r\n.    Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings-except\r\n     global translations-associated with the PCID specified in the INVPCID descriptor. In some cases, the\r\n     instruction may invalidate global translations or mappings for other PCIDs as well.\r\n.    All-context invalidation, including global translations: If the INVPCID type is 2, the logical processor invalidates\r\n     all mappings-including global translations-associated with any PCID.\r\n.    All-context invalidation: If the INVPCID type is 3, the logical processor invalidates all mappings-except global\r\n     translations-associated with any PCID. In some case, the instruction may invalidate global translations as\r\n     well.\r\nThe INVPCID descriptor comprises 128 bits and consists of a PCID and a linear address as shown in Figure 3-24.\r\nFor INVPCID type 0, the processor uses the full 64 bits of the linear address even outside 64-bit mode; the linear\r\naddress is not used for other INVPCID types.\r\n\r\n\r\n\r\n\r\n                             127                                    64 63                             12 11     0\r\n                                            Linear Address                  Reserved (must be zero)      PCID\r\n\r\n\r\n\r\n\r\n                                                  Figure 3-24. INVPCID Descriptor\r\n\r\n1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page\r\n   (see Section 4.10.2.3, \"Details of TLB Use,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A), the\r\n   instruction invalidates all of them.\r\n\r\n\r\n\r\nIf CR4.PCIDE = 0, a logical processor does not cache information for any PCID other than 000H. In this case,\r\nexecutions with INVPCID types 0 and 1 are allowed only if the PCID specified in the INVPCID descriptor is 000H;\r\nexecutions with INVPCID types 2 and 3 invalidate mappings only for PCID 000H. Note that CR4.PCIDE must be 0\r\noutside 64-bit mode (see Chapter 4.10.1, \"Process-Context Identifiers (PCIDs)\" of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3A).\r\n\r\nOperation\r\nINVPCID_TYPE <- value of register operand;              // must be in the range of 0-3\r\nINVPCID_DESC <- value of memory operand;\r\nCASE INVPCID_TYPE OF\r\n   0:                  // individual-address invalidation\r\n       PCID <- INVPCID_DESC[11:0];\r\n       L_ADDR <- INVPCID_DESC[127:64];\r\n       Invalidate mappings for L_ADDR associated with PCID except global translations;\r\n       BREAK;\r\n   1:                  // single PCID invalidation\r\n       PCID <- INVPCID_DESC[11:0];\r\n       Invalidate all mappings associated with PCID except global translations;\r\n       BREAK;\r\n   2:                  // all PCID invalidation including global translations\r\n       Invalidate all mappings for all PCIDs, including global translations;\r\n       BREAK;\r\n   3:                  // all PCID invalidation retaining global translations\r\n       Invalidate all mappings for all PCIDs except global translations;\r\n       BREAK;\r\nESAC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nINVPCID:    void _invpcid(unsigned __int32 type, void * descriptor);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the current privilege level is not 0.\r\n                        If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains an unusable segment.\r\n                        If the source operand is located in an execute-only code segment.\r\n                        If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n                        If bits 63:12 of INVPCID_DESC are not all zero.\r\n                        If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.\r\n                        If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#PF(fault-code)         If a page fault occurs in accessing the memory operand.\r\n#SS(0)                  If the memory operand effective address is outside the SS segment limit.\r\n                        If the SS register contains an unusable segment.\r\n#UD                     If if CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n                        If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                       If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n                          If bits 63:12 of INVPCID_DESC are not all zero.\r\n                          If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.\r\n                          If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#UD                       If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n                          If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                    The INVPCID instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                    If the current privilege level is not 0.\r\n                          If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is\r\n                          in a non-canonical form.\r\n                          If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n                          If bits 63:12 of INVPCID_DESC are not all zero.\r\n                          If CR4.PCIDE=0, INVPCID_TYPE is either 0 or 1, and INVPCID_DESC[11:0] is not zero.\r\n                          If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#PF(fault-code)           If a page fault occurs in accessing the memory operand.\r\n#SS(0)                    If the memory destination operand is in the SS segment and the memory address is in a non-\r\n                          canonical form.\r\n#UD                       If the LOCK prefix is used.\r\n                          If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "INVPCID"
    }, 
    {
      "description": "IRET/IRETD-Interrupt Return\r\nOpcode                   Instruction              Op/     64-Bit   Compat/ Description\r\n                                                  En      … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "IRET"
    }, 
    {
      "description": "-R:IRET", 
      "mnem": "IRETD"
    }, 
    {
      "description": "-R:IRET", 
      "mnem": "IRETQ"
    }, 
    {
      "description": "JMP-Jump\r\n Opcode                 Instruction              Op/     64-Bit   Compat/ Description\r\n                                                 En      Mode     Leg Mode\r\ … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "JMP"
    }, 
    {
      "description": "Jcc-Jump if Condition Is Met\r\n Opcode                        Instruction   Op/   64-Bit   Compat/ Description\r\n                                             En    Mode     Leg … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "Jcc"
    }, 
    {
      "description": "-R:KADDW", 
      "mnem": "KADDB"
    }, 
    {
      "description": "-R:KADDW", 
      "mnem": "KADDD"
    }, 
    {
      "description": "-R:KADDW", 
      "mnem": "KADDQ"
    }, 
    {
      "description": "KADDW/KADDB/KADDQ/KADDD-ADD Two Masks\r\n Opcode/                               Op/En    64/32      CPUID      Description\r\n Instruction                                    bit Mode   Feature\r\n                                                Support    Flag\r\n VEX.L1.0F.W0 4A /r                    RVR      V/V        AVX512DQ   Add 16 bits masks in k2 and k3 and place result in k1.\r\n KADDW k1, k2, k3\r\n VEX.L1.66.0F.W0 4A /r                 RVR      V/V        AVX512DQ   Add 8 bits masks in k2 and k3 and place result in k1.\r\n KADDB k1, k2, k3\r\n VEX.L1.0F.W1 4A /r                    RVR      V/V        AVX512BW   Add 64 bits masks in k2 and k3 and place result in k1.\r\n KADDQ k1, k2, k3\r\n VEX.L1.66.0F.W1 4A /r                 RVR      V/V        AVX512BW   Add 32 bits masks in k2 and k3 and place result in k1.\r\n KADDD k1, k2, k3\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n        Op/En             Operand 1                Operand 2                                Operand 3\r\n        RVR              ModRM:reg (w)            VEX.1vvv (r)                ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nAdds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.\r\n\r\nOperation\r\nKADDW\r\nDEST[15:0] <- SRC1[15:0] + SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKADDB\r\nDEST[7:0] <- SRC1[7:0] + SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKADDQ\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKADDD\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KADDW"
    }, 
    {
      "description": "-R:KANDW", 
      "mnem": "KANDB"
    }, 
    {
      "description": "-R:KANDW", 
      "mnem": "KANDD"
    }, 
    {
      "description": "-R:KANDNW", 
      "mnem": "KANDNB"
    }, 
    {
      "description": "-R:KANDNW", 
      "mnem": "KANDND"
    }, 
    {
      "description": "-R:KANDNW", 
      "mnem": "KANDNQ"
    }, 
    {
      "description": "KANDNW/KANDNB/KANDNQ/KANDND-Bitwise Logical AND NOT Masks\r\n Opcode/                      Op/En       64/32      CPUID        Description\r\n Instruction                              bit Mode   Feature\r\n                                          Support    Flag\r\n VEX.NDS.L1.0F.W0 42 /r       RVR         V/V        AVX512F      Bitwise AND NOT 16 bits masks k2 and k3 and place result in\r\n KANDNW k1, k2, k3                                                k1.\r\n VEX.L1.66.0F.W0 42 /r        RVR         V/V        AVX512DQ     Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1.\r\n KANDNB k1, k2, k3\r\n VEX.L1.0F.W1 42 /r           RVR         V/V        AVX512BW     Bitwise AND NOT 64 bits masks k2 and k3 and place result in\r\n KANDNQ k1, k2, k3                                                k1.\r\n VEX.L1.66.0F.W1 42 /r        RVR         V/V        AVX512BW     Bitwise AND NOT 32 bits masks k2 and k3 and place result in\r\n KANDND k1, k2, k3                                                k1.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n    Op/En                  Operand 1                            Operand 2                              Operand 3\r\n     RVR                  ModRM:reg (w)                        VEX.1vvv (r)             ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector\r\nmask k1.\r\n\r\nOperation\r\nKANDNW\r\nDEST[15:0] <- (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKANDNB\r\nDEST[7:0] <- (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKANDNQ\r\nDEST[63:0] <- (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKANDND\r\nDEST[31:0] <- (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KANDNW"
    }, 
    {
      "description": "-R:KANDW", 
      "mnem": "KANDQ"
    }, 
    {
      "description": "KANDW/KANDB/KANDQ/KANDD-Bitwise Logical AND Masks\r\n Opcode/                        Op/En     64/32       CPUID        Description\r\n Instruction                              bit Mode    Feature\r\n                                          Support     Flag\r\n VEX.NDS.L1.0F.W0 41 /r         RVR       V/V         AVX512F      Bitwise AND 16 bits masks k2 and k3 and place result in k1.\r\n KANDW k1, k2, k3\r\n VEX.L1.66.0F.W0 41 /r          RVR       V/V         AVX512DQ     Bitwise AND 8 bits masks k2 and k3 and place result in k1.\r\n KANDB k1, k2, k3\r\n VEX.L1.0F.W1 41 /r             RVR       V/V         AVX512BW     Bitwise AND 64 bits masks k2 and k3 and place result in k1.\r\n KANDQ k1, k2, k3\r\n VEX.L1.66.0F.W1 41 /r          RVR       V/V         AVX512BW     Bitwise AND 32 bits masks k2 and k3 and place result in k1.\r\n KANDD k1, k2, k3\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n    Op/En                  Operand 1                         Operand 2                               Operand 3\r\n     RVR                  ModRM:reg (w)                     VEX.1vvv (r)             ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1.\r\n\r\nOperation\r\nKANDW\r\nDEST[15:0] <- SRC1[15:0] BITWISE AND SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKANDB\r\nDEST[7:0] <- SRC1[7:0] BITWISE AND SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\n\r\nKANDQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKANDD\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KANDW"
    }, 
    {
      "description": "-R:KMOVW", 
      "mnem": "KMOVB"
    }, 
    {
      "description": "-R:KMOVW", 
      "mnem": "KMOVD"
    }, 
    {
      "description": "-R:KMOVW", 
      "mnem": "KMOVQ"
    }, 
    {
      "description": "KMOVW/KMOVB/KMOVQ/KMOVD-Move from and to Mask Registers\r\n Opcode/                        Op/En     64/32        CPUID       Description\r\n Instruction                              bit Mode     Feature\r\n                                          Support      Flag\r\n VEX.L0.0F.W0 90 /r             RM        V/V          AVX512F     Move 16 bits mask from k2/m16 and store the result in k1.\r\n KMOVW k1, k2/m16\r\n VEX.L0.66.0F.W0 90 /r          RM        V/V          AVX512DQ    Move 8 bits mask from k2/m8 and store the result in k1.\r\n KMOVB k1, k2/m8\r\n VEX.L0.0F.W1 90 /r             RM        V/V          AVX512BW    Move 64 bits mask from k2/m64 and store the result in k1.\r\n KMOVQ k1, k2/m64\r\n VEX.L0.66.0F.W1 90 /r          RM        V/V          AVX512BW    Move 32 bits mask from k2/m32 and store the result in k1.\r\n KMOVD k1, k2/m32\r\n VEX.L0.0F.W0 91 /r             MR        V/V          AVX512F     Move 16 bits mask from k1 and store the result in m16.\r\n KMOVW m16, k1\r\n VEX.L0.66.0F.W0 91 /r          MR        V/V          AVX512DQ    Move 8 bits mask from k1 and store the result in m8.\r\n KMOVB m8, k1\r\n VEX.L0.0F.W1 91 /r             MR        V/V          AVX512BW    Move 64 bits mask from k1 and store the result in m64.\r\n KMOVQ m64, k1\r\n VEX.L0.66.0F.W1 91 /r          MR        V/V          AVX512BW    Move 32 bits mask from k1 and store the result in m32.\r\n KMOVD m32, k1\r\n VEX.L0.0F.W0 92 /r             RR        V/V          AVX512F     Move 16 bits mask from r32 to k1.\r\n KMOVW k1, r32\r\n VEX.L0.66.0F.W0 92 /r          RR        V/V          AVX512DQ    Move 8 bits mask from r32 to k1.\r\n KMOVB k1, r32\r\n VEX.L0.F2.0F.W1 92 /r          RR        V/I          AVX512BW    Move 64 bits mask from r64 to k1.\r\n KMOVQ k1, r64\r\n VEX.L0.F2.0F.W0 92 /r          RR        V/V          AVX512BW    Move 32 bits mask from r32 to k1.\r\n KMOVD k1, r32\r\n VEX.L0.0F.W0 93 /r             RR        V/V          AVX512F     Move 16 bits mask from k1 to r32.\r\n KMOVW r32, k1\r\n VEX.L0.66.0F.W0 93 /r          RR        V/V          AVX512DQ    Move 8 bits mask from k1 to r32.\r\n KMOVB r32, k1\r\n VEX.L0.F2.0F.W1 93 /r          RR        V/I          AVX512BW    Move 64 bits mask from k1 to r64.\r\n KMOVQ r64, k1\r\n VEX.L0.F2.0F.W0 93 /r          RR        V/V          AVX512BW    Move 32 bits mask from k1 to r32.\r\n KMOVD r32, k1\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n     Op/En                           Operand 1                                            Operand 2\r\n      RM                          ModRM:reg (w)                                          ModRM:r/m (r)\r\n      MR            ModRM:r/m (w, ModRM:[7:6] must not be 11b)                           ModRM:reg (r)\r\n      RR                          ModRM:reg (w)                            ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nCopies values from the source operand (second operand) to the destination operand (first operand). The source\r\nand destination operands can be mask registers, memory location or general purpose. The instruction cannot be\r\nused to transfer data between general purpose registers and or memory locations.\r\nWhen moving to a mask register, the result is zero extended to MAX_KL size (i.e., 64 bits currently). When moving\r\nto a general-purpose register (GPR), the result is zero-extended to the size of the destination. In 32-bit mode, the\r\ndefault GPR destination's size is 32 bits. In 64-bit mode, the default GPR destination's size is 64 bits. Note that\r\nREX.W cannot be used to modify the size of the general-purpose destination.\r\n\r\n\r\n\r\n\r\nOperation\r\nKMOVW\r\nIF *destination is a memory location*\r\n    DEST[15:0] <- SRC[15:0]\r\nIF *destination is a mask register or a GPR *\r\n    DEST <- ZeroExtension(SRC[15:0])\r\n\r\nKMOVB\r\nIF *destination is a memory location*\r\n    DEST[7:0] <- SRC[7:0]\r\nIF *destination is a mask register or a GPR *\r\n    DEST <- ZeroExtension(SRC[7:0])\r\n\r\nKMOVQ\r\nIF *destination is a memory location or a GPR*\r\n    DEST[63:0] <- SRC[63:0]\r\nIF *destination is a mask register*\r\n    DEST <- ZeroExtension(SRC[63:0])\r\n\r\nKMOVD\r\nIF *destination is a memory location*\r\n    DEST[31:0] <- SRC[31:0]\r\nIF *destination is a mask register or a GPR *\r\n    DEST <- ZeroExtension(SRC[31:0])\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKMOVW __mmask16 _mm512_kmov(__mmask16 a);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nInstructions with RR operand encoding See Exceptions Type K20.\r\nInstructions with RM or MR operand encoding See Exceptions Type K21.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KMOVW"
    }, 
    {
      "description": "-R:KNOTW", 
      "mnem": "KNOTB"
    }, 
    {
      "description": "-R:KNOTW", 
      "mnem": "KNOTD"
    }, 
    {
      "description": "-R:KNOTW", 
      "mnem": "KNOTQ"
    }, 
    {
      "description": "KNOTW/KNOTB/KNOTQ/KNOTD-NOT Mask Register\r\n Opcode/                              Op/En      64/32      CPUID          Description\r\n Instruction                                     bit Mode   Feature Flag\r\n                                                 Support\r\n VEX.L0.0F.W0 44 /r                   RR         V/V        AVX512F        Bitwise NOT of 16 bits mask k2.\r\n KNOTW k1, k2\r\n VEX.L0.66.0F.W0 44 /r                RR         V/V        AVX512DQ       Bitwise NOT of 8 bits mask k2.\r\n KNOTB k1, k2\r\n VEX.L0.0F.W1 44 /r                   RR         V/V        AVX512BW       Bitwise NOT of 64 bits mask k2.\r\n KNOTQ k1, k2\r\n VEX.L0.66.0F.W1 44 /r                RR         V/V        AVX512BW       Bitwise NOT of 32 bits mask k2.\r\n KNOTD k1, k2\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n    Op/En                            Operand 1                                              Operand 2\r\n       RR                          ModRM:reg (w)                             ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise NOT of vector mask k2 and writes the result into vector mask k1.\r\n\r\nOperation\r\nKNOTW\r\nDEST[15:0] <- BITWISE NOT SRC[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKNOTB\r\nDEST[7:0] <- BITWISE NOT SRC[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKNOTQ\r\nDEST[63:0] <- BITWISE NOT SRC[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKNOTD\r\nDEST[31:0] <- BITWISE NOT SRC[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKNOTW __mmask16 _mm512_knot(__mmask16 a);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KNOTW"
    }, 
    {
      "description": "-R:KORW", 
      "mnem": "KORB"
    }, 
    {
      "description": "-R:KORW", 
      "mnem": "KORD"
    }, 
    {
      "description": "-R:KORW", 
      "mnem": "KORQ"
    }, 
    {
      "description": "-R:KORTESTW", 
      "mnem": "KORTESTB"
    }, 
    {
      "description": "-R:KORTESTW", 
      "mnem": "KORTESTD"
    }, 
    {
      "description": "-R:KORTESTW", 
      "mnem": "KORTESTQ"
    }, 
    {
      "description": "KORTESTW/KORTESTB/KORTESTQ/KORTESTD-OR Masks And Set Flags\r\n  Opcode/                 Op/   64/32         CPUID       Description\r\n  Instruction             En    bit Mode      Feature\r\n                                Support       Flag\r\n  VEX.L0.0F.W0 98 /r      RR    V/V           AVX512F     Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly.\r\n  KORTESTW k1, k2\r\n  VEX.L0.66.0F.W0 98 /r   RR    V/V           AVX512DQ    Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly.\r\n  KORTESTB k1, k2\r\n  VEX.L0.0F.W1 98 /r      RR    V/V           AVX512BW    Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly.\r\n  KORTESTQ k1, k2\r\n  VEX.L0.66.0F.W1 98 /r   RR    V/V           AVX512BW    Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly.\r\n  KORTESTD k1, k2\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n      Op/En                        Operand 1                                                Operand 2\r\n       RR                        ModRM:reg (w)                               ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise OR between the vector mask register k2, and the vector mask register k1, and sets CF and ZF\r\nbased on the operation result.\r\nZF flag is set if both sources are 0x0. CF is set if, after the OR operation is done, the operation result is all 1's.\r\n\r\nOperation\r\nKORTESTW\r\nTMP[15:0] <- DEST[15:0] BITWISE OR SRC[15:0]\r\nIF(TMP[15:0]=0)\r\n    THEN ZF <- 1\r\n    ELSE ZF <- 0\r\nFI;\r\nIF(TMP[15:0]=FFFFh)\r\n    THEN CF <- 1\r\n    ELSE CF <- 0\r\nFI;\r\n\r\nKORTESTB\r\nTMP[7:0] <- DEST[7:0] BITWISE OR SRC[7:0]\r\nIF(TMP[7:0]=0)\r\n    THEN ZF <- 1\r\n    ELSE ZF <- 0\r\nFI;\r\nIF(TMP[7:0]==FFh)\r\n    THEN CF <- 1\r\n    ELSE CF <- 0\r\n\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKORTESTQ\r\nTMP[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]\r\nIF(TMP[63:0]=0)\r\n    THEN ZF <- 1\r\n    ELSE ZF <- 0\r\nFI;\r\nIF(TMP[63:0]==FFFFFFFF_FFFFFFFFh)\r\n    THEN CF <- 1\r\n    ELSE CF <- 0\r\nFI;\r\n\r\nKORTESTD\r\nTMP[31:0] <- DEST[31:0] BITWISE OR SRC[31:0]\r\nIF(TMP[31:0]=0)\r\n    THEN ZF <- 1\r\n    ELSE ZF <- 0\r\nFI;\r\nIF(TMP[31:0]=FFFFFFFFh)\r\n    THEN CF <- 1\r\n    ELSE CF <- 0\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKORTESTW __mmask16 _mm512_kortest[cz](__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nThe ZF flag is set if the result of OR-ing both sources is all 0s.\r\nThe CF flag is set if the result of OR-ing both sources is all 1s.\r\nThe OF, SF, AF, and PF flags are set to 0.\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KORTESTW"
    }, 
    {
      "description": "KORW/KORB/KORQ/KORD-Bitwise Logical OR Masks\r\n Opcode/                         Op/En       64/32      CPUID        Description\r\n Instruction                                 bit Mode   Feature\r\n                                             Support    Flag\r\n VEX.NDS.L1.0F.W0 45 /r          RVR         V/V        AVX512F      Bitwise OR 16 bits masks k2 and k3 and place result in k1.\r\n KORW k1, k2, k3\r\n VEX.L1.66.0F.W0 45 /r           RVR         V/V        AVX512DQ     Bitwise OR 8 bits masks k2 and k3 and place result in k1.\r\n KORB k1, k2, k3\r\n VEX.L1.0F.W1 45 /r              RVR         V/V        AVX512BW     Bitwise OR 64 bits masks k2 and k3 and place result in k1.\r\n KORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 45 /r           RVR         V/V        AVX512BW     Bitwise OR 32 bits masks k2 and k3 and place result in k1.\r\n KORD k1, k2, k3\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n    Op/En                  Operand 1                         Operand 2                               Operand 3\r\n     RVR                  ModRM:reg (w)                     VEX.1vvv (r)               ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise OR between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1 (three-operand form).\r\n\r\nOperation\r\nKORW\r\nDEST[15:0] <- SRC1[15:0] BITWISE OR SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKORB\r\nDEST[7:0] <- SRC1[7:0] BITWISE OR SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKORQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKORD\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKORW __mmask16 _mm512_kor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KORW"
    }, 
    {
      "description": "-R:KSHIFTLW", 
      "mnem": "KSHIFTLB"
    }, 
    {
      "description": "-R:KSHIFTLW", 
      "mnem": "KSHIFTLD"
    }, 
    {
      "description": "-R:KSHIFTLW", 
      "mnem": "KSHIFTLQ"
    }, 
    {
      "description": "KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD-Shift Left Mask Registers\r\n  Opcode/                         Op/En      64/32        CPUID         Description\r\n  Instruction                                bit Mode     Feature\r\n                                             Support      Flag\r\n  VEX.L0.66.0F3A.W1 32 /r         RRI        V/V          AVX512F       Shift left 16 bits in k2 by immediate and write result in k1.\r\n  KSHIFTLW k1, k2, imm8\r\n  VEX.L0.66.0F3A.W0 32 /r         RRI        V/V          AVX512DQ      Shift left 8 bits in k2 by immediate and write result in k1.\r\n  KSHIFTLB k1, k2, imm8\r\n  VEX.L0.66.0F3A.W1 33 /r         RRI        V/V          AVX512BW      Shift left 64 bits in k2 by immediate and write result in k1.\r\n  KSHIFTLQ k1, k2, imm8\r\n  VEX.L0.66.0F3A.W0 33 /r         RRI        V/V          AVX512BW      Shift left 32 bits in k2 by immediate and write result in k1.\r\n  KSHIFTLD k1, k2, imm8\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En                 Operand 1                             Operand 2                                  Operand 3\r\n       RRI               ModRM:reg (w)              ModRM:r/m (r, ModRM:[7:6] must be 11b)                     Imm8\r\n\r\nDescription\r\nShifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and\r\nplace the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destina-\r\ntion are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for\r\nword shift), 31 (for doubleword shift) or 63 (for quadword shift).\r\n\r\nOperation\r\nKSHIFTLW\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=15\r\n    THEN DEST[15:0] <- SRC1[15:0] << COUNT;\r\nFI;\r\n\r\nKSHIFTLB\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=7\r\n        THEN    DEST[7:0] <- SRC1[7:0] << COUNT;\r\nFI;\r\n\r\nKSHIFTLQ\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=63\r\n        THEN    DEST[63:0] <- SRC1[63:0] << COUNT;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKSHIFTLD\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=31\r\n        THEN    DEST[31:0] <- SRC1[31:0] << COUNT;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCompiler auto generates KSHIFTLW when needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KSHIFTLW"
    }, 
    {
      "description": "-R:KSHIFTRW", 
      "mnem": "KSHIFTRB"
    }, 
    {
      "description": "-R:KSHIFTRW", 
      "mnem": "KSHIFTRD"
    }, 
    {
      "description": "-R:KSHIFTRW", 
      "mnem": "KSHIFTRQ"
    }, 
    {
      "description": "KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD-Shift Right Mask Registers\r\n Opcode/                          Op/En    64/32         CPUID         Description\r\n Instruction                               bit Mode      Feature\r\n                                           Support       Flag\r\n VEX.L0.66.0F3A.W1 30 /r          RRI      V/V           AVX512F       Shift right 16 bits in k2 by immediate and write result in k1.\r\n KSHIFTRW k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 30 /r          RRI      V/V           AVX512DQ      Shift right 8 bits in k2 by immediate and write result in k1.\r\n KSHIFTRB k1, k2, imm8\r\n VEX.L0.66.0F3A.W1 31 /r          RRI      V/V           AVX512BW      Shift right 64 bits in k2 by immediate and write result in k1.\r\n KSHIFTRQ k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 31 /r          RRI      V/V           AVX512BW      Shift right 32 bits in k2 by immediate and write result in k1.\r\n KSHIFTRD k1, k2, imm8\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n    Op/En                  Operand 1                                Operand 2                                 Operand 3\r\n     RRI                 ModRM:reg (w)                ModRM:r/m (r, ModRM:[7:6] must be 11b)                     Imm8\r\n\r\nDescription\r\nShifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place\r\nthe least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are\r\nzero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift),\r\n31 (for doubleword shift) or 63 (for quadword shift).\r\n\r\nOperation\r\nKSHIFTRW\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=15\r\n    THEN DEST[15:0] <- SRC1[15:0] >> COUNT;\r\nFI;\r\n\r\nKSHIFTRB\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=7\r\n        THEN    DEST[7:0] <- SRC1[7:0] >> COUNT;\r\nFI;\r\n\r\nKSHIFTRQ\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=63\r\n        THEN    DEST[63:0] <- SRC1[63:0] >> COUNT;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKSHIFTRD\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=31\r\n        THEN    DEST[31:0] <- SRC1[31:0] >> COUNT;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCompiler auto generates KSHIFTRW when needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KSHIFTRW"
    }, 
    {
      "description": "-R:KTESTW", 
      "mnem": "KTESTB"
    }, 
    {
      "description": "-R:KTESTW", 
      "mnem": "KTESTD"
    }, 
    {
      "description": "-R:KTESTW", 
      "mnem": "KTESTQ"
    }, 
    {
      "description": "KTESTW/KTESTB/KTESTQ/KTESTD-Packed Bit Test Masks and Set Flags\r\n Opcode/                   Op      64/32       CPUID          Description\r\n Instruction               En      bit Mode    Feature\r\n                                   Support     Flag\r\n VEX.L0.0F.W0 99 /r        RR      V/V         AVX512DQ       Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask\r\n KTESTW k1, k2                                                register sources.\r\n VEX.L0.66.0F.W0 99 /r     RR      V/V         AVX512DQ       Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask\r\n KTESTB k1, k2                                                register sources.\r\n VEX.L0.0F.W1 99 /r        RR      V/V         AVX512BW       Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask\r\n KTESTQ k1, k2                                                register sources.\r\n VEX.L0.66.0F.W1 99 /r     RR      V/V         AVX512BW       Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask\r\n KTESTD k1, k2                                                register sources.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n       Op/En                Operand 1                                             Operand2\r\n        RR                ModRM:reg (r)                            ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise comparison of the bits of the first source operand and corresponding bits in the second source\r\noperand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of\r\nthe inverted first source operand with the second source operand produces all zeros the CF is set else the CF is\r\nclear. Only the EFLAGS register is updated.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nKTESTW\r\nTEMP[15:0] <- SRC2[15:0] AND SRC1[15:0]\r\nIF (TEMP[15:0] = = 0)\r\n    THEN ZF <-1;\r\n    ELSE ZF <- 0;\r\nFI;\r\nTEMP[15:0] <- SRC2[15:0] AND NOT SRC1[15:0]\r\nIF (TEMP[15:0] = = 0)\r\n    THEN CF <-1;\r\n    ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nKTESTB\r\nTEMP[7:0] <- SRC2[7:0] AND SRC1[7:0]\r\nIF (TEMP[7:0] = = 0)\r\n    THEN ZF <-1;\r\n    ELSE ZF <- 0;\r\nFI;\r\nTEMP[7:0] <- SRC2[7:0] AND NOT SRC1[7:0]\r\nIF (TEMP[7:0] = = 0)\r\n    THEN CF <-1;\r\n    ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\n\r\n\r\n\r\n\r\nKTESTQ\r\nTEMP[63:0] <- SRC2[63:0] AND SRC1[63:0]\r\nIF (TEMP[63:0] = = 0)\r\n    THEN ZF <-1;\r\n    ELSE ZF <- 0;\r\nFI;\r\nTEMP[63:0] <- SRC2[63:0] AND NOT SRC1[63:0]\r\nIF (TEMP[63:0] = = 0)\r\n    THEN CF <-1;\r\n    ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nKTESTD\r\nTEMP[31:0] <- SRC2[31:0] AND SRC1[31:0]\r\nIF (TEMP[31:0] = = 0)\r\n    THEN ZF <-1;\r\n    ELSE ZF <- 0;\r\nFI;\r\nTEMP[31:0] <- SRC2[31:0] AND NOT SRC1[31:0]\r\nIF (TEMP[31:0] = = 0)\r\n    THEN CF <-1;\r\n    ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KTESTW"
    }, 
    {
      "description": "KUNPCKBW/KUNPCKWD/KUNPCKDQ-Unpack for Mask Registers\r\n Opcode/                        Op/En     64/32      CPUID         Description\r\n Instruction                              bit Mode   Feature\r\n                                          Support    Flag\r\n VEX.NDS.L1.66.0F.W0 4B /r      RVR       V/V        AVX512F       Unpack and interleave 8 bits masks in k2 and k3 and write\r\n KUNPCKBW k1, k2, k3                                               word result in k1.\r\n VEX.NDS.L1.0F.W0 4B /r         RVR       V/V        AVX512BW      Unpack and interleave 16 bits in k2 and k3 and write double-\r\n KUNPCKWD k1, k2, k3                                               word result in k1.\r\n VEX.NDS.L1.0F.W1 4B /r         RVR       V/V        AVX512BW      Unpack and interleave 32 bits masks in k2 and k3 and write\r\n KUNPCKDQ k1, k2, k3                                               quadword result in k1.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n    Op/En                  Operand 1                           Operand 2                              Operand 3\r\n    RVR                   ModRM:reg (w)                     VEX.1vvv (r)               ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nUnpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first\r\noperand (destination operand), starting from the low bytes. The result is zero-extended in the destination.\r\n\r\nOperation\r\nKUNPCKBW\r\nDEST[7:0] <- SRC2[7:0]\r\nDEST[15:8] <- SRC1[7:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKUNPCKWD\r\nDEST[15:0] <- SRC2[15:0]\r\nDEST[31:16] <- SRC1[15:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nKUNPCKDQ\r\nDEST[31:0] <- SRC2[31:0]\r\nDEST[63:32] <- SRC1[31:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);\r\nKUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);\r\nKUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KUNPCKBW"
    }, 
    {
      "description": "-R:KUNPCKBW", 
      "mnem": "KUNPCKDQ"
    }, 
    {
      "description": "-R:KUNPCKBW", 
      "mnem": "KUNPCKWD"
    }, 
    {
      "description": "-R:KXNORW", 
      "mnem": "KXNORB"
    }, 
    {
      "description": "-R:KXNORW", 
      "mnem": "KXNORD"
    }, 
    {
      "description": "-R:KXNORW", 
      "mnem": "KXNORQ"
    }, 
    {
      "description": "KXNORW/KXNORB/KXNORQ/KXNORD-Bitwise Logical XNOR Masks\r\n Opcode/                      Op/En   64/32         CPUID         Description\r\n Instruction                          bit Mode      Feature\r\n                                      Support       Flag\r\n VEX.NDS.L1.0F.W0 46 /r       RVR     V/V           AVX512F       Bitwise XNOR 16 bits masks k2 and k3 and place result in k1.\r\n KXNORW k1, k2, k3\r\n VEX.L1.66.0F.W0 46 /r        RVR     V/V           AVX512DQ      Bitwise XNOR 8 bits masks k2 and k3 and place result in k1.\r\n KXNORB k1, k2, k3\r\n VEX.L1.0F.W1 46 /r           RVR     V/V           AVX512BW      Bitwise XNOR 64 bits masks k2 and k3 and place result in k1.\r\n KXNORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 46 /r        RVR     V/V           AVX512BW      Bitwise XNOR 32 bits masks k2 and k3 and place result in k1.\r\n KXNORD k1, k2, k3\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n   Op/En                  Operand 1                           Operand 2                              Operand 3\r\n    RVR               ModRM:reg (w)                       VEX.1vvv (r)                ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector\r\nmask k1 (three-operand form).\r\n\r\nOperation\r\nKXNORW\r\nDEST[15:0] <- NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKXNORB\r\nDEST[7:0] <- NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKXNORQ\r\nDEST[63:0] <- NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKXNORD\r\nDEST[31:0] <- NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KXNORW"
    }, 
    {
      "description": "-R:KXORW", 
      "mnem": "KXORB"
    }, 
    {
      "description": "-R:KXORW", 
      "mnem": "KXORD"
    }, 
    {
      "description": "-R:KXORW", 
      "mnem": "KXORQ"
    }, 
    {
      "description": "KXORW/KXORB/KXORQ/KXORD-Bitwise Logical XOR Masks\r\n Opcode/                        Op/En     64/32      CPUID          Description\r\n Instruction                              bit Mode   Feature\r\n                                          Support    Flag\r\n VEX.NDS.L1.0F.W0 47 /r         RVR       V/V        AVX512F        Bitwise XOR 16 bits masks k2 and k3 and place result in k1.\r\n KXORW k1, k2, k3\r\n VEX.L1.66.0F.W0 47 /r          RVR       V/V        AVX512DQ       Bitwise XOR 8 bits masks k2 and k3 and place result in k1.\r\n KXORB k1, k2, k3\r\n VEX.L1.0F.W1 47 /r             RVR       V/V        AVX512BW       Bitwise XOR 64 bits masks k2 and k3 and place result in k1.\r\n KXORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 47 /r          RVR       V/V        AVX512BW       Bitwise XOR 32 bits masks k2 and k3 and place result in k1.\r\n KXORD k1, k2, k3\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n    Op/En                  Operand 1                        Operand 2                                Operand 3\r\n     RVR                  ModRM:reg (w)                     VEX.1vvv (r)              ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise XOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1 (three-operand form).\r\n\r\nOperation\r\nKXORW\r\nDEST[15:0] <- SRC1[15:0] BITWISE XOR SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKXORB\r\nDEST[7:0] <- SRC1[7:0] BITWISE XOR SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKXORQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKXORD\r\nDEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "KXORW"
    }, 
    {
      "description": "LAHF-Load Status Flags into AH Register\r\n Opcode                    Instruction                      Op/   64-Bit     Compat/ Description\r\n                                                            En    Mode       Leg Mode\r\n 9F                        LAHF                             NP    Invalid*   Valid    Load: AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF).\r\n NOTES:\r\n *Valid in specific steppings. See Description section.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n   Op/En               Operand 1                          Operand 2                  Operand 3                    Operand 4\r\n      NP                   NA                                NA                         NA                            NA\r\n\r\nDescription\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only\r\nif CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n    THEN\r\n         IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;\r\n              THEN AH <- RFLAGS(SF:ZF:0:AF:0:PF:1:CF);\r\n              ELSE #UD;\r\n         FI;\r\n    ELSE\r\n         AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF);\r\nFI;\r\n\r\nFlags Affected\r\nNone. The state of the flags in the EFLAGS register is not affected.\r\n\r\nProtected Mode Exceptions\r\n#UD                      If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD                      If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.\r\n                         If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LAHF"
    }, 
    {
      "description": "LAR-Load Access Rights Byte\r\nOpcode                     Instruction                    Op/    64-Bit       Compat/ Description\r\n                                                          En     Mode         Leg Mode\r\n0F 02 /r                   LAR r16, r16/m16               RM     Valid        Valid        r16 <- access rights referenced by r16/m16\r\n0F 02 /r                   LAR reg, r32/m161              RM     Valid        Valid        reg <- access rights referenced by r32/m16\r\nNOTES:\r\n1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n    Op/En                 Operand 1                      Operand 2                      Operand 3                   Operand 4\r\n      RM               ModRM:reg (w)                   ModRM:r/m (r)                        NA                         NA\r\n\r\nDescription\r\nLoads the access rights from the segment descriptor specified by the second operand (source operand) into the\r\nfirst operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a\r\nregister or a memory location) contains the segment selector for the segment descriptor being accessed. If the\r\nsource operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-\r\npurpose register.\r\nThe processor performs access checks as part of the loading process. Once loaded in the destination register, soft-\r\nware can perform additional checks on the access rights information.\r\nThe access rights for a segment descriptor include fields located in the second doubleword (bytes 4-7) of the\r\nsegment descriptor. The following fields are loaded by the LAR instruction:\r\n.   Bits 7:0 are returned as 0\r\n.   Bits 11:8 return the segment type.\r\n.   Bit 12 returns the S flag.\r\n.   Bits 14:13 return the DPL.\r\n.   Bit 15 returns the P flag.\r\n.   The following fields are returned only if the operand size is greater than 16 bits:\r\n    - Bits 19:16 are undefined.\r\n    - Bit 20 returns the software-available bit in the descriptor.\r\n    - Bit 21 returns the L flag.\r\n    - Bit 22 returns the D/B flag.\r\n    - Bit 23 returns the G flag.\r\n    - Bits 31:24 are returned as 0.\r\nThis instruction performs the following checks before it loads the access rights in the destination register:\r\n.   Checks that the segment selector is not NULL.\r\n.   Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being\r\n    accessed\r\n.   Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for\r\n    (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in\r\n    Table 3-52.\r\n.   If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at\r\n    the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment\r\n    selector).\r\nIf the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no\r\naccess rights are loaded in the destination operand.\r\n\r\n\r\n\r\nThe LAR instruction can only be executed in protected mode and IA-32e mode.\r\n                                             Table 3-52. Segment and Gate Types\r\n      Type                            Protected Mode                                               IA-32e Mode\r\n                                  Name                        Valid                       Name                         Valid\r\n        0          Reserved                                    No          Reserved                                     No\r\n        1          Available 16-bit TSS                        Yes         Reserved                                     No\r\n        2          LDT                                         Yes         LDT                                          No\r\n        3          Busy 16-bit TSS                             Yes         Reserved                                     No\r\n        4          16-bit call gate                            Yes         Reserved                                     No\r\n        5          16-bit/32-bit task gate                     Yes         Reserved                                     No\r\n        6          16-bit interrupt gate                       No          Reserved                                     No\r\n        7          16-bit trap gate                            No          Reserved                                     No\r\n        8          Reserved                                    No          Reserved                                     No\r\n        9          Available 32-bit TSS                        Yes         Available 64-bit TSS                         Yes\r\n        A          Reserved                                    No          Reserved                                     No\r\n        B          Busy 32-bit TSS                             Yes         Busy 64-bit TSS                              Yes\r\n        C          32-bit call gate                            Yes         64-bit call gate                             Yes\r\n        D          Reserved                                    No          Reserved                                     No\r\n        E          32-bit interrupt gate                       No          64-bit interrupt gate                        No\r\n        F          32-bit trap gate                            No          64-bit trap gate                             No\r\n\r\nOperation\r\nIF Offset(SRC) > descriptor table limit\r\n    THEN\r\n        ZF <- 0;\r\n    ELSE\r\n        SegmentDescriptor <- descriptor referenced by SRC;\r\n        IF SegmentDescriptor(Type) != conforming code segment\r\n        and (CPL > DPL) or (RPL > DPL)\r\n        or SegmentDescriptor(Type) is not valid for instruction\r\n             THEN\r\n                  ZF <- 0;\r\n             ELSE\r\n                  DEST <- access rights from SegmentDescriptor as given in Description section;\r\n                  ZF <- 1;\r\n        FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                        selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and the memory operand effective address is unaligned while\r\n                        the current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                     The LAR instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                     The LAR instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                  If the memory operand effective address referencing the SS segment is in a non-canonical\r\n                        form.\r\n#GP(0)                  If the memory operand effective address is in a non-canonical form.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and the memory operand effective address is unaligned while\r\n                        the current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LAR"
    }, 
    {
      "description": "LDDQU-Load Unaligned Integer 128 Bits\r\n    Opcode/                                        Op/   64/32-bit CPUID       Description\r\n    Instruction                                    En    Mode      Feature\r\n                                                                   Flag\r\n    F2 0F F0 /r                                    RM    V/V        SSE3       Load unaligned data from mem and return\r\n    LDDQU xmm1, mem                                                            double quadword in xmm1.\r\n\r\n    VEX.128.F2.0F.WIG F0 /r                        RM    V/V        AVX        Load unaligned packed integer values from\r\n    VLDDQU xmm1, m128                                                          mem to xmm1.\r\n\r\n    VEX.256.F2.0F.WIG F0 /r                        RM    V/V        AVX        Load unaligned packed integer values from\r\n    VLDDQU ymm1, m256                                                          mem to ymm1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n      Op/En             Operand 1                 Operand 2                  Operand 3                   Operand 4\r\n       RM             ModRM:reg (w)             ModRM:r/m (r)                   NA                           NA\r\n\r\nDescription\r\nThe instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is:\r\n32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched\r\nfrom memory and placed in a destination register (first operand). The source operand need not be aligned on a\r\n32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.\r\nThis instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line\r\nboundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use\r\n(V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that\r\nare known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.\r\n\r\nImplementation Notes\r\n.      If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be\r\n       loaded more than once. For that reason, the usage of (V)LDDQU should be avoided when using uncached or\r\n       write-combining (WC) memory regions. For uncached or WC memory regions, keep using (V)MOVDQU.\r\n.      This instruction is a replacement for (V)MOVDQU (load) in situations where cache line splits significantly affect\r\n       performance. It should not be used in situations where store-load forwarding is performance critical. If\r\n       performance of store-load forwarding is critical to the application, use (V)MOVDQA store-load pairs when data\r\n       is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.\r\n.      If the memory address is not aligned on 32/16-byte boundary, some implementations may load up to 64/32\r\n       bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to\r\n       access the appropriate 32/16 bytes. Developers of multi-threaded or multi-processor software should be aware\r\n       that on these processors the loads will be performed in a non-atomic way.\r\n.      If alignment checking is enabled (CR0.AM = 1, RFLAGS.AC = 1, and CPL = 3), an alignment-check exception\r\n       (#AC) may or may not be generated (depending on processor implementation) when the memory address is\r\n       not aligned on an 8-byte boundary.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nLDDQU (128-bit Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVLDDQU (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVLDDQU (VEX.256 encoded version)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nLDDQU:    __m128i _mm_lddqu_si128 (__m128i * p);\r\n\r\nVLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4;\r\nNote treatment of #AC varies.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LDDQU"
    }, 
    {
      "description": "LDMXCSR-Load MXCSR Register\r\n Opcode/                                            Op/     64/32-bit CPUID     Description\r\n Instruction                                        En      Mode      Feature\r\n                                                                      Flag\r\n 0F AE /2                                           M       V/V       SSE       Load MXCSR register from m32.\r\n LDMXCSR m32\r\n VEX.LZ.0F.WIG AE /2                                M       V/V       AVX       Load MXCSR register from m32.\r\n VLDMXCSR m32\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n    Op/En              Operand 1                Operand 2                   Operand 3                  Operand 4\r\n      M            ModRM:r/m (r)                   NA                           NA                        NA\r\n\r\nDescription\r\nLoads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location.\r\nSee \"MXCSR Control and Status Register\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1, for a description of the MXCSR register and its contents.\r\nThe LDMXCSR instruction is typically used in conjunction with the (V)STMXCSR instruction, which stores the\r\ncontents of the MXCSR register in memory.\r\nThe default MXCSR value at reset is 1F80H.\r\nIf a (V)LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception\r\nflag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only\r\nupon the execution of the next instruction that meets both conditions below:\r\n.   the instruction must operate on an XMM or YMM register operand,\r\n.   the instruction causes that particular SIMD floating-point exception to be reported.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nIf VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nMXCSR <- m32;\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\n_mm_setcsr(unsigned int i)\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 5; additionally\r\n#GP                     For an attempt to set reserved bits in MXCSR.\r\n#UD                     If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LDMXCSR"
    }, 
    {
      "description": "LDS/LES/LFS/LGS/LSS-Load Far Pointer\r\n Opcode                   Instruction                 Op/    64-Bit    Compat/ Description\r\n                                             … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "LDS"
    }, 
    {
      "description": "LEA-Load Effective Address\r\nOpcode                       Instruction                     Op/   64-Bit        Compat/ Description\r\n                                                             En    Mode          Leg Mode\r\n8D /r                        LEA r16,m                       RM    Valid         Valid       Store effective address for m in register r16.\r\n8D /r                        LEA r32,m                       RM    Valid         Valid       Store effective address for m in register r32.\r\nREX.W + 8D /r                LEA r64,m                       RM    Valid         N.E.        Store effective address for m in register r64.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n    Op/En              Operand 1                         Operand 2                       Operand 3                       Operand 4\r\n     RM             ModRM:reg (w)                      ModRM:r/m (r)                         NA                             NA\r\n\r\nDescription\r\nComputes the effective address of the second operand (the source operand) and stores it in the first operand\r\n(destination operand). The source operand is a memory address (offset part) specified with one of the processors\r\naddressing modes; the destination operand is a general-purpose register. The address-size and operand-size attri-\r\nbutes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of\r\nthe instruction is determined by the chosen register; the address-size attribute is determined by the attribute of\r\nthe code segment.\r\n                 Table 3-53. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes\r\n  Operand Size       Address Size                                                 Action Performed\r\n        16                   16            16-bit effective address is calculated and stored in requested 16-bit register destination.\r\n        16                   32            32-bit effective address is calculated. The lower 16 bits of the address are stored in the\r\n                                           requested 16-bit register destination.\r\n        32                   16            16-bit effective address is calculated. The 16-bit address is zero-extended and stored in the\r\n                                           requested 32-bit register destination.\r\n        32                   32            32-bit effective address is calculated and stored in the requested 32-bit register destination.\r\n\r\nDifferent assemblers may use different algorithms based on the size attribute and symbolic reference of the source\r\noperand.\r\nIn 64-bit mode, the instruction's destination operand is governed by operand size attribute, the default operand\r\nsize is 32 bits. Address calculation is governed by address size attribute, the default address size is 64-bits. In 64-\r\nbit mode, address size of 16 bits is not encodable. See Table 3-54.\r\n                   Table 3-54. 64-bit Mode LEA Operation with Address and Operand Size Attributes\r\n  Operand Size       Address Size                                                 Action Performed\r\n        16                   32            32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are\r\n                                           stored in the requested 16-bit register destination (using 66H prefix).\r\n        16                   64            64-bit effective address is calculated (default address size). The lower 16 bits of the address\r\n                                           are stored in the requested 16-bit register destination (using 66H prefix).\r\n        32                   32            32-bit effective address is calculated (using 67H prefix) and stored in the requested 32-bit\r\n                                           register destination.\r\n        32                   64            64-bit effective address is calculated (default address size) and the lower 32 bits of the\r\n                                           address are stored in the requested 32-bit register destination.\r\n        64                   32            32-bit effective address is calculated (using 67H prefix), zero-extended to 64-bits, and stored\r\n                                           in the requested 64-bit register destination (using REX.W).\r\n        64                   64            64-bit effective address is calculated (default address size) and all 64-bits of the address are\r\n                                           stored in the requested 64-bit register destination (using REX.W).\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF OperandSize = 16 and AddressSize = 16\r\n    THEN\r\n        DEST <- EffectiveAddress(SRC); (* 16-bit address *)\r\n    ELSE IF OperandSize = 16 and AddressSize = 32\r\n        THEN\r\n             temp <- EffectiveAddress(SRC); (* 32-bit address *)\r\n             DEST <- temp[0:15]; (* 16-bit address *)\r\n        FI;\r\n    ELSE IF OperandSize = 32 and AddressSize = 16\r\n        THEN\r\n             temp <- EffectiveAddress(SRC); (* 16-bit address *)\r\n             DEST <- ZeroExtend(temp); (* 32-bit address *)\r\n        FI;\r\n    ELSE IF OperandSize = 32 and AddressSize = 32\r\n        THEN\r\n             DEST <- EffectiveAddress(SRC); (* 32-bit address *)\r\n        FI;\r\n    ELSE IF OperandSize = 16 and AddressSize = 64\r\n        THEN\r\n             temp <- EffectiveAddress(SRC); (* 64-bit address *)\r\n             DEST <- temp[0:15]; (* 16-bit address *)\r\n        FI;\r\n    ELSE IF OperandSize = 32 and AddressSize = 64\r\n        THEN\r\n             temp <- EffectiveAddress(SRC); (* 64-bit address *)\r\n             DEST <- temp[0:31]; (* 16-bit address *)\r\n        FI;\r\n    ELSE IF OperandSize = 64 and AddressSize = 64\r\n        THEN\r\n             DEST <- EffectiveAddress(SRC); (* 64-bit address *)\r\n        FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                    If source operand is not a memory location.\r\n                       If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n", 
      "mnem": "LEA"
    }, 
    {
      "description": "LEAVE-High Level Procedure Exit\r\n Opcode                    Instruction          Op/     64-Bit   Compat/ Description\r\n                                                En      Mode     Leg Mode\r\n C9                        LEAVE                NP      Valid    Valid       Set SP to BP, then pop BP.\r\n C9                        LEAVE                NP      N.E.     Valid       Set ESP to EBP, then pop EBP.\r\n C9                        LEAVE                NP      Valid    N.E.        Set RSP to RBP, then pop RBP.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n   Op/En              Operand 1             Operand 2                    Operand 3                    Operand 4\r\n      NP                 NA                    NA                           NA                            NA\r\n\r\nDescription\r\nReleases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in\r\nthe EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame.\r\nThe old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then\r\npopped from the stack into the EBP register, restoring the calling procedure's stack frame.\r\nA RET instruction is commonly executed following a LEAVE instruction to return program control to the calling\r\nprocedure.\r\nSee \"Procedure Calls for Block-Structured Languages\" in Chapter 7 of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits; 32-bit operation cannot be encoded. See the\r\nsummary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF StackAddressSize = 32\r\n    THEN\r\n        ESP <- EBP;\r\n    ELSE IF StackAddressSize = 64\r\n        THEN RSP <- RBP; FI;\r\n    ELSE IF StackAddressSize = 16\r\n        THEN SP <- BP; FI;\r\nFI;\r\n\r\nIF OperandSize = 32\r\n    THEN EBP <- Pop();\r\n    ELSE IF OperandSize = 64\r\n        THEN RBP <- Pop(); FI;\r\n    ELSE IF OperandSize = 16\r\n        THEN BP <- Pop(); FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#SS(0)              If the EBP register points to a location that is not within the limits of the current stack\r\n                    segment.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If the EBP register points to a location outside of the effective address space from 0 to FFFFH.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If the EBP register points to a location outside of the effective address space from 0 to FFFFH.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If the stack address is in a non-canonical form.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LEAVE"
    }, 
    {
      "description": "-R:LDS", 
      "mnem": "LES"
    }, 
    {
      "description": "LFENCE-Load Fence\r\n Opcode                   Instruction                 Op/    64-Bit      Compat/ Description\r\n                                                      En     Mode        Leg Mode\r\n 0F AE E8                 LFENCE                      NP     Valid       Valid       Serializes load operations.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n   Op/En            Operand 1                    Operand 2                       Operand 3                         Operand 4\r\n    NP                   NA                           NA                            NA                                NA\r\n\r\nDescription\r\nPerforms a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruc-\r\ntion. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruc-\r\ntion begins execution until LFENCE completes. In particular, an instruction that loads from memory and that\r\nprecedes an LFENCE receives data from memory prior to completion of the LFENCE. (An LFENCE that follows an\r\ninstruction that stores to memory might complete before the data being stored have become globally visible.)\r\nInstructions following an LFENCE may be fetched from memory before the LFENCE, but they will not execute until\r\nthe LFENCE completes.\r\nWeakly ordered memory types can be used to achieve higher processor performance through such techniques as\r\nout-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the\r\ndata is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE\r\ninstruction provides a performance-efficient way of ensuring load ordering between routines that produce weakly-\r\nordered results and routines that consume that data.\r\nProcessors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC,\r\nand WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution.\r\nThus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches\r\nspeculatively just before, during, or after the execution of an LFENCE instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nSpecification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor\r\nignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is\r\nin the range 8-F.\r\n\r\nOperation\r\nWait_On_Following_Instructions_Until(preceding_instructions_complete);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_lfence(void)\r\n\r\nExceptions (All Modes of Operation)\r\n#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                        If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LFENCE"
    }, 
    {
      "description": "-R:LDS", 
      "mnem": "LFS"
    }, 
    {
      "description": "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register\r\n Opcode                Instruction               Op/   64-Bit     Compat/ Description\r\n                                                 En    Mode       Leg Mode\r\n 0F 01 /2              LGDT m16&32               M     N.E.       Valid         Load m into GDTR.\r\n 0F 01 /3              LIDT m16&32               M     N.E.       Valid         Load m into IDTR.\r\n 0F 01 /2              LGDT m16&64               M     Valid      N.E.          Load m into GDTR.\r\n 0F 01 /3              LIDT m16&64               M     Valid      N.E.          Load m into IDTR.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n   Op/En            Operand 1                  Operand 2                    Operand 3                       Operand 4\r\n      M            ModRM:r/m (r)                  NA                            NA                              NA\r\n\r\nDescription\r\nLoads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor\r\ntable register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a\r\nlinear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor\r\ntable (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-\r\nbit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute\r\nis 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here,\r\nthe high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is\r\nfilled with zeros.\r\nThe LGDT and LIDT instructions are used only in operating-system software; they are not used in application\r\nprograms. They are the only instructions that directly load a linear address (that is, not a segment-relative\r\naddress) and a limit in protected mode. They are commonly executed in real-address mode to allow processor\r\ninitialization prior to switching to protected mode.\r\nIn 64-bit mode, the instruction's operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the\r\nsummary chart at the beginning of this section for encoding data and limits.\r\nSee \"SGDT-Store Global Descriptor Table Register\" in Chapter 4, Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF Instruction is LIDT\r\n     THEN\r\n         IF OperandSize = 16\r\n               THEN\r\n                    IDTR(Limit) <- SRC[0:15];\r\n                    IDTR(Base) <- SRC[16:47] AND 00FFFFFFH;\r\n               ELSE IF 32-bit Operand Size\r\n                    THEN\r\n                         IDTR(Limit) <- SRC[0:15];\r\n                         IDTR(Base) <- SRC[16:47];\r\n                    FI;\r\n               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)\r\n                    THEN\r\n                         IDTR(Limit) <- SRC[0:15];\r\n                         IDTR(Base) <- SRC[16:79];\r\n                    FI;\r\n         FI;\r\n     ELSE (* Instruction is LGDT *)\r\n         IF OperandSize = 16\r\n               THEN\r\n                    GDTR(Limit) <- SRC[0:15];\r\n                    GDTR(Base) <- SRC[16:47] AND 00FFFFFFH;\r\n               ELSE IF 32-bit Operand Size\r\n                    THEN\r\n                         GDTR(Limit) <- SRC[0:15];\r\n                         GDTR(Base) <- SRC[16:47];\r\n                    FI;\r\n               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)\r\n                    THEN\r\n                         GDTR(Limit) <- SRC[0:15];\r\n                         GDTR(Base) <- SRC[16:79];\r\n                    FI;\r\n         FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                       If source operand is not a memory location.\r\n                          If the LOCK prefix is used.\r\n#GP(0)                    If the current privilege level is not 0.\r\n                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                          If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                          selector.\r\n#SS(0)                    If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)           If a page fault occurs.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If source operand is not a memory location.\r\n                    If the LOCK prefix is used.\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 If source operand is not a memory location.\r\n                    If the LOCK prefix is used.\r\n#GP(0)              The LGDT and LIDT instructions are not recognized in virtual-8086 mode.\r\n#GP                 If the current privilege level is not 0.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If the memory address is in a non-canonical form.\r\n#UD                 If source operand is not a memory location.\r\n                    If the LOCK prefix is used.\r\n#PF(fault-code)     If a page fault occurs.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LGDT"
    }, 
    {
      "description": "-R:LDS", 
      "mnem": "LGS"
    }, 
    {
      "description": "-R:LGDT", 
      "mnem": "LIDT"
    }, 
    {
      "description": "LLDT-Load Local Descriptor Table Register\r\n Opcode                     Instruction          Op/    64-Bit    Compat/ Description\r\n                                                 En     Mode      Leg Mode\r\n 0F 00 /2                   LLDT r/m16           M      Valid     Valid      Load segment selector r/m16 into LDTR.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n   Op/En               Operand 1              Operand 2                   Operand 3                   Operand 4\r\n     M               ModRM:r/m (r)               NA                          NA                          NA\r\n\r\nDescription\r\nLoads the source operand into the segment selector field of the local descriptor table register (LDTR). The source\r\noperand (a general-purpose register or a memory location) contains a segment selector that points to a local\r\ndescriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses the segment selector\r\nto locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit\r\nand base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS,\r\nGS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current\r\ntask.\r\nIf bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently.\r\nHowever, all subsequent references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions)\r\ncause a general protection exception (#GP).\r\nThe operand-size attribute has no effect on this instruction.\r\nThe LLDT instruction is provided for use in operating-system software; it should not be used in application\r\nprograms. This instruction can only be executed in protected mode or 64-bit mode.\r\nIn 64-bit mode, the operand size is fixed at 16 bits.\r\n\r\nOperation\r\nIF SRC(Offset) > descriptor table limit\r\n    THEN #GP(segment selector); FI;\r\n\r\nIF segment selector is valid\r\n\r\n   Read segment descriptor;\r\n\r\n   IF SegmentDescriptor(Type) != LDT\r\n        THEN #GP(segment selector); FI;\r\n   IF segment descriptor is not present\r\n        THEN #NP(segment selector); FI;\r\n\r\n    LDTR(SegmentSelector) <- SRC;\r\n    LDTR(SegmentDescriptor) <- GDTSegmentDescriptor;\r\nELSE LDTR <- INVALID\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#GP(selector)       If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT\r\n                    is not a Local Descriptor Table.\r\n                    Segment selector is beyond GDT limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#NP(selector)       If the LDT descriptor is not present.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 The LLDT instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 The LLDT instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If the memory address is in a non-canonical form.\r\n#GP(selector)       If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT\r\n                    is not a Local Descriptor Table.\r\n                    Segment selector is beyond GDT limit.\r\n#NP(selector)       If the LDT descriptor is not present.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LLDT"
    }, 
    {
      "description": "LMSW-Load Machine Status Word\r\n Opcode                   Instruction                 Op/   64-Bit   Compat/ Description\r\n                                                      En    Mode     Leg Mode\r\n 0F 01 /6                 LMSW r/m16                  M     Valid    Valid      Loads r/m16 in machine status word of CR0.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En               Operand 1                   Operand 2                 Operand 3                   Operand 4\r\n      M             ModRM:r/m (r)                      NA                       NA                          NA\r\n\r\nDescription\r\nLoads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can\r\nbe a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which\r\ncontains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are\r\nnot affected. The operand-size attribute has no effect on this instruction.\r\nIf the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected\r\nmode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back\r\nto real-address mode.\r\nThe LMSW instruction is provided for use in operating-system software; it should not be used in application\r\nprograms. In protected or virtual-8086 mode, it can only be executed at CPL 0.\r\nThis instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to\r\nrun on IA-32 and Intel 64 processors beginning with Intel386 processors should use the MOV (control registers)\r\ninstruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0,\r\nallowing a procedure or program to switch between protected and real-address modes.\r\nThis instruction is a serializing instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed\r\nat 16 bits.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nCR0[0:3] <- SRC[0:3];\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the current privilege level is not 0.\r\n                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                       selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              The LMSW instruction is not recognized in real-address mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If the memory address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LMSW"
    }, 
    {
      "description": "LOCK-Assert LOCK# Signal Prefix\r\n Opcode                    Instruction                   Op/   64-Bit   Compat/ Description\r\n                                                         En    Mode     Leg Mode\r\n F0                        LOCK                          NP    Valid    Valid       Asserts LOCK# signal for duration of the\r\n                                                                                    accompanying instruction.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En               Operand 1                    Operand 2                   Operand 3                    Operand 4\r\n      NP                   NA                            NA                        NA                            NA\r\n\r\nDescription\r\nCauses the processor's LOCK# signal to be asserted during execution of the accompanying instruction (turns the\r\ninstruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the\r\nprocessor has exclusive use of any shared memory while the signal is asserted.\r\nIn most IA-32 and all Intel 64 processors, locking may occur without the LOCK# signal being asserted. See the \"IA-\r\n32 Architecture Compatibility\" section below for more details.\r\nThe LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions\r\nwhere the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B,\r\nCMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of\r\nthese instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be\r\ngenerated. An undefined opcode exception will also be generated if the LOCK prefix is used with any instruction not\r\nin the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of\r\nthe LOCK prefix.\r\nThe LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory\r\nlocation in shared memory environment.\r\nThe integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed\r\nfor arbitrarily misaligned fields.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nBeginning with the P6 family processors, when the LOCK prefix is prefixed to an instruction and the memory area\r\nbeing accessed is cached internally in the processor, the LOCK# signal is generally not asserted. Instead, only the\r\nprocessor's cache is locked. Here, the processor's cache coherency mechanism ensures that the operation is\r\ncarried out atomically with regards to memory. See \"Effects of a Locked Operation on Internal Processor Caches\"\r\nin Chapter 8 of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, the for more informa-\r\ntion on locking of caches.\r\n\r\nOperation\r\nAssertLOCK#(DurationOfAccompaningInstruction);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD                     If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS,\r\n                        CMPXCHG, CMPXCH8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,\r\n                        XCHG.\r\n                        Other exceptions can be generated by the instruction when the LOCK prefix is applied.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LOCK"
    }, 
    {
      "description": "LODS/LODSB/LODSW/LODSD/LODSQ-Load String\r\n Opcode                 Instruction               Op/     64-Bit   Compat/ Description\r\n                                                  En      Mode     Leg Mode\r\n AC                     LODS m8                   NP      Valid    Valid       For legacy mode, Load byte at address DS:(E)SI\r\n                                                                               into AL. For 64-bit mode load byte at address\r\n                                                                               (R)SI into AL.\r\n AD                     LODS m16                  NP      Valid    Valid       For legacy mode, Load word at address\r\n                                                                               DS:(E)SI into AX. For 64-bit mode load word at\r\n                                                                               address (R)SI into AX.\r\n AD                     LODS m32                  NP      Valid    Valid       For legacy mode, Load dword at address\r\n                                                                               DS:(E)SI into EAX. For 64-bit mode load dword\r\n                                                                               at address (R)SI into EAX.\r\n REX.W + AD             LODS m64                  NP      Valid    N.E.        Load qword at address (R)SI into RAX.\r\n AC                     LODSB                     NP      Valid    Valid       For legacy mode, Load byte at address DS:(E)SI\r\n                                                                               into AL. For 64-bit mode load byte at address\r\n                                                                               (R)SI into AL.\r\n AD                     LODSW                     NP      Valid    Valid       For legacy mode, Load word at address\r\n                                                                               DS:(E)SI into AX. For 64-bit mode load word at\r\n                                                                               address (R)SI into AX.\r\n AD                     LODSD                     NP      Valid    Valid       For legacy mode, Load dword at address\r\n                                                                               DS:(E)SI into EAX. For 64-bit mode load dword\r\n                                                                               at address (R)SI into EAX.\r\n REX.W + AD             LODSQ                     NP      Valid    N.E.        Load qword at address (R)SI into RAX.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n   Op/En           Operand 1                  Operand 2                    Operand 3                     Operand 4\r\n      NP               NA                        NA                           NA                             NA\r\n\r\nDescription\r\nLoads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The\r\nsource operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers\r\n(depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be over-\r\nridden with a segment override prefix.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be\r\nspecified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source\r\nvalue. The destination operand is then automatically selected to match the size of the source operand (the AL\r\nregister for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form\r\nis provided to allow documentation; however, note that the documentation provided by this form can be\r\nmisleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or\r\ndoubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI\r\nregisters, which must be loaded correctly before the load string instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the LODS instructions.\r\nHere also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the desti-\r\nnation operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte\r\nloaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).\r\nAfter the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the\r\n(E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS\r\nregister. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.)\r\nThe (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for\r\ndoubleword operations.\r\n\r\n\r\n\r\nIn 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQ load the quadword at address\r\n(R)SI into RAX. The (R)SI register is then incremented or decremented automatically according to the setting of\r\nthe DF flag in the EFLAGS register.\r\nThe LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes,\r\nwords, or doublewords. More often, however, these instructions are used within a LOOP construct because further\r\nprocessing of the data moved into the register is usually necessary before the next transfer can be made. See\r\n\"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix\" in Chapter 4 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 2B, for a description of the REP prefix.\r\n\r\nOperation\r\nIF AL <- SRC; (* Byte load *)\r\n    THEN AL <- SRC; (* Byte load *)\r\n        IF DF = 0\r\n             THEN (E)SI <- (E)SI + 1;\r\n             ELSE (E)SI <- (E)SI - 1;\r\n        FI;\r\nELSE IF AX <- SRC; (* Word load *)\r\n    THEN IF DF = 0\r\n             THEN (E)SI <- (E)SI + 2;\r\n             ELSE (E)SI <- (E)SI - 2;\r\n        IF;\r\n    FI;\r\nELSE IF EAX <- SRC; (* Doubleword load *)\r\n    THEN IF DF = 0\r\n             THEN (E)SI <- (E)SI + 4;\r\n             ELSE (E)SI <- (E)SI - 4;\r\n        FI;\r\n    FI;\r\nELSE IF RAX <- SRC; (* Quadword load *)\r\n    THEN IF DF = 0\r\n             THEN (R)SI <- (R)SI + 8;\r\n             ELSE (R)SI <- (R)SI - 8;\r\n        FI;\r\n    FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                       If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                    If a memory operand effective address is outside the SS segment limit.\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LODS"
    }, 
    {
      "description": "-R:LODS", 
      "mnem": "LODSB"
    }, 
    {
      "description": "-R:LODS", 
      "mnem": "LODSD"
    }, 
    {
      "description": "-R:LODS", 
      "mnem": "LODSQ"
    }, 
    {
      "description": "-R:LODS", 
      "mnem": "LODSW"
    }, 
    {
      "description": "LOOP/LOOPcc-Loop According to ECX Counter\r\nOpcode                       Instruction               Op/    64-Bit   Compat/ Description\r\n                                                       En     Mode     Leg Mode\r\nE2 cb                        LOOP rel8                 D      Valid    Valid      Decrement count; jump short if count != 0.\r\nE1 cb                        LOOPE rel8                D      Valid    Valid      Decrement count; jump short if count != 0 and\r\n                                                                                  ZF = 1.\r\nE0 cb                        LOOPNE rel8               D      Valid    Valid      Decrement count; jump short if count != 0 and\r\n                                                                                  ZF = 0.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En             Operand 1                      Operand 2                  Operand 3                   Operand 4\r\n     D                 Offset                           NA                        NA                           NA\r\n\r\nDescription\r\nPerforms a loop operation using the RCX, ECX or CX register as a counter (depending on whether address size is 64\r\nbits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W; but 64-bit address size can be over-ridden\r\nusing a 67H prefix.\r\nEach time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is\r\n0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If\r\nthe count is not zero, a near jump is performed to the destination (target) operand, which is presumably the\r\ninstruction at the beginning of the loop.\r\nThe target instruction is specified with a relative offset (a signed offset relative to the current value of the instruc-\r\ntion pointer in the IP/EIP/RIP register). This offset is generally specified as a label in assembly code, but at the\r\nmachine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer.\r\nOffsets of -128 to +127 are allowed with this instruction.\r\nSome forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before\r\nthe count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction\r\nto indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag;\r\nthe ZF flag is changed by other instructions in the loop.\r\n\r\nOperation\r\nIF (AddressSize = 32)\r\n    THEN Count is ECX;\r\nELSE IF (AddressSize = 64)\r\n    Count is RCX;\r\nELSE Count is CX;\r\nFI;\r\n\r\nCount <- Count - 1;\r\n\r\nIF Instruction is not LOOP\r\n     THEN\r\n         IF (Instruction <- LOOPE) or (Instruction <- LOOPZ)\r\n               THEN IF (ZF = 1) and (Count != 0)\r\n                         THEN BranchCond <- 1;\r\n                         ELSE BranchCond <- 0;\r\n                    FI;\r\n               ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ)\r\n                    IF (ZF = 0 ) and (Count != 0)\r\n                         THEN BranchCond <- 1;\r\n                         ELSE BranchCond <- 0;\r\n\r\n\r\n\r\n\r\n                    FI;\r\n          FI;\r\n      ELSE (* Instruction = LOOP *)\r\n          IF (Count != 0)\r\n                THEN BranchCond <- 1;\r\n                ELSE BranchCond <- 0;\r\n          FI;\r\nFI;\r\n\r\nIF BranchCond = 1\r\n    THEN\r\n        IF OperandSize = 32\r\n             THEN EIP <- EIP + SignExtend(DEST);\r\n             ELSE IF OperandSize = 64\r\n                 THEN RIP <- RIP + SignExtend(DEST);\r\n                 FI;\r\n             ELSE IF OperandSize = 16\r\n                 THEN EIP <- EIP AND 0000FFFFH;\r\n                 FI;\r\n        FI;\r\n        IF OperandSize = (32 or 64)\r\n             THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit\r\n                 #GP; FI;\r\n                 FI;\r\n        FI;\r\n    ELSE\r\n        Terminate loop and continue program execution at (R/E)IP;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the offset being jumped to is beyond the limits of the CS segment.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If the offset being jumped to is beyond the limits of the CS segment or is outside of the effec-\r\n                        tive address space from 0 to FFFFH. This condition can occur if a 32-bit address size override\r\n                        prefix is used.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                  If the offset being jumped to is in a non-canonical form.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LOOP"
    }, 
    {
      "description": "-R:LOOP", 
      "mnem": "LOOPcc"
    }, 
    {
      "description": "LSL-Load Segment Limit\r\nOpcode                     Instruction                    Op/    64-Bit       Compat/ Description\r\n                                                          En     Mode         Leg Mode\r\n0F 03 /r                   LSL r16, r16/m16               RM     Valid        Valid        Load: r16 <- segment limit, selector r16/m16.\r\n0F 03 /r                   LSL r32, r32/m16*              RM     Valid        Valid        Load: r32 <- segment limit, selector r32/m16.\r\nREX.W + 0F 03 /r           LSL r64, r32/m16*              RM     Valid        Valid        Load: r64 <- segment limit, selector r32/m16\r\nNOTES:\r\n* For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n    Op/En             Operand 1                         Operand 2                       Operand 3                   Operand 4\r\n     RM             ModRM:reg (w)                     ModRM:r/m (r)                         NA                          NA\r\n\r\nDescription\r\nLoads the unscrambled segment limit from the segment descriptor specified with the second operand (source\r\noperand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source\r\noperand (which can be a register or a memory location) contains the segment selector for the segment descriptor\r\nbeing accessed. The destination operand is a general-purpose register.\r\nThe processor performs access checks as part of the loading process. Once loaded in the destination register, soft-\r\nware can compare the segment limit with the offset of a pointer.\r\nThe segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment\r\ndescriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination\r\noperand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the\r\ngranularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit\r\nbefore loading it into the destination operand. The translation is performed by shifting the 20-bit \"raw\" limit left 12\r\nbits and filling the low-order 12 bits with 1s.\r\nWhen the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size\r\nis 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits\r\nare loaded into the destination operand.\r\nThis instruction performs the following checks before it loads the segment limit into the destination register:\r\n.    Checks that the segment selector is not NULL.\r\n.    Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being\r\n     accessed\r\n.    Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for\r\n     (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the\r\n     following table.\r\n.    If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor\r\n     is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of\r\n     the segment selector).\r\nIf the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no\r\nvalue is loaded in the destination operand.\r\n\r\n\r\n\r\n\r\n\r\n                                          Table 3-55. Segment and Gate Descriptor Types\r\n       Type                               Protected Mode                                       IA-32e Mode\r\n                                  Name                     Valid                    Name                        Valid\r\n         0           Reserved                               No         Upper 8 byte of a 16-Byte                Yes\r\n                                                                       descriptor\r\n         1           Available 16-bit TSS                   Yes        Reserved                                  No\r\n         2           LDT                                    Yes        LDT                                      Yes\r\n         3           Busy 16-bit TSS                        Yes        Reserved                                  No\r\n         4           16-bit call gate                       No         Reserved                                  No\r\n         5           16-bit/32-bit task gate                No         Reserved                                  No\r\n         6           16-bit interrupt gate                  No         Reserved                                  No\r\n         7           16-bit trap gate                       No         Reserved                                  No\r\n         8           Reserved                               No         Reserved                                  No\r\n         9           Available 32-bit TSS                   Yes        64-bit TSS                               Yes\r\n         A           Reserved                               No         Reserved                                  No\r\n         B           Busy 32-bit TSS                        Yes        Busy 64-bit TSS                          Yes\r\n         C           32-bit call gate                       No         64-bit call gate                          No\r\n         D           Reserved                               No         Reserved                                  No\r\n         E           32-bit interrupt gate                  No         64-bit interrupt gate                     No\r\n         F           32-bit trap gate                       No         64-bit trap gate                          No\r\n\r\nOperation\r\nIF SRC(Offset) > descriptor table limit\r\n    THEN ZF <- 0; FI;\r\n\r\nRead segment descriptor;\r\n\r\nIF SegmentDescriptor(Type) != conforming code segment\r\nand (CPL > DPL) OR (RPL > DPL)\r\nor Segment type is not valid for instruction\r\n        THEN\r\n            ZF <- 0;\r\n        ELSE\r\n            temp <- SegmentLimit([SRC]);\r\n            IF (G <- 1)\r\n                 THEN temp <- ShiftLeft(12, temp) OR 00000FFFH;\r\n            ELSE IF OperandSize = 32\r\n                 THEN DEST <- temp; FI;\r\n            ELSE IF OperandSize = 64 (* REX.W used *)\r\n                 THEN DEST (* Zero-extended *) <- temp; FI;\r\n            ELSE (* OperandSize = 16 *)\r\n                 DEST <- temp AND FFFFH;\r\n            FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0.\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and the memory operand effective address is unaligned while\r\n                    the current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 The LSL instruction cannot be executed in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                 The LSL instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If the memory operand effective address referencing the SS segment is in a non-canonical\r\n                    form.\r\n#GP(0)              If the memory operand effective address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and the memory operand effective address is unaligned while\r\n                    the current privilege level is 3.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LSL"
    }, 
    {
      "description": "-R:LDS", 
      "mnem": "LSS"
    }, 
    {
      "description": "LTR-Load Task Register\r\n Opcode                     Instruction                  Op/       64-Bit   Compat/ Description\r\n                                                         En        Mode     Leg Mode\r\n 0F 00 /3                   LTR r/m16                    M         Valid    Valid       Load r/m16 into task register.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n   Op/En             Operand 1                      Operand 2                       Operand 3                    Operand 4\r\n     M             ModRM:r/m (r)                        NA                             NA                            NA\r\n\r\nDescription\r\nLoads the source operand into the segment selector field of the task register. The source operand (a general-\r\npurpose register or a memory location) contains a segment selector that points to a task state segment (TSS).\r\nAfter the segment selector is loaded in the task register, the processor uses the segment selector to locate the\r\nsegment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base\r\naddress for the TSS from the segment descriptor into the task register. The task pointed to by the task register is\r\nmarked busy, but a switch to the task does not occur.\r\nThe LTR instruction is provided for use in operating-system software; it should not be used in application programs.\r\nIt can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish\r\nthe first task to be executed.\r\nThe operand-size attribute has no effect on this instruction.\r\nIn 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the\r\n64-bit base.\r\n\r\nOperation\r\nIF SRC is a NULL selector\r\n    THEN #GP(0);\r\n\r\nIF SRC(Offset) > descriptor table limit OR IF SRC(type) != global\r\n    THEN #GP(segment selector); FI;\r\n\r\nRead segment descriptor;\r\n\r\nIF segment descriptor is not for an available TSS\r\n    THEN #GP(segment selector); FI;\r\nIF segment descriptor is not present\r\n    THEN #NP(segment selector); FI;\r\n\r\nTSSsegmentDescriptor(busy) <- 1;\r\n(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)\r\n\r\nTaskRegister(SegmentSelector) <- SRC;\r\nTaskRegister(SegmentDescriptor) <- TSSSegmentDescriptor;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the source operand contains a NULL segment selector.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n#GP(selector)       If the source selector points to a segment that is not a TSS or to one for a task that is already\r\n                    busy.\r\n                    If the selector points to LDT or is beyond the GDT limit.\r\n#NP(selector)       If the TSS is marked not present.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 The LTR instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD                  The LTR instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If the memory address is in a non-canonical form.\r\n                    If the source operand contains a NULL segment selector.\r\n#GP(selector)       If the source selector points to a segment that is not a TSS or to one for a task that is already\r\n                    busy.\r\n                    If the selector points to LDT or is beyond the GDT limit.\r\n                    If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero.\r\n#NP(selector)       If the TSS is marked not present.\r\n#PF(fault-code)     If a page fault occurs.\r\n#UD                 If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LTR"
    }, 
    {
      "description": "LZCNT- Count the Number of Leading Zero Bits\r\n Opcode/Instruction                Op/     64/32       CPUID        Description\r\n                                   En      -bit        Feature\r\n                                           Mode        Flag\r\n F3 0F BD /r                       RM      V/V         LZCNT        Count the number of leading zero bits in r/m16, return result in r16.\r\n LZCNT r16, r/m16\r\n\r\n F3 0F BD /r                       RM      V/V         LZCNT        Count the number of leading zero bits in r/m32, return result in r32.\r\n LZCNT r32, r/m32\r\n\r\n F3 REX.W 0F BD /r                 RM      V/N.E.      LZCNT        Count the number of leading zero bits in r/m64, return result in r64.\r\n LZCNT r64, r/m64\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n   Op/En             Operand 1                       Operand 2                       Operand 3                        Operand 4\r\n    RM             ModRM:reg (w)                    ModRM:r/m (r)                        NA                               NA\r\n\r\nDescription\r\nCounts the number of leading most significant zero bits in a source operand (second operand) returning the result\r\ninto a destination (first operand).\r\nLZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It\r\nshould be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR.\r\nIn 64-bit mode 64-bit operand size requires REX.W=1.\r\n\r\nOperation\r\ntemp <- OperandSize - 1\r\nDEST <- 0\r\nWHILE (temp >= 0) AND (Bit(SRC, temp) = 0)\r\nDO\r\n   temp <- temp - 1\r\n   DEST <- DEST+ 1\r\nOD\r\n\r\nIF DEST = OperandSize\r\n    CF <- 1\r\nELSE\r\n    CF <- 0\r\nFI\r\n\r\nIF DEST = 0\r\n    ZF <- 1\r\nELSE\r\n    ZF <- 0\r\nFI\r\n\r\nFlags Affected\r\nZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set\r\nto 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nLZCNT:          unsigned __int32 _lzcnt_u32(unsigned __int32 src);\r\n\r\nLZCNT:          unsigned __int64 _lzcnt_u64(unsigned __int64 src);\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n                         If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n                         selector.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#PF (fault-code)         For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0)                   If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0)                   If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0)                   For an illegal address in the SS segment.\r\n#PF (fault-code)         For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                   If the memory address is in a non-canonical form.\r\n#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code)         For a page fault.\r\n#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the\r\n                         current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "LZCNT"
    }, 
    {
      "description": "MASKMOVDQU-Store Selected Bytes of Double Quadword\r\n Opcode/                                            Op/   64/32-bit CPUID       Description\r\n Instruction                                        En    Mode      Feature\r\n                                                                    Flag\r\n 66 0F F7 /r                                        RM    V/V       SSE2        Selectively write bytes from xmm1 to\r\n MASKMOVDQU xmm1, xmm2                                                          memory location using the byte mask in\r\n                                                                                xmm2. The default memory location is\r\n                                                                                specified by DS:DI/EDI/RDI.\r\n VEX.128.66.0F.WIG F7 /r                            RM    V/V       AVX         Selectively write bytes from xmm1 to\r\n VMASKMOVDQU xmm1, xmm2                                                         memory location using the byte mask in\r\n                                                                                xmm2. The default memory location is\r\n                                                                                specified by DS:DI/EDI/RDI.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding1\r\n    Op/En           Operand 1                    Operand 2                    Operand 3                  Operand 4\r\n     RM            ModRM:reg (r)                ModRM:r/m (r)                    NA                          NA\r\n\r\n\r\nDescription\r\nStores selected bytes from the source operand (first operand) into an 128-bit memory location. The mask operand\r\n(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-\r\nands are XMM registers. The memory location specified by the effective address in the DI/EDI/RDI register (the\r\ndefault segment register is DS, but this may be overridden with a segment-override prefix). The memory location\r\ndoes not need to be aligned on a natural boundary. (The size of the store address depends on the address-size\r\nattribute.)\r\nThe most significant bit in each byte of the mask operand determines whether the corresponding byte in the source\r\noperand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.\r\nThe MASKMOVDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The\r\nnon-temporal hint is implemented by using a write combining (WC) memory type protocol (see \"Caching of\r\nTemporal vs. Non-Temporal Data\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing opera-\r\ntion implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVDQU\r\ninstructions if multiple processors might use different memory types to read/write the destination memory loca-\r\ntions.\r\nBehavior with a mask of all 0s is as follows:\r\n.    No data will be written to memory.\r\n.    Signaling of breakpoints (code or data) is not guaranteed; different processor implementations may signal or\r\n     not signal these breakpoints.\r\n.    Exceptions associated with addressing memory and page faults may still be signaled (implementation\r\n     dependent).\r\n.    If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these\r\n     memory types is not guaranteed (that is, is reserved) and is implementation-specific.\r\nThe MASKMOVDQU instruction can be used to improve performance of algorithms that need to merge data on a\r\nbyte-by-byte basis. MASKMOVDQU should not cause a read for ownership; doing so generates unnecessary band-\r\nwidth since data is to be written directly using the byte-mask without allocating old data prior to the store.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nIf VMASKMOVDQU is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will\r\ncause an #UD exception.\r\n\r\n1.ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOperation\r\n\r\nIF (MASK[7] = 1)\r\n    THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;\r\nIF (MASK[15] = 1)\r\n    THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;\r\n    (* Repeat operation for 3rd through 14th bytes in source operand *)\r\nIF (MASK[127] = 1)\r\n    THEN DEST[DI/EDI +15] <- SRC[127:120] ELSE (* Memory location unchanged *); FI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_maskmoveu_si128(__m128i d, __m128i n, char * p)\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                    If VEX.L= 1\r\n                       If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MASKMOVDQU"
    }, 
    {
      "description": "MASKMOVQ-Store Selected Bytes of Quadword\r\n Opcode/                                        Op/   64-Bit       Compat/ Description\r\n Instruction                                    En    Mode         Leg Mode\r\n 0F F7 /r                                       RM    Valid        Valid     Selectively write bytes from mm1 to memory\r\n MASKMOVQ mm1, mm2                                                           location using the byte mask in mm2. The\r\n                                                                             default memory location is specified by\r\n                                                                             DS:DI/EDI/RDI.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n    Op/En          Operand 1                  Operand 2                    Operand 3                    Operand 4\r\n     RM           ModRM:reg (r)             ModRM:r/m (r)                     NA                            NA\r\n\r\n\r\nDescription\r\nStores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand\r\n(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-\r\nands are MMX technology registers. The memory location specified by the effective address in the DI/EDI/RDI\r\nregister (the default segment register is DS, but this may be overridden with a segment-override prefix). The\r\nmemory location does not need to be aligned on a natural boundary. (The size of the store address depends on the\r\naddress-size attribute.)\r\nThe most significant bit in each byte of the mask operand determines whether the corresponding byte in the source\r\noperand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.\r\nThe MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-\r\ntemporal hint is implemented by using a write combining (WC) memory type protocol (see \"Caching of Temporal\r\nvs. Non-Temporal Data\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation imple-\r\nmented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVQ instructions if\r\nmultiple processors might use different memory types to read/write the destination memory locations.\r\nThis instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer\r\nis set to 0 and the x87 FPU tag word is set to all 0s [valid]).\r\nThe behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:\r\n.    No data will be written to memory.\r\n.    Transition from x87 FPU to MMX technology state will occur.\r\n.    Exceptions associated with addressing memory and page faults may still be signaled (implementation\r\n     dependent).\r\n.    Signaling of breakpoints (code or data) is not guaranteed (implementation dependent).\r\n.    If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these\r\n     memory types is not guaranteed (that is, is reserved) and is implementation-specific.\r\nThe MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-\r\nby-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is\r\nto be written directly using the byte-mask without allocating old data prior to the store.\r\nIn 64-bit mode, the memory address is specified by DS:RDI.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n\r\nIF (MASK[7] = 1)\r\n    THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;\r\nIF (MASK[15] = 1)\r\n    THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;\r\n    (* Repeat operation for 3rd through 6th bytes in source operand *)\r\nIF (MASK[63] = 1)\r\n    THEN DEST[DI/EDI +15] <- SRC[63:56] ELSE (* Memory location unchanged *); FI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_maskmove_si64(__m64d, __m64n, char * p)\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MASKMOVQ"
    }, 
    {
      "description": "MAXPD-Maximum of Packed Double-Precision Floating-Point Values\r\n Opcode/                                  Op /    64/32        CPUID          Description\r\n Instruction                              En      bit Mode     Feature\r\n                                                  Support      Flag\r\n 66 0F 5F /r                              RM      V/V          SSE2           Return the maximum double-precision floating-point\r\n MAXPD xmm1, xmm2/m128                                                        values between xmm1 and xmm2/m128.\r\n VEX.NDS.128.66.0F.WIG 5F /r              RVM     V/V          AVX            Return the maximum double-precision floating-point\r\n VMAXPD xmm1, xmm2, xmm3/m128                                                 values between xmm2 and xmm3/m128.\r\n VEX.NDS.256.66.0F.WIG 5F /r              RVM     V/V          AVX            Return the maximum packed double-precision\r\n VMAXPD ymm1, ymm2, ymm3/m256                                                 floating-point values between ymm2 and\r\n                                                                              ymm3/m256.\r\n EVEX.NDS.128.66.0F.W1 5F /r              FV      V/V          AVX512VL       Return the maximum packed double-precision\r\n VMAXPD xmm1 {k1}{z}, xmm2,                                    AVX512F        floating-point values between xmm2 and\r\n xmm3/m128/m64bcst                                                            xmm3/m128/m64bcst and store result in xmm1\r\n                                                                              subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5F /r              FV      V/V          AVX512VL       Return the maximum packed double-precision\r\n VMAXPD ymm1 {k1}{z}, ymm2,                                    AVX512F        floating-point values between ymm2 and\r\n ymm3/m256/m64bcst                                                            ymm3/m256/m64bcst and store result in ymm1\r\n                                                                              subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5F /r              FV      V/V          AVX512F        Return the maximum packed double-precision\r\n VMAXPD zmm1 {k1}{z}, zmm2,                                                   floating-point values between zmm2 and\r\n zmm3/m512/m64bcst{sae}                                                       zmm3/m512/m64bcst and store result in zmm1\r\n                                                                              subject to writemask k1.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n      Op/En               Operand 1                      Operand 2                   Operand 3                    Operand 4\r\n        RM             ModRM:reg (r, w)                 ModRM:r/m (r)                    NA                           NA\r\n       RVM              ModRM:reg (w)                     VEX.vvvv                 ModRM:r/m (r)                      NA\r\n        FV              ModRM:reg (w)                    EVEX.vvvv                 ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed double-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the maximum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a\r\nsequence of instructions, such as a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n        ELSE DEST <-SRC2;\r\n  FI;\r\n}\r\n\r\nVMAXPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[63:0])\r\n                    ELSE\r\n                         DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[i+63:i])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMAXPD (VEX.256 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])\r\nDEST[191:128] <-MAX(SRC1[191:128], SRC2[191:128])\r\nDEST[255:192] <-MAX(SRC1[255:192], SRC2[255:192])\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMAXPD (VEX.128 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMAXPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MAX(DEST[63:0], SRC[63:0])\r\nDEST[127:64] <-MAX(DEST[127:64], SRC[127:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);\r\nVMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);\r\nVMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMAXPD __m512d _mm512_max_round_pd( __m512d a, __m512d b, int);\r\nVMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);\r\nVMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);\r\nVMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);\r\nVMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);\r\n(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MAXPD"
    }, 
    {
      "description": "MAXPS-Maximum of Packed Single-Precision Floating-Point Values\r\n Opcode/                             Op /     64/32         CPUID      Description\r\n Instruction                         En       bit Mode      Feature\r\n                                              Support       Flag\r\n 0F 5F /r                            RM       V/V           SSE        Return the maximum single-precision floating-point values\r\n MAXPS xmm1, xmm2/m128                                                 between xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5F /r            RVM      V/V           AVX        Return the maximum single-precision floating-point values\r\n VMAXPS xmm1, xmm2,                                                    between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 5F /r            RVM      V/V           AVX        Return the maximum single-precision floating-point values\r\n VMAXPS ymm1, ymm2,                                                    between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 5F /r            FV       V/V           AVX512VL   Return the maximum packed single-precision floating-point\r\n VMAXPS xmm1 {k1}{z}, xmm2,                                 AVX512F    values between xmm2 and xmm3/m128/m32bcst and store\r\n xmm3/m128/m32bcst                                                     result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5F /r            FV       V/V           AVX512VL   Return the maximum packed single-precision floating-point\r\n VMAXPS ymm1 {k1}{z}, ymm2,                                 AVX512F    values between ymm2 and ymm3/m256/m32bcst and store\r\n ymm3/m256/m32bcst                                                     result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5F /r            FV       V/V           AVX512F    Return the maximum packed single-precision floating-point\r\n VMAXPS zmm1 {k1}{z}, zmm2,                                            values between zmm2 and zmm3/m512/m32bcst and store\r\n zmm3/m512/m32bcst{sae}                                                result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n     Op/En               Operand 1                       Operand 2                   Operand 3                  Operand 4\r\n      RM              ModRM:reg (r, w)               ModRM:r/m (r)                      NA                          NA\r\n      RVM              ModRM:reg (w)                     VEX.vvvv               ModRM:r/m (r)                       NA\r\n       FV              ModRM:reg (w)                     EVEX.vvvv               ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed single-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the maximum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n        ELSE DEST <-SRC2;\r\n  FI;\r\n}\r\n\r\nVMAXPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[31:0])\r\n                    ELSE\r\n                         DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[i+31:i])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMAXPS (VEX.256 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])\r\nDEST[159:128] <-MAX(SRC1[159:128], SRC2[159:128])\r\nDEST[191:160] <-MAX(SRC1[191:160], SRC2[191:160])\r\nDEST[223:192] <-MAX(SRC1[223:192], SRC2[223:192])\r\nDEST[255:224] <-MAX(SRC1[255:224], SRC2[255:224])\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMAXPS (VEX.128 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMAXPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MAX(DEST[31:0], SRC[31:0])\r\nDEST[63:32] <-MAX(DEST[63:32], SRC[63:32])\r\nDEST[95:64] <-MAX(DEST[95:64], SRC[95:64])\r\nDEST[127:96] <-MAX(DEST[127:96], SRC[127:96])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXPS __m512 _mm512_max_ps( __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_mask_max_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_maskz_max_ps( __mmask16 k, __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_max_round_ps( __m512 a, __m512 b, int);\r\nVMAXPS __m512 _mm512_mask_max_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMAXPS __m512 _mm512_maskz_max_round_ps( __mmask16 k, __m512 a, __m512 b, int);\r\nVMAXPS __m256 _mm256_mask_max_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMAXPS __m256 _mm256_maskz_max_ps( __mmask8 k, __m256 a, __m256 b);\r\nVMAXPS __m128 _mm_mask_max_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMAXPS __m128 _mm_maskz_max_ps( __mmask8 k, __m128 a, __m128 b);\r\nVMAXPS __m256 _mm256_max_ps (__m256 a, __m256 b);\r\nMAXPS __m128 _mm_max_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MAXPS"
    }, 
    {
      "description": "MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value\r\n Opcode/                         Op /    64/32       CPUID        Description\r\n Instruction                     En      bit Mode    Feature\r\n                                         Support     Flag\r\n F2 0F 5F /r                     RM      V/V         SSE2         Return the maximum scalar double-precision floating-point\r\n MAXSD xmm1, xmm2/m64                                             value between xmm2/m64 and xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5F /r     RVM     V/V         AVX          Return the maximum scalar double-precision floating-point\r\n VMAXSD xmm1, xmm2,                                               value between xmm3/m64 and xmm2.\r\n xmm3/m64\r\n EVEX.NDS.LIG.F2.0F.W1 5F /r     T1S     V/V         AVX512F      Return the maximum scalar double-precision floating-point\r\n VMAXSD xmm1 {k1}{z}, xmm2,                                       value between xmm3/m64 and xmm2.\r\n xmm3/m64{sae}\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n       Op/En             Operand 1                  Operand 2                   Operand 3                    Operand 4\r\n        RM            ModRM:reg (r, w)            ModRM:r/m (r)                    NA                            NA\r\n       RVM             ModRM:reg (w)                VEX.vvvv                 ModRM:r/m (r)                       NA\r\n        T1S            ModRM:reg (w)                EVEX.vvvv                ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nCompares the low double-precision floating-point values in the first source operand and the second source\r\noperand, and returns the maximum value to the low quadword of the destination operand. The second source\r\noperand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM\r\nregisters. When the second source operand is a memory operand, only 64 bits are accessed.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source\r\noperand be returned, the action of MAXSD can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMAXSD is encoded with VEX.L=0. Encoding VMAXSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n        ELSE DEST <-SRC2;\r\n  FI;\r\n}\r\n\r\nVMAXSD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- MAX(SRC1[63:0], SRC2[63:0])\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMAXSD (VEX.128 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMAXSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MAX(DEST[63:0], SRC[63:0])\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXSD __m128d _mm_max_round_sd( __m128d a, __m128d b, int);\r\nVMAXSD __m128d _mm_mask_max_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMAXSD __m128d _mm_maskz_max_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMAXSD __m128d _mm_max_sd(__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MAXSD"
    }, 
    {
      "description": "MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value\r\n Opcode/                              Op /   64/32        CPUID      Description\r\n Instruction                          En     bit Mode     Feature\r\n                                             Support      Flag\r\n F3 0F 5F /r                          RM     V/V          SSE        Return the maximum scalar single-precision floating-point\r\n MAXSS xmm1, xmm2/m32                                                value between xmm2/m32 and xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5F /r          RVM    V/V          AVX        Return the maximum scalar single-precision floating-point\r\n VMAXSS xmm1, xmm2,                                                  value between xmm3/m32 and xmm2.\r\n xmm3/m32\r\n EVEX.NDS.LIG.F3.0F.W0 5F /r          T1S    V/V          AVX512F    Return the maximum scalar single-precision floating-point\r\n VMAXSS xmm1 {k1}{z}, xmm2,                                          value between xmm3/m32 and xmm2.\r\n xmm3/m32{sae}\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n      Op/En               Operand 1                     Operand 2                 Operand 3                     Operand 4\r\n        RM             ModRM:reg (r, w)            ModRM:r/m (r)                      NA                            NA\r\n       RVM              ModRM:reg (w)                   VEX.vvvv                ModRM:r/m (r)                       NA\r\n       T1S             ModRM:reg (w)                    EVEX.vvvv               ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nCompares the low single-precision floating-point values in the first source operand and the second source operand,\r\nand returns the maximum value to the low doubleword of the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN from either source\r\noperand be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 32-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-\r\nsponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. Bits\r\n(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL:128) of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMAXSS is encoded with VEX.L=0. Encoding VMAXSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n        ELSE DEST <-SRC2;\r\n  FI;\r\n}\r\n\r\nVMAXSS (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- MAX(SRC1[31:0], SRC2[31:0])\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMAXSS (VEX.128 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMAXSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MAX(DEST[31:0], SRC[31:0])\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXSS __m128 _mm_max_round_ss( __m128 a, __m128 b, int);\r\nVMAXSS __m128 _mm_mask_max_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMAXSS __m128 _mm_maskz_max_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMAXSS __m128 _mm_max_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MAXSS"
    }, 
    {
      "description": "MFENCE-Memory Fence\r\n Opcode                    Instruction                   Op/    64-Bit       Compat/ Description\r\n                                                         En     Mode         Leg Mode\r\n 0F AE F0                  MFENCE                        NP     Valid        Valid       Serializes load and store operations.\r\n\r\n\r\n\r\n                                                   Instruction Operand Encoding\r\n    Op/En               Operand 1                      Operand 2                      Operand 3                      Operand 4\r\n      NP                    NA                             NA                             NA                            NA\r\n\r\n\r\nDescription\r\nPerforms a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior\r\nthe MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes\r\nthe MFENCE instruction in program order becomes globally visible before any load or store instruction that follows\r\nthe MFENCE instruction.1 The MFENCE instruction is ordered with respect to all load and store instructions, other\r\nMFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID\r\ninstruction). MFENCE does not serialize the instruction stream.\r\nWeakly ordered memory types can be used to achieve higher processor performance through such techniques as\r\nout-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of\r\ndata recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the\r\nproducer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store\r\nordering between routines that produce weakly-ordered results and routines that consume that data.\r\nProcessors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and\r\nWT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it\r\nis not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches specula-\r\ntively just before, during, or after the execution of an MFENCE instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nSpecification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor\r\nignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded by any opcode of the form 0F AE Fx, where x\r\nis in the range 0-7.\r\n\r\nOperation\r\n\r\nWait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_mfence(void)\r\n\r\nExceptions (All Modes of Operation)\r\n#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                        If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n1. A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.\r\n\r\n\r\n", 
      "mnem": "MFENCE"
    }, 
    {
      "description": "MINPD-Minimum of Packed Double-Precision Floating-Point Values\r\n Opcode/                               Op /    64/32         CPUID         Description\r\n Instruction                           En      bit Mode      Feature\r\n                                               Support       Flag\r\n 66 0F 5D /r                           RM      V/V           SSE2          Return the minimum double-precision floating-point values\r\n MINPD xmm1, xmm2/m128                                                     between xmm1 and xmm2/mem\r\n VEX.NDS.128.66.0F.WIG 5D /r           RVM     V/V           AVX           Return the minimum double-precision floating-point values\r\n VMINPD xmm1, xmm2,                                                        between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 5D /r           RVM     V/V           AVX           Return the minimum packed double-precision floating-point\r\n VMINPD ymm1, ymm2,                                                        values between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 5D /r           FV      V/V           AVX512VL      Return the minimum packed double-precision floating-point\r\n VMINPD xmm1 {k1}{z}, xmm2,                                  AVX512F       values between xmm2 and xmm3/m128/m64bcst and store\r\n xmm3/m128/m64bcst                                                         result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5D /r           FV      V/V           AVX512VL      Return the minimum packed double-precision floating-point\r\n VMINPD ymm1 {k1}{z}, ymm2,                                  AVX512F       values between ymm2 and ymm3/m256/m64bcst and store\r\n ymm3/m256/m64bcst                                                         result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5D /r           FV      V/V           AVX512F       Return the minimum packed double-precision floating-point\r\n VMINPD zmm1 {k1}{z}, zmm2,                                                values between zmm2 and zmm3/m512/m64bcst and store\r\n zmm3/m512/m64bcst{sae}                                                    result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n        Op/En                  Operand 1                     Operand 2                   Operand 3                 Operand 4\r\n          RM                ModRM:reg (r, w)               ModRM:r/m (r)                    NA                         NA\r\n         RVM                 ModRM:reg (w)                   VEX.vvvv                 ModRM:r/m (r)                    NA\r\n          FV                 ModRM:reg (w)                  EVEX.vvvv                 ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed double-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the minimum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MINPD can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n         ELSE DEST <-SRC2;\r\n   FI;\r\n}\r\n\r\nVMINPD (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[63:0])\r\n                    ELSE\r\n                         DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[i+63:i])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMINPD (VEX.256 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[191:128] <-MIN(SRC1[191:128], SRC2[191:128])\r\nDEST[255:192] <-MIN(SRC1[255:192], SRC2[255:192])\r\n\r\nVMINPD (VEX.128 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINPD __m512d _mm512_min_pd( __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_mask_min_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_maskz_min_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_min_round_pd( __m512d a, __m512d b, int);\r\nVMINPD __m512d _mm512_mask_min_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMINPD __m512d _mm512_maskz_min_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMINPD __m256d _mm256_mask_min_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVMINPD __m256d _mm256_maskz_min_pd( __mmask8 k, __m256d a, __m256d b);\r\nVMINPD __m128d _mm_mask_min_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMINPD __m128d _mm_maskz_min_pd( __mmask8 k, __m128d a, __m128d b);\r\nVMINPD __m256d _mm256_min_pd (__m256d a, __m256d b);\r\nMINPD __m128d _mm_min_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MINPD"
    }, 
    {
      "description": "MINPS-Minimum of Packed Single-Precision Floating-Point Values\r\n Opcode/                         Op /    64/32        CPUID         Description\r\n Instruction                     En      bit Mode     Feature\r\n                                         Support      Flag\r\n 0F 5D /r                        RM      V/V          SSE           Return the minimum single-precision floating-point values\r\n MINPS xmm1, xmm2/m128                                              between xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5D /r        RVM     V/V          AVX           Return the minimum single-precision floating-point values\r\n VMINPS xmm1, xmm2,                                                 between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 5D /r        RVM     V/V          AVX           Return the minimum single double-precision floating-point\r\n VMINPS ymm1, ymm2,                                                 values between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 5D /r        FV      V/V          AVX512VL      Return the minimum packed single-precision floating-point\r\n VMINPS xmm1 {k1}{z}, xmm2,                           AVX512F       values between xmm2 and xmm3/m128/m32bcst and store\r\n xmm3/m128/m32bcst                                                  result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5D /r        FV      V/V          AVX512VL      Return the minimum packed single-precision floating-point\r\n VMINPS ymm1 {k1}{z}, ymm2,                           AVX512F       values between ymm2 and ymm3/m256/m32bcst and store\r\n ymm3/m256/m32bcst                                                  result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5D /r        FV      V/V          AVX512F       Return the minimum packed single-precision floating-point\r\n VMINPS zmm1 {k1}{z}, zmm2,                                         values between zmm2 and zmm3/m512/m32bcst and store\r\n zmm3/m512/m32bcst{sae}                                             result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n      Op/En              Operand 1                   Operand 2                     Operand 3                    Operand 4\r\n        RM            ModRM:reg (r, w)              ModRM:r/m (r)                      NA                           NA\r\n       RVM             ModRM:reg (w)                  VEX.vvvv                    ModRM:r/m (r)                     NA\r\n        FV             ModRM:reg (w)                 EVEX.vvvv                    ModRM:r/m (r)                     NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed single-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the minimum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MINPS can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n         ELSE DEST <-SRC2;\r\n   FI;\r\n}\r\n\r\nVMINPS (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[31:0])\r\n                    ELSE\r\n                         DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[i+31:i])\r\n               FI;\r\n               ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMINPS (VEX.256 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[159:128] <-MIN(SRC1[159:128], SRC2[159:128])\r\nDEST[191:160] <-MIN(SRC1[191:160], SRC2[191:160])\r\nDEST[223:192] <-MIN(SRC1[223:192], SRC2[223:192])\r\nDEST[255:224] <-MIN(SRC1[255:224], SRC2[255:224])\r\n\r\nVMINPS (VEX.128 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMINPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINPS __m512 _mm512_min_ps( __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_mask_min_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_maskz_min_ps( __mmask16 k, __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_min_round_ps( __m512 a, __m512 b, int);\r\nVMINPS __m512 _mm512_mask_min_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMINPS __m512 _mm512_maskz_min_round_ps( __mmask16 k, __m512 a, __m512 b, int);\r\nVMINPS __m256 _mm256_mask_min_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMINPS __m256 _mm256_maskz_min_ps( __mmask8 k, __m256 a, __m25 b);\r\nVMINPS __m128 _mm_mask_min_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMINPS __m128 _mm_maskz_min_ps( __mmask8 k, __m128 a, __m128 b);\r\nVMINPS __m256 _mm256_min_ps (__m256 a, __m256 b);\r\nMINPS __m128 _mm_min_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MINPS"
    }, 
    {
      "description": "MINSD-Return Minimum Scalar Double-Precision Floating-Point Value\r\n Opcode/                                    Op /   64/32            CPUID     Description\r\n Instruction                                En     bit Mode         Feature\r\n                                                   Support          Flag\r\n F2 0F 5D /r                                RM     V/V              SSE2      Return the minimum scalar double-precision floating-\r\n MINSD xmm1, xmm2/m64                                                         point value between xmm2/m64 and xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5D /r                RVM    V/V              AVX       Return the minimum scalar double-precision floating-\r\n VMINSD xmm1, xmm2, xmm3/m64                                                  point value between xmm3/m64 and xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 5D /r                T1S    V/V              AVX512F   Return the minimum scalar double-precision floating-\r\n VMINSD xmm1 {k1}{z}, xmm2,                                                   point value between xmm3/m64 and xmm2.\r\n xmm3/m64{sae}\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n        Op/En                   Operand 1                     Operand 2                 Operand 3                   Operand 4\r\n         RM                 ModRM:reg (r, w)                ModRM:r/m (r)                   NA                         NA\r\n         RVM                 ModRM:reg (w)                    VEX.vvvv                ModRM:r/m (r)                    NA\r\n         T1S                 ModRM:reg (w)                    EVEX.vvvv               ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nCompares the low double-precision floating-point values in the first source operand and the second source\r\noperand, and returns the minimum value to the low quadword of the destination operand. When the source\r\noperand is a memory operand, only the 64 bits are accessed.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, then SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand\r\n(from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of\r\ninstructions, such as, a comparison followed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMINSD is encoded with VEX.L=0. Encoding VMINSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n         ELSE DEST <-SRC2;\r\n   FI;\r\n}\r\n\r\nMINSD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- MIN(SRC1[63:0], SRC2[63:0])\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMINSD (VEX.128 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);\r\nVMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMINSD __m128d _mm_min_sd(__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MINSD"
    }, 
    {
      "description": "MINSS-Return Minimum Scalar Single-Precision Floating-Point Value\r\n Opcode/                                    Op /     64/32          CPUID     Description\r\n Instruction                                En       bit Mode       Feature\r\n                                                     Support        Flag\r\n F3 0F 5D /r                                RM       V/V            SSE       Return the minimum scalar single-precision floating-\r\n MINSS xmm1,xmm2/m32                                                          point value between xmm2/m32 and xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5D /r                RVM      V/V            AVX       Return the minimum scalar single-precision floating-\r\n VMINSS xmm1,xmm2, xmm3/m32                                                   point value between xmm3/m32 and xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 5D /r                T1S      V/V            AVX512F   Return the minimum scalar single-precision floating-\r\n VMINSS xmm1 {k1}{z}, xmm2,                                                   point value between xmm3/m32 and xmm2.\r\n xmm3/m32{sae}\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n         Op/En                   Operand 1                      Operand 2               Operand 3                   Operand 4\r\n           RM                 ModRM:reg (r, w)               ModRM:r/m (r)                  NA                          NA\r\n          RVM                  ModRM:reg (w)                    VEX.vvvv               ModRM:r/m (r)                    NA\r\n          T1S                  ModRM:reg (w)                    EVEX.vvvv              ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nCompares the low single-precision floating-point values in the first source operand and the second source operand\r\nand returns the minimum value to the low doubleword of the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN\r\nversion of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN in either source\r\noperand be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 32-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-\r\nsponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by (E)VEX.vvvv. Bits\r\n(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMINSS is encoded with VEX.L=0. Encoding VMINSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n         ELSE DEST <-SRC2;\r\n   FI;\r\n}\r\n\r\nMINSS (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- MIN(SRC1[31:0], SRC2[31:0])\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMINSS (VEX.128 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINSS __m128 _mm_min_round_ss( __m128 a, __m128 b, int);\r\nVMINSS __m128 _mm_mask_min_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMINSS __m128 _mm_maskz_min_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMINSS __m128 _mm_min_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MINSS"
    }, 
    {
      "description": "MONITOR-Set Up Monitor Address\r\nOpcode                   Instruction                  Op/   64-Bit      Compat/ Description\r\n                                                      En    Mode        Leg Mode\r\n0F 01 C8                 MONITOR                      NP    Valid       Valid       Sets up a linear address range to be\r\n                                                                                    monitored by hardware and activates the\r\n                                                                                    monitor. The address range should be a write-\r\n                                                                                    back memory caching type. The address is\r\n                                                                                    DS:EAX (DS:RAX in 64-bit mode).\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n   Op/En              Operand 1                    Operand 2                    Operand 3                    Operand 4\r\n    NP                   NA                           NA                            NA                           NA\r\n\r\n\r\nDescription\r\nThe MONITOR instruction arms address monitoring hardware using an address specified in EAX (the address range\r\nthat the monitoring hardware checks for store operations can be determined by using CPUID). A store to an\r\naddress within the specified address range triggers the monitoring hardware. The state of monitor hardware is\r\nused by MWAIT.\r\nThe content of EAX is an effective address (in 64-bit mode, RAX is used). By default, the DS segment is used to\r\ncreate a linear address that is monitored. Segment overrides can be used.\r\nECX and EDX are also used. They communicate other information to MONITOR. ECX specifies optional extensions.\r\nEDX specifies optional hints; it does not change the architectural behavior of the instruction. For the Pentium 4\r\nprocessor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the\r\nprocessor; undefined extensions in ECX raises a general protection fault.\r\nThe address range must use memory of the write-back type. Only write-back memory will correctly trigger the\r\nmonitoring hardware. Additional information on determining what address range to use in order to prevent false\r\nwake-ups is described in Chapter 8, \"Multiple-Processor Management\" of the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3A.\r\nThe MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction\r\nis subject to the permission checking and faults associated with a byte load. Like a load, MONITOR sets the A-bit\r\nbut not the D-bit in page tables.\r\nCPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,\r\nMONITOR may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode\r\nexception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE\r\nMSR; disabling MONITOR clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-\r\ntion.\r\nThe instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nMONITOR sets up an address range for the monitor hardware using the content of EAX (RAX in 64-bit mode) as an\r\neffective address and puts the monitor hardware in armed state. Always use memory of the write-back caching\r\ntype. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are\r\nused to communicate other information to the monitor hardware.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMONITOR:      void _mm_monitor(void const *p, unsigned extensions,unsigned hints)\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the value in EAX is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n                    selector.\r\n                    If ECX != 0.\r\n#SS(0)              If the value in EAX is outside the SS segment limit.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n                    If current privilege level is not 0.\r\n\r\nReal Address Mode Exceptions\r\n#GP                 If the CS, DS, ES, FS, or GS register is used to access memory and the value in EAX is outside\r\n                    of the effective address space from 0 to FFFFH.\r\n                    If ECX != 0.\r\n#SS                 If the SS register is used to access memory and the value in EAX is outside of the effective\r\n                    address space from 0 to FFFFH.\r\n#UD                 If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#UD                 The MONITOR instruction is not recognized in virtual-8086 mode (even if\r\n                    CPUID.01H:ECX.MONITOR[bit 3] = 1).\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical\r\n                    form.\r\n                    If RCX != 0.\r\n#SS(0)              If the SS register is used to access memory and the value in EAX is in a non-canonical form.\r\n#PF(fault-code)     For a page fault.\r\n#UD                 If the current privilege level is not 0.\r\n                    If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MONITOR"
    }, 
    {
      "description": "MOV-Move\r\n Opcode              Instruction           Op/   64-Bit   Compat/ Description\r\n                                           En    Mode     Leg Mode\r\n 88 /r          … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOV"
    }, 
    {
      "description": "MOV-Move to/from Control Registers\r\nOpcode/                                                 Op/    64-Bit       Compat/ Description\r\nInstruction                                             En     Mode         Leg Mode\r\n0F 20/r                                                 MR     N.E.         Valid        Move control register to r32.\r\nMOV r32, CR0-CR7\r\n0F 20/r                                                 MR     Valid        N.E.         Move extended control register to r64.\r\nMOV r64, CR0-CR7\r\nREX.R + 0F 20 /0                                        MR     Valid        N.E.         Move extended CR8 to r64.1\r\nMOV r64, CR8\r\n0F 22 /r                                                RM     N.E.         Valid        Move r32 to control register.\r\nMOV CR0-CR7, r32\r\n0F 22 /r                                                RM     Valid        N.E.         Move r64 to extended control register.\r\nMOV CR0-CR7, r64\r\nREX.R + 0F 22 /0                                        RM     Valid        N.E.         Move r64 to extended CR8.1\r\nMOV CR8, r64\r\nNOTE:\r\n1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not\r\n   architecturally defined as a serializing instruction. For more information, see Chapter 8 in Intel 64 and IA-32 Architectures Soft-\r\n   ware Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En             Operand 1                      Operand 2                       Operand 3                      Operand 4\r\n    MR             ModRM:r/m (w)                   ModRM:reg (r)                       NA                                NA\r\n    RM             ModRM:reg (w)                   ModRM:r/m (r)                       NA                                NA\r\n\r\n\r\nDescription\r\nMoves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose register or the\r\ncontents of a general purpose register to a control register. The operand size for these instructions is always 32 bits\r\nin non-64-bit modes, regardless of the operand-size attribute. (See \"Control Registers\" in Chapter 2 of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a detailed description of the flags and\r\nfields in the control registers.) This instruction can be executed only when the current privilege level is 0.\r\nAt the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read.\r\nThe 2 bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.\r\nAttempts to reference CR1, CR5, CR6, CR7, and CR9-CR15 result in undefined opcode (#UD) exceptions.\r\nWhen loading control registers, programs should not attempt to change the reserved bits; that is, always set\r\nreserved bits to the value previously read. An attempt to change CR4's reserved bits will cause a general protection\r\nfault. Reserved bits in CR0 and CR3 remain clear after any load of those registers; attempts to set them have no\r\nimpact. On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set after any load of CR0; attempts to\r\nclear this bit have no impact.\r\nIn certain cases, these instructions have the side effect of invalidating entries in the TLBs and the paging-structure\r\ncaches. See Section 4.10.4.1, \"Operations that Invalidate TLBs and Paging-Structure Caches,\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A for details.\r\nThe following side effects are implementation-specific for the Pentium 4, Intel Xeon, and P6 processor family: when\r\nmodifying PE or PG in register CR0, or PSE or PAE in register CR4, all TLB entries are flushed, including global\r\nentries. Software should not depend on this functionality in all Intel 64 or IA-32 processors.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits. The REX.R prefix must be used to access CR8. Use\r\nof REX.B permits access to additional registers (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of\r\n\r\n\r\n\r\n\r\nthe REX.R prefix to specify a register other than CR8 causes an invalid-opcode exception. See the summary chart\r\nat the beginning of this section for encoding data and limits.\r\nIf CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates\r\nentries in the TLBs and the paging-structure caches (see Section 4.10.4.1, \"Operations that Invalidate TLBs and\r\nPaging-Structure Caches,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A). The\r\ninstruction does not modify bit 63 of CR3, which is reserved and always 0.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the current privilege level is not 0.\r\n                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n                        when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n                        If an attempt is made to write a 1 to any reserved bit in CR4.\r\n                        If an attempt is made to write 1 to CR4.PCIDE.\r\n                        If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading\r\n                        of a control register causes the PDPT to be loaded into the processor.\r\n#UD                     If the LOCK prefix is used.\r\n                        If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If an attempt is made to write a 1 to any reserved bit in CR4.\r\n                        If an attempt is made to write 1 to CR4.PCIDE.\r\n                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n                        when the PE flag is set to 0).\r\n#UD                     If the LOCK prefix is used.\r\n                        If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                  These instructions cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#GP(0)                  If the current privilege level is not 0.\r\n                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n                        when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n                        If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.\r\n                        If an attempt is made to clear CR0.PG[bit 31] while CR4.PCIDE = 1.\r\n                        If an attempt is made to write a 1 to any reserved bit in CR3.\r\n                        If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].\r\n#UD                     If the LOCK prefix is used.\r\n                        If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n                    when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n                    If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.\r\n                    If an attempt is made to clear CR0.PG[bit 31].\r\n                    If an attempt is made to write a 1 to any reserved bit in CR4.\r\n                    If an attempt is made to write a 1 to any reserved bit in CR8.\r\n                    If an attempt is made to write a 1 to any reserved bit in CR3.\r\n                    If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].\r\n#UD                 If the LOCK prefix is used.\r\n                    If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n                    If the REX.R prefix is used to specify a register other than CR8.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOV"
    }, 
    {
      "description": "MOV-Move to/from Debug Registers\r\nOpcode/                                             Op/   64-Bit   Compat/ Description\r\nInstruction                                         En    Mode     Leg Mode\r\n0F 21/r                                             MR    N.E.     Valid      Move debug register to r32.\r\nMOV r32, DR0-DR7\r\n0F 21/r                                             MR    Valid    N.E.       Move extended debug register to r64.\r\nMOV r64, DR0-DR7\r\n0F 23 /r                                            RM    N.E.     Valid      Move r32 to debug register.\r\nMOV DR0-DR7, r32\r\n0F 23 /r                                            RM    Valid    N.E.       Move r64 to extended debug register.\r\nMOV DR0-DR7, r64\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n      Op/En          Operand 1                   Operand 2                 Operand 3                   Operand 4\r\n       MR          ModRM:r/m (w)                ModRM:reg (r)                 NA                            NA\r\n       RM          ModRM:reg (w)                ModRM:r/m (r)                 NA                            NA\r\n\r\n\r\nDescription\r\nMoves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose\r\nregister or vice versa. The operand size for these instructions is always 32 bits in non-64-bit modes, regardless of\r\nthe operand-size attribute. (See Section 17.2, \"Debug Registers\", of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 3A, for a detailed description of the flags and fields in the debug registers.)\r\nThe instructions must be executed at privilege level 0 or in real-address mode.\r\nWhen the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a\r\nmanner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer\r\nto DR6 and DR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in an\r\nundefined opcode (#UD) exception. (The CR4 register was added to the IA-32 Architecture beginning with the\r\nPentium processor.)\r\nAt the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read.\r\nThe two bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits. Use of the REX.B prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalid-\r\nopcode exception. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF ((DE = 1) and (SRC or DEST = DR4 or DR5))\r\n     THEN\r\n         #UD;\r\n     ELSE\r\n         DEST <- SRC;\r\n\r\nFI;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n                    DR5.\r\n                    If the LOCK prefix is used.\r\n#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n                    DR5.\r\n                    If the LOCK prefix is used.\r\n#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              The debug registers cannot be loaded or read when in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the current privilege level is not 0.\r\n                    If an attempt is made to write a 1 to any of bits 63:32 in DR6.\r\n                    If an attempt is made to write a 1 to any of bits 63:32 in DR7.\r\n#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n                    DR5.\r\n                    If the LOCK prefix is used.\r\n                    If the REX.R prefix is used.\r\n#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOV"
    }, 
    {
      "description": "MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values\r\n Opcode/                                      Op/En       64/32        CPUID      Description\r\n Instruction … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOVAPD"
    }, 
    {
      "description": "MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values\r\n Opcode/                                     Op/En       64/32        CPUID      Description\r\n Instruction  … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOVAPS"
    }, 
    {
      "description": "MOVBE-Move Data After Swapping Bytes\r\n Opcode                   Instruction           Op/   64-Bit     Compat/ Description\r\n                                                En    Mode       Leg Mode\r\n 0F 38 F0 /r              MOVBE r16, m16        RM    Valid      Valid      Reverse byte order in m16 and move to r16.\r\n 0F 38 F0 /r              MOVBE r32, m32        RM    Valid      Valid      Reverse byte order in m32 and move to r32.\r\n REX.W + 0F 38 F0 /r      MOVBE r64, m64        RM    Valid      N.E.       Reverse byte order in m64 and move to r64.\r\n 0F 38 F1 /r              MOVBE m16, r16        MR    Valid      Valid      Reverse byte order in r16 and move to m16.\r\n 0F 38 F1 /r              MOVBE m32, r32        MR    Valid      Valid      Reverse byte order in r32 and move to m32.\r\n REX.W + 0F 38 F1 /r      MOVBE m64, r64        MR    Valid      N.E.       Reverse byte order in r64 and move to m64.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n      Op/En            Operand 1              Operand 2                  Operand 3                   Operand 4\r\n       RM          ModRM:reg (w)            ModRM:r/m (r)                   NA                          NA\r\n       MR          ModRM:r/m (w)            ModRM:reg (r)                   NA                          NA\r\n\r\n\r\nDescription\r\nPerforms a byte swap operation on the data copied from the second operand (source operand) and store the result\r\nin the first operand (destination operand). The source operand can be a general-purpose register, or memory loca-\r\ntion; the destination register can be a general-purpose register, or a memory location; however, both operands can\r\nnot be registers, and only one operand can be a memory location. Both operands must be the same size, which can\r\nbe a word, a doubleword or quadword.\r\nThe MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus\r\nproviding support for converting little-endian values to big-endian format and vice versa.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nTEMP <- SRC\r\n\r\nIF ( OperandSize = 16)\r\n     THEN\r\n         DEST[7:0] <- TEMP[15:8];\r\n         DEST[15:8] <- TEMP[7:0];\r\n     ELES IF ( OperandSize = 32)\r\n         DEST[7:0] <- TEMP[31:24];\r\n         DEST[15:8] <- TEMP[23:16];\r\n         DEST[23:16] <- TEMP[15:8];\r\n         DEST[31:23] <- TEMP[7:0];\r\n     ELSE IF ( OperandSize = 64)\r\n         DEST[7:0] <- TEMP[63:56];\r\n         DEST[15:8] <- TEMP[55:48];\r\n         DEST[23:16] <- TEMP[47:40];\r\n         DEST[31:24] <- TEMP[39:32];\r\n         DEST[39:32] <- TEMP[31:24];\r\n         DEST[47:40] <- TEMP[23:16];\r\n         DEST[55:48] <- TEMP[15:8];\r\n         DEST[63:56] <- TEMP[7:0];\r\n\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)              If the destination operand is in a non-writable segment.\r\n                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                    If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If REP (F3H) prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If REP (F3H) prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If REP (F3H) prefix is used.\r\n                    If REPNE (F2H) prefix is used and CPUID.01H:ECX.SSE4_2[bit 20] = 0.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#SS(0)              If the stack address is in a non-canonical form.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n                    If the LOCK prefix is used.\r\n                    If REP (F3H) prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVBE"
    }, 
    {
      "description": "MOVD/MOVQ-Move Doubleword/Move Quadword\r\nOpcode/                               Op/ En   64/32-bit CPUID     Description\r\nInstruction                                    Mode      Feature\r\n                                                         Flag\r\n0F 6E /r                              RM       V/V       MMX       Move doubleword from r/m32 to mm.\r\nMOVD mm, r/m32\r\nREX.W + 0F 6E /r                      RM       V/N.E.    MMX       Move quadword from r/m64 to mm.\r\nMOVQ mm, r/m64\r\n0F 7E /r                              MR       V/V       MMX       Move doubleword from mm to r/m32.\r\nMOVD r/m32, mm\r\nREX.W + 0F 7E /r                      MR       V/N.E.    MMX       Move quadword from mm to r/m64.\r\nMOVQ r/m64, mm\r\n66 0F 6E /r                           RM       V/V       SSE2      Move doubleword from r/m32 to xmm.\r\nMOVD xmm, r/m32\r\n66 REX.W 0F 6E /r                     RM       V/N.E.    SSE2      Move quadword from r/m64 to xmm.\r\nMOVQ xmm, r/m64\r\n66 0F 7E /r                           MR       V/V       SSE2      Move doubleword from xmm register to r/m32.\r\nMOVD r/m32, xmm\r\n 66 REX.W 0F 7E /r                    MR       V/N.E.    SSE2      Move quadword from xmm register to r/m64.\r\nMOVQ r/m64, xmm\r\nVEX.128.66.0F.W0 6E /                 RM       V/V       AVX       Move doubleword from r/m32 to xmm1.\r\nVMOVD xmm1, r32/m32\r\nVEX.128.66.0F.W1 6E /r                RM       V/N.E1.   AVX       Move quadword from r/m64 to xmm1.\r\nVMOVQ xmm1, r64/m64\r\nVEX.128.66.0F.W0 7E /r                MR       V/V       AVX       Move doubleword from xmm1 register to r/m32.\r\nVMOVD r32/m32, xmm1\r\nVEX.128.66.0F.W1 7E /r                MR       V/N.E1.   AVX       Move quadword from xmm1 register to r/m64.\r\nVMOVQ r64/m64, xmm1\r\nEVEX.128.66.0F.W0 6E /r               T1S-RM V/V         AVX512F   Move doubleword from r/m32 to xmm1.\r\nVMOVD xmm1, r32/m32\r\nEVEX.128.66.0F.W1 6E /r               T1S-RM V/N.E.1     AVX512F   Move quadword from r/m64 to xmm1.\r\nVMOVQ xmm1, r64/m64\r\nEVEX.128.66.0F.W0 7E /r               T1S-MR V/V         AVX512F   Move doubleword from xmm1 register to r/m32.\r\nVMOVD r32/m32, xmm1\r\nEVEX.128.66.0F.W1 7E /r               T1S-MR V/N.E.1     AVX512F   Move quadword from xmm1 register to r/m64.\r\nVMOVQ r64/m64, xmm1\r\n\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n  sion is used.\r\n\r\n\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n     Op/En              Operand 1                  Operand 2                 Operand 3               Operand 4\r\n       RM             ModRM:reg (w)               ModRM:r/m (r)                 NA                      NA\r\n       MR             ModRM:r/m (w)               ModRM:reg (r)                 NA                      NA\r\n    T1S-RM            ModRM:reg (w)               ModRM:r/m (r)                 NA                      NA\r\n    T1S-MR            ModRM:r/m (w)               ModRM:reg (r)                 NA                      NA\r\n\r\n\r\nDescription\r\nCopies a doubleword from the source operand (second operand) to the destination operand (first operand). The\r\nsource and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or\r\n32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an\r\nMMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low\r\ndoubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot\r\nbe used to transfer data between MMX technology registers, between XMM registers, between general-purpose\r\nregisters, or between memory locations.\r\nWhen the destination operand is an MMX technology register, the source operand is written to the low doubleword\r\nof the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the\r\nsource operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\nMOVD/Q with XMM destination:\r\nMoves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM\r\nregister. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit\r\nmemory location.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding YMM destination register remain\r\nunchanged. Qword operation requires the use of REX.W=1.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires\r\nthe use of VEX.W=1.\r\nEVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires\r\nthe use of EVEX.W=1.\r\n\r\n\r\nMOVD/Q with 32/64 reg/mem destination:\r\nStores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register.\r\nQword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nIf VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will\r\ncause an #UD exception.\r\n\r\nOperation\r\nMOVD (when destination operand is MMX technology register)\r\n  DEST[31:0] <- SRC;\r\n  DEST[63:32] <- 00000000H;\r\n\r\nMOVD (when destination operand is XMM register)\r\n  DEST[31:0] <- SRC;\r\n  DEST[127:32] <- 000000000000000000000000H;\r\n  DEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nMOVD (when source operand is MMX technology or XMM register)\r\n  DEST <- SRC[31:0];\r\n\r\nVMOVD (VEX-encoded version when destination is an XMM register)\r\n  DEST[31:0] <- SRC[31:0]\r\n  DEST[VLMAX-1:32] <- 0\r\n\r\nMOVQ (when destination operand is XMM register)\r\n  DEST[63:0] <- SRC[63:0];\r\n  DEST[127:64] <- 0000000000000000H;\r\n  DEST[VLMAX-1:128] (Unmodified)\r\n\r\nMOVQ (when destination operand is r/m64)\r\n  DEST[63:0] <- SRC[63:0];\r\n\r\nMOVQ (when source operand is XMM register or r/m64)\r\n  DEST <- SRC[63:0];\r\n\r\nVMOVQ (VEX-encoded version when destination is an XMM register)\r\n  DEST[63:0] <- SRC[63:0]\r\n  DEST[VLMAX-1:64] <- 0\r\n\r\nVMOVD (EVEX-encoded version when destination is an XMM register)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[511:32] <- 0H\r\n\r\nVMOVQ (EVEX-encoded version when destination is an XMM register)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[511:64] <- 0H\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVD:         __m64 _mm_cvtsi32_si64 (int i )\r\nMOVD:         int _mm_cvtsi64_si32 ( __m64m )\r\nMOVD:         __m128i _mm_cvtsi32_si128 (int a)\r\nMOVD:         int _mm_cvtsi128_si32 ( __m128i a)\r\nMOVQ:         __int64 _mm_cvtsi128_si64(__m128i);\r\nMOVQ:         __m128i _mm_cvtsi64_si128(__int64);\r\nVMOVD         __m128i _mm_cvtsi32_si128( int);\r\nVMOVD         int _mm_cvtsi128_si32( __m128i );\r\nVMOVQ         __m128i _mm_cvtsi64_si128 (__int64);\r\nVMOVQ         __int64 _mm_cvtsi128_si64(__m128i );\r\nVMOVQ         __m128i _mm_loadl_epi64( __m128i * s);\r\nVMOVQ         void _mm_storel_epi64( __m128i * d, __m128i s);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n#UD                 If VEX.L = 1.\r\n                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVD"
    }, 
    {
      "description": "MOVDDUP-Replicate Double FP Values\r\n Opcode/                                Op / En    64/32        CPUID      Description\r\n Instruction                                       bit Mode     Feature\r\n                                                   Support      Flag\r\n F2 0F 12 /r                            RM         V/V          SSE3       Move double-precision floating-point value from\r\n MOVDDUP xmm1, xmm2/m64                                                    xmm2/m64 and duplicate into xmm1.\r\n VEX.128.F2.0F.WIG 12 /r                RM         V/V          AVX        Move double-precision floating-point value from\r\n VMOVDDUP xmm1, xmm2/m64                                                   xmm2/m64 and duplicate into xmm1.\r\n VEX.256.F2.0F.WIG 12 /r                RM         V/V          AVX        Move even index double-precision floating-point\r\n VMOVDDUP ymm1, ymm2/m256                                                  values from ymm2/mem and duplicate each element\r\n                                                                           into ymm1.\r\n EVEX.128.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512VL   Move double-precision floating-point value from\r\n VMOVDDUP xmm1 {k1}{z},                                         AVX512F    xmm2/m64 and duplicate each element into xmm1\r\n xmm2/m64                                                                  subject to writemask k1.\r\n EVEX.256.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512VL   Move even index double-precision floating-point\r\n VMOVDDUP ymm1 {k1}{z},                                         AVX512F    values from ymm2/m256 and duplicate each element\r\n ymm2/m256                                                                 into ymm1 subject to writemask k1.\r\n EVEX.512.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512F    Move even index double-precision floating-point\r\n VMOVDDUP zmm1 {k1}{z},                                                    values from zmm2/m512 and duplicate each element\r\n zmm2/m512                                                                 into zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n      Op/En                 Operand 1                     Operand 2              Operand 3                 Operand 4\r\n        RM                ModRM:reg (w)                  ModRM:r/m (r)              NA                        NA\r\n     DUP-RM               ModRM:reg (w)                  ModRM:r/m (r)              NA                        NA\r\n\r\nDescription\r\nFor 256-bit or higher versions: Duplicates even-indexed double-precision floating-point values from the source\r\noperand (the second operand) and into adjacent pair and store to the destination operand (the first operand).\r\nFor 128-bit versions: Duplicates the low double-precision floating-point value from the source operand (the second\r\noperand) and store to the destination operand (the first operand).\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register are unchanged. The\r\nsource operand is XMM register or a 64-bit memory location.\r\nVEX.128 and EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. The source\r\noperand is XMM register or a 64-bit memory location. The destination is updated conditionally under the writemask\r\nfor EVEX version.\r\nVEX.256 and EVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed. The source\r\noperand is YMM register or a 256-bit memory location. The destination is updated conditionally under the\r\nwritemask for EVEX version.\r\nEVEX.512 encoded version: The destination is updated according to the writemask. The source operand is ZMM\r\nregister or a 512-bit memory location.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n                         SRC           X3                  X2          X1      X0\r\n\r\n\r\n\r\n\r\n                         DEST          X2                 X2           X0      X0\r\n\r\n\r\n                                              Figure 4-2. VMOVDDUP Operation\r\n\r\n\r\nOperation\r\nVMOVDDUP (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nTMP_SRC[63:0] <- SRC[63:0]\r\nTMP_SRC[127:64] <- SRC[63:0]\r\nIF VL >= 256\r\n    TMP_SRC[191:128] <- SRC[191:128]\r\n    TMP_SRC[255:192] <- SRC[191:128]\r\nFI;\r\nIF VL >= 512\r\n    TMP_SRC[319:256] <- SRC[319:256]\r\n    TMP_SRC[383:320] <- SRC[319:256]\r\n    TMP_SRC[477:384] <- SRC[477:384]\r\n    TMP_SRC[511:484] <- SRC[477:384]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <- TMP_SRC[i+63:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDDUP (VEX.256 encoded version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[191:128] <-SRC[191:128]\r\nDEST[255:192] <-SRC[191:128]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMOVDDUP (VEX.128 encoded version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\nMOVDDUP (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVDDUP __m512d _mm512_movedup_pd( __m512d a);\r\nVMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);\r\nVMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);\r\nVMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);\r\nVMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);\r\nVMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);\r\nVMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);\r\nMOVDDUP __m256d _mm256_movedup_pd (__m256d a);\r\nMOVDDUP __m128d _mm_movedup_pd (__m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E5NF.\r\n#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVDDUP"
    }, 
    {
      "description": "MOVDQ2Q-Move Quadword from XMM to MMX Technology Register\r\n Opcode                   Instruction                 Op/    64-Bit   Compat/ Description\r\n                                                      En     Mode     Leg Mode\r\n F2 0F D6 /r              MOVDQ2Q mm, xmm             RM     Valid    Valid       Move low quadword from xmm to mmx\r\n                                                                                  register.\r\n\r\n\r\n\r\n                                                Instruction Operand Encoding\r\n  Op/En              Operand 1                   Operand 2                    Operand 3                Operand 4\r\n    RM              ModRM:reg (w)               ModRM:r/m (r)                    NA                       NA\r\n\r\n\r\nDescription\r\nMoves the low quadword from the source operand (second operand) to the destination operand (first operand).\r\nThe source operand is an XMM register and the destination operand is an MMX technology register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST <- SRC[63:0];\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVDQ2Q:             __m64 _mm_movepi64_pi64 ( __m128i a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM                     If CR0.TS[bit 3] = 1.\r\n#UD                     If CR0.EM[bit 2] = 1.\r\n                        If CR4.OSFXSR[bit 9] = 0.\r\n                        If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                        If the LOCK prefix is used.\r\n#MF                     If there is a pending x87 FPU exception.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n", 
      "mnem": "MOVDQ2Q"
    }, 
    {
      "description": "MOVDQA/VMOVDQA/VMOVDQA32/VMOVDQA64-Move Aligned Packed Integer Values\r\n Opcode/                         Op/En    64/32      CPUID         Description\r\n Instruction            … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOVDQA"
    }, 
    {
      "description": "MOVDQU/VMOVDQU/VMOVDQU8/VMOVDQU16/VMOVDQU32/VMOVDQU64-Move Unaligned Packed Integer Values\r\n Opcode/                                    Op/En       64/32      CPUID      Descri … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOVDQU"
    }, 
    {
      "description": "MOVHLPS-Move Packed Single-Precision Floating-Point Values High to Low\r\n Opcode/                             Op /   64/32       CPUID             Description\r\n Instruction                         En     bit Mode    Feature\r\n                                            Support     Flag\r\n 0F 12 /r                            RM     V/V         SSE               Move two packed single-precision floating-point values\r\n MOVHLPS xmm1, xmm2                                                       from high quadword of xmm2 to low quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 12 /r            RVM    V/V         AVX               Merge two packed single-precision floating-point values\r\n VMOVHLPS xmm1, xmm2, xmm3                                                from high quadword of xmm3 and low quadword of xmm2.\r\n EVEX.NDS.128.0F.W0 12 /r            RVM    V/V         AVX512F           Merge two packed single-precision floating-point values\r\n VMOVHLPS xmm1, xmm2, xmm3                                                from high quadword of xmm3 and low quadword of xmm2.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding1\r\n       Op/En                Operand 1                  Operand 2                        Operand 3                   Operand 4\r\n        RM                ModRM:reg (w)            ModRM:r/m (r)                           NA                           NA\r\n       RVM                ModRM:reg (w)                 vvvv (r)                     ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nThis instruction cannot be used for memory to register moves.\r\n128-bit two-argument form:\r\nMoves two packed single-precision floating-point values from the high quadword of the second XMM argument\r\n(second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of\r\nthe destination operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register remain\r\nunchanged.\r\n128-bit and EVEX three-argument form\r\nMoves two packed single-precision floating-point values from the high quadword of the third XMM argument (third\r\noperand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM\r\nargument (second operand) to the high quadword of the destination (first operand). Bits (MAX_VL-1:128) of the\r\ncorresponding destination register are zeroed.\r\nIf VMOVHLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVHLPS (128-bit two-argument form)\r\nDEST[63:0] <- SRC[127:64]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVHLPS (128-bit three-argument form - VEX & EVEX)\r\nDEST[63:0] <- SRC2[127:64]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7; additionally\r\n#UD                      If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E7NM.128.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVHLPS"
    }, 
    {
      "description": "MOVHPD-Move High Packed Double-Precision Floating-Point Value\r\n Opcode/                            Op / En    64/32       CPUID        Description\r\n Instruction                                   bit Mode    Feature\r\n                                               Support     Flag\r\n 66 0F 16 /r                        RM         V/V         SSE2         Move double-precision floating-point value from m64\r\n MOVHPD xmm1, m64                                                       to high quadword of xmm1.\r\n VEX.NDS.128.66.0F.WIG 16 /r        RVM        V/V         AVX          Merge double-precision floating-point value from m64\r\n VMOVHPD xmm2, xmm1, m64                                                and the low quadword of xmm1.\r\n EVEX.NDS.128.66.0F.W1 16 /r        T1S        V/V         AVX512F      Merge double-precision floating-point value from m64\r\n VMOVHPD xmm2, xmm1, m64                                                and the low quadword of xmm1.\r\n 66 0F 17 /r                        MR         V/V         SSE2         Move double-precision floating-point value from high\r\n MOVHPD m64, xmm1                                                       quadword of xmm1 to m64.\r\n VEX.128.66.0F.WIG 17 /r            MR         V/V         AVX          Move double-precision floating-point value from high\r\n VMOVHPD m64, xmm1                                                      quadword of xmm1 to m64.\r\n EVEX.128.66.0F.W1 17 /r            T1S-MR     V/V         AVX512F      Move double-precision floating-point value from high\r\n VMOVHPD m64, xmm1                                                      quadword of xmm1 to m64.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n        Op/En              Operand 1                  Operand 2                   Operand 3                   Operand 4\r\n         RM             ModRM:reg (r, w)             ModRM:r/m (r)                    NA                          NA\r\n        RVM              ModRM:reg (w)                 VEX.vvvv                 ModRM:r/m (r)                     NA\r\n         MR              ModRM:r/m (w)               ModRM:reg (r)                    NA                          NA\r\n         T1S             ModRM:reg (w)                EVEX.vvvv                 ModRM:r/m (r)                     NA\r\n       T1S-MR            ModRM:r/m (w)               ModRM:reg (r)                    NA                          NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves a double-precision floating-point value from the source 64-bit memory operand and stores it in the high 64-\r\nbits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of\r\nthe corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads a double-precision floating-point value from the source 64-bit memory operand (the third operand) and\r\nstores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source\r\noperand (second operand) are copied to the low 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\n128-bit store:\r\nStores a double-precision floating-point value from the high 64-bits of the XMM register source (second operand)\r\nto the 64-bit memory location (first operand).\r\nNote: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store.\r\nFor VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVHPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVHPD (128-bit Legacy SSE load)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVHPD (VEX.128 & EVEX encoded load)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVHPD (store)\r\nDEST[63:0] <- SRC[127:64]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)\r\nMOVHPD void _mm_storeh_pd (double *p, __m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                     If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVHPD"
    }, 
    {
      "description": "MOVHPS-Move High Packed Single-Precision Floating-Point Values\r\n Opcode/                         Op / En   64/32      CPUID       Description\r\n Instruction                               bit Mode   Feature\r\n                                           Support    Flag\r\n 0F 16 /r                        RM        V/V        SSE         Move two packed single-precision floating-point values\r\n MOVHPS xmm1, m64                                                 from m64 to high quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 16 /r        RVM       V/V        AVX         Merge two packed single-precision floating-point values\r\n VMOVHPS xmm2, xmm1, m64                                          from m64 and the low quadword of xmm1.\r\n EVEX.NDS.128.0F.W0 16 /r        T2        V/V        AVX512F     Merge two packed single-precision floating-point values\r\n VMOVHPS xmm2, xmm1, m64                                          from m64 and the low quadword of xmm1.\r\n 0F 17 /r                        MR        V/V        SSE         Move two packed single-precision floating-point values\r\n MOVHPS m64, xmm1                                                 from high quadword of xmm1 to m64.\r\n VEX.128.0F.WIG 17 /r            MR        V/V        AVX         Move two packed single-precision floating-point values\r\n VMOVHPS m64, xmm1                                                from high quadword of xmm1 to m64.\r\n EVEX.128.0F.W0 17 /r            T2-MR     V/V        AVX512F     Move two packed single-precision floating-point values\r\n VMOVHPS m64, xmm1                                                from high quadword of xmm1 to m64.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n       Op/En             Operand 1                Operand 2                  Operand 3                    Operand 4\r\n        RM            ModRM:reg (r, w)           ModRM:r/m (r)                  NA                            NA\r\n        RVM            ModRM:reg (w)               VEX.vvvv                ModRM:r/m (r)                      NA\r\n        MR             ModRM:r/m (w)             ModRM:reg (r)                  NA                            NA\r\n         T2            ModRM:reg (w)              EVEX.vvvv                ModRM:r/m (r)                      NA\r\n       T2-MR           ModRM:r/m (w)             ModRM:reg (r)                  NA                            NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves two packed single-precision floating-point values from the source 64-bit memory operand and stores them\r\nin the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits\r\n(MAX_VL-1:128) of the corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads two single-precision floating-point values from the source 64-bit memory operand (the third operand) and\r\nstores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source\r\noperand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\n128-bit store:\r\nStores two packed single-precision floating-point values from the high 64-bits of the XMM register source (second\r\noperand) to the 64-bit memory location (first operand).\r\nNote: VMOVHPS (store) (VEX.NDS.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store.\r\nFor VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVHPS (128-bit Legacy SSE load)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVHPS (VEX.128 and EVEX encoded load)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVHPS (store)\r\nDEST[63:0] <- SRC[127:64]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)\r\nMOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                      If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVHPS"
    }, 
    {
      "description": "MOVLHPS-Move Packed Single-Precision Floating-Point Values Low to High\r\n Opcode/                             Op /   64/32        CPUID         Description\r\n Instruction                         En     bit Mode     Feature\r\n                                            Support      Flag\r\n 0F 16 /r                            RM     V/V          SSE           Move two packed single-precision floating-point values from\r\n MOVLHPS xmm1, xmm2                                                    low quadword of xmm2 to high quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 16 /r            RVM    V/V          AVX           Merge two packed single-precision floating-point values\r\n VMOVLHPS xmm1, xmm2, xmm3                                             from low quadword of xmm3 and low quadword of xmm2.\r\n EVEX.NDS.128.0F.W0 16 /r            RVM    V/V          AVX512F       Merge two packed single-precision floating-point values\r\n VMOVLHPS xmm1, xmm2, xmm3                                             from low quadword of xmm3 and low quadword of xmm2.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding1\r\n        Op/En                Operand 1                  Operand 2                    Operand 3                   Operand 4\r\n         RM                ModRM:reg (w)               ModRM:r/m (r)                    NA                           NA\r\n        RVM                ModRM:reg (w)                 vvvv (r)                 ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nThis instruction cannot be used for memory to register moves.\r\n128-bit two-argument form:\r\nMoves two packed single-precision floating-point values from the low quadword of the second XMM argument\r\n(second operand) to the high quadword of the first XMM register (first argument). The low quadword of the desti-\r\nnation operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register are unmodified.\r\n128-bit three-argument forms:\r\nMoves two packed single-precision floating-point values from the low quadword of the third XMM argument (third\r\noperand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM\r\nargument (second operand) to the low quadword of the destination (first operand). Bits (MAX_VL-1:128) of the\r\ncorresponding destination register are zeroed.\r\nIf VMOVLHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVLHPS (128-bit two-argument form)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVLHPS (128-bit three-argument form - VEX & EVEX)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7; additionally\r\n#UD                      If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E7NM.128.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVLHPS"
    }, 
    {
      "description": "MOVLPD-Move Low Packed Double-Precision Floating-Point Value\r\n Opcode/                         Op / En   64/32        CPUID     Description\r\n Instruction                               bit Mode     Feature\r\n                                           Support      Flag\r\n 66 0F 12 /r                     RM        V/V          SSE2      Move double-precision floating-point value from m64 to\r\n MOVLPD xmm1, m64                                                 low quadword of xmm1.\r\n VEX.NDS.128.66.0F.WIG 12 /r     RVM       V/V          AVX       Merge double-precision floating-point value from m64\r\n VMOVLPD xmm2, xmm1, m64                                          and the high quadword of xmm1.\r\n EVEX.NDS.128.66.0F.W1 12 /r     T1S       V/V          AVX512F   Merge double-precision floating-point value from m64\r\n VMOVLPD xmm2, xmm1, m64                                          and the high quadword of xmm1.\r\n 66 0F 13/r                      MR        V/V          SSE2      Move double-precision floating-point value from low\r\n MOVLPD m64, xmm1                                                 quadword of xmm1 to m64.\r\n VEX.128.66.0F.WIG 13/r          MR        V/V          AVX       Move double-precision floating-point value from low\r\n VMOVLPD m64, xmm1                                                quadword of xmm1 to m64.\r\n EVEX.128.66.0F.W1 13/r          T1S-MR    V/V          AVX512F   Move double-precision floating-point value from low\r\n VMOVLPD m64, xmm1                                                quadword of xmm1 to m64.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n       Op/En              Operand 1               Operand 2                 Operand 3                    Operand 4\r\n        RM             ModRM:reg (r, w)          ModRM:r/m (r)                  NA                           NA\r\n        RVM             ModRM:r/m (r)                 VEX.vvvv            ModRM:r/m (r)                      NA\r\n        MR             ModRM:r/m (w)             ModRM:reg (r)                  NA                           NA\r\n        T1S            ModRM:reg (w)              EVEX.vvvv               ModRM:r/m (r)                      NA\r\n      T1S-MR           ModRM:r/m (w)             ModRM:reg (r)                  NA                           NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves a double-precision floating-point value from the source 64-bit memory operand and stores it in the low 64-\r\nbits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of\r\nthe corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads a double-precision floating-point value from the source 64-bit memory operand (third operand), merges it\r\nwith the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the\r\ndestination XMM register (first operand). Bits (MAX_VL-1:128) of the corresponding destination register are\r\nzeroed.\r\n128-bit store:\r\nStores a double-precision floating-point value from the low 64-bits of the XMM register source (second operand) to\r\nthe 64-bit memory location (first operand).\r\nNote: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store.\r\nFor VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVLPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVLPD (128-bit Legacy SSE load)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\nVMOVLPD (VEX.128 & EVEX encoded load)\r\n\r\n\r\n\r\nDEST[63:0] <- SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVLPD (store)\r\nDEST[63:0] <- SRC[63:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)\r\nMOVLPD void _mm_storel_pd (double *p, __m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                     If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVLPD"
    }, 
    {
      "description": "MOVLPS-Move Low Packed Single-Precision Floating-Point Values\r\n Opcode/                         Op / En   64/32         CPUID        Description\r\n Instruction                               bit Mode      Feature\r\n                                           Support       Flag\r\n 0F 12 /r                        RM        V/V           SSE          Move two packed single-precision floating-point values\r\n MOVLPS xmm1, m64                                                     from m64 to low quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 12 /r        RVM       V/V           AVX          Merge two packed single-precision floating-point values\r\n VMOVLPS xmm2, xmm1, m64                                              from m64 and the high quadword of xmm1.\r\n EVEX.NDS.128.0F.W0 12 /r        T2        V/V           AVX512F      Merge two packed single-precision floating-point values\r\n VMOVLPS xmm2, xmm1, m64                                              from m64 and the high quadword of xmm1.\r\n 0F 13/r                         MR        V/V           SSE          Move two packed single-precision floating-point values\r\n MOVLPS m64, xmm1                                                     from low quadword of xmm1 to m64.\r\n VEX.128.0F.WIG 13/r             MR        V/V           AVX          Move two packed single-precision floating-point values\r\n VMOVLPS m64, xmm1                                                    from low quadword of xmm1 to m64.\r\n EVEX.128.0F.W0 13/r             T2-MR     V/V           AVX512F      Move two packed single-precision floating-point values\r\n VMOVLPS m64, xmm1                                                    from low quadword of xmm1 to m64.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n        Op/En             Operand 1                    Operand 2                    Operand 3                   Operand 4\r\n         RM            ModRM:reg (r, w)               ModRM:r/m (r)                    NA                          NA\r\n        RVM             ModRM:reg (w)                   VEX.vvvv                 ModRM:r/m (r)                     NA\r\n         MR             ModRM:r/m (w)                 ModRM:reg (r)                    NA                          NA\r\n         T2             ModRM:reg (w)                  EVEX.vvvv                 ModRM:r/m (r)                     NA\r\n       T2-MR            ModRM:r/m (w)                 ModRM:reg (r)                    NA                          NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves two packed single-precision floating-point values from the source 64-bit memory operand and stores them\r\nin the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits\r\n(MAX_VL-1:128) of the corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads two packed single-precision floating-point values from the source 64-bit memory operand (the third\r\noperand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them\r\nin the low 128-bits of the destination register (the first operand). Bits (MAX_VL-1:128) of the corresponding desti-\r\nnation register are zeroed.\r\n128-bit store:\r\nLoads two packed single-precision floating-point values from the low 64-bits of the XMM register source (second\r\noperand) to the 64-bit memory location (first operand).\r\nNote: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For\r\nVMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\n\r\n\r\nIf VMOVLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVLPS (128-bit Legacy SSE load)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVLPS (VEX.128 & EVEX encoded load)\r\nDEST[63:0] <- SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVLPS (store)\r\nDEST[63:0] <- SRC[63:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)\r\nMOVLPS void _mm_storel_pi (__m64 *p, __m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                      If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVLPS"
    }, 
    {
      "description": "MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask\r\nOpcode/                                 Op/    64/32-bit CPUID             Description\r\nInstruction                             En     Mode      Feature\r\n                                                         Flag\r\n66 0F 50 /r                             RM     V/V            SSE2         Extract 2-bit sign mask from xmm and store in reg. The\r\nMOVMSKPD reg, xmm                                                          upper bits of r32 or r64 are filled with zeros.\r\n\r\nVEX.128.66.0F.WIG 50 /r                 RM     V/V            AVX          Extract 2-bit sign mask from xmm2 and store in reg.\r\nVMOVMSKPD reg, xmm2                                                        The upper bits of r32 or r64 are zeroed.\r\n\r\nVEX.256.66.0F.WIG 50 /r                 RM     V/V            AVX          Extract 4-bit sign mask from ymm2 and store in reg.\r\nVMOVMSKPD reg, ymm2                                                        The upper bits of r32 or r64 are zeroed.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding\r\n   Op/En             Operand 1                 Operand 2                        Operand 3                      Operand 4\r\n     RM            ModRM:reg (w)              ModRM:r/m (r)                         NA                             NA\r\n\r\n\r\nDescription\r\nExtracts the sign bits from the packed double-precision floating-point values in the source operand (second\r\noperand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The\r\nsource operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored\r\nin the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.\r\nIn 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R\r\nprefix. The default operand size is 64-bit in 64-bit mode.\r\n128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.\r\nVEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose\r\nregister.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\n(V)MOVMSKPD (128-bit versions)\r\nDEST[0] <- SRC[63]\r\nDEST[1] <- SRC[127]\r\nIF DEST = r32\r\n    THEN DEST[31:2] <- 0;\r\n    ELSE DEST[63:2] <- 0;\r\nFI\r\n\r\nVMOVMSKPD (VEX.256 encoded version)\r\nDEST[0] <- SRC[63]\r\nDEST[1] <- SRC[127]\r\nDEST[2] <- SRC[191]\r\nDEST[3] <- SRC[255]\r\nIF DEST = r32\r\n    THEN DEST[31:4] <- 0;\r\n    ELSE DEST[63:4] <- 0;\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVMSKPD:           int _mm_movemask_pd ( __m128d a)\r\nVMOVMSKPD:          _mm256_movemask_pd(__m256d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 7; additionally\r\n#UD                      If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVMSKPD"
    }, 
    {
      "description": "MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask\r\n Opcode/                                 Op/    64/32-bit CPUID          Description\r\n Instruction                             En     Mode      Feature\r\n                                                          Flag\r\n 0F 50 /r                                RM     V/V        SSE           Extract 4-bit sign mask from xmm and store in reg.\r\n MOVMSKPS reg, xmm                                                       The upper bits of r32 or r64 are filled with zeros.\r\n\r\n VEX.128.0F.WIG 50 /r                    RM     V/V        AVX           Extract 4-bit sign mask from xmm2 and store in reg.\r\n VMOVMSKPS reg, xmm2                                                     The upper bits of r32 or r64 are zeroed.\r\n\r\n VEX.256.0F.WIG 50 /r                    RM     V/V        AVX           Extract 8-bit sign mask from ymm2 and store in reg.\r\n VMOVMSKPS reg, ymm2                                                     The upper bits of r32 or r64 are zeroed.\r\n\r\n\r\n\r\n                                          Instruction Operand Encoding1\r\n   Op/En              Operand 1               Operand 2                    Operand 3                        Operand 4\r\n    RM            ModRM:reg (w)            ModRM:r/m (r)                       NA                               NA\r\n\r\n\r\nDescription\r\nExtracts the sign bits from the packed single-precision floating-point values in the source operand (second\r\noperand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand).\r\nThe source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The\r\nmask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand\r\nbeyond the mask are filled with zeros.\r\nIn 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R\r\nprefix. The default operand size is 64-bit in 64-bit mode.\r\n128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.\r\nVEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose\r\nregister.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nDEST[0] <- SRC[31];\r\nDEST[1] <- SRC[63];\r\nDEST[2] <- SRC[95];\r\nDEST[3] <- SRC[127];\r\n\r\nIF DEST = r32\r\n    THEN DEST[31:4] <- ZeroExtend;\r\n    ELSE DEST[63:4] <- ZeroExtend;\r\nFI;\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\n(V)MOVMSKPS (128-bit version)\r\nDEST[0] <- SRC[31]\r\nDEST[1] <- SRC[63]\r\nDEST[2] <- SRC[95]\r\nDEST[3] <- SRC[127]\r\nIF DEST = r32\r\n    THEN DEST[31:4] <- 0;\r\n    ELSE DEST[63:4] <- 0;\r\nFI\r\n\r\nVMOVMSKPS (VEX.256 encoded version)\r\nDEST[0] <- SRC[31]\r\nDEST[1] <- SRC[63]\r\nDEST[2] <- SRC[95]\r\nDEST[3] <- SRC[127]\r\nDEST[4] <- SRC[159]\r\nDEST[5] <- SRC[191]\r\nDEST[6] <- SRC[223]\r\nDEST[7] <- SRC[255]\r\nIF DEST = r32\r\n    THEN DEST[31:8] <- 0;\r\n    ELSE DEST[63:8] <- 0;\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nint _mm_movemask_ps(__m128 a)\r\nint _mm256_movemask_ps(__m256 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 7; additionally\r\n#UD                      If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVMSKPS"
    }, 
    {
      "description": "MOVNTDQ-Store Packed Integers Using Non-Temporal Hint\r\n Opcode/                        Op /     64/32      CPUID            Description\r\n Instruction                    En       bit Mode   Feature Flag\r\n                                         Support\r\n 66 0F E7 /r                    MR       V/V        SSE2             Move packed integer values in xmm1 to m128 using non-\r\n MOVNTDQ m128, xmm1                                                  temporal hint.\r\n VEX.128.66.0F.WIG E7 /r        MR       V/V        AVX              Move packed integer values in xmm1 to m128 using non-\r\n VMOVNTDQ m128, xmm1                                                 temporal hint.\r\n VEX.256.66.0F.WIG E7 /r        MR       V/V        AVX              Move packed integer values in ymm1 to m256 using non-\r\n VMOVNTDQ m256, ymm1                                                 temporal hint.\r\n EVEX.128.66.0F.W0 E7 /r        FVM      V/V        AVX512VL         Move packed integer values in xmm1 to m128 using non-\r\n VMOVNTDQ m128, xmm1                                AVX512F          temporal hint.\r\n EVEX.256.66.0F.W0 E7 /r        FVM      V/V        AVX512VL         Move packed integer values in zmm1 to m256 using non-\r\n VMOVNTDQ m256, ymm1                                AVX512F          temporal hint.\r\n EVEX.512.66.0F.W0 E7 /r        FVM      V/V        AVX512F          Move packed integer values in zmm1 to m512 using non-\r\n VMOVNTDQ m512, zmm1                                                 temporal hint.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding1\r\n       Op/En                 Operand 1                 Operand 2                   Operand 3                  Operand 4\r\n        MR                 ModRM:r/m (w)             ModRM:reg (r)                    NA                         NA\r\n        FVM                ModRM:r/m (w)             ModRM:reg (r)                    NA                         NA\r\n\r\nDescription\r\nMoves the packed integers in the source operand (second operand) to the destination operand (first operand) using\r\na non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM\r\nregister, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, double-\r\nwords, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory\r\noperand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit\r\nversion) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple proces-\r\nsors might use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will\r\n#UD.\r\n\r\nOperation\r\nVMOVNTDQ(EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTDQ (Legacy and VEX versions)\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);\r\nVMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);\r\nMOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD                     If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTDQ"
    }, 
    {
      "description": "MOVNTDQA-Load Double Quadword Non-Temporal Aligned Hint\r\n Opcode/                         Op /    64/32       CPUID           Description\r\n Instruction                     En      bit Mode    Feature Flag\r\n                                         Support\r\n 66 0F 38 2A /r                  RM      V/V         SSE4_1          Move double quadword from m128 to xmm1 using non-\r\n MOVNTDQA xmm1, m128                                                 temporal hint if WC memory type.\r\n VEX.128.66.0F38.WIG 2A /r       RM      V/V         AVX             Move double quadword from m128 to xmm using non-\r\n VMOVNTDQA xmm1, m128                                                temporal hint if WC memory type.\r\n VEX.256.66.0F38.WIG 2A /r       RM      V/V         AVX2            Move 256-bit data from m256 to ymm using non-temporal\r\n VMOVNTDQA ymm1, m256                                                hint if WC memory type.\r\n EVEX.128.66.0F38.W0 2A /r       FVM     V/V         AVX512VL        Move 128-bit data from m128 to xmm using non-temporal\r\n VMOVNTDQA xmm1, m128                                AVX512F         hint if WC memory type.\r\n EVEX.256.66.0F38.W0 2A /r       FVM     V/V         AVX512VL        Move 256-bit data from m256 to ymm using non-temporal\r\n VMOVNTDQA ymm1, m256                                AVX512F         hint if WC memory type.\r\n EVEX.512.66.0F38.W0 2A /r       FVM     V/V         AVX512F         Move 512-bit data from m512 to zmm using non-temporal\r\n VMOVNTDQA zmm1, m512                                                hint if WC memory type.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding1\r\n        Op/En                Operand 1                 Operand 2                   Operand 3               Operand 4\r\n         RM              ModRM:reg (w)               ModRM:r/m (r)                    NA                      NA\r\n         FVM             ModRM:reg (w)               ModRM:r/m (r)                    NA                      NA\r\n\r\nDescription\r\nMOVNTDQA loads a double quadword from the source operand (second operand) to the destination operand (first\r\noperand) using a non-temporal hint if the memory source is WC (write combining) memory type. For WC memory\r\ntype, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an\r\naligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped\r\nand flushed. Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the\r\ntemporary internal buffer if data is available. The temporary internal buffer may be flushed by the processor at any\r\ntime for any reason, for example:\r\n. A load operation other than a MOVNTDQA which references memory already resident in a temporary internal\r\nbuffer.\r\n. A non-WC reference to memory already resident in a temporary internal buffer.\r\n. Interleaving of reads and writes to a single temporary internal buffer.\r\n. Repeated (V)MOVNTDQA loads of a particular 16-byte item in a streaming line.\r\n. Certain micro-architectural conditions including resource shortages, detection of\r\na mis-speculation condition, and various fault conditions\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when reading the\r\ndata from memory. Using this protocol, the processor\r\ndoes not read the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into\r\nthe cache hierarchy. The memory type of the region being read can override the non-temporal hint, if the memory\r\naddress specified for the non-temporal read is not a WC memory region. Information on non-temporal reads and\r\nwrites can be found in \"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32\r\nArchitecture Software Developer's Manual, Volume 3A.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\na MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use\r\ndifferent memory types for the referenced memory locations or to synchronize reads of a processor with writes by\r\nother agents in the system. A processor's implementation of the streaming load hint does not override the effective\r\nmemory type, but the implementation of the hint is processor dependent. For example, a processor implementa-\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\ntion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alter-\r\nnatively, another implementation may optimize cache reads generated by MOVNTDQA on WB memory type to\r\nreduce cache evictions.\r\nThe 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the instruction will cause a #GP.\r\nThe 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.\r\nThe 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.\r\n\r\nOperation\r\nMOVNTDQA (128bit- Legacy SSE form)\r\nDEST <-SRC\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVNTDQA (VEX.128 and EVEX.128 encoded form)\r\nDEST <- SRC\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVNTDQA (VEX.256 and EVEX.256 encoded forms)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVNTDQA (EVEX.512 encoded form)\r\nDEST[511:0] <- SRC[511:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTDQA __m512i _mm512_stream_load_si512(void * p);\r\nMOVNTDQA __m128i _mm_stream_load_si128 (__m128i *p);\r\nVMOVNTDQA __m256i _mm_stream_load_si256 (__m256i *p);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTDQA"
    }, 
    {
      "description": "MOVNTI-Store Doubleword Using Non-Temporal Hint\r\nOpcode                    Instruction                    Op/    64-Bit   Compat/ Description\r\n                                                         En     Mode     Leg Mode\r\n0F C3 /r                  MOVNTI m32, r32                MR     Valid    Valid      Move doubleword from r32 to m32 using non-\r\n                                                                                    temporal hint.\r\nREX.W + 0F C3 /r          MOVNTI m64, r64                MR     Valid    N.E.       Move quadword from r64 to m64 using non-\r\n                                                                                    temporal hint.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n   Op/En              Operand 1                        Operand 2                 Operand 3                   Operand 4\r\n    MR              ModRM:r/m (w)                     ModRM:reg (r)                 NA                          NA\r\n\r\n\r\nDescription\r\nMoves the doubleword integer in the source operand (second operand) to the destination operand (first operand)\r\nusing a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a\r\ngeneral-purpose register. The destination operand is a 32-bit memory location.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTI instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVNTI:        void _mm_stream_si32 (int *p, int a)\r\nMOVNTI:        void _mm_stream_si64(__int64 *p, __int64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0)                  For an illegal address in the SS segment.\r\n#PF(fault-code)         For a page fault.\r\n#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                        If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                    If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD                    If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                       If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code)        For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        For a page fault.\r\n#UD                    If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                       If the LOCK prefix is used.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTI"
    }, 
    {
      "description": "MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint\r\n Opcode/                         Op /      64/32       CPUID             Description\r\n Instruction                     En        bit Mode    Feature\r\n                                           Support     Flag\r\n 66 0F 2B /r                     MR        V/V         SSE2              Move packed double-precision values in xmm1 to m128 using\r\n MOVNTPD m128, xmm1                                                      non-temporal hint.\r\n VEX.128.66.0F.WIG 2B /r         MR        V/V         AVX               Move packed double-precision values in xmm1 to m128 using\r\n VMOVNTPD m128, xmm1                                                     non-temporal hint.\r\n VEX.256.66.0F.WIG 2B /r         MR        V/V         AVX               Move packed double-precision values in ymm1 to m256 using\r\n VMOVNTPD m256, ymm1                                                     non-temporal hint.\r\n EVEX.128.66.0F.W1 2B /r         FVM       V/V         AVX512VL          Move packed double-precision values in xmm1 to m128 using\r\n VMOVNTPD m128, xmm1                                   AVX512F           non-temporal hint.\r\n EVEX.256.66.0F.W1 2B /r         FVM       V/V         AVX512VL          Move packed double-precision values in ymm1 to m256 using\r\n VMOVNTPD m256, ymm1                                   AVX512F           non-temporal hint.\r\n EVEX.512.66.0F.W1 2B /r         FVM       V/V         AVX512F           Move packed double-precision values in zmm1 to m512 using\r\n VMOVNTPD m512, zmm1                                                     non-temporal hint.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding1\r\n       Op/En                 Operand 1                    Operand 2                    Operand 3                    Operand 4\r\n         MR                ModRM:r/m (w)                 ModRM:reg (r)                     NA                           NA\r\n        FVM                ModRM:r/m (w)                 ModRM:reg (r)                     NA                           NA\r\n\r\nDescription\r\nMoves the packed double-precision floating-point values in the source operand (second operand) to the destination\r\noperand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The\r\nsource operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double-\r\nprecision, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The\r\nmemory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte\r\n(EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will\r\n#UD.\r\n\r\nOperation\r\nVMOVNTPD (EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTPD (Legacy and VEX versions)\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTPD void _mm512_stream_pd(double * p, __m512d a);\r\nVMOVNTPD void _mm256_stream_pd (double * p, __m256d a);\r\nMOVNTPD void _mm_stream_pd (double * p, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTPD"
    }, 
    {
      "description": "MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint\r\n Opcode/                         Op /   64/32         CPUID            Description\r\n Instruction                     En     bit Mode      Feature\r\n                                        Support       Flag\r\n 0F 2B /r                        MR     V/V           SSE              Move packed single-precision values xmm1 to mem using\r\n MOVNTPS m128, xmm1                                                    non-temporal hint.\r\n VEX.128.0F.WIG 2B /r            MR     V/V           AVX              Move packed single-precision values xmm1 to mem using\r\n VMOVNTPS m128, xmm1                                                   non-temporal hint.\r\n VEX.256.0F.WIG 2B /r            MR     V/V           AVX              Move packed single-precision values ymm1 to mem using\r\n VMOVNTPS m256, ymm1                                                   non-temporal hint.\r\n EVEX.128.0F.W0 2B /r            FVM    V/V           AVX512VL         Move packed single-precision values in xmm1 to m128\r\n VMOVNTPS m128, xmm1                                  AVX512F          using non-temporal hint.\r\n EVEX.256.0F.W0 2B /r            FVM    V/V           AVX512VL         Move packed single-precision values in ymm1 to m256\r\n VMOVNTPS m256, ymm1                                  AVX512F          using non-temporal hint.\r\n EVEX.512.0F.W0 2B /r            FVM    V/V           AVX512F          Move packed single-precision values in zmm1 to m512\r\n VMOVNTPS m512, zmm1                                                   using non-temporal hint.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding1\r\n       Op/En              Operand 1                   Operand 2                    Operand 3                     Operand 4\r\n        MR              ModRM:r/m (w)               ModRM:reg (r)                      NA                            NA\r\n        FVM             ModRM:r/m (w)               ModRM:reg (r)                      NA                            NA\r\n\r\nDescription\r\nMoves the packed single-precision floating-point values in the source operand (second operand) to the destination\r\noperand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The\r\nsource operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single-preci-\r\nsion, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory\r\noperand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512\r\nencoded version) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTPS instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVMOVNTPS (EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTPS\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTPS void _mm512_stream_ps(float * p, __m512d a);\r\nMOVNTPS void _mm_stream_ps (float * p, __m128d a);\r\nVMOVNTPS void _mm256_stream_ps (float * p, __m256 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTPS"
    }, 
    {
      "description": "MOVNTQ-Store of Quadword Using Non-Temporal Hint\r\nOpcode                   Instruction               Op/   64-Bit   Compat/ Description\r\n                                                   En    Mode     Leg Mode\r\n0F E7 /r                 MOVNTQ m64, mm            MR    Valid    Valid        Move quadword from mm to m64 using non-\r\n                                                                               temporal hint.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En             Operand 1                   Operand 2                Operand 3                      Operand 4\r\n    MR             ModRM:r/m (w)               ModRM:reg (r)                   NA                           NA\r\n\r\n\r\nDescription\r\nMoves the quadword in the source operand (second operand) to the destination operand (first operand) using a\r\nnon-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX tech-\r\nnology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The\r\ndestination operand is a 64-bit memory location.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVNTQ:         void _mm_stream_pi(__m64 * p, __m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVNTQ"
    }, 
    {
      "description": "-R:MOVD", 
      "mnem": "MOVQ"
    }, 
    {
      "description": "MOVQ-Move Quadword\r\nOpcode/                               Op/ En     64/32-bit CPUID     Description\r\nInstruction                                      Mode      Feature\r\n                                                           Flag\r\n0F 6F /r                              RM         V/V       MMX       Move quadword from mm/m64 to mm.\r\nMOVQ mm, mm/m64\r\n0F 7F /r                              MR         V/V       MMX       Move quadword from mm to mm/m64.\r\nMOVQ mm/m64, mm\r\nF3 0F 7E /r                           RM         V/V       SSE2      Move quadword from xmm2/mem64 to xmm1.\r\nMOVQ xmm1, xmm2/m64\r\nVEX.128.F3.0F.WIG 7E /r               RM         V/V       AVX       Move quadword from xmm2 to xmm1.\r\nVMOVQ xmm1, xmm2/m64\r\nEVEX.128.F3.0F.W1 7E /r               T1S-RM V/V           AVX512F   Move quadword from xmm2/m64 to xmm1.\r\nVMOVQ xmm1, xmm2/m64\r\n66 0F D6 /r                           MR         V/V       SSE2      Move quadword from xmm1 to xmm2/mem64.\r\nMOVQ xmm2/m64, xmm1\r\nVEX.128.66.0F.WIG D6 /r               MR         V/V       AVX       Move quadword from xmm2 register to xmm1/m64.\r\nVMOVQ xmm1/m64, xmm2\r\nEVEX.128.66.0F.W1 D6 /r               T1S-MR V/V           AVX512F   Move quadword from xmm2 register to xmm1/m64.\r\nVMOVQ xmm1/m64, xmm2\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n  Op/En              Operand 1                 Operand 2                Operand 3                 Operand 4\r\n   RM            ModRM:reg (w)             ModRM:r/m (r)                   NA                        NA\r\n   MR            ModRM:r/m (w)             ModRM:reg (r)                   NA                        NA\r\n T1S-RM          ModRM:reg (w)             ModRM:r/m (r)                   NA                        NA\r\n T1S-MR          ModRM:r/m (w)             ModRM:reg (r)                   NA                        NA\r\n\r\n\r\nDescription\r\nCopies a quadword from the source operand (second operand) to the destination operand (first operand). The\r\nsource and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations.\r\nThis instruction can be used to move a quadword between two MMX technology registers or between an MMX tech-\r\nnology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM\r\nregister and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.\r\nWhen the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM\r\nregister, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.\r\nIn 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in the form of REX.R permits this instruc-\r\ntion to access additional registers (XMM8-XMM15).\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nIf VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVQ instruction when operating on MMX technology registers and memory locations:\r\n  DEST <- SRC;\r\n\r\nMOVQ instruction when source and destination operands are XMM registers:\r\n  DEST[63:0] <- SRC[63:0];\r\n  DEST[127:64] <- 0000000000000000H;\r\n\r\nMOVQ instruction when source operand is XMM register and destination\r\noperand is memory location:\r\n   DEST <- SRC[63:0];\r\n\r\nMOVQ instruction when source operand is memory location and destination\r\noperand is XMM register:\r\n   DEST[63:0] <- SRC;\r\n   DEST[127:64] <- 0000000000000000H;\r\n\r\nVMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (VEX.128.66.0F D6) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (7E - EVEX encoded version) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (D6 - EVEX encoded version) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (7E) with memory source:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (7E - EVEX encoded version) with memory source:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[:MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (D6) with memory dest:\r\nDEST[63:0] <- SRC2[63:0]\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVQ __m128i _mm_loadu_si64( void * s);\r\nVMOVQ void _mm_storeu_si64( void * d, __m128i s);\r\nMOVQ            m128i _mm_mov_epi64(__m128i a)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVQ"
    }, 
    {
      "description": "MOVQ2DQ-Move Quadword from MMX Technology to XMM Register\r\nOpcode                  Instruction                  Op/   64-Bit    Compat/ Description\r\n                                                     En    Mode      Leg Mode\r\nF3 0F D6 /r             MOVQ2DQ xmm, mm              RM    Valid     Valid       Move quadword from mmx to low quadword\r\n                                                                                 of xmm.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En            Operand 1                   Operand 2                    Operand 3                   Operand 4\r\n    RM            ModRM:reg (w)               ModRM:r/m (r)                     NA                          NA\r\n\r\n\r\nDescription\r\nMoves the quadword from the source operand (second operand) to the low quadword of the destination operand\r\n(first operand). The source operand is an MMX technology register and the destination operand is an XMM register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[63:0] <- SRC[63:0];\r\nDEST[127:64] <- 00000000000000000H;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVQ2DQ:        __128i _mm_movpi64_pi64 ( __m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM                   If CR0.TS[bit 3] = 1.\r\n#UD                   If CR0.EM[bit 2] = 1.\r\n                      If CR4.OSFXSR[bit 9] = 0.\r\n                      If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n                      If the LOCK prefix is used.\r\n#MF                   If there is a pending x87 FPU exception.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n", 
      "mnem": "MOVQ2DQ"
    }, 
    {
      "description": "MOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String\r\n  Opcode              Instruction                Op/     64-Bit   Compat/ Description\r\n                        … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MOVS"
    }, 
    {
      "description": "-R:MOVS", 
      "mnem": "MOVSB"
    }, 
    {
      "description": "-R:MOVS", 
      "mnem": "MOVSD"
    }, 
    {
      "description": "MOVSD-Move or Merge Scalar Double-Precision Floating-Point Value\r\n Opcode/                                      Op / En   64/32         CPUID     Description\r\n Instruction                                            bit Mode      Feature\r\n                                                        Support       Flag\r\n F2 0F 10 /r                                  RM        V/V           SSE2      Move scalar double-precision floating-point value\r\n MOVSD xmm1, xmm2                                                               from xmm2 to xmm1 register.\r\n F2 0F 10 /r                                  RM        V/V           SSE2      Load scalar double-precision floating-point value\r\n MOVSD xmm1, m64                                                                from m64 to xmm1 register.\r\n F2 0F 11 /r                                  MR        V/V           SSE2      Move scalar double-precision floating-point value\r\n MOVSD xmm1/m64, xmm2                                                           from xmm2 register to xmm1/m64.\r\n VEX.NDS.LIG.F2.0F.WIG 10 /r                  RVM       V/V           AVX       Merge scalar double-precision floating-point value\r\n VMOVSD xmm1, xmm2, xmm3                                                        from xmm2 and xmm3 to xmm1 register.\r\n VEX.LIG.F2.0F.WIG 10 /r                      XM        V/V           AVX       Load scalar double-precision floating-point value\r\n VMOVSD xmm1, m64                                                               from m64 to xmm1 register.\r\n VEX.NDS.LIG.F2.0F.WIG 11 /r                  MVR       V/V           AVX       Merge scalar double-precision floating-point value\r\n VMOVSD xmm1, xmm2, xmm3                                                        from xmm2 and xmm3 registers to xmm1.\r\n VEX.LIG.F2.0F.WIG 11 /r                      MR        V/V           AVX       Store scalar double-precision floating-point value\r\n VMOVSD m64, xmm1                                                               from xmm1 register to m64.\r\n EVEX.NDS.LIG.F2.0F.W1 10 /r                  RVM       V/V           AVX512F   Merge scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, xmm2, xmm3                                                from xmm2 and xmm3 registers to xmm1 under\r\n                                                                                writemask k1.\r\n EVEX.LIG.F2.0F.W1 10 /r                      T1S-RM    V/V           AVX512F   Load scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, m64                                                       from m64 to xmm1 register under writemask k1.\r\n EVEX.NDS.LIG.F2.0F.W1 11 /r                  MVR       V/V           AVX512F   Merge scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, xmm2, xmm3                                                from xmm2 and xmm3 registers to xmm1 under\r\n                                                                                writemask k1.\r\n EVEX.LIG.F2.0F.W1 11 /r                      T1S-MR    V/V           AVX512F   Store scalar double-precision floating-point value\r\n VMOVSD m64 {k1}, xmm1                                                          from xmm1 register to m64 under writemask k1.\r\n\r\n\r\n\r\n                                                    Instruction Operand Encoding\r\n       Op/En                  Operand 1                       Operand 2               Operand 3                   Operand 4\r\n         RM                ModRM:reg (r, w)                ModRM:r/m (r)                  NA                          NA\r\n        RVM                 ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                     NA\r\n         MR                 ModRM:r/m (w)                  ModRM:reg (r)                  NA                          NA\r\n         XM                 ModRM:reg (w)                  ModRM:r/m (r)                  NA                          NA\r\n        MVR                 ModRM:r/m (w)                      vvvv (r)             ModRM:reg (r)                     NA\r\n      T1S-RM               ModRM:reg (r, w)                ModRM:r/m (r)                  NA                          NA\r\n      T1S-MR                ModRM:r/m (w)                  ModRM:reg (r)                  NA                          NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nMoves a scalar double-precision floating-point value from the source operand (second operand) to the destination\r\noperand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations.\r\nThis instruction can be used to move a double-precision floating-point value to and from the low quadword of an\r\nXMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low\r\nquadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.\r\nLegacy version: When the source and destination operands are XMM registers, bits MAX_VL:64 of the destination\r\noperand remains unchanged. When the source operand is a memory location and destination operand is an XMM\r\nregisters, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAX_VL:128 of the desti-\r\nnation operand remains unchanged.\r\nVEX and EVEX encoded register-register syntax: Moves a scalar double-precision floating-point value from the\r\nsecond source operand (the third operand) to the low quadword element of the destination operand (the first\r\noperand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand).\r\nBits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination\r\noperand is an XMM registers, bits MAX_VL:64 of the destination operand is cleared to all 0s.\r\nEVEX encoded versions: The low quadword of the destination is updated according to the writemask.\r\nNote: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b,\r\notherwise instruction will #UD.\r\n\r\nOperation\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 10 /r: VMOVSD xmm1, m64 with support for 32 registers)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC[63:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[511:64] <- 0\r\n\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD m64, xmm1 with support for 32 registers)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC[63:0]\r\n    ELSE      *DEST[63:0] remains unchanged*   ; merging-masking\r\nFI;\r\n\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC2[63:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\r\nDEST[63:0] <-SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)\r\nDEST[63:0] <-SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[MAX_VL-1:64] <-0\r\n\r\nMOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)\r\nDEST[63:0] <-SRC[63:0]\r\n\r\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);\r\nVMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);\r\nVMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);\r\nVMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);\r\nVMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);\r\nMOVSD __m128d _mm_load_sd (double *p)\r\nMOVSD void _mm_store_sd (double *p, __m128d a)\r\nMOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                      If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E10.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVSD"
    }, 
    {
      "description": "MOVSHDUP-Replicate Single FP Values\r\n Opcode/                           Op /        64/32        CPUID         Description\r\n Instruction                       En          bit Mode     Feature\r\n                                               Support      Flag\r\n F3 0F 16 /r                       RM          V/V          SSE3          Move odd index single-precision floating-point values from\r\n MOVSHDUP xmm1, xmm2/m128                                                 xmm2/mem and duplicate each element into xmm1.\r\n VEX.128.F3.0F.WIG 16 /r           RM          V/V          AVX           Move odd index single-precision floating-point values from\r\n VMOVSHDUP xmm1, xmm2/m128                                                xmm2/mem and duplicate each element into xmm1.\r\n VEX.256.F3.0F.WIG 16 /r           RM          V/V          AVX           Move odd index single-precision floating-point values from\r\n VMOVSHDUP ymm1, ymm2/m256                                                ymm2/mem and duplicate each element into ymm1.\r\n EVEX.128.F3.0F.W0 16 /r           FVM         V/V          AVX512VL      Move odd index single-precision floating-point values from\r\n VMOVSHDUP xmm1 {k1}{z},                                    AVX512F       xmm2/m128 and duplicate each element into xmm1 under\r\n xmm2/m128                                                                writemask.\r\n EVEX.256.F3.0F.W0 16 /r           FVM         V/V          AVX512VL      Move odd index single-precision floating-point values from\r\n VMOVSHDUP ymm1 {k1}{z},                                    AVX512F       ymm2/m256 and duplicate each element into ymm1 under\r\n ymm2/m256                                                                writemask.\r\n EVEX.512.F3.0F.W0 16 /r           FVM         V/V          AVX512F       Move odd index single-precision floating-point values from\r\n VMOVSHDUP zmm1 {k1}{z},                                                  zmm2/m512 and duplicate each element into zmm1 under\r\n zmm2/m512                                                                writemask.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n       Op/En               Operand 1                       Operand 2                    Operand 3                  Operand 4\r\n         RM             ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA\r\n        FVM             ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA\r\n\r\nDescription\r\nDuplicates odd-indexed single-precision floating-point values from the source operand (the second operand) to\r\nadjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an\r\nXMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM\r\nor ZMM register.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.\r\nEVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n                     SRC      X7          X6         X5         X4        X3       X2        X1        X0\r\n\r\n\r\n\r\n\r\n                     DEST     X7          X7         X5         X5        X3       X3        X1        X1\r\n\r\n\r\n                                               Figure 4-3. MOVSHDUP Operation\r\n\r\n\r\nOperation\r\nVMOVSHDUP (EVEX encoded versions)\r\n\r\n\r\n\r\n\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nTMP_SRC[31:0] <- SRC[63:32]\r\nTMP_SRC[63:32] <- SRC[63:32]\r\nTMP_SRC[95:64] <- SRC[127:96]\r\nTMP_SRC[127:96] <- SRC[127:96]\r\nIF VL >= 256\r\n    TMP_SRC[159:128] <- SRC[191:160]\r\n    TMP_SRC[191:160] <- SRC[191:160]\r\n    TMP_SRC[223:192] <- SRC[255:224]\r\n    TMP_SRC[255:224] <- SRC[255:224]\r\nFI;\r\nIF VL >= 512\r\n    TMP_SRC[287:256] <- SRC[319:288]\r\n    TMP_SRC[319:288] <- SRC[319:288]\r\n    TMP_SRC[351:320] <- SRC[383:352]\r\n    TMP_SRC[383:352] <- SRC[383:352]\r\n    TMP_SRC[415:384] <- SRC[447:416]\r\n    TMP_SRC[447:416] <- SRC[447:416]\r\n    TMP_SRC[479:448] <- SRC[511:480]\r\n    TMP_SRC[511:480] <- SRC[511:480]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i] <- TMP_SRC[i+31:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVSHDUP (VEX.256 encoded version)\r\nDEST[31:0] <- SRC[63:32]\r\nDEST[63:32] <- SRC[63:32]\r\nDEST[95:64] <- SRC[127:96]\r\nDEST[127:96] <- SRC[127:96]\r\nDEST[159:128] <- SRC[191:160]\r\nDEST[191:160] <- SRC[191:160]\r\nDEST[223:192] <- SRC[255:224]\r\nDEST[255:224] <- SRC[255:224]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVSHDUP (VEX.128 encoded version)\r\nDEST[31:0] <- SRC[63:32]\r\nDEST[63:32] <- SRC[63:32]\r\nDEST[95:64] <- SRC[127:96]\r\nDEST[127:96] <- SRC[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\nMOVSHDUP (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC[63:32]\r\n\r\n\r\n\r\nDEST[63:32] <-SRC[63:32]\r\nDEST[95:64] <-SRC[127:96]\r\nDEST[127:96] <-SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);\r\nVMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);\r\nVMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);\r\nVMOVSHDUP __m256 _mm256_mask_movehdup_ps(__m256 s, __mmask8 k, __m256 a);\r\nVMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);\r\nVMOVSHDUP __m128 _mm_mask_movehdup_ps(__m128 s, __mmask8 k, __m128 a);\r\nVMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);\r\nVMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);\r\nVMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVSHDUP"
    }, 
    {
      "description": "MOVSLDUP-Replicate Single FP Values\r\n Opcode/                               Op /        64/32       CPUID          Description\r\n Instruction                           En          bit Mode    Feature\r\n                                                   Support     Flag\r\n F3 0F 12 /r                           A           V/V         SSE3           Move even index single-precision floating-point values from\r\n MOVSLDUP xmm1, xmm2/m128                                                     xmm2/mem and duplicate each element into xmm1.\r\n VEX.128.F3.0F.WIG 12 /r               RM          V/V         AVX            Move even index single-precision floating-point values from\r\n VMOVSLDUP xmm1, xmm2/m128                                                    xmm2/mem and duplicate each element into xmm1.\r\n VEX.256.F3.0F.WIG 12 /r               RM          V/V         AVX            Move even index single-precision floating-point values from\r\n VMOVSLDUP ymm1, ymm2/m256                                                    ymm2/mem and duplicate each element into ymm1.\r\n EVEX.128.F3.0F.W0 12 /r               FVM         V/V         AVX512VL       Move even index single-precision floating-point values from\r\n VMOVSLDUP xmm1 {k1}{z},                                       AVX512F        xmm2/m128 and duplicate each element into xmm1 under\r\n xmm2/m128                                                                    writemask.\r\n EVEX.256.F3.0F.W0 12 /r               FVM         V/V         AVX512VL       Move even index single-precision floating-point values from\r\n VMOVSLDUP ymm1 {k1}{z},                                       AVX512F        ymm2/m256 and duplicate each element into ymm1 under\r\n ymm2/m256                                                                    writemask.\r\n EVEX.512.F3.0F.W0 12 /r               FVM         V/V         AVX512F        Move even index single-precision floating-point values from\r\n VMOVSLDUP zmm1 {k1}{z},                                                      zmm2/m512 and duplicate each element into zmm1 under\r\n zmm2/m512                                                                    writemask.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n        Op/En                  Operand 1                       Operand 2                    Operand 3                  Operand 4\r\n         RM                 ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA\r\n        FVM                 ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA\r\n\r\nDescription\r\nDuplicates even-indexed single-precision floating-point values from the source operand (the second operand). See\r\nFigure 4-4. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the\r\ndestination operand is an XMM, YMM or ZMM register.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.\r\nEVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n                         SRC      X7          X6         X5          X4       X3       X2        X1        X0\r\n\r\n\r\n\r\n\r\n                         DEST     X6          X6         X4          X4       X2       X2        X0        X0\r\n\r\n\r\n                                                   Figure 4-4. MOVSLDUP Operation\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMOVSLDUP (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nTMP_SRC[31:0] <- SRC[31:0]\r\nTMP_SRC[63:32] <- SRC[31:0]\r\nTMP_SRC[95:64] <- SRC[95:64]\r\nTMP_SRC[127:96] <- SRC[95:64]\r\nIF VL >= 256\r\n    TMP_SRC[159:128] <- SRC[159:128]\r\n    TMP_SRC[191:160] <- SRC[159:128]\r\n    TMP_SRC[223:192] <- SRC[223:192]\r\n    TMP_SRC[255:224] <- SRC[223:192]\r\nFI;\r\nIF VL >= 512\r\n    TMP_SRC[287:256] <- SRC[287:256]\r\n    TMP_SRC[319:288] <- SRC[287:256]\r\n    TMP_SRC[351:320] <- SRC[351:320]\r\n    TMP_SRC[383:352] <- SRC[351:320]\r\n    TMP_SRC[415:384] <- SRC[415:384]\r\n    TMP_SRC[447:416] <- SRC[415:384]\r\n    TMP_SRC[479:448] <- SRC[479:448]\r\n    TMP_SRC[511:480] <- SRC[479:448]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i] <- TMP_SRC[i+31:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVSLDUP (VEX.256 encoded version)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[63:32] <- SRC[31:0]\r\nDEST[95:64] <- SRC[95:64]\r\nDEST[127:96] <- SRC[95:64]\r\nDEST[159:128] <- SRC[159:128]\r\nDEST[191:160] <- SRC[159:128]\r\nDEST[223:192] <- SRC[223:192]\r\nDEST[255:224] <- SRC[223:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVSLDUP (VEX.128 encoded version)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[63:32] <- SRC[31:0]\r\nDEST[95:64] <- SRC[95:64]\r\nDEST[127:96] <- SRC[95:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nMOVSLDUP (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[63:32] <-SRC[31:0]\r\nDEST[95:64] <-SRC[95:64]\r\nDEST[127:96] <-SRC[95:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSLDUP __m512 _mm512_moveldup_ps( __m512 a);\r\nVMOVSLDUP __m512 _mm512_mask_moveldup_ps(__m512 s, __mmask16 k, __m512 a);\r\nVMOVSLDUP __m512 _mm512_maskz_moveldup_ps( __mmask16 k, __m512 a);\r\nVMOVSLDUP __m256 _mm256_mask_moveldup_ps(__m256 s, __mmask8 k, __m256 a);\r\nVMOVSLDUP __m256 _mm256_maskz_moveldup_ps( __mmask8 k, __m256 a);\r\nVMOVSLDUP __m128 _mm_mask_moveldup_ps(__m128 s, __mmask8 k, __m128 a);\r\nVMOVSLDUP __m128 _mm_maskz_moveldup_ps( __mmask8 k, __m128 a);\r\nVMOVSLDUP __m256 _mm256_moveldup_ps (__m256 a);\r\nVMOVSLDUP __m128 _mm_moveldup_ps (__m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n#UD                     If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVSLDUP"
    }, 
    {
      "description": "-R:MOVS", 
      "mnem": "MOVSQ"
    }, 
    {
      "description": "MOVSS-Move or Merge Scalar Single-Precision Floating-Point Value\r\n Opcode/                                Op / En   64/32         CPUID       Description\r\n Instruction                                      bit Mode      Feature\r\n                                                  Support       Flag\r\n F3 0F 10 /r                            RM        V/V           SSE         Merge scalar single-precision floating-point value\r\n MOVSS xmm1, xmm2                                                           from xmm2 to xmm1 register.\r\n F3 0F 10 /r                            RM        V/V           SSE         Load scalar single-precision floating-point value from\r\n MOVSS xmm1, m32                                                            m32 to xmm1 register.\r\n VEX.NDS.LIG.F3.0F.WIG 10 /r            RVM       V/V           AVX         Merge scalar single-precision floating-point value\r\n VMOVSS xmm1, xmm2, xmm3                                                    from xmm2 and xmm3 to xmm1 register\r\n VEX.LIG.F3.0F.WIG 10 /r                XM        V/V           AVX         Load scalar single-precision floating-point value from\r\n VMOVSS xmm1, m32                                                           m32 to xmm1 register.\r\n F3 0F 11 /r                            MR        V/V           SSE         Move scalar single-precision floating-point value\r\n MOVSS xmm2/m32, xmm1                                                       from xmm1 register to xmm2/m32.\r\n VEX.NDS.LIG.F3.0F.WIG 11 /r            MVR       V/V           AVX         Move scalar single-precision floating-point value\r\n VMOVSS xmm1, xmm2, xmm3                                                    from xmm2 and xmm3 to xmm1 register.\r\n VEX.LIG.F3.0F.WIG 11 /r                MR        V/V           AVX         Move scalar single-precision floating-point value\r\n VMOVSS m32, xmm1                                                           from xmm1 register to m32.\r\n EVEX.NDS.LIG.F3.0F.W0 10 /r            RVM       V/V           AVX512F     Move scalar single-precision floating-point value\r\n VMOVSS xmm1 {k1}{z}, xmm2, xmm3                                            from xmm2 and xmm3 to xmm1 register under\r\n                                                                            writemask k1.\r\n EVEX.LIG.F3.0F.W0 10 /r                T1S-RM    V/V           AVX512F     Move scalar single-precision floating-point values\r\n VMOVSS xmm1 {k1}{z}, m32                                                   from m32 to xmm1 under writemask k1.\r\n EVEX.NDS.LIG.F3.0F.W0 11 /r            MVR       V/V           AVX512F     Move scalar single-precision floating-point value\r\n VMOVSS xmm1 {k1}{z}, xmm2, xmm3                                            from xmm2 and xmm3 to xmm1 register under\r\n                                                                            writemask k1.\r\n EVEX.LIG.F3.0F.W0 11 /r                T1S-MR    V/V           AVX512F     Move scalar single-precision floating-point values\r\n VMOVSS m32 {k1}, xmm1                                                      from xmm1 to m32 under writemask k1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n      Op/En             Operand 1                   Operand 2                     Operand 3                     Operand 4\r\n       RM            ModRM:reg (r, w)             ModRM:r/m (r)                       NA                            NA\r\n      RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                       NA\r\n       MR            ModRM:r/m (w)                ModRM:reg (r)                       NA                            NA\r\n       XM            ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA\r\n      MVR            ModRM:r/m (w)                   vvvv (r)                   ModRM:reg (r)                       NA\r\n     T1S-RM          ModRM:reg (r, w)             ModRM:r/m (r)                       NA                            NA\r\n     T1S-MR          ModRM:r/m (w)                ModRM:reg (r)                       NA                            NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nMoves a scalar single-precision floating-point value from the source operand (second operand) to the destination\r\noperand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations.\r\nThis instruction can be used to move a single-precision floating-point value to and from the low doubleword of an\r\nXMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low\r\ndoublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.\r\nLegacy version: When the source and destination operands are XMM registers, bits (MAX_VL-1:32) of the corre-\r\nsponding destination register are unmodified. When the source operand is a memory location and destination\r\noperand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAX_VL:128 of the\r\ndestination operand remains unchanged.\r\nVEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the\r\nsecond source operand (the third operand) to the low doubleword element of the destination operand (the first\r\noperand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand).\r\nBits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination\r\noperand is an XMM registers, bits MAX_VL:32 of the destination operand is cleared to all 0s.\r\nEVEX encoded versions: The low doubleword of the destination is updated according to the writemask.\r\nNote: For memory store form instruction \"VMOVSS m32, xmm1\", VEX.vvvv is reserved and must be 1111b other-\r\nwise instruction will #UD. For memory store form instruction \"VMOVSS mv {k1}, xmm1\", EVEX.vvvv is reserved\r\nand must be 1111b otherwise instruction will #UD.\r\nSoftware should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 11 /r when the source operand is memory and the destination is an XMM register)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC[31:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[511:32] <- 0\r\n\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 10 /r when the source operand is an XMM register and the destination is memory)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC[31:0]\r\n    ELSE      *DEST[31:0] remains unchanged*   ; merging-masking\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 10/11 /r where the source and destination are XMM registers)\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC2[31:0]\r\n    ELSE\r\n         IF *merging-masking*              ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                         ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n         FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVSS (Legacy SSE version when the source and destination operands are both XMM registers)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 11 /r where the destination is an XMM register)\r\nDEST[31:0] <-SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 10 /r where the source and destination are XMM registers)\r\nDEST[31:0] <-SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[MAX_VL-1:32] <-0\r\n\r\nMOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)\r\nDEST[31:0] <-SRC[31:0]\r\n\r\nMOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[127:32] <-0\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);\r\nVMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);\r\nVMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);\r\nVMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);\r\nVMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);\r\nMOVSS __m128 _mm_load_ss(float * p)\r\nMOVSS void_mm_store_ss(float * p, __m128 a)\r\nMOVSS __m128 _mm_move_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD                      If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E10.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVSS"
    }, 
    {
      "description": "-R:MOVS", 
      "mnem": "MOVSW"
    }, 
    {
      "description": "MOVSX/MOVSXD-Move with Sign-Extension\r\nOpcode                    Instruction               Op/     64-Bit    Compat/ Description\r\n                                                    En      Mode      Leg Mode\r\n0F BE /r                  MOVSX r16, r/m8           RM      Valid     Valid       Move byte to word with sign-extension.\r\n0F BE /r                  MOVSX r32, r/m8           RM      Valid     Valid       Move byte to doubleword with sign-\r\n                                                                                  extension.\r\nREX + 0F BE /r            MOVSX r64, r/m8*          RM      Valid     N.E.        Move byte to quadword with sign-extension.\r\n0F BF /r                  MOVSX r32, r/m16          RM      Valid     Valid       Move word to doubleword, with sign-\r\n                                                                                  extension.\r\nREX.W + 0F BF /r          MOVSX r64, r/m16          RM      Valid     N.E.        Move word to quadword with sign-extension.\r\nREX.W** + 63 /r           MOVSXD r64, r/m32         RM      Valid     N.E.        Move doubleword to quadword with sign-\r\n                                                                                  extension.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without\r\n   REX.W.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En            Operand 1                   Operand 2                     Operand 3                    Operand 4\r\n    RM             ModRM:reg (w)              ModRM:r/m (r)                      NA                           NA\r\n\r\n\r\nDescription\r\nCopies the contents of the source operand (register or memory location) to the destination operand (register) and\r\nsign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- SignExtend(SRC);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                      If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                   If a memory operand effective address is outside the SS segment limit.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVSX"
    }, 
    {
      "description": "-R:MOVSX", 
      "mnem": "MOVSXD"
    }, 
    {
      "description": "MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values\r\n Opcode/                               Op / En   64/32      CPUID            Description\r\n Instruction                                     bit Mode   Feature\r\n                                                 Support    Flag\r\n 66 0F 10 /r                           RM        V/V        SSE2             Move unaligned packed double-precision floating-\r\n MOVUPD xmm1, xmm2/m128                                                      point from xmm2/mem to xmm1.\r\n 66 0F 11 /r                           MR        V/V        SSE2             Move unaligned packed double-precision floating-\r\n MOVUPD xmm2/m128, xmm1                                                      point from xmm1 to xmm2/mem.\r\n VEX.128.66.0F.WIG 10 /r               RM        V/V        AVX              Move unaligned packed double-precision floating-\r\n VMOVUPD xmm1, xmm2/m128                                                     point from xmm2/mem to xmm1.\r\n VEX.128.66.0F.WIG 11 /r               MR        V/V        AVX              Move unaligned packed double-precision floating-\r\n VMOVUPD xmm2/m128, xmm1                                                     point from xmm1 to xmm2/mem.\r\n VEX.256.66.0F.WIG 10 /r               RM        V/V        AVX              Move unaligned packed double-precision floating-\r\n VMOVUPD ymm1, ymm2/m256                                                     point from ymm2/mem to ymm1.\r\n VEX.256.66.0F.WIG 11 /r               MR        V/V        AVX              Move unaligned packed double-precision floating-\r\n VMOVUPD ymm2/m256, ymm1                                                     point from ymm1 to ymm2/mem.\r\n EVEX.128.66.0F.W1 10 /r               FVM-RM    V/V        AVX512VL         Move unaligned packed double-precision floating-\r\n VMOVUPD xmm1 {k1}{z}, xmm2/m128                            AVX512F          point from xmm2/m128 to xmm1 using\r\n                                                                             writemask k1.\r\n EVEX.128.66.0F.W1 11 /r               FVM-MR    V/V        AVX512VL         Move unaligned packed double-precision floating-\r\n VMOVUPD xmm2/m128 {k1}{z}, xmm1                            AVX512F          point from xmm1 to xmm2/m128 using\r\n                                                                             writemask k1.\r\n EVEX.256.66.0F.W1 10 /r               FVM-RM    V/V        AVX512VL         Move unaligned packed double-precision floating-\r\n VMOVUPD ymm1 {k1}{z}, ymm2/m256                            AVX512F          point from ymm2/m256 to ymm1 using\r\n                                                                             writemask k1.\r\n EVEX.256.66.0F.W1 11 /r               FVM-MR    V/V        AVX512VL         Move unaligned packed double-precision floating-\r\n VMOVUPD ymm2/m256 {k1}{z}, ymm1                            AVX512F          point from ymm1 to ymm2/m256 using\r\n                                                                             writemask k1.\r\n EVEX.512.66.0F.W1 10 /r               FVM-RM    V/V        AVX512F          Move unaligned packed double-precision floating-\r\n VMOVUPD zmm1 {k1}{z}, zmm2/m512                                             point values from zmm2/m512 to zmm1 using\r\n                                                                             writemask k1.\r\n EVEX.512.66.0F.W1 11 /r               FVM-MR    V/V        AVX512F          Move unaligned packed double-precision floating-\r\n VMOVUPD zmm2/m512 {k1}{z}, zmm1                                             point values from zmm1 to zmm2/m512 using\r\n                                                                             writemask k1.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n       Op/En             Operand 1                 Operand 2                     Operand 3                   Operand 4\r\n        RM             ModRM:reg (w)             ModRM:r/m (r)                      NA                           NA\r\n        MR             ModRM:r/m (w)             ModRM:reg (r)                      NA                           NA\r\n      FVM-RM           ModRM:reg (w)             ModRM:r/m (r)                      NA                           NA\r\n      RVM-MR           ModRM:r/m (w)             ModRM:reg (r)                      NA                           NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory\r\nlocation, to store the contents of a ZMM register into a memory. The destination operand is updated according to\r\nthe writemask.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version:\r\nMoves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\n\r\n\r\n128-bit versions:\r\nMoves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nWhen the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte\r\nboundary without causing a general-protection exception (#GP) to be generated\r\nVEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\nOperation\r\nVMOVUPD (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <- SRC[i+63:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPD (EVEX encoded versions, store-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i]<- SRC[i+63:i]\r\n         ELSE *DEST[i+63:i] remains unchanged*           ; merging-masking\r\n\r\n   FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVUPD (EVEX encoded versions, load-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+63:i] <- SRC[i+63:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPD (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVUPD (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVUPD (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVUPD (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVUPD (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVUPD __m512d _mm512_loadu_pd( void * s);\r\nVMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);\r\nVMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);\r\nVMOVUPD void _mm512_storeu_pd( void * d, __m512d a);\r\nVMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);\r\nVMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);\r\nVMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);\r\nVMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);\r\nVMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);\r\nVMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);\r\nVMOVUPD void _mm_mask_storeu_pd( void * d, __mmask8 k, __m128d a);\r\nMOVUPD __m256d _mm256_loadu_pd (double * p);\r\nMOVUPD void _mm256_storeu_pd( double *p, __m256d a);\r\nMOVUPD __m128d _mm_loadu_pd (double * p);\r\nMOVUPD void _mm_storeu_pd( double *p, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nNote treatment of #AC varies; additionally\r\n#UD                     If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVUPD"
    }, 
    {
      "description": "MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values\r\n Opcode/                               Op / En    64/32          CPUID        Description\r\n Instruction                                      bit Mode       Feature\r\n                                                  Support        Flag\r\n 0F 10 /r                              RM         V/V            SSE          Move unaligned packed single-precision\r\n MOVUPS xmm1, xmm2/m128                                                       floating-point from xmm2/mem to xmm1.\r\n 0F 11 /r                              MR         V/V            SSE          Move unaligned packed single-precision\r\n MOVUPS xmm2/m128, xmm1                                                       floating-point from xmm1 to xmm2/mem.\r\n VEX.128.0F.WIG 10 /r                  RM         V/V            AVX          Move unaligned packed single-precision\r\n VMOVUPS xmm1, xmm2/m128                                                      floating-point from xmm2/mem to xmm1.\r\n VEX.128.0F 11.WIG /r                  MR         V/V            AVX          Move unaligned packed single-precision\r\n VMOVUPS xmm2/m128, xmm1                                                      floating-point from xmm1 to xmm2/mem.\r\n VEX.256.0F 10.WIG /r                  RM         V/V            AVX          Move unaligned packed single-precision\r\n VMOVUPS ymm1, ymm2/m256                                                      floating-point from ymm2/mem to ymm1.\r\n VEX.256.0F 11.WIG /r                  MR         V/V            AVX          Move unaligned packed single-precision\r\n VMOVUPS ymm2/m256, ymm1                                                      floating-point from ymm1 to ymm2/mem.\r\n EVEX.128.0F.W0 10 /r                  FVM-RM     V/V            AVX512VL     Move unaligned packed single-precision\r\n VMOVUPS xmm1 {k1}{z}, xmm2/m128                                 AVX512F      floating-point values from xmm2/m128 to\r\n                                                                              xmm1 using writemask k1.\r\n EVEX.256.0F.W0 10 /r                  FVM-RM     V/V            AVX512VL     Move unaligned packed single-precision\r\n VMOVUPS ymm1 {k1}{z}, ymm2/m256                                 AVX512F      floating-point values from ymm2/m256 to\r\n                                                                              ymm1 using writemask k1.\r\n EVEX.512.0F.W0 10 /r                  FVM-RM     V/V            AVX512F      Move unaligned packed single-precision\r\n VMOVUPS zmm1 {k1}{z}, zmm2/m512                                              floating-point values from zmm2/m512 to\r\n                                                                              zmm1 using writemask k1.\r\n EVEX.128.0F.W0 11 /r                  FVM-MR     V/V            AVX512VL     Move unaligned packed single-precision\r\n VMOVUPS xmm2/m128 {k1}{z}, xmm1                                 AVX512F      floating-point values from xmm1 to\r\n                                                                              xmm2/m128 using writemask k1.\r\n EVEX.256.0F.W0 11 /r                  FVM-MR     V/V            AVX512VL     Move unaligned packed single-precision\r\n VMOVUPS ymm2/m256 {k1}{z}, ymm1                                 AVX512F      floating-point values from ymm1 to\r\n                                                                              ymm2/m256 using writemask k1.\r\n EVEX.512.0F.W0 11 /r                  FVM-MR     V/V            AVX512F      Move unaligned packed single-precision\r\n VMOVUPS zmm2/m512 {k1}{z}, zmm1                                              floating-point values from zmm1 to\r\n                                                                              zmm2/m512 using writemask k1.\r\n\r\n\r\n\r\n                                         Instruction Operand Encoding\r\n       Op/En             Operand 1                Operand 2                     Operand 3                   Operand 4\r\n        RM             ModRM:reg (w)             ModRM:r/m (r)                     NA                           NA\r\n        MR             ModRM:r/m (w)             ModRM:reg (r)                     NA                           NA\r\n      FVM-RM           ModRM:reg (w)             ModRM:r/m (r)                     NA                           NA\r\n      RVM-MR           ModRM:r/m (w)             ModRM:reg (r)                     NA                           NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32\r\nmemory location, to store the contents of a ZMM register into memory. The destination operand is updated\r\naccording to the writemask.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 and EVEX.256 encoded versions:\r\nMoves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\n\r\n\r\n128-bit versions:\r\nMoves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nWhen the source or destination operand is a memory operand, the operand may be unaligned without causing a\r\ngeneral-protection exception (#GP) to be generated.\r\nVEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\nOperation\r\nVMOVUPS (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i] <- SRC[i+31:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPS (EVEX encoded versions, store-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i]<- SRC[i+31:i]\r\n         ELSE *DEST[i+31:i] remains unchanged*           ; merging-masking\r\n    FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVUPS (EVEX encoded versions, load-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN DEST[i+31:i] <- SRC[i+31:i]\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPS (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVUPS (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVUPS (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVUPS (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVUPS (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVUPS __m512 _mm512_loadu_ps( void * s);\r\nVMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);\r\nVMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);\r\nVMOVUPS void _mm512_storeu_ps( void * d, __m512 a);\r\nVMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);\r\nVMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);\r\nVMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);\r\nVMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);\r\nVMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);\r\nVMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);\r\nVMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);\r\nMOVUPS __m256 _mm256_loadu_ps ( float * p);\r\nMOVUPS void _mm256 _storeu_ps( float *p, __m256 a);\r\nMOVUPS __m128 _mm_loadu_ps ( float * p);\r\nMOVUPS void _mm_storeu_ps( float *p, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nNote treatment of #AC varies;\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#UD                      If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVUPS"
    }, 
    {
      "description": "MOVZX-Move with Zero-Extend\r\n Opcode                   Instruction                   Op/    64-Bit      Compat/ Description\r\n                                                        En     Mode        Leg Mode\r\n 0F B6 /r                 MOVZX r16, r/m8               RM     Valid       Valid        Move byte to word with zero-extension.\r\n 0F B6 /r                 MOVZX r32, r/m8               RM     Valid       Valid        Move byte to doubleword, zero-extension.\r\n REX.W + 0F B6 /r         MOVZX r64, r/m8*              RM     Valid       N.E.         Move byte to quadword, zero-extension.\r\n 0F B7 /r                 MOVZX r32, r/m16              RM     Valid       Valid        Move word to doubleword, zero-extension.\r\n REX.W + 0F B7 /r         MOVZX r64, r/m16              RM     Valid       N.E.         Move word to quadword, zero-extension.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En             Operand 1                     Operand 2                       Operand 3                     Operand 4\r\n    RM              ModRM:reg (w)                ModRM:r/m (r)                        NA                             NA\r\n\r\n\r\nDescription\r\nCopies the contents of the source operand (register or memory location) to the destination operand (register) and\r\nzero extends the value. The size of the converted value depends on the operand-size attribute.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart\r\nat the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- ZeroExtend(SRC);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                     If a memory operand effective address is outside the SS segment limit.\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                   If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                If the memory address is in a non-canonical form.\r\n#PF(fault-code)       If a page fault occurs.\r\n#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the\r\n                      current privilege level is 3.\r\n#UD                   If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MOVZX"
    }, 
    {
      "description": "MPSADBW - Compute Multiple Packed Sums of Absolute Difference\r\nOpcode/                                          Op/      64/32-bit CPUID       Description\r\nInstruction        … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "MPSADBW"
    }, 
    {
      "description": "MUL-Unsigned Multiply\r\n Opcode                    Instruction                   Op/   64-Bit          Compat/ Description\r\n                                                         En    Mode            Leg Mode\r\n F6 /4                     MUL r/m8                      M     Valid           Valid         Unsigned multiply (AX <- AL * r/m8).\r\n REX + F6 /4               MUL r/m8*                     M     Valid           N.E.          Unsigned multiply (AX <- AL * r/m8).\r\n F7 /4                     MUL r/m16                     M     Valid           Valid         Unsigned multiply (DX:AX <- AX * r/m16).\r\n F7 /4                     MUL r/m32                     M     Valid           Valid         Unsigned multiply (EDX:EAX <- EAX * r/m32).\r\n REX.W + F7 /4             MUL r/m64                     M     Valid           N.E.          Unsigned multiply (RDX:RAX <- RAX * r/m64).\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En              Operand 1                      Operand 2                           Operand 3                    Operand 4\r\n     M              ModRM:r/m (r)                        NA                                 NA                           NA\r\n\r\n\r\nDescription\r\nPerforms an unsigned multiplication of the first operand (destination operand) and the second operand (source\r\noperand) and stores the result in the destination operand. The destination operand is an implied operand located in\r\nregister AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose\r\nregister or a memory location. The action of this instruction and the location of the result depends on the opcode\r\nand the operand size as shown in Table 4-9.\r\nThe result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size),\r\nwith the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of\r\nthe product are 0, the CF and OF flags are cleared; otherwise, the flags are set.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\n\r\n\r\n                                                     Table 4-9. MUL Results\r\n           Operand Size                       Source 1                                Source 2                      Destination\r\n Byte                             AL                                   r/m8                               AX\r\n Word                             AX                                   r/m16                              DX:AX\r\n Doubleword                       EAX                                  r/m32                              EDX:EAX\r\n Quadword                         RAX                                  r/m64                              RDX:RAX\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF (Byte operation)\r\n    THEN\r\n         AX <- AL * SRC;\r\n    ELSE (* Word or doubleword operation *)\r\n         IF OperandSize = 16\r\n              THEN\r\n                  DX:AX <- AX * SRC;\r\n              ELSE IF OperandSize = 32\r\n                  THEN EDX:EAX <- EAX * SRC; FI;\r\n              ELSE (* OperandSize = 64 *)\r\n                  RDX:RAX <- RAX * SRC;\r\n         FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and\r\nPF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                     If a memory operand effective address is outside the SS segment limit.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                     If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                  If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                  If the memory address is in a non-canonical form.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n\r\n\r\n", 
      "mnem": "MUL"
    }, 
    {
      "description": "MULPD-Multiply Packed Double-Precision Floating-Point Values\r\n Opcode/                                Op /    64/32        CPUID      Description\r\n Instruction                            En      bit Mode     Feature\r\n                                                Support      Flag\r\n 66 0F 59 /r                            RM      V/V          SSE2       Multiply packed double-precision floating-point values\r\n MULPD xmm1, xmm2/m128                                                  in xmm2/m128 with xmm1 and store result in xmm1.\r\n VEX.NDS.128.66.0F.WIG 59 /r            RVM     V/V          AVX        Multiply packed double-precision floating-point values\r\n VMULPD xmm1,xmm2, xmm3/m128                                            in xmm3/m128 with xmm2 and store result in xmm1.\r\n VEX.NDS.256.66.0F.WIG 59 /r            RVM     V/V          AVX        Multiply packed double-precision floating-point values\r\n VMULPD ymm1, ymm2, ymm3/m256                                           in ymm3/m256 with ymm2 and store result in ymm1.\r\n EVEX.NDS.128.66.0F.W1 59 /r            FV      V/V          AVX512VL   Multiply packed double-precision floating-point values\r\n VMULPD xmm1 {k1}{z}, xmm2,                                  AVX512F    from xmm3/m128/m64bcst to xmm2 and store result\r\n xmm3/m128/m64bcst                                                      in xmm1.\r\n EVEX.NDS.256.66.0F.W1 59 /r            FV      V/V          AVX512VL   Multiply packed double-precision floating-point values\r\n VMULPD ymm1 {k1}{z}, ymm2,                                  AVX512F    from ymm3/m256/m64bcst to ymm2 and store result\r\n ymm3/m256/m64bcst                                                      in ymm1.\r\n EVEX.NDS.512.66.0F.W1 59 /r            FV      V/V          AVX512F    Multiply packed double-precision floating-point values\r\n VMULPD zmm1 {k1}{z}, zmm2,                                             in zmm3/m512/m64bcst with zmm2 and store result\r\n zmm3/m512/m64bcst{er}                                                  in zmm1.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n      Op/En             Operand 1                      Operand 2                Operand 3                      Operand 4\r\n        RM           ModRM:reg (r, w)                 ModRM:r/m (r)                 NA                            NA\r\n       RVM            ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                       NA\r\n        FV            ModRM:reg (w)                   EVEX.vvvv (r)           ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nMultiply packed double-precision floating-point values from the first source operand with corresponding values in\r\nthe second source operand, and stores the packed double-precision floating-point results in the destination\r\noperand.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the\r\ncorresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the destination YMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+63:i] <- SRC1[i+63:i] * SRC2[63:0]\r\n                    ELSE\r\n                         DEST[i+63:i] <- SRC1[i+63:i] * SRC2[i+63:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                            ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMULPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] * SRC2[127:64]\r\nDEST[191:128] <-SRC1[191:128] * SRC2[191:128]\r\nDEST[255:192] <-SRC1[255:192] * SRC2[255:192]\r\nDEST[MAX_VL-1:256] <-0;\r\n.\r\nVMULPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] * SRC2[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] * SRC[63:0]\r\nDEST[127:64] <-DEST[127:64] * SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_mul_round_pd( __m512d a, __m512d b, int);\r\nVMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);\r\nMULPD __m128d _mm_mul_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MULPD"
    }, 
    {
      "description": "MULPS-Multiply Packed Single-Precision Floating-Point Values\r\n Opcode/                                     Op /     64/32         CPUID      Description\r\n Instruction                                 En       bit Mode      Feature\r\n                                                      Support       Flag\r\n 0F 59 /r                                    RM       V/V           SSE        Multiply packed single-precision floating-point values in\r\n MULPS xmm1, xmm2/m128                                                         xmm2/m128 with xmm1 and store result in xmm1.\r\n VEX.NDS.128.0F.WIG 59 /r                    RVM      V/V           AVX        Multiply packed single-precision floating-point values in\r\n VMULPS xmm1,xmm2, xmm3/m128                                                   xmm3/m128 with xmm2 and store result in xmm1.\r\n VEX.NDS.256.0F.WIG 59 /r                    RVM      V/V           AVX        Multiply packed single-precision floating-point values in\r\n VMULPS ymm1, ymm2, ymm3/m256                                                  ymm3/m256 with ymm2 and store result in ymm1.\r\n EVEX.NDS.128.0F.W0 59 /r                    FV       V/V           AVX512VL   Multiply packed single-precision floating-point values\r\n VMULPS xmm1 {k1}{z}, xmm2,                                         AVX512F    from xmm3/m128/m32bcst to xmm2 and store result in\r\n xmm3/m128/m32bcst                                                             xmm1.\r\n EVEX.NDS.256.0F.W0 59 /r                    FV       V/V           AVX512VL   Multiply packed single-precision floating-point values\r\n VMULPS ymm1 {k1}{z}, ymm2,                                         AVX512F    from ymm3/m256/m32bcst to ymm2 and store result in\r\n ymm3/m256/m32bcst                                                             ymm1.\r\n EVEX.NDS.512.0F.W0 59 /r                    FV       V/V           AVX512F    Multiply packed single-precision floating-point values in\r\n VMULPS zmm1 {k1}{z}, zmm2,                                                    zmm3/m512/m32bcst with zmm2 and store result in\r\n zmm3/m512/m32bcst {er}                                                        zmm1.\r\n\r\n\r\n\r\n                                                     Instruction Operand Encoding\r\n        Op/En                   Operand 1                       Operand 2                Operand 3                   Operand 4\r\n          RM                 ModRM:reg (r, w)                  ModRM:r/m (r)                 NA                          NA\r\n         RVM                  ModRM:reg (w)                    VEX.vvvv (r)            ModRM:r/m (r)                     NA\r\n          FV                  ModRM:reg (w)                    EVEX.vvvv (r)           ModRM:r/m (r)                     NA\r\n\r\nDescription\r\nMultiply the packed single-precision floating-point values from the first source operand with the corresponding\r\nvalues in the second source operand, and stores the packed double-precision floating-point results in the destina-\r\ntion operand.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the\r\ncorresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the destination YMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULPS (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- SRC1[i+31:i] * SRC2[31:0]\r\n                    ELSE\r\n                         DEST[i+31:i] <- SRC1[i+31:i] * SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                            ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMULPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[159:128] <-SRC1[159:128] * SRC2[159:128]\r\nDEST[191:160]<-SRC1[191:160] * SRC2[191:160]\r\nDEST[223:192] <-SRC1[223:192] * SRC2[223:192]\r\nDEST[255:224] <-SRC1[255:224] * SRC2[255:224].\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVMULPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULPS __m512 _mm512_mul_ps( __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_mask_mul_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_maskz_mul_ps(__mmask16 k, __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_mul_round_ps( __m512 a, __m512 b, int);\r\nVMULPS __m512 _mm512_mask_mul_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMULPS __m512 _mm512_maskz_mul_round_ps(__mmask16 k, __m512 a, __m512 b, int);\r\nVMULPS __m256 _mm256_mask_mul_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMULPS __m256 _mm256_maskz_mul_ps(__mmask8 k, __m256 a, __m256 b);\r\nVMULPS __m128 _mm_mask_mul_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMULPS __m128 _mm_maskz_mul_ps(__mmask8 k, __m128 a, __m128 b);\r\nVMULPS __m256 _mm256_mul_ps (__m256 a, __m256 b);\r\nMULPS __m128 _mm_mul_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MULPS"
    }, 
    {
      "description": "MULSD-Multiply Scalar Double-Precision Floating-Point Value\r\n Opcode/                                Op /    64/32       CPUID     Description\r\n Instruction                            En      bit Mode    Feature\r\n                                                Support     Flag\r\n F2 0F 59 /r                            RM      V/V         SSE2      Multiply the low double-precision floating-point value in\r\n MULSD xmm1,xmm2/m64                                                  xmm2/m64 by low double-precision floating-point\r\n                                                                      value in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 59 /r            RVM     V/V         AVX       Multiply the low double-precision floating-point value in\r\n VMULSD xmm1,xmm2, xmm3/m64                                           xmm3/m64 by low double-precision floating-point\r\n                                                                      value in xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 59 /r            T1S     V/V         AVX512F   Multiply the low double-precision floating-point value in\r\n VMULSD xmm1 {k1}{z}, xmm2,                                           xmm3/m64 by low double-precision floating-point\r\n xmm3/m64 {er}                                                        value in xmm2.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n       Op/En              Operand 1                    Operand 2               Operand 3                     Operand 4\r\n        RM             ModRM:reg (r, w)               ModRM:r/m (r)                 NA                           NA\r\n       RVM              ModRM:reg (w)                 VEX.vvvv (r)            ModRM:r/m (r)                      NA\r\n        T1S             ModRM:reg (w)                 EVEX.vvvv (r)           ModRM:r/m (r)                      NA\r\n\r\nDescription\r\nMultiplies the low double-precision floating-point value in the second source operand by the low double-precision\r\nfloating-point value in the first source operand, and stores the double-precision floating-point result in the destina-\r\ntion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source\r\noperand and the destination operands are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:64) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the\r\nsame bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[63:0] <- SRC1[63:0] * SRC2[63:0]\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[63:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[63:0] <- 0\r\n              FI\r\n    FI;\r\nENDFOR\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMULSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] * SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULSD __m128d _mm_mask_mul_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMULSD __m128d _mm_maskz_mul_sd( __mmask8 k, __m128d a, __m128d b);\r\nVMULSD __m128d _mm_mul_round_sd( __m128d a, __m128d b, int);\r\nVMULSD __m128d _mm_mask_mul_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMULSD __m128d _mm_maskz_mul_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMULSD __m128d _mm_mul_sd (__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MULSD"
    }, 
    {
      "description": "MULSS-Multiply Scalar Single-Precision Floating-Point Values\r\n Opcode/                              Op /   64/32       CPUID      Description\r\n Instruction                          En     bit Mode    Feature\r\n                                             Support     Flag\r\n F3 0F 59 /r                          RM     V/V         SSE        Multiply the low single-precision floating-point value in\r\n MULSS xmm1,xmm2/m32                                                xmm2/m32 by the low single-precision floating-point\r\n                                                                    value in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 59 /r          RVM    V/V         AVX        Multiply the low single-precision floating-point value in\r\n VMULSS xmm1,xmm2, xmm3/m32                                         xmm3/m32 by the low single-precision floating-point\r\n                                                                    value in xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 59 /r          T1S    V/V         AVX512F    Multiply the low single-precision floating-point value in\r\n VMULSS xmm1 {k1}{z}, xmm2,                                         xmm3/m32 by the low single-precision floating-point\r\n xmm3/m32 {er}                                                      value in xmm2.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n       Op/En              Operand 1                 Operand 2                 Operand 3                     Operand 4\r\n        RM             ModRM:reg (r, w)            ModRM:r/m (r)                  NA                            NA\r\n        RVM             ModRM:reg (w)              VEX.vvvv (r)             ModRM:r/m (r)                       NA\r\n        T1S             ModRM:reg (w)              EVEX.vvvv (r)            ModRM:r/m (r)                       NA\r\n\r\nDescription\r\nMultiplies the low single-precision floating-point value from the second source operand by the low single-precision\r\nfloating-point value in the first source operand, and stores the single-precision floating-point result in the destina-\r\ntion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source\r\noperand and the destination operands are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three\r\nhigh-order doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULSS (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n    THEN\r\n         SET_RM(EVEX.RC);\r\n    ELSE\r\n         SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n    THEN      DEST[31:0] <- SRC1[31:0] * SRC2[31:0]\r\n    ELSE\r\n         IF *merging-masking*               ; merging-masking\r\n              THEN *DEST[31:0] remains unchanged*\r\n              ELSE                          ; zeroing-masking\r\n                  THEN DEST[31:0] <- 0\r\n              FI\r\n    FI;\r\nENDFOR\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMULSS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] * SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);\r\nVMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);\r\nVMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMULSS __m128 _mm_mul_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nUnderflow, Overflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MULSS"
    }, 
    {
      "description": "MULX - Unsigned Multiply Without Affecting Flags\r\n Opcode/                         Op/    64/32    CPUID     Description\r\n Instruction                     En     -bit     Feature\r\n                                        Mode     Flag\r\n VEX.NDD.LZ.F2.0F38.W0 F6 /r     RVM    V/V      BMI2      Unsigned multiply of r/m32 with EDX without affecting arithmetic\r\n MULX r32a, r32b, r/m32                                    flags.\r\n VEX.NDD.LZ.F2.0F38.W1 F6 /r     RVM    V/N.E.   BMI2      Unsigned multiply of r/m64 with RDX without affecting arithmetic\r\n MULX r64a, r64b, r/m64                                    flags.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n  Op/En           Operand 1                  Operand 2                    Operand 3                       Operand 4\r\n                                                                                                RDX/EDX is implied 64/32 bits\r\n   RVM           ModRM:reg (w)              VEX.vvvv (w)                 ModRM:r/m (r)\r\n                                                                                                           source\r\n\r\n\r\nDescription\r\nPerforms an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand\r\n(the third operand) and stores the low half of the result in the second destination (second operand), the high half\r\nof the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This\r\nenables efficient programming where the software can interleave add with carry operations and multiplications.\r\nIf the first and second operand are identical, it will contain the high half of the multiplication result.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\n// DEST1: ModRM:reg\r\n// DEST2: VEX.vvvv\r\nIF (OperandSize = 32)\r\n    SRC1 <- EDX;\r\n    DEST2 <- (SRC1*SRC2)[31:0];\r\n    DEST1 <- (SRC1*SRC2)[63:32];\r\nELSE IF (OperandSize = 64)\r\n    SRC1 <- RDX;\r\n         DEST2 <- (SRC1*SRC2)[63:0];\r\n         DEST1 <- (SRC1*SRC2)[127:64];\r\nFI\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language when possible.\r\nunsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);\r\nunsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD                      If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MULX"
    }, 
    {
      "description": "MWAIT-Monitor Wait\r\n Opcode                Instruction              Op/   64-Bit     Compat/ Description\r\n                                                En    Mode       Leg Mode\r\n 0F 01 C9              MWAIT                    NP    Valid      Valid      A hint that allow the processor to stop\r\n                                                                            instruction execution and enter an\r\n                                                                            implementation-dependent optimized state\r\n                                                                            until occurrence of a class of events.\r\n\r\n\r\n\r\n                                           Instruction Operand Encoding\r\n   Op/En           Operand 1                 Operand 2                   Operand 3                  Operand 4\r\n    NP                NA                        NA                          NA                         NA\r\n\r\n\r\nDescription\r\nMWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state.\r\nThere are two principal targeted usages: address-range monitor and advanced power management. Both usages\r\nof MWAIT require the use of the MONITOR instruction.\r\nCPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,\r\nMWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode\r\nexception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE\r\nMSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-\r\ntion.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized\r\nstate the processor should enter. The first processors to implement MWAIT supported only the zero value for EAX\r\nand ECX. Later processors allowed setting ECX[0] to enable masked interrupts as break events for MWAIT (see\r\nbelow). Software can use the CPUID instruction to determine the extensions and hints supported by the processor.\r\n\r\nMWAIT for Address Range Monitoring\r\nFor address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions\r\nallow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized opera-\r\ntion to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter\r\nan implementation-dependent-optimized state while waiting for an event or a store operation to the address range\r\narmed by MONITOR.\r\nThe following cause the processor to exit the implementation-dependent-optimized state: a store to the address\r\nrange armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the\r\nBINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause\r\nthe processor to exit the implementation-dependent-optimized state.\r\nIn addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state\r\neither (1) if the interrupt would be delivered to software (e.g., as it would be if HLT had been executed instead of\r\nMWAIT); or (2) if ECX[0] = 1. Software can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1.\r\n(Implementation-specific conditions may result in an interrupt causing the processor to exit the implementation-\r\ndependent-optimized state even if interrupts are masked and ECX[0] = 0.)\r\nFollowing exit from the implementation-dependent-optimized state, control passes to the instruction following the\r\nMWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before\r\nexecution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the\r\nMWAIT instruction following the handling of an SMI.\r\nIf the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has\r\nnot been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-opti-\r\nmized state. Execution will resume at the instruction following the MWAIT.\r\n\r\n\r\n\r\n\r\n\r\nMWAIT for Power Management\r\nMWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while\r\nwaiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions\r\nfor power management is indicated by CPUID.05H:ECX[bit 0] reporting 1.\r\nEAX and ECX are used to communicate the additional information to the MWAIT instruction, such as the kind of\r\noptimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may\r\ncontain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions\r\nmay cause a processor to ignore the hint and enter a different optimized state. Future processor implementations\r\nmay implement several optimized \"waiting\" states and will select among those states based on the hint argument.\r\nTable 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.\r\n\r\n\r\n                                         Table 4-10. MWAIT Extension Register (ECX)\r\n         Bits                                                             Description\r\n 0                     Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if\r\n                       CPUID.05H:ECX[bit 1] = 1.\r\n 31: 1                 Reserved\r\n\r\n\r\n\r\n                                           Table 4-11. MWAIT Hints Register (EAX)\r\n         Bits                                                             Description\r\n 3:0                   Sub C-state within a C-state, indicated by bits [7:4]\r\n 7:4                   Target C-state*\r\n                       Value of 0 means C1; 1 means C2 and so on\r\n                       Value of 01111B means C0\r\n\r\n\r\n                       Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states\r\n 31: 8                 Reserved\r\n\r\nNote that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address\r\nrange armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by\r\nother processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such\r\ncases.\r\nFor additional details of MWAIT extensions, see Chapter 14, \"Power and Thermal Management,\" of Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\nOperation\r\n(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension\r\nMWAIT EAX, ECX *)\r\n{\r\nWHILE ( (\"Monitor Hardware is in armed state\")) {\r\n    implementation_dependent_optimized_state(EAX, ECX); }\r\nSet the state of Monitor Hardware as triggered;\r\n}\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMWAIT:          void _mm_mwait(unsigned extensions, unsigned hints)\r\n\r\n\r\n\r\n\r\n\r\nExample\r\nMONITOR/MWAIT instruction pair must be coded in the same loop because execution of the MWAIT instruction will\r\ntrigger the monitor hardware. It is not a proper usage to execute MONITOR once and then execute MWAIT in a\r\nloop. Setting up MONITOR without executing MWAIT has no adverse effects.\r\nTypically the MONITOR/MWAIT pair is used in a sequence, such as:\r\n\r\nEAX = Logical Address(Trigger)\r\nECX = 0 (*Hints *)\r\nEDX = 0 (* Hints *)\r\n\r\nIF ( !trigger_store_happened) {\r\n     MONITOR EAX, ECX, EDX\r\n     IF ( !trigger_store_happened ) {\r\n            MWAIT EAX, ECX\r\n     }\r\n}\r\nThe above code sequence makes sure that a triggering store does not happen between the first check of the trigger\r\nand the execution of the monitor instruction. Without the second check that triggering store would go un-noticed.\r\nTypical usage of MONITOR and MWAIT would have the above code sequence within a loop.\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                   If ECX[31:1] != 0.\r\n                         If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD                      If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n                         If current privilege level is not 0.\r\n\r\nReal Address Mode Exceptions\r\n#GP                      If ECX[31:1] != 0.\r\n                         If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD                      If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#UD                      The MWAIT instruction is not recognized in virtual-8086 mode (even if\r\n                         CPUID.01H:ECX.MONITOR[bit 3] = 1).\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0)                   If RCX[63:1] != 0.\r\n                         If RCX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD                      If the current privilege level is not 0.\r\n                         If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "MWAIT"
    }, 
    {
      "description": "NEG-Two's Complement Negation\r\n Opcode                   Instruction                   Op/   64-Bit       Compat/ Description\r\n                                                        En    Mode         Leg Mode\r\n F6 /3                    NEG r/m8                      M     Valid        Valid       Two's complement negate r/m8.\r\n REX + F6 /3              NEG r/m8*                     M     Valid        N.E.        Two's complement negate r/m8.\r\n F7 /3                    NEG r/m16                     M     Valid        Valid       Two's complement negate r/m16.\r\n F7 /3                    NEG r/m32                     M     Valid        Valid       Two's complement negate r/m32.\r\n REX.W + F7 /3            NEG r/m64                     M     Valid        N.E.        Two's complement negate r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n  Op/En              Operand 1                      Operand 2                      Operand 3                      Operand 4\r\n     M            ModRM:r/m (r, w)                      NA                             NA                             NA\r\n\r\n\r\nDescription\r\nReplaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent\r\nto subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory\r\nlocation.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF DEST = 0\r\n    THEN CF <- 0;\r\n    ELSE CF <- 1;\r\nFI;\r\nDEST <- [- (DEST)]\r\n\r\nFlags Affected\r\nThe CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set\r\naccording to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the destination is located in a non-writable segment.\r\n                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                 If a memory operand effective address is outside the SS segment limit.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)              If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)     If a page fault occurs.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)              If the memory address is in a non-canonical form.\r\n#PF(fault-code)     For a page fault.\r\n#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the\r\n                    current privilege level is 3.\r\n#UD                 If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "NEG"
    }, 
    {
      "description": "NOP-No Operation\r\n Opcode                  Instruction                 Op/     64-Bit   Compat/ Description\r\n                                                     En      Mode     Leg Mode\r\n 90                      NOP                         NP      Valid    Valid       One byte no-operation instruction.\r\n 0F 1F /0                NOP r/m16                   M       Valid    Valid       Multi-byte no-operation instruction.\r\n 0F 1F /0                NOP r/m32                   M       Valid    Valid       Multi-byte no-operation instruction.\r\n\r\n\r\n\r\n                                             Instruction Operand Encoding\r\n     Op/En          Operand 1                    Operand 2                    Operand 3                     Operand 4\r\n      NP                NA                           NA                          NA                             NA\r\n       M           ModRM:r/m (r)                     NA                          NA                             NA\r\n\r\n\r\nDescription\r\nThis instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction\r\nstream but does not impact machine context, except for the EIP register.\r\nThe multi-byte form of NOP is available on processors with model encoding:\r\n.     CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B\r\nThe multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The\r\ninstruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nThe one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.\r\nThe multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode\r\nexception on processors that do not support the multi-byte NOP instruction.\r\nThe memory operand form of the instruction allows software to create a byte sequence of \"no operation\" as one\r\ninstruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and\r\n64-bit mode) are:\r\n\r\n\r\n                         Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction\r\n    Length           Assembly                                                         Byte Sequence\r\n    2 bytes          66 NOP                                                           66 90H\r\n    3 bytes          NOP DWORD ptr [EAX]                                              0F 1F 00H\r\n    4 bytes          NOP DWORD ptr [EAX + 00H]                                        0F 1F 40 00H\r\n    5 bytes          NOP DWORD ptr [EAX + EAX*1 + 00H]                                0F 1F 44 00 00H\r\n    6 bytes          66 NOP DWORD ptr [EAX + EAX*1 + 00H]                             66 0F 1F 44 00 00H\r\n    7 bytes          NOP DWORD ptr [EAX + 00000000H]                                  0F 1F 80 00 00 00 00H\r\n    8 bytes          NOP DWORD ptr [EAX + EAX*1 + 00000000H]                          0F 1F 84 00 00 00 00 00H\r\n    9 bytes          66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]                       66 0F 1F 84 00 00 00 00 00H\r\n\r\n\r\nFlags Affected\r\nNone\r\n\r\nExceptions (All Operating Modes)\r\n#UD                    If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "NOP"
    }, 
    {
      "description": "NOT-One's Complement Negation\r\n Opcode                    Instruction                  Op/    64-Bit      Compat/ Description\r\n                                                        En     Mode        Leg Mode\r\n F6 /2                     NOT r/m8                     M      Valid       Valid        Reverse each bit of r/m8.\r\n REX + F6 /2               NOT r/m8*                    M      Valid       N.E.         Reverse each bit of r/m8.\r\n F7 /2                     NOT r/m16                    M      Valid       Valid        Reverse each bit of r/m16.\r\n F7 /2                     NOT r/m32                    M      Valid       Valid        Reverse each bit of r/m32.\r\n REX.W + F7 /2             NOT r/m64                    M      Valid       N.E.         Reverse each bit of r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En             Operand 1                     Operand 2                       Operand 3                        Operand 4\r\n      M           ModRM:r/m (r, w)                     NA                             NA                               NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores\r\nthe result in the destination operand location. The destination operand can be a register or a memory location.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- NOT DEST;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                  If the destination operand points to a non-writable segment.\r\n                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                        If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                  If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)         If a page fault occurs.\r\n#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the\r\n                        current privilege level is 3.\r\n#UD                     If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                     If a memory operand effective address is outside the SS segment limit.\r\n#UD                     If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                 If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                 If the memory address is in a non-canonical form.\r\n#PF(fault-code)        If a page fault occurs.\r\n#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the\r\n                       current privilege level is 3.\r\n#UD                    If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "NOT"
    }, 
    {
      "description": "OR-Logical Inclusive OR\r\n Opcode                    Instruction                  Op/     64-Bit      Compat/ Description\r\n                                                        En      Mode        Leg Mode\r\n 0C ib                     OR AL, imm8                  I       Valid       Valid       AL OR imm8.\r\n 0D iw                     OR AX, imm16                 I       Valid       Valid       AX OR imm16.\r\n 0D id                     OR EAX, imm32                I       Valid       Valid       EAX OR imm32.\r\n REX.W + 0D id             OR RAX, imm32                I       Valid       N.E.        RAX OR imm32 (sign-extended).\r\n 80 /1 ib                  OR r/m8, imm8                MI      Valid       Valid       r/m8 OR imm8.\r\n REX + 80 /1 ib            OR r/m8*, imm8               MI      Valid       N.E.        r/m8 OR imm8.\r\n 81 /1 iw                  OR r/m16, imm16              MI      Valid       Valid        r/m16 OR imm16.\r\n 81 /1 id                  OR r/m32, imm32              MI      Valid       Valid        r/m32 OR imm32.\r\n REX.W + 81 /1 id          OR r/m64, imm32              MI      Valid       N.E.         r/m64 OR imm32 (sign-extended).\r\n 83 /1 ib                  OR r/m16, imm8               MI      Valid       Valid       r/m16 OR imm8 (sign-extended).\r\n 83 /1 ib                  OR r/m32, imm8               MI      Valid       Valid       r/m32 OR imm8 (sign-extended).\r\n REX.W + 83 /1 ib          OR r/m64, imm8               MI      Valid       N.E.        r/m64 OR imm8 (sign-extended).\r\n 08 /r                     OR r/m8, r8                  MR      Valid       Valid       r/m8 OR r8.\r\n REX + 08 /r               OR r/m8*, r8*                MR      Valid       N.E.        r/m8 OR r8.\r\n 09 /r                     OR r/m16, r16                MR      Valid       Valid       r/m16 OR r16.\r\n 09 /r                     OR r/m32, r32                MR      Valid       Valid       r/m32 OR r32.\r\n REX.W + 09 /r             OR r/m64, r64                MR      Valid       N.E.        r/m64 OR r64.\r\n 0A /r                     OR r8, r/m8                  RM      Valid       Valid       r8 OR r/m8.\r\n REX + 0A /r               OR r8*, r/m8*                RM      Valid       N.E.        r8 OR r/m8.\r\n 0B /r                     OR r16, r/m16                RM      Valid       Valid       r16 OR r/m16.\r\n 0B /r                     OR r32, r/m32                RM      Valid       Valid       r32 OR r/m32.\r\n REX.W + 0B /r             OR r64, r/m64                RM      Valid       N.E.        r64 OR r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n   Op/En               Operand 1                    Operand 2                       Operand 3                     Operand 4\r\n     I              AL/AX/EAX/RAX                  imm8/16/32                          NA                             NA\r\n    MI              ModRM:r/m (r, w)               imm8/16/32                          NA                             NA\r\n    MR              ModRM:r/m (r, w)               ModRM:reg (r)                       NA                             NA\r\n    RM              ModRM:reg (r, w)               ModRM:r/m (r)                       NA                             NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores\r\nthe result in the destination operand location. The source operand can be an immediate, a register, or a memory\r\nlocation; the destination operand can be a register or a memory location. (However, two memory operands cannot\r\nbe used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the\r\nfirst and second operands are 0; otherwise, each bit is set to 1.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\n\r\n\r\n\r\n\r\n\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST OR SRC;\r\n\r\nFlags Affected\r\nThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                    If the destination operand points to a non-writable segment.\r\n                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n                          If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0)                    If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)           If a page fault occurs.\r\n#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the\r\n                          current privilege level is 3.\r\n#UD                       If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS                       If a memory operand effective address is outside the SS segment limit.\r\n#UD                       If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0)                    If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code)           If a page fault occurs.\r\n#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD                       If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0)                    If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0)                    If the memory address is in a non-canonical form.\r\n#PF(fault-code)           If a page fault occurs.\r\n#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the\r\n                          current privilege level is 3.\r\n#UD                       If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "OR"
    }, 
    {
      "description": "ORPD-Bitwise Logical OR of Packed Double Precision Floating-Point Values\r\n Opcode/                            Op /      64/32      CPUID           Description\r\n Instruction                        En        bit Mode   Feature\r\n                                              Support    Flag\r\n 66 0F 56/r                         RM        V/V        SSE2            Return the bitwise logical OR of packed double-precision\r\n ORPD xmm1, xmm2/m128                                                    floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 56 /r            RVM       V/V        AVX             Return the bitwise logical OR of packed double-precision\r\n VORPD xmm1,xmm2, xmm3/m128                                              floating-point values in xmm2 and xmm3/mem.\r\n VEX.NDS.256.66.0F 56 /r            RVM       V/V        AVX             Return the bitwise logical OR of packed double-precision\r\n VORPD ymm1, ymm2, ymm3/m256                                             floating-point values in ymm2 and ymm3/mem.\r\n EVEX.NDS.128.66.0F.W1 56 /r        FV        V/V        AVX512VL        Return the bitwise logical OR of packed double-precision\r\n VORPD xmm1 {k1}{z}, xmm2,                               AVX512DQ        floating-point values in xmm2 and xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst                                                       subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 56 /r        FV        V/V        AVX512VL        Return the bitwise logical OR of packed double-precision\r\n VORPD ymm1 {k1}{z}, ymm2,                               AVX512DQ        floating-point values in ymm2 and ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst                                                       subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 56 /r        FV        V/V        AVX512DQ        Return the bitwise logical OR of packed double-precision\r\n VORPD zmm1 {k1}{z}, zmm2,                                               floating-point values in zmm2 and zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst                                                       subject to writemask k1.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n          Op/En               Operand 1                    Operand 2                       Operand 3                 Operand 4\r\n              RM           ModRM:reg (r, w)              ModRM:r/m (r)                         NA                        NA\r\n           RVM              ModRM:reg (w)                 VEX.vvvv (r)                   ModRM:r/m (r)                   NA\r\n              FV            ModRM:reg (w)                EVEX.vvvv (r)                   ModRM:r/m (r)                   NA\r\n\r\nDescription\r\nPerforms a bitwise logical OR of the two, four or eight packed double-precision floating-point values from the first\r\nsource operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVORPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n   i <- j * 64\r\n   IF k1[j] OR *no writemask*\r\n        THEN\r\n             IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                  THEN\r\n                       DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[63:0]\r\n                  ELSE\r\n                       DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[i+63:i]\r\n             FI;\r\n        ELSE\r\n             IF *merging-masking*                 ; merging-masking\r\n                  THEN *DEST[i+63:i] remains unchanged*\r\n                  ELSE *zeroing-masking*               ; zeroing-masking\r\n                       DEST[i+63:i] <- 0\r\n             FI\r\n   FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVORPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] BITWISE OR SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] BITWISE OR SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVORPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nORPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] BITWISE OR SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVORPD __m512d _mm512_or_pd ( __m512d a, __m512d b);\r\nVORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);\r\nVORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);\r\nVORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);\r\nVORPD __m128d _mm_mask_or_pd ( __m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVORPD __m128d _mm_maskz_or_pd (__mmask8 k, __m128d a, __m128d b);\r\nVORPD __m256d _mm256_or_pd (__m256d a, __m256d b);\r\nORPD __m128d _mm_or_pd (__m128d a, __m128d b);\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ORPD"
    }, 
    {
      "description": "ORPS-Bitwise Logical OR of Packed Single Precision Floating-Point Values\r\n Opcode/                                   Op /      64/32        CPUID        Description\r\n Instruction                               En        bit Mode     Feature\r\n                                                     Support      Flag\r\n 0F 56 /r                                  RM        V/V          SSE          Return the bitwise logical OR of packed single-precision\r\n ORPS xmm1, xmm2/m128                                                          floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 56 /r                      RVM       V/V           AVX         Return the bitwise logical OR of packed single-precision\r\n VORPS xmm1,xmm2, xmm3/m128                                                    floating-point values in xmm2 and xmm3/mem.\r\n VEX.NDS.256.0F 56 /r                      RVM       V/V           AVX         Return the bitwise logical OR of packed single-precision\r\n VORPS ymm1, ymm2, ymm3/m256                                                   floating-point values in ymm2 and ymm3/mem.\r\n EVEX.NDS.128.0F.W0 56 /r                  FV        V/V          AVX512VL     Return the bitwise logical OR of packed single-precision\r\n VORPS xmm1 {k1}{z}, xmm2,                                        AVX512DQ     floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst                                                             subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 56 /r                  FV        V/V          AVX512VL     Return the bitwise logical OR of packed single-precision\r\n VORPS ymm1 {k1}{z}, ymm2,                                        AVX512DQ     floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst                                                             subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 56 /r                  FV        V/V           AVX512DQ    Return the bitwise logical OR of packed single-precision\r\n VORPS zmm1 {k1}{z}, zmm2,                                                     floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst                                                             subject to writemask k1.\r\n\r\n\r\n\r\n                                                      Instruction Operand Encoding\r\n        Op/En                    Operand 1                      Operand 2                 Operand 3                   Operand 4\r\n          RM                 ModRM:reg (r, w)                 ModRM:r/m (r)                   NA                         NA\r\n         RVM                   ModRM:reg (w)                    VEX.vvvv (r)            ModRM:r/m (r)                    NA\r\n          FV                   ModRM:reg (w)                  EVEX.vvvv (r)             ModRM:r/m (r)                    NA\r\n\r\nDescription\r\nPerforms a bitwise logical OR of the four, eight or sixteen packed single-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVORPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n                    THEN\r\n                         DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[31:0]\r\n                    ELSE\r\n                         DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                 ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE *zeroing-masking*               ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVORPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] BITWISE OR SRC2[159:128]\r\nDEST[191:160] <- SRC1[191:160] BITWISE OR SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] BITWISE OR SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] BITWISE OR SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVORPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nORPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);\r\nVORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);\r\nVORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);\r\nVORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);\r\nVORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);\r\nVORPS __m256 _mm256_or_ps (__m256 a, __m256 b);\r\nORPS __m128 _mm_or_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "ORPS"
    }, 
    {
      "description": "OUT-Output to Port\r\n Opcode*                  Instruction                    Op/   64-Bit   Compat/ Description\r\n                                                         En    Mode     Leg Mode\r\n E6 ib                    OUT imm8, AL                   I     Valid    Valid       Output byte in AL to I/O port address imm8.\r\n E7 ib                    OUT imm8, AX                   I     Valid    Valid       Output word in AX to I/O port address imm8.\r\n E7 ib                    OUT imm8, EAX                  I     Valid    Valid       Output doubleword in EAX to I/O port address\r\n                                                                                    imm8.\r\n EE                       OUT DX, AL                     NP    Valid    Valid       Output byte in AL to I/O port address in DX.\r\n EF                       OUT DX, AX                     NP    Valid    Valid       Output word in AX to I/O port address in DX.\r\n EF                       OUT DX, EAX                    NP    Valid    Valid       Output doubleword in EAX to I/O port address\r\n                                                                                    in DX.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n                                                 Instruction Operand Encoding\r\n  Op/En              Operand 1                     Operand 2                    Operand 3                     Operand 4\r\n      I                imm8                              NA                        NA                            NA\r\n      NP                NA                               NA                        NA                            NA\r\n\r\n\r\nDescription\r\nCopies the value from the second operand (source operand) to the I/O port specified with the destination operand\r\n(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being\r\naccessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.\r\nUsing a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source\r\noperand allows I/O ports from 0 to 65,535 to be accessed.\r\nThe size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size\r\nattribute of the instruction for a 16- or 32-bit I/O port.\r\nAt the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits\r\nof the port address will be 0.\r\nThis instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 18,\r\n\"Input/Output,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more infor-\r\nmation on accessing I/O ports in the I/O address space.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nAfter executing an OUT instruction, the Pentium processor ensures that the EWBE# pin has been sampled active\r\nbefore it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,\r\nbut it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the\r\nEWBE# pin.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n     THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n         IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n              THEN (* I/O operation is not allowed *)\r\n                   #GP(0);\r\n              ELSE ( * I/O operation is allowed *)\r\n                   DEST <- SRC; (* Writes to selected I/O port *)\r\n         FI;\r\n     ELSE (Real Mode or Protected Mode with CPL <= IOPL *)\r\n         DEST <- SRC; (* Writes to selected I/O port *)\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0)                 If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n                       corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD                    If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0)                 If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code)        If a page fault occurs.\r\n#UD                    If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\nSame as protected mode exceptions.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "OUT"
    }, 
    {
      "description": "OUTS/OUTSB/OUTSW/OUTSD-Output String to Port\r\n Opcode*                   Instruction                   Op/    64-Bit       Compat/ Description\r\n                               … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "OUTS"
    }, 
    {
      "description": "-R:OUTS", 
      "mnem": "OUTSB"
    }, 
    {
      "description": "-R:OUTS", 
      "mnem": "OUTSD"
    }, 
    {
      "description": "-R:OUTS", 
      "mnem": "OUTSW"
    }, 
    {
      "description": "PABSB/PABSW/PABSD/PABSQ - Packed Absolute Value\r\nOpcode/                          Op/   64/32 bit   CPUID        Description\r\nInstruction                      En    Mode      … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PABSB"
    }, 
    {
      "description": "-R:PABSB", 
      "mnem": "PABSD"
    }, 
    {
      "description": "-R:PABSB", 
      "mnem": "PABSQ"
    }, 
    {
      "description": "-R:PABSB", 
      "mnem": "PABSW"
    }, 
    {
      "description": "-R:PACKSSWB", 
      "mnem": "PACKSSDW"
    }, 
    {
      "description": "PACKSSWB/PACKSSDW-Pack with Signed Saturation\r\nOpcode/                                   Op/   64/32 bit   CPUID        Description\r\nInstruction                               … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PACKSSWB"
    }, 
    {
      "description": "PACKUSDW-Pack with Unsigned Saturation\r\n Opcode/                            Op /     64/32        CPUID             Description\r\n Instruction                        En        … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PACKUSDW"
    }, 
    {
      "description": "PACKUSWB-Pack with Unsigned Saturation\r\nOpcode/                                             Op/   64/32 bit    CPUID        Description\r\nInstruction                           … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PACKUSWB"
    }, 
    {
      "description": "PADDB/PADDW/PADDD/PADDQ-Add Packed Integers\r\n Opcode/                         Op /   64/32      CPUID      Description\r\n Instruction                     En     bit Mode   Fea … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PADDB"
    }, 
    {
      "description": "-R:PADDB", 
      "mnem": "PADDD"
    }, 
    {
      "description": "-R:PADDB", 
      "mnem": "PADDQ"
    }, 
    {
      "description": "PADDSB/PADDSW-Add Packed Signed Integers with Signed Saturation\r\nOpcode/                                              Op/    64/32 bit   CPUID       Description\r\nInstruction  … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PADDSB"
    }, 
    {
      "description": "-R:PADDSB", 
      "mnem": "PADDSW"
    }, 
    {
      "description": "PADDUSB/PADDUSW-Add Packed Unsigned Integers with Unsigned Saturation\r\nOpcode/                                             Op/   64/32 bit     CPUID        Description\r\nInstr … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PADDUSB"
    }, 
    {
      "description": "-R:PADDUSB", 
      "mnem": "PADDUSW"
    }, 
    {
      "description": "-R:PADDB", 
      "mnem": "PADDW"
    }, 
    {
      "description": "PALIGNR - Packed Align Right\r\nOpcode/                                          Op/    64/32 bit   CPUID        Description\r\nInstruction                                      E … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PALIGNR"
    }, 
    {
      "description": "PAND-Logical AND\r\nOpcode/                                            Op/   64/32 bit   CPUID        Description\r\nInstruction                                        En    Mode        Feature Flag\r\n                                                         Support\r\n0F DB /r1                                          RM    V/V         MMX            Bitwise AND mm/m64 and mm.\r\nPAND mm, mm/m64\r\n66 0F DB /r                                        RM    V/V         SSE2           Bitwise AND of xmm2/m128 and xmm1.\r\nPAND xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG DB /r                        RVM V/V           AVX            Bitwise AND of xmm3/m128 and xmm.\r\nVPAND xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG DB /r                        RVM V/V           AVX2           Bitwise AND of ymm2, and ymm3/m256 and\r\nVPAND ymm1, ymm2, ymm3/.m256                                                        store result in ymm1.\r\n\r\nEVEX.NDS.128.66.0F.W0 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed doubleword integers in\r\nVPANDD xmm1 {k1}{z}, xmm2,                                           AVX512F        xmm2 and xmm3/m128/m32bcst and store\r\nxmm3/m128/m32bcst                                                                   result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed doubleword integers in\r\nVPANDD ymm1 {k1}{z}, ymm2,                                           AVX512F        ymm2 and ymm3/m256/m32bcst and store\r\nymm3/m256/m32bcst                                                                   result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 DB /r                        FV    V/V         AVX512F        Bitwise AND of packed doubleword integers in\r\nVPANDD zmm1 {k1}{z}, zmm2,                                                          zmm2 and zmm3/m512/m32bcst and store\r\nzmm3/m512/m32bcst                                                                   result in zmm1 using writemask k1.\r\nEVEX.NDS.128.66.0F.W1 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed quadword integers in\r\nVPANDQ xmm1 {k1}{z}, xmm2,                                           AVX512F        xmm2 and xmm3/m128/m64bcst and store\r\nxmm3/m128/m64bcst                                                                   result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed quadword integers in\r\nVPANDQ ymm1 {k1}{z}, ymm2,                                           AVX512F        ymm2 and ymm3/m256/m64bcst and store\r\nymm3/m256/m64bcst                                                                   result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 DB /r                        FV    V/V         AVX512F        Bitwise AND of packed quadword integers in\r\nVPANDQ zmm1 {k1}{z}, zmm2,                                                          zmm2 and zmm3/m512/m64bcst and store\r\nzmm3/m512/m64bcst                                                                   result in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n   Op/En              Operand 1                   Operand 2                   Operand 3                     Operand 4\r\n    RM             ModRM:reg (r, w)             ModRM:r/m (r)                     NA                            NA\r\n   RVM             ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                      NA\r\n    FV             ModRM:reg (w)                EVEX.vvvv (r)                ModRM:r/m (r)                      NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical AND operation on the first source operand and second source operand and stores the\r\nresult in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second\r\noperands are 1, otherwise it is set to 0.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1 at 32/64-bit granularity.\r\nVEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\nOperation\r\nPAND (64-bit operand)\r\nDEST <- DEST AND SRC\r\n\r\n\r\nPAND (128-bit Legacy SSE version)\r\nDEST <- DEST AND SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPAND (VEX.128 encoded version)\r\nDEST <- SRC1 AND SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPAND (VEX.256 encoded instruction)\r\nDEST[255:0] <- (SRC1[255:0] AND SRC2[255:0])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPANDD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[31:0]\r\n                    ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[i+31:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPANDQ (EVEX encoded versions)\r\n\r\n\r\n\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[63:0]\r\n                    ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[i+63:i]\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);\r\nVPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPAND: __m64 _mm_and_si64 (__m64 m1, __m64 m2)\r\n(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)\r\nVPAND:     __m256i _mm256_and_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "PAND"
    }, 
    {
      "description": "PANDN-Logical AND NOT\r\nOpcode/                                             Op/   64/32 bit   CPUID            Description\r\nInstruction                                         En    Mode        Feature\r\n                                                          Support     Flag\r\n0F DF /r1                                           RM    V/V         MMX              Bitwise AND NOT of mm/m64 and mm.\r\nPANDN mm, mm/m64\r\n66 0F DF /r                                         RM    V/V         SSE2             Bitwise AND NOT of xmm2/m128 and xmm1.\r\nPANDN xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG DF /r                         RVM V/V           AVX              Bitwise AND NOT of xmm3/m128 and xmm2.\r\nVPANDN xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG DF /r                         RVM V/V           AVX2             Bitwise AND NOT of ymm2, and ymm3/m256\r\nVPANDN ymm1, ymm2, ymm3/m256                                                           and store result in ymm1.\r\n\r\nEVEX.NDS.128.66.0F.W0 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed doubleword\r\nVPANDND xmm1 {k1}{z}, xmm2,                                           AVX512F          integers in xmm2 and xmm3/m128/m32bcst\r\nxmm3/m128/m32bcst                                                                      and store result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed doubleword\r\nVPANDND ymm1 {k1}{z}, ymm2,                                           AVX512F          integers in ymm2 and ymm3/m256/m32bcst\r\nymm3/m256/m32bcst                                                                      and store result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 DF /r                         FV    V/V         AVX512F          Bitwise AND NOT of packed doubleword\r\nVPANDND zmm1 {k1}{z}, zmm2,                                                            integers in zmm2 and zmm3/m512/m32bcst\r\nzmm3/m512/m32bcst                                                                      and store result in zmm1 using writemask k1.\r\nEVEX.NDS.128.66.0F.W1 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed quadword\r\nVPANDNQ xmm1 {k1}{z}, xmm2,                                           AVX512F          integers in xmm2 and xmm3/m128/m64bcst\r\nxmm3/m128/m64bcst                                                                      and store result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed quadword\r\nVPANDNQ ymm1 {k1}{z}, ymm2,                                           AVX512F          integers in ymm2 and ymm3/m256/m64bcst\r\nymm3/m256/m64bcst                                                                      and store result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 DF /r                         FV    V/V         AVX512F          Bitwise AND NOT of packed quadword\r\nVPANDNQ zmm1 {k1}{z}, zmm2,                                                            integers in zmm2 and zmm3/m512/m64bcst\r\nzmm3/m512/m64bcst                                                                      and store result in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n                                               Instruction Operand Encoding\r\n  Op/En             Operand 1                    Operand 2                    Operand 3                       Operand 4\r\n    RM           ModRM:reg (r, w)              ModRM:r/m (r)                      NA                              NA\r\n   RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                        NA\r\n    FV            ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                        NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second\r\nsource operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-\r\nsponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1 at 32/64-bit granularity.\r\nVEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\nOperation\r\nPANDN (64-bit operand)\r\nDEST <- NOT(DEST) AND SRC\r\n\r\n\r\nPANDN (128-bit Legacy SSE version)\r\nDEST <- NOT(DEST) AND SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPANDN (VEX.128 encoded version)\r\nDEST <- NOT(SRC1) AND SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPANDN (VEX.256 encoded instruction)\r\nDEST[255:0] <- ((NOT SRC1[255:0]) AND SRC2[255:0])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPANDND (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 32\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[31:0])\r\n                    ELSE DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+31:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+31:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPANDNQ (EVEX encoded versions)\r\n\r\n\r\n\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n    i <- j * 64\r\n    IF k1[j] OR *no writemask*\r\n         THEN\r\n               IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n                    THEN DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[63:0])\r\n                    ELSE DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])\r\n               FI;\r\n         ELSE\r\n               IF *merging-masking*                ; merging-masking\r\n                    THEN *DEST[i+63:i] remains unchanged*\r\n                    ELSE                           ; zeroing-masking\r\n                         DEST[i+63:i] <- 0\r\n               FI\r\n    FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);\r\nVPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);\r\nVPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)\r\n(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)\r\nVPANDN:       __m256i _mm256_andnot_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "PANDN"
    }, 
    {
      "description": "PAUSE-Spin Loop Hint\r\n Opcode                   Instruction                 Op/   64-Bit   Compat/ Description\r\n                                                      En    Mode     Leg Mode\r\n F3 90                    PAUSE                       NP    Valid    Valid       Gives hint to processor that improves\r\n                                                                                 performance of spin-wait loops.\r\n\r\n\r\n\r\n                                              Instruction Operand Encoding\r\n   Op/En               Operand 1                Operand 2                    Operand 3                    Operand 4\r\n    NP                    NA                          NA                        NA                            NA\r\n\r\n\r\nDescription\r\nImproves the performance of spin-wait loops. When executing a \"spin-wait loop,\" processors will suffer a severe\r\nperformance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE\r\ninstruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint\r\nto avoid the memory order violation in most situations, which greatly improves processor performance. For this\r\nreason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.\r\nAn additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a\r\nspin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of\r\npower while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-\r\nwait loop greatly reduces the processor's power consumption.\r\nThis instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.\r\nIn earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon\r\nprocessors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.\r\nThis instruction does not change the architectural state of the processor (that is, it performs essentially a delaying\r\nno-op operation).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nExecute_Next_Instruction(DELAY);\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD                     If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "PAUSE"
    }, 
    {
      "description": "PAVGB/PAVGW-Average Packed Integers\r\nOpcode/                                             Op/   64/32 bit   CPUID        Description\r\nInstruction                               … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PAVGB"
    }, 
    {
      "description": "-R:PAVGB", 
      "mnem": "PAVGW"
    }, 
    {
      "description": "PBLENDVB - Variable Blend Packed Bytes\r\nOpcode/                                               Op/        64/32 bit   CPUID        Description\r\nInstruction                     … [Строка слишком длинная. Вы можете скачать файл]
      "mnem": "PBLENDVB"
    }, 
    {
      "description": "PBLENDW - Blend Packed Words\r\nOpcode/                                              Op/   64/32 bit   CPUID       Description\r\nInstruction                                          En    Mode        Feature\r\n                                                           Support     Flag\r\n66 0F 3A 0E /r ib                                    RMI   V/V         SSE4_1      Select words from xmm1 and xmm2/m128\r\nPBLENDW xmm1, xmm2/m128, imm8                                                      from mask specified in imm8 and store the\r\n                                                                                   values into xmm1.\r\nVEX.NDS.128.66.0F3A.WIG 0E /r ib                     RVMI V/V          AVX         Select words from xmm2 and xmm3/m128\r\nVPBLENDW xmm1, xmm2, xmm3/m128, imm8                                               from mask specified in imm8 and store the\r\n                                                                                   values into xmm1.\r\nVEX.NDS.256.66.0F3A.WIG 0E /r ib                     RVMI V/V          AVX2        Select words from ymm2 and ymm3/m256\r\nVPBLENDW ymm1, ymm2, ymm3/m256, imm8                                               from mask specified in imm8 and store the\r\n                                                                                   values into ymm1.\r\n\r\n\r\n\r\n                                            Instruction Operand Encoding\r\n  Op/En            Operand 1                   Operand 2                      Operand 3                   Operand 4\r\n    RMI         ModRM:reg (r, w)             ModRM:r/m (r)                       imm8                         NA\r\n   RVMI          ModRM:reg (w)                VEX.vvvv (r)                   ModRM:r/m (r)                   imm8\r\n\r\n\r\nDescription\r\nWords from the source operand (second operand) are conditionally written to the destination operand (first\r\noperand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask\r\nthat determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,\r\ncorresponding to a word, is \"1\", then the word is copied, else the word element in the destination operand is\r\nunchanged.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nPBLENDW (128-bit Legacy SSE version)\r\nIF (imm8[0] = 1) THEN DEST[15:0] <- SRC[15:0]\r\nELSE DEST[15:0] <- DEST[15:0]\r\nIF (imm8[1] = 1) THEN DEST[31:16] <- SRC[31:16]\r\nELSE DEST[31:16] <- DEST[31:16]\r\nIF (imm8[2] = 1) THEN DEST[47:32] <- SRC[47:32]\r\nELSE DEST[47:32] <- DEST[47:32]\r\nIF (imm8[3] = 1) THEN DEST[63:48] <- SRC[63:48]\r\nELSE DEST[63:48] <- DEST[63:48]\r\nIF (imm8[4] = 1) THEN DEST[79:64] <- SRC[79:64]\r\nELSE DEST[79:64] <- DEST[79:64]\r\nIF (imm8[5] = 1) THEN DEST[95:80] <- SRC[95:80]\r\nELSE DEST[95:80] <- DEST[95:80]\r\nIF (imm8[6] = 1) THEN DEST[111:96] <- SRC[111:96]\r\nELSE DEST[111:96] <- DEST[111:96]\r\nIF (imm8[7] = 1) THEN DEST[127:112] <- SRC[127:112]\r\n\r\n\r\n\r\nELSE DEST[127:112] <- DEST[127:112]\r\n\r\nVPBLENDW (VEX.128 encoded version)\r\nIF (imm8[0] = 1) THEN DEST[15:0] <- SRC2[15:0]\r\nELSE DEST[15:0] <- SRC1[15:0]\r\nIF (imm8[1] = 1) THEN DEST[31:16] <- SRC2[31:16]\r\nELSE DEST[31:16] <- SRC1[31:16]\r\nIF (imm8[2] = 1) THEN DEST[47:32] <- SRC2[47:32]\r\nELSE DEST[47:32] <- SRC1[47:32]\r\nIF (imm8[3] = 1) THEN DEST[63:48] <- SRC2[63:48]\r\nELSE DEST[63:48] <- SRC1[63:48]\r\nIF (imm8[4] = 1) THEN DEST[79:64] <- SRC2[79:64]\r\nELSE DEST[79:64] <- SRC1[79:64]\r\nIF (imm8[5] = 1) THEN DEST[95:80] <- SRC2[95:80]\r\nELSE DEST[95:80] <- SRC1[95:80]\r\nIF (imm8[6] = 1) THEN DEST[111:96] <- SRC2[111:96]\r\nELSE DEST[111:96] <- SRC1[111:96]\r\nIF (imm8[7] = 1) THEN DEST[127:112] <- SRC2[127:112]\r\nELSE DEST[127:112] <- SRC1[127:112]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPBLENDW (VEX.256 encoded version)\r\nIF (imm8[0] == 1) THEN DEST[15:0] <- SRC2[15:0]\r\nELSE DEST[15:0] <- SRC1[15:0]\r\nIF (imm8[1] == 1) THEN DEST[31:16] <- SRC2[31:16]\r\nELSE DEST[31:16] <- SRC1[31:16]\r\nIF (imm8[2] == 1) THEN DEST[47:32] <- SRC2[47:32]\r\nELSE DEST[47:32] <- SRC1[47:32]\r\nIF (imm8[3] == 1) THEN DEST[63:48] <- SRC2[63:48]\r\nELSE DEST[63:48] <- SRC1[63:48]\r\nIF (imm8[4] == 1) THEN DEST[79:64] <- SRC2[79:64]\r\nELSE DEST[79:64] <- SRC1[79:64]\r\nIF (imm8[5] == 1) THEN DEST[95:80] <- SRC2[95:80]\r\nELSE DEST[95:80] <- SRC1[95:80]\r\nIF (imm8[6] == 1) THEN DEST[111:96] <- SRC2[111:96]\r\nELSE DEST[111:96] <- SRC1[111:96]\r\nIF (imm8[7] == 1) THEN DEST[127:112] <- SRC2[127:112]\r\nELSE DEST[127:112] <- SRC1[127:112]\r\nIF (imm8[0] == 1) THEN DEST[143:128] <- SRC2[143:128]\r\nELSE DEST[143:128] <- SRC1[143:128]\r\nIF (imm8[1] == 1) THEN DEST[159:144] <- SRC2[159:144]\r\nELSE DEST[159:144] <- SRC1[159:144]\r\nIF (imm8[2] == 1) THEN DEST[175:160] <- SRC2[175:160]\r\nELSE DEST[175:160] <- SRC1[175:160]\r\nIF (imm8[3] == 1) THEN DEST[191:176] <- SRC2[191:176]\r\nELSE DEST[191:176] <- SRC1[191:176]\r\nIF (imm8[4] == 1) THEN DEST[207:192] <- SRC2[207:192]\r\nELSE DEST[207:192] <- SRC1[207:192]\r\nIF (imm8[5] == 1) THEN DEST[223:208] <- SRC2[223:208]\r\nELSE DEST[223:208] <- SRC1[223:208]\r\nIF (imm8[6] == 1) THEN DEST[239:224] <- SRC2[239:224]\r\nELSE DEST[239:224] <- SRC1[239:224]\r\nIF (imm8[7] == 1) THEN DEST[255:240] <- SRC2[255:240]\r\nELSE DEST[255:240] <- SRC1[255:240]\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)PBLENDW:      __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);\r\nVPBLENDW:        __m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD                    If VEX.L = 1 and AVX2 = 0.\r\n\r\n\r\n\r\n\r\n", 
      "mnem": "PBLENDW"
    }, 
    {
      "description": "PCLMULQDQ - Carry-Less Multiplication Quadword\r\n Opcode/                                                Op/    64/32 bit   CPUID       Description\r\n Instruction                                            En     Mode        Feature\r\n                                                               Support     Flag\r\n 66 0F 3A 44 /r ib                                      RMI    V/V         PCLMUL-     Carry-less multiplication of one quadword of\r\n PCLMULQDQ xmm1, xmm2/m128, imm8                                           QDQ         xmm1 by one quadword of xmm2/m128,\r\n                                                                                       stores the 128-bit result in xmm1. The imme-\r\n                                                                                       diate is used to determine which quadwords\r\n                                                                                       of xmm1 and xmm2/m128 should be used.\r\n VEX.NDS.128.66.0F3A.WIG 44 /r ib                       RVMI V/V           Both PCL-   Carry-less multiplication of one quadword of\r\n VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8                                    MULQDQ      xmm2 by one quadword of xmm3/m128,\r\n                                                                           and AVX     stores the 128-bit result in xmm1. The imme-\r\n                                                                           flags       diate is used to determine which quadwords\r\n                                                                                       of xmm2 and xmm3/m128 should be used.\r\n\r\n\r\n\r\n                                                  Instruction Operand Encoding\r\n     Op/En            Operand 1                     Operand2                      Operand3                      Operand4\r\n     RMI           ModRM:reg (r, w)               ModRM:r/m (r)                      imm8                          NA\r\n     RVMI           ModRM:reg (w)                  VEX.vvvv (r)                  ModRM:r/m (r)                    imm8\r\n\r\n\r\nDescription\r\nPerforms a carry-less multiplication of two quadwords, selected from the first source and second source operand\r\naccording to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to\r\nuse according to Table 4-13, other bits of the immediate byte are ignored.\r\n\r\n                              Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte\r\n        Imm[4]               Imm[0]                                         PCLMULQDQ Operation\r\n                                                          1\r\n 0                     0                     CL_MUL( SRC2 [63:0], SRC1[63:0] )\r\n 0                     1                     CL_MUL( SRC2[63:0], SRC1[127:64] )\r\n 1                     0                     CL_MUL( SRC2[127:64], SRC1[63:0] )\r\n 1                     1                     CL_MUL( SRC2[127:64], SRC1[127:64] )\r\nNOTES:\r\n1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-\r\n   and.\r\n\r\n\r\n The first source operand and the destination operand are the same