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// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package x86asm implements decoding of x86 machine code.
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// An Inst is a single instruction.
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Prefix Prefixes // Prefixes applied to the instruction.
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Op Op // Opcode mnemonic
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Opcode uint32 // Encoded opcode bits, left aligned (first byte is Opcode>>24, etc)
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Args Args // Instruction arguments, in Intel order
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Mode int // processor mode in bits: 16, 32, or 64
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AddrSize int // address size in bits: 16, 32, or 64
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DataSize int // operand size in bits: 16, 32, or 64
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MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, and so on.
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Len int // length of encoded instruction in bytes
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PCRel int // length of PC-relative address in instruction encoding
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PCRelOff int // index of start of PC-relative address in instruction encoding
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// Prefixes is an array of prefixes associated with a single instruction.
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// The prefixes are listed in the same order as found in the instruction:
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// each prefix byte corresponds to one slot in the array. The first zero
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// in the array marks the end of the prefixes.
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type Prefixes [14]Prefix
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// A Prefix represents an Intel instruction prefix.
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// The low 8 bits are the actual prefix byte encoding,
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// and the top 8 bits contain distinguishing bits and metadata.
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// Metadata about the role of a prefix in an instruction.
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PrefixImplicit Prefix = 0x8000 // prefix is implied by instruction text
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PrefixIgnored Prefix = 0x4000 // prefix is ignored: either irrelevant or overridden by a later prefix
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PrefixInvalid Prefix = 0x2000 // prefix makes entire instruction invalid (bad LOCK)
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// Memory segment overrides.
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PrefixES Prefix = 0x26 // ES segment override
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PrefixCS Prefix = 0x2E // CS segment override
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PrefixSS Prefix = 0x36 // SS segment override
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PrefixDS Prefix = 0x3E // DS segment override
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PrefixFS Prefix = 0x64 // FS segment override
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PrefixGS Prefix = 0x65 // GS segment override
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PrefixPN Prefix = 0x12E // predict not taken (conditional branch only)
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PrefixPT Prefix = 0x13E // predict taken (conditional branch only)
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PrefixDataSize Prefix = 0x66 // operand size override
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PrefixData16 Prefix = 0x166
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PrefixData32 Prefix = 0x266
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PrefixAddrSize Prefix = 0x67 // address size override
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PrefixAddr16 Prefix = 0x167
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PrefixAddr32 Prefix = 0x267
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PrefixLOCK Prefix = 0xF0 // lock
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PrefixREPN Prefix = 0xF2 // repeat not zero
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PrefixXACQUIRE Prefix = 0x1F2
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PrefixBND Prefix = 0x2F2
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PrefixREP Prefix = 0xF3 // repeat
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PrefixXRELEASE Prefix = 0x1F3
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// The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10).
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// the other bits are set or not according to the intended use.
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PrefixREX Prefix = 0x40 // REX 64-bit extension prefix
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PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width)
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PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm)
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PrefixREXX Prefix = 0x02 // extension bit X (index field in sib)
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PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
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PrefixVEX2Bytes Prefix = 0xC5 // Short form of vex prefix
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PrefixVEX3Bytes Prefix = 0xC4 // Long form of vex prefix
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// IsREX reports whether p is a REX prefix byte.
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func (p Prefix) IsREX() bool {86
return p&0xF0 == PrefixREX
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func (p Prefix) IsVEX() bool {90
return p&0xFF == PrefixVEX2Bytes || p&0xFF == PrefixVEX3Bytes
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func (p Prefix) String() string {94
p &^= PrefixImplicit | PrefixIgnored | PrefixInvalid
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if s := prefixNames[p]; s != "" {101
if p&PrefixREXW != 0 {104
if p&PrefixREXR != 0 {107
if p&PrefixREXX != 0 {110
if p&PrefixREXB != 0 {116
return fmt.Sprintf("Prefix(%#x)", int(p))119
// An Op is an x86 opcode.
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func (op Op) String() string {124
if i < 0 || i >= len(opNames) || opNames[i] == "" {125
return fmt.Sprintf("Op(%d)", i)130
// An Args holds the instruction arguments.
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// If an instruction has fewer than 4 arguments,
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// the final elements in the array are nil.
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// An Arg is a single instruction argument,
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// one of these types: Reg, Mem, Imm, Rel.
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// Note that the implements of Arg that follow are all sized
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// so that on a 64-bit machine the data can be inlined in
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// the interface value instead of requiring an allocation.
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// A Reg is a single register.
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// The zero Reg value has no name but indicates “no register.”
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// Instruction pointer.
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// 387 floating point registers.
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// Segment registers.
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// Control registers.
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func (r Reg) String() string {340
if i < 0 || i >= len(regNames) || regNames[i] == "" {341
return fmt.Sprintf("Reg(%d)", i)346
// A Mem is a memory reference.
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// The general form is Segment:[Base+Scale*Index+Disp].
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func (m Mem) String() string {359
var base, plus, scale, index, disp string
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base = m.Base.String()
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scale = fmt.Sprintf("%d*", m.Scale)371
index = m.Index.String()
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if m.Disp != 0 || m.Base == 0 && m.Scale == 0 {374
disp = fmt.Sprintf("%+#x", m.Disp)376
return "[" + base + plus + scale + index + disp + "]"
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// A Rel is an offset relative to the current instruction pointer.
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func (r Rel) String() string {385
return fmt.Sprintf(".%+d", r)388
// An Imm is an integer constant.
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func (i Imm) String() string {394
return fmt.Sprintf("%#x", int64(i))397
func (i Inst) String() string {399
for _, p := range i.Prefix {403
if p&PrefixImplicit != 0 {406
fmt.Fprintf(&buf, "%v ", p)
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fmt.Fprintf(&buf, "%v", i.Op)
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for _, v := range i.Args {414
fmt.Fprintf(&buf, "%s%v", sep, v)
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func isReg(a Arg) bool {425
func isSegReg(a Arg) bool {427
return ok && ES <= r && r <= GS
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func isMem(a Arg) bool {435
func isImm(a Arg) bool {440
func regBytes(a Arg) int {445
if AL <= r && r <= R15B {448
if AX <= r && r <= R15W {451
if EAX <= r && r <= R15L {454
if RAX <= r && r <= R15 {460
func isSegment(p Prefix) bool {462
case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
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// The Op definitions and string list are in tables.go.
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var prefixNames = map[Prefix]string{480
PrefixAddrSize: "ADDRSIZE",
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PrefixDataSize: "DATASIZE",
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PrefixAddr16: "ADDR16",
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PrefixData16: "DATA16",
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PrefixAddr32: "ADDR32",
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PrefixData32: "DATA32",
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PrefixXACQUIRE: "XACQUIRE",
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PrefixXRELEASE: "XRELEASE",
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var regNames = [...]string{