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1// Inferno utils/6c/list.c
2// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/6c/list.c
3//
4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
6// Portions Copyright © 1997-1999 Vita Nuova Limited
7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
8// Portions Copyright © 2004,2006 Bruce Ellis
9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
11// Portions Copyright © 2009 The Go Authors. All rights reserved.
12//
13// Permission is hereby granted, free of charge, to any person obtaining a copy
14// of this software and associated documentation files (the "Software"), to deal
15// in the Software without restriction, including without limitation the rights
16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17// copies of the Software, and to permit persons to whom the Software is
18// furnished to do so, subject to the following conditions:
19//
20// The above copyright notice and this permission notice shall be included in
21// all copies or substantial portions of the Software.
22//
23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29// THE SOFTWARE.
30
31package x86
32
33import (
34"github.com/twitchyliquid64/golang-asm/obj"
35"fmt"
36)
37
38var Register = []string{
39"AL", // [D_AL]
40"CL",
41"DL",
42"BL",
43"SPB",
44"BPB",
45"SIB",
46"DIB",
47"R8B",
48"R9B",
49"R10B",
50"R11B",
51"R12B",
52"R13B",
53"R14B",
54"R15B",
55"AX", // [D_AX]
56"CX",
57"DX",
58"BX",
59"SP",
60"BP",
61"SI",
62"DI",
63"R8",
64"R9",
65"R10",
66"R11",
67"R12",
68"R13",
69"R14",
70"R15",
71"AH",
72"CH",
73"DH",
74"BH",
75"F0", // [D_F0]
76"F1",
77"F2",
78"F3",
79"F4",
80"F5",
81"F6",
82"F7",
83"M0",
84"M1",
85"M2",
86"M3",
87"M4",
88"M5",
89"M6",
90"M7",
91"K0",
92"K1",
93"K2",
94"K3",
95"K4",
96"K5",
97"K6",
98"K7",
99"X0",
100"X1",
101"X2",
102"X3",
103"X4",
104"X5",
105"X6",
106"X7",
107"X8",
108"X9",
109"X10",
110"X11",
111"X12",
112"X13",
113"X14",
114"X15",
115"X16",
116"X17",
117"X18",
118"X19",
119"X20",
120"X21",
121"X22",
122"X23",
123"X24",
124"X25",
125"X26",
126"X27",
127"X28",
128"X29",
129"X30",
130"X31",
131"Y0",
132"Y1",
133"Y2",
134"Y3",
135"Y4",
136"Y5",
137"Y6",
138"Y7",
139"Y8",
140"Y9",
141"Y10",
142"Y11",
143"Y12",
144"Y13",
145"Y14",
146"Y15",
147"Y16",
148"Y17",
149"Y18",
150"Y19",
151"Y20",
152"Y21",
153"Y22",
154"Y23",
155"Y24",
156"Y25",
157"Y26",
158"Y27",
159"Y28",
160"Y29",
161"Y30",
162"Y31",
163"Z0",
164"Z1",
165"Z2",
166"Z3",
167"Z4",
168"Z5",
169"Z6",
170"Z7",
171"Z8",
172"Z9",
173"Z10",
174"Z11",
175"Z12",
176"Z13",
177"Z14",
178"Z15",
179"Z16",
180"Z17",
181"Z18",
182"Z19",
183"Z20",
184"Z21",
185"Z22",
186"Z23",
187"Z24",
188"Z25",
189"Z26",
190"Z27",
191"Z28",
192"Z29",
193"Z30",
194"Z31",
195"CS", // [D_CS]
196"SS",
197"DS",
198"ES",
199"FS",
200"GS",
201"GDTR", // [D_GDTR]
202"IDTR", // [D_IDTR]
203"LDTR", // [D_LDTR]
204"MSW", // [D_MSW]
205"TASK", // [D_TASK]
206"CR0", // [D_CR]
207"CR1",
208"CR2",
209"CR3",
210"CR4",
211"CR5",
212"CR6",
213"CR7",
214"CR8",
215"CR9",
216"CR10",
217"CR11",
218"CR12",
219"CR13",
220"CR14",
221"CR15",
222"DR0", // [D_DR]
223"DR1",
224"DR2",
225"DR3",
226"DR4",
227"DR5",
228"DR6",
229"DR7",
230"TR0", // [D_TR]
231"TR1",
232"TR2",
233"TR3",
234"TR4",
235"TR5",
236"TR6",
237"TR7",
238"TLS", // [D_TLS]
239"MAXREG", // [MAXREG]
240}
241
242func init() {
243obj.RegisterRegister(REG_AL, REG_AL+len(Register), rconv)
244obj.RegisterOpcode(obj.ABaseAMD64, Anames)
245obj.RegisterRegisterList(obj.RegListX86Lo, obj.RegListX86Hi, rlconv)
246obj.RegisterOpSuffix("386", opSuffixString)
247obj.RegisterOpSuffix("amd64", opSuffixString)
248}
249
250func rconv(r int) string {
251if REG_AL <= r && r-REG_AL < len(Register) {
252return Register[r-REG_AL]
253}
254return fmt.Sprintf("Rgok(%d)", r-obj.RBaseAMD64)
255}
256
257func rlconv(bits int64) string {
258reg0, reg1 := decodeRegisterRange(bits)
259return fmt.Sprintf("[%s-%s]", rconv(reg0), rconv(reg1))
260}
261
262func opSuffixString(s uint8) string {
263return "." + opSuffix(s).String()
264}
265