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1// Inferno utils/6c/6.out.h2// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/6c/6.out.h3//4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)6// Portions Copyright © 1997-1999 Vita Nuova Limited7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)8// Portions Copyright © 2004,2006 Bruce Ellis9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others11// Portions Copyright © 2009 The Go Authors. All rights reserved.12//13// Permission is hereby granted, free of charge, to any person obtaining a copy14// of this software and associated documentation files (the "Software"), to deal15// in the Software without restriction, including without limitation the rights16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell17// copies of the Software, and to permit persons to whom the Software is18// furnished to do so, subject to the following conditions:19//20// The above copyright notice and this permission notice shall be included in21// all copies or substantial portions of the Software.22//23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN29// THE SOFTWARE.30)38REG_CL42REG_DL43REG_BL44REG_SPB45REG_BPB46REG_SIB47REG_DIB48REG_R8B49REG_R9B50REG_R10B51REG_R11B52REG_R12B53REG_R13B54REG_R14B55REG_R15B56REG_AX58REG_CX59REG_DX60REG_BX61REG_SP62REG_BP63REG_SI64REG_DI65REG_R866REG_R967REG_R1068REG_R1169REG_R1270REG_R1371REG_R1472REG_R1573REG_AH75REG_CH76REG_DH77REG_BH78REG_F080REG_F181REG_F282REG_F383REG_F484REG_F585REG_F686REG_F787REG_M089REG_M190REG_M291REG_M392REG_M493REG_M594REG_M695REG_M796REG_K098REG_K199REG_K2100REG_K3101REG_K4102REG_K5103REG_K6104REG_K7105REG_X0107REG_X1108REG_X2109REG_X3110REG_X4111REG_X5112REG_X6113REG_X7114REG_X8115REG_X9116REG_X10117REG_X11118REG_X12119REG_X13120REG_X14121REG_X15122REG_X16123REG_X17124REG_X18125REG_X19126REG_X20127REG_X21128REG_X22129REG_X23130REG_X24131REG_X25132REG_X26133REG_X27134REG_X28135REG_X29136REG_X30137REG_X31138REG_Y0140REG_Y1141REG_Y2142REG_Y3143REG_Y4144REG_Y5145REG_Y6146REG_Y7147REG_Y8148REG_Y9149REG_Y10150REG_Y11151REG_Y12152REG_Y13153REG_Y14154REG_Y15155REG_Y16156REG_Y17157REG_Y18158REG_Y19159REG_Y20160REG_Y21161REG_Y22162REG_Y23163REG_Y24164REG_Y25165REG_Y26166REG_Y27167REG_Y28168REG_Y29169REG_Y30170REG_Y31171REG_Z0173REG_Z1174REG_Z2175REG_Z3176REG_Z4177REG_Z5178REG_Z6179REG_Z7180REG_Z8181REG_Z9182REG_Z10183REG_Z11184REG_Z12185REG_Z13186REG_Z14187REG_Z15188REG_Z16189REG_Z17190REG_Z18191REG_Z19192REG_Z20193REG_Z21194REG_Z22195REG_Z23196REG_Z24197REG_Z25198REG_Z26199REG_Z27200REG_Z28201REG_Z29202REG_Z30203REG_Z31204REG_CS206REG_SS207REG_DS208REG_ES209REG_FS210REG_GS211REG_CR0219REG_CR1220REG_CR2221REG_CR3222REG_CR4223REG_CR5224REG_CR6225REG_CR7226REG_CR8227REG_CR9228REG_CR10229REG_CR11230REG_CR12231REG_CR13232REG_CR14233REG_CR15234REG_DR0236REG_DR1237REG_DR2238REG_DR3239REG_DR4240REG_DR5241REG_DR6242REG_DR7243REG_TR0245REG_TR1246REG_TR2247REG_TR3248REG_TR4249REG_TR5250REG_TR6251REG_TR7252REG_TLS254MAXREG256)278// https://www.uclibc.org/docs/psABI-x86_64.pdf, figure 3.36280var AMD64DWARFRegisters = map[int16]int16{281REG_AX: 0,282REG_DX: 1,283REG_CX: 2,284REG_BX: 3,285REG_SI: 4,286REG_DI: 5,287REG_BP: 6,288REG_SP: 7,289REG_R8: 8,290REG_R9: 9,291REG_R10: 10,292REG_R11: 11,293REG_R12: 12,294REG_R13: 13,295REG_R14: 14,296REG_R15: 15,297// 16 is "Return Address RA", whatever that is.298// 17-24 vector registers (X/Y/Z).299REG_X0: 17,300REG_X1: 18,301REG_X2: 19,302REG_X3: 20,303REG_X4: 21,304REG_X5: 22,305REG_X6: 23,306REG_X7: 24,307// 25-32 extended vector registers (X/Y/Z).308REG_X8: 25,309REG_X9: 26,310REG_X10: 27,311REG_X11: 28,312REG_X12: 29,313REG_X13: 30,314REG_X14: 31,315REG_X15: 32,316// ST registers. %stN => FN.317REG_F0: 33,318REG_F1: 34,319REG_F2: 35,320REG_F3: 36,321REG_F4: 37,322REG_F5: 38,323REG_F6: 39,324REG_F7: 40,325// MMX registers. %mmN => MN.326REG_M0: 41,327REG_M1: 42,328REG_M2: 43,329REG_M3: 44,330REG_M4: 45,331REG_M5: 46,332REG_M6: 47,333REG_M7: 48,334// 48 is flags, which doesn't have a name.335REG_ES: 50,336REG_CS: 51,337REG_SS: 52,338REG_DS: 53,339REG_FS: 54,340REG_GS: 55,341// 58 and 59 are {fs,gs}base, which don't have names.342REG_TR: 62,343REG_LDTR: 63,344// 64-66 are mxcsr, fcw, fsw, which don't have names.345}374// https://www.uclibc.org/docs/psABI-i386.pdf, table 2.14376var X86DWARFRegisters = map[int16]int16{377REG_AX: 0,378REG_CX: 1,379REG_DX: 2,380REG_BX: 3,381REG_SP: 4,382REG_BP: 5,383REG_SI: 6,384REG_DI: 7,385// 8 is "Return Address RA", whatever that is.386// 9 is flags, which doesn't have a name.387// ST registers. %stN => FN.388REG_F0: 11,389REG_F1: 12,390REG_F2: 13,391REG_F3: 14,392REG_F4: 15,393REG_F5: 16,394REG_F6: 17,395REG_F7: 18,396// XMM registers. %xmmN => XN.397REG_X0: 21,398REG_X1: 22,399REG_X2: 23,400REG_X3: 24,401REG_X4: 25,402REG_X5: 26,403REG_X6: 27,404REG_X7: 28,405// MMX registers. %mmN => MN.406REG_M0: 29,407REG_M1: 30,408REG_M2: 31,409REG_M3: 32,410REG_M4: 33,411REG_M5: 34,412REG_M6: 35,413REG_M7: 36,414// 39 is mxcsr, which doesn't have a name.415REG_ES: 40,416REG_CS: 41,417REG_SS: 42,418REG_DS: 43,419REG_FS: 44,420REG_GS: 45,421REG_TR: 48,422REG_LDTR: 49,423}424