podman

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// cmd/7l/list.c and cmd/7l/sub.c from Vita Nuova.
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// https://code.google.com/p/ken-cc/source/browse/
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//
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// 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// 	Portions Copyright © 1997-1999 Vita Nuova Limited
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// 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// 	Portions Copyright © 2004,2006 Bruce Ellis
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// 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// 	Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package arm64
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import (
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	"github.com/twitchyliquid64/golang-asm/obj"
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	"fmt"
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)
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var strcond = [16]string{
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	"EQ",
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	"NE",
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	"HS",
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	"LO",
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	"MI",
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	"PL",
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	"VS",
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	"VC",
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	"HI",
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	"LS",
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	"GE",
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	"LT",
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	"GT",
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	"LE",
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	"AL",
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	"NV",
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}
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func init() {
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	obj.RegisterRegister(obj.RBaseARM64, REG_SPECIAL+1024, rconv)
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	obj.RegisterOpcode(obj.ABaseARM64, Anames)
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	obj.RegisterRegisterList(obj.RegListARM64Lo, obj.RegListARM64Hi, rlconv)
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	obj.RegisterOpSuffix("arm64", obj.CConvARM)
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}
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func arrange(a int) string {
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	switch a {
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	case ARNG_8B:
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		return "B8"
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	case ARNG_16B:
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		return "B16"
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	case ARNG_4H:
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		return "H4"
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	case ARNG_8H:
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		return "H8"
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	case ARNG_2S:
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		return "S2"
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	case ARNG_4S:
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		return "S4"
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	case ARNG_1D:
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		return "D1"
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	case ARNG_2D:
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		return "D2"
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	case ARNG_B:
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		return "B"
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	case ARNG_H:
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		return "H"
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	case ARNG_S:
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		return "S"
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	case ARNG_D:
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		return "D"
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	case ARNG_1Q:
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		return "Q1"
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	default:
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		return ""
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	}
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}
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func rconv(r int) string {
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	ext := (r >> 5) & 7
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	if r == REGG {
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		return "g"
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	}
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	switch {
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	case REG_R0 <= r && r <= REG_R30:
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		return fmt.Sprintf("R%d", r-REG_R0)
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	case r == REG_R31:
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		return "ZR"
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	case REG_F0 <= r && r <= REG_F31:
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		return fmt.Sprintf("F%d", r-REG_F0)
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	case REG_V0 <= r && r <= REG_V31:
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		return fmt.Sprintf("V%d", r-REG_V0)
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	case COND_EQ <= r && r <= COND_NV:
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		return strcond[r-COND_EQ]
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	case r == REGSP:
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		return "RSP"
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	case r == REG_DAIFSet:
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		return "DAIFSet"
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	case r == REG_DAIFClr:
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		return "DAIFClr"
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	case r == REG_PLDL1KEEP:
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		return "PLDL1KEEP"
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	case r == REG_PLDL1STRM:
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		return "PLDL1STRM"
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	case r == REG_PLDL2KEEP:
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		return "PLDL2KEEP"
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	case r == REG_PLDL2STRM:
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		return "PLDL2STRM"
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	case r == REG_PLDL3KEEP:
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		return "PLDL3KEEP"
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	case r == REG_PLDL3STRM:
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		return "PLDL3STRM"
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	case r == REG_PLIL1KEEP:
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		return "PLIL1KEEP"
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	case r == REG_PLIL1STRM:
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		return "PLIL1STRM"
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	case r == REG_PLIL2KEEP:
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		return "PLIL2KEEP"
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	case r == REG_PLIL2STRM:
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		return "PLIL2STRM"
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	case r == REG_PLIL3KEEP:
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		return "PLIL3KEEP"
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	case r == REG_PLIL3STRM:
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		return "PLIL3STRM"
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	case r == REG_PSTL1KEEP:
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		return "PSTL1KEEP"
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	case r == REG_PSTL1STRM:
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		return "PSTL1STRM"
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	case r == REG_PSTL2KEEP:
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		return "PSTL2KEEP"
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	case r == REG_PSTL2STRM:
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		return "PSTL2STRM"
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	case r == REG_PSTL3KEEP:
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		return "PSTL3KEEP"
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	case r == REG_PSTL3STRM:
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		return "PSTL3STRM"
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	case REG_UXTB <= r && r < REG_UXTH:
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		if ext != 0 {
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			return fmt.Sprintf("%s.UXTB<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.UXTB", regname(r))
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		}
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	case REG_UXTH <= r && r < REG_UXTW:
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		if ext != 0 {
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			return fmt.Sprintf("%s.UXTH<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.UXTH", regname(r))
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		}
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	case REG_UXTW <= r && r < REG_UXTX:
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		if ext != 0 {
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			return fmt.Sprintf("%s.UXTW<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.UXTW", regname(r))
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		}
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	case REG_UXTX <= r && r < REG_SXTB:
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		if ext != 0 {
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			return fmt.Sprintf("%s.UXTX<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.UXTX", regname(r))
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		}
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	case REG_SXTB <= r && r < REG_SXTH:
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		if ext != 0 {
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			return fmt.Sprintf("%s.SXTB<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.SXTB", regname(r))
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		}
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	case REG_SXTH <= r && r < REG_SXTW:
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		if ext != 0 {
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			return fmt.Sprintf("%s.SXTH<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.SXTH", regname(r))
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		}
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	case REG_SXTW <= r && r < REG_SXTX:
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		if ext != 0 {
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			return fmt.Sprintf("%s.SXTW<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.SXTW", regname(r))
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		}
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	case REG_SXTX <= r && r < REG_SPECIAL:
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		if ext != 0 {
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			return fmt.Sprintf("%s.SXTX<<%d", regname(r), ext)
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		} else {
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			return fmt.Sprintf("%s.SXTX", regname(r))
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		}
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	// bits 0-4 indicate register, bits 5-7 indicate shift amount, bit 8 equals to 0.
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	case REG_LSL <= r && r < (REG_LSL+1<<8):
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		return fmt.Sprintf("R%d<<%d", r&31, (r>>5)&7)
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	case REG_ARNG <= r && r < REG_ELEM:
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		return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
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	case REG_ELEM <= r && r < REG_ELEM_END:
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		return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
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	}
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	// Return system register name.
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	name, _, _ := SysRegEnc(int16(r))
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	if name != "" {
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		return name
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	}
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	return fmt.Sprintf("badreg(%d)", r)
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}
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func DRconv(a int) string {
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	if a >= C_NONE && a <= C_NCLASS {
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		return cnames7[a]
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	}
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	return "C_??"
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}
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func rlconv(list int64) string {
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	str := ""
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	// ARM64 register list follows ARM64 instruction decode schema
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	// | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... |
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	// +----+----+-----+---------+---------+-----+
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	// |    | Q  | ... | opcode  |   size  | ... |
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	firstReg := int(list & 31)
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	opcode := (list >> 12) & 15
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	var regCnt int
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	var t string
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	switch opcode {
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	case 0x7:
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		regCnt = 1
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	case 0xa:
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		regCnt = 2
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	case 0x6:
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		regCnt = 3
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	case 0x2:
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		regCnt = 4
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	default:
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		regCnt = -1
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	}
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	// Q:size
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	arng := ((list>>30)&1)<<2 | (list>>10)&3
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	switch arng {
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	case 0:
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		t = "B8"
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	case 4:
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		t = "B16"
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	case 1:
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		t = "H4"
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	case 5:
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		t = "H8"
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	case 2:
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		t = "S2"
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	case 6:
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		t = "S4"
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	case 3:
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		t = "D1"
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	case 7:
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		t = "D2"
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	}
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	for i := 0; i < regCnt; i++ {
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		if str == "" {
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			str += "["
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		} else {
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			str += ","
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		}
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		str += fmt.Sprintf("V%d.", (firstReg+i)&31)
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		str += t
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	}
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	str += "]"
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	return str
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}
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func regname(r int) string {
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	if r&31 == 31 {
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		return "ZR"
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	}
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	return fmt.Sprintf("R%d", r&31)
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}
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