podman

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// Copyright 2018 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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/*
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Package arm64 implements an ARM64 assembler. Go assembly syntax is different from GNU ARM64
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syntax, but we can still follow the general rules to map between them.
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Instructions mnemonics mapping rules
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1. Most instructions use width suffixes of instruction names to indicate operand width rather than
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using different register names.
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  Examples:
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    ADC R24, R14, R12          <=>     adc x12, x24
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    ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
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    FCMPS F2, F3               <=>     fcmp s3, s2
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    FCMPD F2, F3               <=>     fcmp d3, d2
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    FCVTDH F2, F3              <=>     fcvt h3, d2
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2. Go uses .P and .W suffixes to indicate post-increment and pre-increment.
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  Examples:
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    MOVD.P -8(R10), R8         <=>      ldr x8, [x10],#-8
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    MOVB.W 16(R16), R10        <=>      ldrsb x10, [x16,#16]!
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    MOVBU.W 16(R16), R10       <=>      ldrb x10, [x16,#16]!
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3. Go uses a series of MOV instructions as load and store.
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64-bit variant ldr, str, stur => MOVD;
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32-bit variant str, stur, ldrsw => MOVW;
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32-bit variant ldr => MOVWU;
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ldrb => MOVBU; ldrh => MOVHU;
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ldrsb, sturb, strb => MOVB;
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ldrsh, sturh, strh =>  MOVH.
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4. Go moves conditions into opcode suffix, like BLT.
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5. Go adds a V prefix for most floating-point and SIMD instructions, except cryptographic extension
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instructions and floating-point(scalar) instructions.
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  Examples:
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    VADD V5.H8, V18.H8, V9.H8         <=>      add v9.8h, v18.8h, v5.8h
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    VLD1.P (R6)(R11), [V31.D1]        <=>      ld1 {v31.1d}, [x6], x11
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    VFMLA V29.S2, V20.S2, V14.S2      <=>      fmla v14.2s, v20.2s, v29.2s
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    AESD V22.B16, V19.B16             <=>      aesd v19.16b, v22.16b
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    SCVTFWS R3, F16                   <=>      scvtf s17, w6
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6. Align directive
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Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned
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to a specified boundary by padding with NOOP instruction. The alignment value supported on arm64
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must be a power of 2 and in the range of [8, 2048].
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  Examples:
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    PCALIGN $16
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    MOVD $2, R0          // This instruction is aligned with 16 bytes.
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    PCALIGN $1024
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    MOVD $3, R1          // This instruction is aligned with 1024 bytes.
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PCALIGN also changes the function alignment. If a function has one or more PCALIGN directives,
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its address will be aligned to the same or coarser boundary, which is the maximum of all the
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alignment values.
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In the following example, the function Add is aligned with 128 bytes.
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  Examples:
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    TEXT ·Add(SB),$40-16
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    MOVD $2, R0
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    PCALIGN $32
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    MOVD $4, R1
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    PCALIGN $128
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    MOVD $8, R2
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    RET
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On arm64, functions in Go are aligned to 16 bytes by default, we can also use PCALGIN to set the
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function alignment. The functions that need to be aligned are preferably using NOFRAME and NOSPLIT
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to avoid the impact of the prologues inserted by the assembler, so that the function address will
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have the same alignment as the first hand-written instruction.
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In the following example, PCALIGN at the entry of the function Add will align its address to 2048 bytes.
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  Examples:
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    TEXT ·Add(SB),NOSPLIT|NOFRAME,$0
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      PCALIGN $2048
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      MOVD $1, R0
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      MOVD $1, R1
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      RET
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Special Cases.
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(1) umov is written as VMOV.
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(2) br is renamed JMP, blr is renamed CALL.
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(3) No need to add "W" suffix: LDARB, LDARH, LDAXRB, LDAXRH, LDTRH, LDXRB, LDXRH.
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(4) In Go assembly syntax, NOP is a zero-width pseudo-instruction serves generic purpose, nothing
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related to real ARM64 instruction. NOOP serves for the hardware nop instruction. NOOP is an alias of
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HINT $0.
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  Examples:
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    VMOV V13.B[1], R20      <=>      mov x20, v13.b[1]
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    VMOV V13.H[1], R20      <=>      mov w20, v13.h[1]
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    JMP (R3)                <=>      br x3
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    CALL (R17)              <=>      blr x17
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    LDAXRB (R19), R16       <=>      ldaxrb w16, [x19]
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    NOOP                    <=>      nop
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Register mapping rules
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1. All basic register names are written as Rn.
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2. Go uses ZR as the zero register and RSP as the stack pointer.
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3. Bn, Hn, Dn, Sn and Qn instructions are written as Fn in floating-point instructions and as Vn
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in SIMD instructions.
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Argument mapping rules
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1. The operands appear in left-to-right assignment order.
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Go reverses the arguments of most instructions.
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    Examples:
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      ADD R11.SXTB<<1, RSP, R25      <=>      add x25, sp, w11, sxtb #1
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      VADD V16, V19, V14             <=>      add d14, d19, d16
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Special Cases.
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(1) Argument order is the same as in the GNU ARM64 syntax: cbz, cbnz and some store instructions,
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such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1.
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  Examples:
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    MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
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    MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
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    STLRH R21, (R19)      <=>    stlrh w21, [x19]
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(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>
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  Examples:
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    MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
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    SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3
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(3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>
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  Examples:
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    FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
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    FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25
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(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>
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  Examples:
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    BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
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    UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5
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(5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>
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  Examples:
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    FCCMPD AL, F8, F26, $0     <=>    fccmp d26, d8, #0x0, al
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    FCCMPS VS, F29, F4, $4     <=>    fccmp s4, s29, #0x4, vs
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    FCCMPED LE, F20, F5, $13   <=>    fccmpe d5, d20, #0xd, le
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    FCCMPES NE, F26, F10, $0   <=>    fccmpe s10, s26, #0x0, ne
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(6) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, $<imm>, $<nzcv>
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  Examples:
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    CCMP MI, R22, $12, $13     <=>    ccmp x22, #0xc, #0xd, mi
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    CCMNW AL, R1, $11, $8      <=>    ccmn w1, #0xb, #0x8, al
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(7) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, <Rm>, $<nzcv>
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  Examples:
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    CCMN VS, R13, R22, $10     <=>    ccmn x13, x22, #0xa, vs
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    CCMPW HS, R19, R14, $11    <=>    ccmp w19, w14, #0xb, cs
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(9) CSEL, CSELW, CSNEG, CSNEGW, CSINC, CSINCW <cond>, <Rn>, <Rm>, <Rd> ;
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FCSELD, FCSELS <cond>, <Fn>, <Fm>, <Fd>
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  Examples:
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    CSEL GT, R0, R19, R1        <=>    csel x1, x0, x19, gt
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    CSNEGW GT, R7, R17, R8      <=>    csneg w8, w7, w17, gt
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    FCSELD EQ, F15, F18, F16    <=>    fcsel d16, d15, d18, eq
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(10) TBNZ, TBZ $<imm>, <Rt>, <label>
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(11) STLXR, STLXRW, STXR, STXRW, STLXRB, STLXRH, STXRB, STXRH  <Rf>, (<Rn|RSP>), <Rs>
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  Examples:
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    STLXR ZR, (R15), R16    <=>    stlxr w16, xzr, [x15]
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    STXRB R9, (R21), R19    <=>    stxrb w19, w9, [x21]
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(12) STLXP, STLXPW, STXP, STXPW (<Rf1>, <Rf2>), (<Rn|RSP>), <Rs>
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  Examples:
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    STLXP (R17, R19), (R4), R5      <=>    stlxp w5, x17, x19, [x4]
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    STXPW (R30, R25), (R22), R13    <=>    stxp w13, w30, w25, [x22]
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2. Expressions for special arguments.
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#<immediate> is written as $<immediate>.
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Optionally-shifted immediate.
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  Examples:
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    ADD $(3151<<12), R14, R20     <=>    add x20, x14, #0xc4f, lsl #12
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    ADDW $1864, R25, R6           <=>    add w6, w25, #0x748
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Optionally-shifted registers are written as <Rm>{<shift><amount>}.
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The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).
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  Examples:
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    ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
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    ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24
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Extended registers are written as <Rm>{.<extend>{<<<amount>}}.
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<extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.
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  Examples:
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    ADDS R19.UXTB<<4, R9, R26     <=>    adds x26, x9, w19, uxtb #4
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    ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx
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Memory references: [<Xn|SP>{,#0}] is written as (Rn|RSP), a base register and an immediate
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offset is written as imm(Rn|RSP), a base register and an offset register is written as (Rn|RSP)(Rm).
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  Examples:
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    LDAR (R22), R9                  <=>    ldar x9, [x22]
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    LDP 28(R17), (R15, R23)         <=>    ldp x15, x23, [x17,#28]
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    MOVWU (R4)(R12<<2), R8          <=>    ldr w8, [x4, x12, lsl #2]
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    MOVD (R7)(R11.UXTW<<3), R25     <=>    ldr x25, [x7,w11,uxtw #3]
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    MOVBU (R27)(R23), R14           <=>    ldrb w14, [x27,x23]
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Register pairs are written as (Rt1, Rt2).
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  Examples:
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    LDP.P -240(R11), (R12, R26)    <=>    ldp x12, x26, [x11],#-240
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Register with arrangement and register with arrangement and index.
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  Examples:
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    VADD V5.H8, V18.H8, V9.H8                     <=>    add v9.8h, v18.8h, v5.8h
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    VLD1 (R2), [V21.B16]                          <=>    ld1 {v21.16b}, [x2]
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    VST1.P V9.S[1], (R16)(R21)                    <=>    st1 {v9.s}[1], [x16], x28
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    VST1.P [V13.H8, V14.H8, V15.H8], (R3)(R14)    <=>    st1 {v13.8h-v15.8h}, [x3], x14
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    VST1.P [V14.D1, V15.D1], (R7)(R23)            <=>    st1 {v14.1d, v15.1d}, [x7], x23
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*/
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package arm64
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