podman

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// Inferno utils/5c/list.c
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// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/5c/list.c
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//
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//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
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//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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//	Portions Copyright © 1997-1999 Vita Nuova Limited
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//	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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//	Portions Copyright © 2004,2006 Bruce Ellis
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//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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//	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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//	Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package arm
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import (
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	"github.com/twitchyliquid64/golang-asm/obj"
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	"fmt"
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)
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func init() {
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	obj.RegisterRegister(obj.RBaseARM, MAXREG, rconv)
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	obj.RegisterOpcode(obj.ABaseARM, Anames)
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	obj.RegisterRegisterList(obj.RegListARMLo, obj.RegListARMHi, rlconv)
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	obj.RegisterOpSuffix("arm", obj.CConvARM)
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}
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func rconv(r int) string {
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	if r == 0 {
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		return "NONE"
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	}
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	if r == REGG {
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		// Special case.
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		return "g"
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	}
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	if REG_R0 <= r && r <= REG_R15 {
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		return fmt.Sprintf("R%d", r-REG_R0)
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	}
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	if REG_F0 <= r && r <= REG_F15 {
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		return fmt.Sprintf("F%d", r-REG_F0)
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	}
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	switch r {
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	case REG_FPSR:
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		return "FPSR"
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	case REG_FPCR:
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		return "FPCR"
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	case REG_CPSR:
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		return "CPSR"
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	case REG_SPSR:
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		return "SPSR"
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	case REG_MB_SY:
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		return "MB_SY"
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	case REG_MB_ST:
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		return "MB_ST"
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	case REG_MB_ISH:
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		return "MB_ISH"
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	case REG_MB_ISHST:
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		return "MB_ISHST"
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	case REG_MB_NSH:
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		return "MB_NSH"
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	case REG_MB_NSHST:
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		return "MB_NSHST"
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	case REG_MB_OSH:
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		return "MB_OSH"
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	case REG_MB_OSHST:
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		return "MB_OSHST"
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	}
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	return fmt.Sprintf("Rgok(%d)", r-obj.RBaseARM)
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}
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func DRconv(a int) string {
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	s := "C_??"
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	if a >= C_NONE && a <= C_NCLASS {
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		s = cnames5[a]
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	}
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	var fp string
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	fp += s
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	return fp
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}
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func rlconv(list int64) string {
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	str := ""
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	for i := 0; i < 16; i++ {
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		if list&(1<<uint(i)) != 0 {
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			if str == "" {
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				str += "["
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			} else {
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				str += ","
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			}
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			// This is ARM-specific; R10 is g.
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			if i == REGG-REG_R0 {
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				str += "g"
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			} else {
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				str += fmt.Sprintf("R%d", i)
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			}
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		}
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	}
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	str += "]"
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	return str
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}
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