podman
410 строк · 6.9 Кб
1// Inferno utils/5c/5.out.h2// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/5c/5.out.h3//4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)6// Portions Copyright © 1997-1999 Vita Nuova Limited7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)8// Portions Copyright © 2004,2006 Bruce Ellis9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others11// Portions Copyright © 2009 The Go Authors. All rights reserved.12//13// Permission is hereby granted, free of charge, to any person obtaining a copy14// of this software and associated documentation files (the "Software"), to deal15// in the Software without restriction, including without limitation the rights16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell17// copies of the Software, and to permit persons to whom the Software is18// furnished to do so, subject to the following conditions:19//20// The above copyright notice and this permission notice shall be included in21// all copies or substantial portions of the Software.22//23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN29// THE SOFTWARE.30package arm32import "github.com/twitchyliquid64/golang-asm/obj"34//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm36const (38NSNAME = 839NSYM = 5040NREG = 1641)42/* -1 disables use of REGARG */44const (45REGARG = -146)47const (49REG_R0 = obj.RBaseARM + iota // must be 16-aligned50REG_R151REG_R252REG_R353REG_R454REG_R555REG_R656REG_R757REG_R858REG_R959REG_R1060REG_R1161REG_R1262REG_R1363REG_R1464REG_R1565REG_F0 // must be 16-aligned67REG_F168REG_F269REG_F370REG_F471REG_F572REG_F673REG_F774REG_F875REG_F976REG_F1077REG_F1178REG_F1279REG_F1380REG_F1481REG_F1582REG_FPSR // must be 2-aligned84REG_FPCR85REG_CPSR // must be 2-aligned87REG_SPSR88REGRET = REG_R090/* compiler allocates R1 up as temps */91/* compiler allocates register variables R3 up */92/* compiler allocates external registers R10 down */93REGEXT = REG_R1094/* these two registers are declared in runtime.h */95REGG = REGEXT - 096REGM = REGEXT - 197REGCTXT = REG_R799REGTMP = REG_R11100REGSP = REG_R13101REGLINK = REG_R14102REGPC = REG_R15103NFREG = 16105/* compiler allocates register variables F0 up */106/* compiler allocates external registers F7 down */107FREGRET = REG_F0108FREGEXT = REG_F7109FREGTMP = REG_F15110)111// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf113var ARMDWARFRegisters = map[int16]int16{}114func init() {116// f assigns dwarfregisters[from:to] = (base):(step*(to-from)+base)117f := func(from, to, base, step int16) {118for r := int16(from); r <= to; r++ {119ARMDWARFRegisters[r] = step*(r-from) + base120}121}122f(REG_R0, REG_R15, 0, 1)123f(REG_F0, REG_F15, 64, 2) // Use d0 through D15, aka S0, S2, ..., S30124}125// Special registers, after subtracting obj.RBaseARM, bit 9 indicates127// a special register and the low bits select the register.128const (129REG_SPECIAL = obj.RBaseARM + 1<<9 + iota130REG_MB_SY131REG_MB_ST132REG_MB_ISH133REG_MB_ISHST134REG_MB_NSH135REG_MB_NSHST136REG_MB_OSH137REG_MB_OSHST138MAXREG140)141const (143C_NONE = iota144C_REG145C_REGREG146C_REGREG2147C_REGLIST148C_SHIFT /* register shift R>>x */149C_SHIFTADDR /* memory address with shifted offset R>>x(R) */150C_FREG151C_PSR152C_FCR153C_SPR /* REG_MB_SY */154C_RCON /* 0xff rotated */156C_NCON /* ~RCON */157C_RCON2A /* OR of two disjoint C_RCON constants */158C_RCON2S /* subtraction of two disjoint C_RCON constants */159C_SCON /* 0xffff */160C_LCON161C_LCONADDR162C_ZFCON163C_SFCON164C_LFCON165C_RACON167C_LACON168C_SBRA170C_LBRA171C_HAUTO /* halfword insn offset (-0xff to 0xff) */173C_FAUTO /* float insn offset (0 to 0x3fc, word aligned) */174C_HFAUTO /* both H and F */175C_SAUTO /* -0xfff to 0xfff */176C_LAUTO177C_HOREG179C_FOREG180C_HFOREG181C_SOREG182C_ROREG183C_SROREG /* both nil and R */184C_LOREG185C_PC187C_SP188C_HREG189C_ADDR /* reference to relocatable address */191// TLS "var" in local exec mode: will become a constant offset from193// thread local base that is ultimately chosen by the program linker.194C_TLS_LE195// TLS "var" in initial exec mode: will become a memory address (chosen197// by the program linker) that the dynamic linker will fill with the198// offset from the thread local base.199C_TLS_IE200C_TEXTSIZE202C_GOK204C_NCLASS /* must be the last */206)207const (209AAND = obj.ABaseARM + obj.A_ARCHSPECIFIC + iota210AEOR211ASUB212ARSB213AADD214AADC215ASBC216ARSC217ATST218ATEQ219ACMP220ACMN221AORR222ABIC223AMVN225/*227* Do not reorder or fragment the conditional branch228* opcodes, or the predication code will break229*/230ABEQ231ABNE232ABCS233ABHS234ABCC235ABLO236ABMI237ABPL238ABVS239ABVC240ABHI241ABLS242ABGE243ABLT244ABGT245ABLE246AMOVWD248AMOVWF249AMOVDW250AMOVFW251AMOVFD252AMOVDF253AMOVF254AMOVD255ACMPF257ACMPD258AADDF259AADDD260ASUBF261ASUBD262AMULF263AMULD264ANMULF265ANMULD266AMULAF267AMULAD268ANMULAF269ANMULAD270AMULSF271AMULSD272ANMULSF273ANMULSD274AFMULAF275AFMULAD276AFNMULAF277AFNMULAD278AFMULSF279AFMULSD280AFNMULSF281AFNMULSD282ADIVF283ADIVD284ASQRTF285ASQRTD286AABSF287AABSD288ANEGF289ANEGD290ASRL292ASRA293ASLL294AMULU295ADIVU296AMUL297AMMUL298ADIV299AMOD300AMODU301ADIVHW302ADIVUHW303AMOVB305AMOVBS306AMOVBU307AMOVH308AMOVHS309AMOVHU310AMOVW311AMOVM312ASWPBU313ASWPW314ARFE316ASWI317AMULA318AMULS319AMMULA320AMMULS321AWORD323AMULL325AMULAL326AMULLU327AMULALU328ABX330ABXRET331ADWORD332ALDREX334ASTREX335ALDREXD336ASTREXD337ADMB339APLD341ACLZ343AREV344AREV16345AREVSH346ARBIT347AXTAB349AXTAH350AXTABU351AXTAHU352ABFX354ABFXU355ABFC356ABFI357AMULWT359AMULWB360AMULBB361AMULAWT362AMULAWB363AMULABB364AMRC // MRC/MCR366ALAST368// aliases370AB = obj.AJMP371ABL = obj.ACALL372)373/* scond byte */375const (376C_SCOND = (1 << 4) - 1377C_SBIT = 1 << 4378C_PBIT = 1 << 5379C_WBIT = 1 << 6380C_FBIT = 1 << 7 /* psr flags-only */381C_UBIT = 1 << 7 /* up bit, unsigned bit */382// These constants are the ARM condition codes encodings,384// XORed with 14 so that C_SCOND_NONE has value 0,385// so that a zeroed Prog.scond means "always execute".386C_SCOND_XOR = 14387C_SCOND_EQ = 0 ^ C_SCOND_XOR389C_SCOND_NE = 1 ^ C_SCOND_XOR390C_SCOND_HS = 2 ^ C_SCOND_XOR391C_SCOND_LO = 3 ^ C_SCOND_XOR392C_SCOND_MI = 4 ^ C_SCOND_XOR393C_SCOND_PL = 5 ^ C_SCOND_XOR394C_SCOND_VS = 6 ^ C_SCOND_XOR395C_SCOND_VC = 7 ^ C_SCOND_XOR396C_SCOND_HI = 8 ^ C_SCOND_XOR397C_SCOND_LS = 9 ^ C_SCOND_XOR398C_SCOND_GE = 10 ^ C_SCOND_XOR399C_SCOND_LT = 11 ^ C_SCOND_XOR400C_SCOND_GT = 12 ^ C_SCOND_XOR401C_SCOND_LE = 13 ^ C_SCOND_XOR402C_SCOND_NONE = 14 ^ C_SCOND_XOR403C_SCOND_NV = 15 ^ C_SCOND_XOR404/* D_SHIFT type */406SHIFT_LL = 0 << 5407SHIFT_LR = 1 << 5408SHIFT_AR = 2 << 5409SHIFT_RR = 3 << 5410)411