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1// Copyright 2015 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// This file encapsulates some of the odd characteristics of the
6// 64-bit PowerPC (PPC64) instruction set, to minimize its interaction
7// with the core of the assembler.
8
9package arch
10
11import (
12"github.com/twitchyliquid64/golang-asm/obj"
13"github.com/twitchyliquid64/golang-asm/obj/ppc64"
14)
15
16func jumpPPC64(word string) bool {
17switch word {
18case "BC", "BCL", "BEQ", "BGE", "BGT", "BL", "BLE", "BLT", "BNE", "BR", "BVC", "BVS", "CALL", "JMP":
19return true
20}
21return false
22}
23
24// IsPPC64RLD reports whether the op (as defined by an ppc64.A* constant) is
25// one of the RLD-like instructions that require special handling.
26// The FMADD-like instructions behave similarly.
27func IsPPC64RLD(op obj.As) bool {
28switch op {
29case ppc64.ARLDC, ppc64.ARLDCCC, ppc64.ARLDCL, ppc64.ARLDCLCC,
30ppc64.ARLDCR, ppc64.ARLDCRCC, ppc64.ARLDMI, ppc64.ARLDMICC,
31ppc64.ARLWMI, ppc64.ARLWMICC, ppc64.ARLWNM, ppc64.ARLWNMCC:
32return true
33case ppc64.AFMADD, ppc64.AFMADDCC, ppc64.AFMADDS, ppc64.AFMADDSCC,
34ppc64.AFMSUB, ppc64.AFMSUBCC, ppc64.AFMSUBS, ppc64.AFMSUBSCC,
35ppc64.AFNMADD, ppc64.AFNMADDCC, ppc64.AFNMADDS, ppc64.AFNMADDSCC,
36ppc64.AFNMSUB, ppc64.AFNMSUBCC, ppc64.AFNMSUBS, ppc64.AFNMSUBSCC:
37return true
38}
39return false
40}
41
42func IsPPC64ISEL(op obj.As) bool {
43return op == ppc64.AISEL
44}
45
46// IsPPC64CMP reports whether the op (as defined by an ppc64.A* constant) is
47// one of the CMP instructions that require special handling.
48func IsPPC64CMP(op obj.As) bool {
49switch op {
50case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU:
51return true
52}
53return false
54}
55
56// IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
57// one of the NEG-like instructions that require special handling.
58func IsPPC64NEG(op obj.As) bool {
59switch op {
60case ppc64.AADDMECC, ppc64.AADDMEVCC, ppc64.AADDMEV, ppc64.AADDME,
61ppc64.AADDZECC, ppc64.AADDZEVCC, ppc64.AADDZEV, ppc64.AADDZE,
62ppc64.ACNTLZDCC, ppc64.ACNTLZD, ppc64.ACNTLZWCC, ppc64.ACNTLZW,
63ppc64.AEXTSBCC, ppc64.AEXTSB, ppc64.AEXTSHCC, ppc64.AEXTSH,
64ppc64.AEXTSWCC, ppc64.AEXTSW, ppc64.ANEGCC, ppc64.ANEGVCC,
65ppc64.ANEGV, ppc64.ANEG, ppc64.ASLBMFEE, ppc64.ASLBMFEV,
66ppc64.ASLBMTE, ppc64.ASUBMECC, ppc64.ASUBMEVCC, ppc64.ASUBMEV,
67ppc64.ASUBME, ppc64.ASUBZECC, ppc64.ASUBZEVCC, ppc64.ASUBZEV,
68ppc64.ASUBZE:
69return true
70}
71return false
72}
73
74func ppc64RegisterNumber(name string, n int16) (int16, bool) {
75switch name {
76case "CR":
77if 0 <= n && n <= 7 {
78return ppc64.REG_CR0 + n, true
79}
80case "VS":
81if 0 <= n && n <= 63 {
82return ppc64.REG_VS0 + n, true
83}
84case "V":
85if 0 <= n && n <= 31 {
86return ppc64.REG_V0 + n, true
87}
88case "F":
89if 0 <= n && n <= 31 {
90return ppc64.REG_F0 + n, true
91}
92case "R":
93if 0 <= n && n <= 31 {
94return ppc64.REG_R0 + n, true
95}
96case "SPR":
97if 0 <= n && n <= 1024 {
98return ppc64.REG_SPR0 + n, true
99}
100}
101return 0, false
102}
103