List of useful materials on FPGA topic -- FPGA useful list

Content

schoolMIPS - A small MIPS CPU core originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris).
RARS - RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs.
schoolRISCV - Tiny RISCV CPU. Originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris) and schoolMIPS project.
LUMOS - Multicycle RISC-V processor that implements a subset of RV32I instruction set, designed for educational use in computer organization classes at Iran University of Science and Technology.
PicoRV32 - PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set.
MIRISCV - CPU core that implements ISA RV32IM.
Ibex - Production-quality open source 32-bit RISC-V CPU that supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
RISCV-DV - RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification.
AAPG - Automated Assembly Program Generator for the RISC-V ISA.
APS - Лекции и лабораторные по курсу «Архитектуры процессорных систем»

SV2V - Converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
hdlgadgets - A human-in-the-loop training tool for rtl-developers, microarchitects and verification engineers allowing experiments with flow control and verification techniques
DESim - Application that provides a graphical user interface (GUI) that represents some of the features of a DE1-SoC board.
openFPGALoader - Universal utility for programming FPGAs.
Digital - Easy-to-use digital logic designer and circuit simulator designed for educational purposes.
WaveDrom - Online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics.
Yosys - Framework for RTL synthesis tools.
Verilator - SystemVerilog simulator and lint system
Icarus Verilog - Intended to compile ALL of the Verilog HDL, as described in the IEEE-1364 standard.
GTKWave - Fully featured GTK+ based wave viewer for Unix and Win32 which reads FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
HDLMake - Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)
Cocotb - Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
PyUVM - UVM written in Python
SVUnit - Framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.