Digital_Design_Lab_Manual

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module ram_reg #(
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	parameter DATA_WIDTH = 8,
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	parameter ADDR_WIDTH = 16
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) (
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	input                   clk,
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	input                   we,
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	input  [DATA_WIDTH-1:0] data_in,
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	input  [ADDR_WIDTH-1:0] addr_in,
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	output [DATA_WIDTH-1:0] data_out,
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	output [ADDR_WIDTH-1:0] addr_out
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);
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reg [DATA_WIDTH-1:0] ram [0:2**ADDR_WIDTH-1];
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reg [ADDR_WIDTH-1:0] addr_reg;
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reg [DATA_WIDTH-1:0] data_in_reg;
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reg [DATA_WIDTH-1:0] data_out_reg
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always @(posedge clk) begin
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	if (we)
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		ram[addr_in] <= data_in_reg;
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		data_in_reg <= data_in;
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		data_out_reg <= ram[addr_in];
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		addr_reg <= addr_in;
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end
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assign data_out = data_out_reg;
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assign addr_out = addr_reg;
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endmodule
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