Digital_Design_Lab_Manual

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module register #(
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	parameter WIDTH = 32
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) (
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	input                  clk, 
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	input                  en,
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	input [WIDTH-1:0]      d,
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	output reg [WIDTH-1:0] q
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);
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always @(posedge clk) begin
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	if (en)
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		q <= d;
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end
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endmodule
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