Digital_Design_Lab_Manual
25 строк · 516.0 Байт
1module ram #(
2parameter DATA_WIDTH = 8,
3parameter ADDR_WIDTH = 11
4) (
5input clk,
6input we,
7input [DATA_WIDTH-1:0] data_in,
8input [ADDR_WIDTH-1:0] addr_in,
9output [DATA_WIDTH-1:0] data_out,
10output [ADDR_WIDTH-1:0] addr_out
11);
12
13reg [DATA_WIDTH-1:0] ram [0:2**ADDR_WIDTH-1];
14reg [ADDR_WIDTH-1:0] addr_reg;
15
16always @(posedge clk) begin
17if (we)
18ram[addr_in] <= data_in;
19addr_reg <= addr_in;
20end
21
22assign data_out = ram[addr_reg];
23assign addr_out = addr_reg;
24
25endmodule
26