Digital_Design_Lab_Manual

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module sevenseg_2 (
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	input  [3:0] in1, 
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	input  [3:0] in2,
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	output [6:0] out1, 
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	output [6:0] out2
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);
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always @(*) begin
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	case (in1)
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		4'b0000: out1 = 7'b0111111;
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		4'b0001: out1 = 7'b0000110;
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		4'b0010: out1 = 7'b1011011;
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		4'b0011: out1 = 7'b1001111;
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		4'b0100: out1 = 7'b1100110;
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		4'b0101: out1 = 7'b1101101;
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		4'b0110: out1 = 7'b1111101;
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		4'b0111: out1 = 7'b0000111;
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		4'b1000: out1 = 7'b1111111;
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		4'b1001: out1 = 7'b1101111;
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		4'b1010: out1 = 7'b1110111;
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		4'b1011: out1 = 7'b1111100;
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		4'b1100: out1 = 7'b0111001;
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		4'b1101: out1 = 7'b1011110;
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		4'b1110: out1 = 7'b1111011;
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		4'b1111: out1 = 7'b1110001;
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		default: out1 = 7'b0000000;	
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	endcase
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	case(in2)
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		4'b0000: out2 = 7'b0111111;
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		4'b0001: out2 = 7'b0000110;
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		4'b0010: out2 = 7'b1011011;
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		4'b0011: out2 = 7'b1001111;
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		4'b0100: out2 = 7'b1100110;
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		4'b0101: out2 = 7'b1101101;
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		4'b0110: out2 = 7'b1111101;
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		4'b0111: out2 = 7'b0000111;
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		4'b1000: out2 = 7'b1111111;
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		4'b1001: out2 = 7'b1101111;
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		4'b1010: out2 = 7'b1110111;
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		4'b1011: out2 = 7'b1111100;
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		4'b1100: out2 = 7'b0111001;
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		4'b1101: out2 = 7'b1011110;
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		4'b1110: out2 = 7'b1111011;
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		4'b1111: out2 = 7'b1110001;
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		default: out2 = 7'b0000000;
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	endcase
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end
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endmodule
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