loom

1
module rk(
2
  input logic clk,
3
  input logic rst,
4
  input logic cs,
5
  input logic inc,
6
  input logic [7:0] d_in,
7
  output logic data_valid,
8
  output logic [7:0] d_out
9
);
10
  always_ff @(posedge clk, posedge rst)
11
  begin
12
    if (rst)
13
      begin
14
      	data_valid <= 1;
15
        d_out <= 'b00000000;
16
      end
17
    else if (clk)
18
      begin
19
      	data_valid <= cs;
20
        if (!cs)
21
          if (inc)
22
            d_out <= d_in + 1;
23
          else
24
            d_out <= d_in - 1;
25
      end
26
  end
27
endmodule
28