loom

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module fsm(
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  input logic clk,  
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  input logic rst,
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  input logic [5:0] c,
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  output logic [2:0] st,
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  output logic [7:0] num
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);
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  logic [2:0] State;  
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  always_comb
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    st = State;
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  always_ff @ (posedge clk, negedge rst)
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  begin
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    if(!rst) begin      
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      num <= 0;
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      State <= 1;
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    end
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    else if(State == 1) begin      
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      if(c[4] == 1 && c[5] == 1) begin
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        num <= 'b00000101;        
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        State <= 2;
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      end      
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      else if(c[2] == 1 && c[3] == 0) begin  
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        num <= 'b00011000;        
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        State <= 4;
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      end      
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      else if(c[0] == 1 || c[2] == 0) begin
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        num <= 'b01100000;        
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        State <= 6;
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      end      
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      else if(c[3] == 1)
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        State <= 5;      
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      else begin
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        num <= 'b00001000;        
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        State <= 1;
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      end    
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    end
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    else if(State == 2) begin      
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      if(c[0] == 1 && c[1] == 1 && c[2] == 1)
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        State <= 2;      
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      else
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        State <= 3;    
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    end
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    else if (State == 3) begin      
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      if(c[0] == 1 && c[1] == 0) begin
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        num <= 'b10010000;        
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        State <= 1;
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      end      
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      else begin
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       num <= 'b00000001;        
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       State <= 3;
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      end   
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    end
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    else if(State == 4) begin      
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      if(c[0] == 1 && c[5] == 0)
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        State <= 4;      
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      else begin
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        num <= 'b10001000;        
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        State <= 3;
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      end    
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    end
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    else if(State == 5) begin      
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      if (c[0] == 1 && c[1] == 1 && c[2] == 1) begin
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       num <= 'b00000001;        
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        State <= 1;
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      end      
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      else
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        State <= 5;    
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    end
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    else if(State == 6) begin      
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      if (c[4] == 1 || c[5] == 1) begin
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        num <= 'b00000001;        
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        State <= 5;
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      end      
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      else
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        State <= 6;    
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    end
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  end  
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endmodule
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