loom

1
/*
2
MIT License
3

4
Copyright (c) 2022 МГТУ им. Н.Э. Баумана, кафедра ИУ-6, Михаил Фетисов,
5

6
https://bmstu.codes/lsx/simodo/loom
7
*/
8

9
#include "SystemVerilogAnalyzer.h"
10
#include "simodo/interpret/AnalyzeException.h"
11
#include "simodo/inout/convert/functions.h"
12
#include "simodo/inout/format/fmt.h"
13

14
using namespace simodo;
15

16
namespace sv
17
{
18
    namespace 
19
    {
20
        interpret::SemanticDataCollector_null null_collector;
21
    }
22

23
    SystemVerilogAnalyzer::SystemVerilogAnalyzer(interpret::ModuleManagement_interface & module_management)
24
        : SystemVerilogSemantics_abstract(module_management)
25
        , _collector(null_collector)
26
    {
27
    }
28

29
    SystemVerilogAnalyzer::SystemVerilogAnalyzer(interpret::ModuleManagement_interface & module_management, 
30
                            interpret::SemanticDataCollector_interface & collector)
31
        : SystemVerilogSemantics_abstract(module_management)
32
        , _collector(collector)
33
    {
34
    }
35

36
    bool SystemVerilogAnalyzer::checkInterpretType(interpret::InterpretType interpret_type) const
37
    {
38
        return interpret_type == interpret::InterpretType::Analyzer;
39
    }
40

41
    interpret::InterpretState SystemVerilogAnalyzer::performOperation(const ast::Node & op)
42
    {
43
        try
44
        {
45
            return SystemVerilogSemantics_abstract::performOperation(op);
46
        }
47
        catch(const interpret::AnalyzeException & e)
48
        {
49
            inter().reporter().reportError(e.location(), e.what());
50
            _number_of_mistakes ++;
51
        }
52

53
        if (_number_of_mistakes >= MAX_NUMBER_OF_MISTAKES) 
54
            throw interpret::AnalyzeException("ScriptAnalyzer::performOperation", 
55
                                    op.token().makeLocation(inter().files()), 
56
                                    inout::fmt("The number of errors has exceeded the allowable limit"));
57
        
58
        return interpret::InterpretState::Flow;
59
    }
60

61
    interpret::InterpretState SystemVerilogAnalyzer::before_start()
62
    {
63
        return SystemVerilogSemantics_abstract::before_start();
64
    }
65

66
    interpret::InterpretState SystemVerilogAnalyzer::before_finish(interpret::InterpretState state)
67
    {
68
        return SystemVerilogSemantics_abstract::before_finish(state);
69
    }
70

71
    // interpret::InterpretState SystemVerilogAnalyzer::executePushConst()
72
    // {
73
    //     inter().stack().pop();
74

75
    //     return interpret::InterpretState::Flow;
76
    // }
77

78
}